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auxioreg.h revision 1.3.10.1
      1  1.3.10.1  thorpej /*	$NetBSD: auxioreg.h,v 1.3.10.1 2002/01/10 19:49:14 thorpej Exp $	*/
      2       1.1      mrg 
      3       1.1      mrg /*
      4       1.2      mrg  * Copyright (c) 2000 Matthew R. Green
      5       1.1      mrg  * All rights reserved.
      6       1.1      mrg  *
      7       1.1      mrg  * Redistribution and use in source and binary forms, with or without
      8       1.1      mrg  * modification, are permitted provided that the following conditions
      9       1.1      mrg  * are met:
     10       1.1      mrg  * 1. Redistributions of source code must retain the above copyright
     11       1.1      mrg  *    notice, this list of conditions and the following disclaimer.
     12       1.1      mrg  * 2. Redistributions in binary form must reproduce the above copyright
     13       1.1      mrg  *    notice, this list of conditions and the following disclaimer in the
     14       1.1      mrg  *    documentation and/or other materials provided with the distribution.
     15       1.1      mrg  * 3. The name of the author may not be used to endorse or promote products
     16       1.1      mrg  *    derived from this software without specific prior written permission.
     17       1.1      mrg  *
     18       1.1      mrg  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     19       1.1      mrg  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     20       1.1      mrg  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     21       1.1      mrg  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     22       1.1      mrg  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
     23       1.1      mrg  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
     24       1.1      mrg  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
     25       1.1      mrg  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
     26       1.1      mrg  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     27       1.1      mrg  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     28       1.1      mrg  * SUCH DAMAGE.
     29       1.1      mrg  */
     30       1.1      mrg 
     31       1.1      mrg /*
     32       1.1      mrg  * The AUXIO registers; their offset in the Ebus2 address space, plus the
     33       1.3      mrg  * bits for each register.  Note that the fdthree (FD), SUNW,CS4231 (AUDIO)
     34       1.3      mrg  * and power (POWER) devices on the Ebus2 have their AUXIO regsiters mapped
     35       1.3      mrg  * into their own "reg" properties, not the "auxio" device's "reg" properties.
     36       1.1      mrg  */
     37       1.1      mrg #define	AUXIO_FD			0x00720000
     38       1.1      mrg #define	AUXIO_FD_DENSENSE_INPUT		0x0
     39       1.1      mrg #define	AUXIO_FD_DENSENSE_OUTPUT	0x1
     40       1.1      mrg 
     41       1.1      mrg #define	AUXIO_AUDIO			0x00722000
     42       1.1      mrg #define	AUXIO_AUDIO_POWERDOWN		0x0
     43       1.1      mrg 
     44       1.1      mrg #define	AUXIO_POWER			0x00724000
     45       1.1      mrg #define	AUXIO_POWER_SYSTEM_OFF		0x0
     46       1.1      mrg #define	AUXIO_POWER_COURTESY_OFF	0x1
     47       1.1      mrg 
     48       1.1      mrg #define	AUXIO_LED			0x00726000
     49  1.3.10.1  thorpej #define	AUXIO_LED_LED			1
     50       1.1      mrg 
     51       1.1      mrg #define	AUXIO_PCI			0x00728000
     52       1.1      mrg #define	AUXIO_PCI_SLOT0			0x0	/* two bits each */
     53       1.1      mrg #define	AUXIO_PCI_SLOT1			0x2
     54       1.1      mrg #define	AUXIO_PCI_SLOT2			0x4
     55       1.1      mrg #define	AUXIO_PCI_SLOT3			0x6
     56       1.1      mrg #define	AUXIO_PCI_MODE			0x8
     57       1.1      mrg 
     58       1.1      mrg #define	AUXIO_FREQ			0x0072a000
     59       1.1      mrg #define	AUXIO_FREQ_FREQ0		0x0
     60       1.1      mrg #define	AUXIO_FREQ_FREQ1		0x1
     61       1.1      mrg #define	AUXIO_FREQ_FREQ2		0x2
     62       1.1      mrg 
     63       1.1      mrg #define	AUXIO_SCSI			0x0072c000
     64       1.1      mrg #define	AUXIO_SCSI_INT_OSC_EN		0x0
     65       1.1      mrg #define	AUXIO_SCSI_EXT_OSC_EN		0x1
     66       1.1      mrg 
     67       1.1      mrg #define	AUXIO_TEMP			0x0072f000
     68       1.1      mrg #define	AUXIO_TEMP_SELECT		0x0
     69       1.1      mrg #define	AUXIO_TEMP_CLOCK		0x1
     70       1.1      mrg #define	AUXIO_TEMP_ENABLE		0x2
     71       1.1      mrg #define	AUXIO_TEMP_DATAOUT		0x3
     72       1.1      mrg #define	AUXIO_TEMP_DATAINT		0x4
     73