ebus.c revision 1.22.2.2
1 /* $NetBSD: ebus.c,v 1.22.2.2 2001/09/13 01:14:39 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000 Matthew R. Green 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 23 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 24 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 25 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 #include "opt_ddb.h" 32 33 /* 34 * UltraSPARC 5 and beyond ebus support. 35 * 36 * note that this driver is not complete: 37 * - ebus2 dma code is completely unwritten 38 * - interrupt establish is written and appears to work 39 * - bus map code is written and appears to work 40 */ 41 42 #undef DEBUG 43 #define DEBUG 44 45 #ifdef DEBUG 46 #define EDB_PROM 0x01 47 #define EDB_CHILD 0x02 48 #define EDB_INTRMAP 0x04 49 #define EDB_BUSMAP 0x08 50 #define EDB_BUSDMA 0x10 51 #define EDB_INTR 0x20 52 int ebus_debug = 0x0; 53 #define DPRINTF(l, s) do { if (ebus_debug & l) printf s; } while (0) 54 #else 55 #define DPRINTF(l, s) 56 #endif 57 58 #include <sys/param.h> 59 #include <sys/conf.h> 60 #include <sys/device.h> 61 #include <sys/errno.h> 62 #include <sys/extent.h> 63 #include <sys/malloc.h> 64 #include <sys/systm.h> 65 #include <sys/time.h> 66 67 #define _SPARC_BUS_DMA_PRIVATE 68 #include <machine/bus.h> 69 #include <machine/autoconf.h> 70 #include <machine/openfirm.h> 71 72 #include <dev/pci/pcivar.h> 73 #include <dev/pci/pcireg.h> 74 #include <dev/pci/pcidevs.h> 75 76 #include <sparc64/dev/iommureg.h> 77 #include <sparc64/dev/iommuvar.h> 78 #include <sparc64/dev/psychoreg.h> 79 #include <sparc64/dev/psychovar.h> 80 #include <sparc64/dev/ebusreg.h> 81 #include <sparc64/dev/ebusvar.h> 82 #include <sparc64/sparc64/cache.h> 83 84 int ebus_match __P((struct device *, struct cfdata *, void *)); 85 void ebus_attach __P((struct device *, struct device *, void *)); 86 87 struct cfattach ebus_ca = { 88 sizeof(struct ebus_softc), ebus_match, ebus_attach 89 }; 90 91 int ebus_setup_attach_args __P((struct ebus_softc *, int, 92 struct ebus_attach_args *)); 93 void ebus_destroy_attach_args __P((struct ebus_attach_args *)); 94 int ebus_print __P((void *, const char *)); 95 void ebus_find_ino __P((struct ebus_softc *, struct ebus_attach_args *)); 96 int ebus_find_node __P((struct pci_attach_args *)); 97 98 /* 99 * here are our bus space and bus dma routines. 100 */ 101 static int ebus_bus_mmap __P((bus_space_tag_t, bus_type_t, bus_addr_t, 102 int, bus_space_handle_t *)); 103 static int _ebus_bus_map __P((bus_space_tag_t, bus_type_t, bus_addr_t, 104 bus_size_t, int, vaddr_t, 105 bus_space_handle_t *)); 106 static void *ebus_intr_establish __P((bus_space_tag_t, int, int, int, 107 int (*) __P((void *)), void *)); 108 109 static int ebus_dmamap_load __P((bus_dma_tag_t, bus_dmamap_t, void *, 110 bus_size_t, struct proc *, int)); 111 static void ebus_dmamap_unload __P((bus_dma_tag_t, bus_dmamap_t)); 112 static void ebus_dmamap_sync __P((bus_dma_tag_t, bus_dmamap_t, bus_addr_t, 113 bus_size_t, int)); 114 int ebus_dmamem_alloc __P((bus_dma_tag_t, bus_size_t, bus_size_t, bus_size_t, 115 bus_dma_segment_t *, int, int *, int)); 116 void ebus_dmamem_free __P((bus_dma_tag_t, bus_dma_segment_t *, int)); 117 int ebus_dmamem_map __P((bus_dma_tag_t, bus_dma_segment_t *, int, size_t, 118 caddr_t *, int)); 119 void ebus_dmamem_unmap __P((bus_dma_tag_t, caddr_t, size_t)); 120 121 int 122 ebus_match(parent, match, aux) 123 struct device *parent; 124 struct cfdata *match; 125 void *aux; 126 { 127 struct pci_attach_args *pa = aux; 128 char name[10]; 129 int node; 130 131 /* Only attach if there's a PROM node. */ 132 node = PCITAG_NODE(pa->pa_tag); 133 if (node == -1) return (0); 134 135 /* Match a real ebus */ 136 OF_getprop(node, "name", &name, sizeof(name)); 137 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 138 PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SUN && 139 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SUN_EBUS && 140 strcmp(name, "ebus") == 0) 141 return (1); 142 143 /* Or a real ebus III */ 144 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 145 PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SUN && 146 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SUN_EBUSIII && 147 strcmp(name, "ebus") == 0) 148 return (1); 149 150 /* Or a PCI-ISA bridge XXX I hope this is on-board. */ 151 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && 152 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_ISA) { 153 return (1); 154 } 155 156 return (0); 157 } 158 159 /* 160 * attach an ebus and all it's children. this code is modeled 161 * after the sbus code which does similar things. 162 */ 163 void 164 ebus_attach(parent, self, aux) 165 struct device *parent, *self; 166 void *aux; 167 { 168 struct ebus_softc *sc = (struct ebus_softc *)self; 169 struct pci_attach_args *pa = aux; 170 struct ebus_attach_args eba; 171 struct ebus_interrupt_map_mask *immp; 172 int node, nmapmask, error; 173 char devinfo[256]; 174 175 printf("\n"); 176 177 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo); 178 printf("%s: %s, revision 0x%02x\n", self->dv_xname, devinfo, 179 PCI_REVISION(pa->pa_class)); 180 181 sc->sc_parent = (struct psycho_softc *)parent; 182 sc->sc_memtag = pa->pa_memt; 183 sc->sc_iotag = pa->pa_iot; 184 sc->sc_childbustag = ebus_alloc_bus_tag(sc, PCI_MEMORY_BUS_SPACE); 185 sc->sc_dmatag = ebus_alloc_dma_tag(sc, pa->pa_dmat); 186 187 node = PCITAG_NODE(pa->pa_tag); 188 if (node == -1) 189 panic("could not find ebus node"); 190 191 sc->sc_node = node; 192 193 /* 194 * fill in our softc with information from the prom 195 */ 196 sc->sc_intmap = NULL; 197 sc->sc_range = NULL; 198 error = getprop(node, "interrupt-map", 199 sizeof(struct ebus_interrupt_map), 200 &sc->sc_nintmap, (void **)&sc->sc_intmap); 201 switch (error) { 202 case 0: 203 immp = &sc->sc_intmapmask; 204 error = getprop(node, "interrupt-map-mask", 205 sizeof(struct ebus_interrupt_map_mask), &nmapmask, 206 (void **)&immp); 207 if (error) 208 panic("could not get ebus interrupt-map-mask"); 209 if (nmapmask != 1) 210 panic("ebus interrupt-map-mask is broken"); 211 break; 212 case ENOENT: 213 break; 214 default: 215 panic("ebus interrupt-map: error %d", error); 216 break; 217 } 218 219 error = getprop(node, "ranges", sizeof(struct ebus_ranges), 220 &sc->sc_nrange, (void **)&sc->sc_range); 221 if (error) 222 panic("ebus ranges: error %d", error); 223 224 /* 225 * now attach all our children 226 */ 227 DPRINTF(EDB_CHILD, ("ebus node %08x, searching children...\n", node)); 228 for (node = firstchild(node); node; node = nextsibling(node)) { 229 char *name = getpropstring(node, "name"); 230 231 if (ebus_setup_attach_args(sc, node, &eba) != 0) { 232 printf("ebus_attach: %s: incomplete\n", name); 233 continue; 234 } else { 235 DPRINTF(EDB_CHILD, ("- found child `%s', attaching\n", 236 eba.ea_name)); 237 (void)config_found(self, &eba, ebus_print); 238 } 239 ebus_destroy_attach_args(&eba); 240 } 241 } 242 243 int 244 ebus_setup_attach_args(sc, node, ea) 245 struct ebus_softc *sc; 246 int node; 247 struct ebus_attach_args *ea; 248 { 249 int n, rv; 250 251 bzero(ea, sizeof(struct ebus_attach_args)); 252 rv = getprop(node, "name", 1, &n, (void **)&ea->ea_name); 253 if (rv != 0) 254 return (rv); 255 ea->ea_name[n] = '\0'; 256 257 ea->ea_node = node; 258 ea->ea_bustag = sc->sc_childbustag; 259 ea->ea_dmatag = sc->sc_dmatag; 260 261 rv = getprop(node, "reg", sizeof(struct ebus_regs), &ea->ea_nregs, 262 (void **)&ea->ea_regs); 263 if (rv) 264 return (rv); 265 266 rv = getprop(node, "address", sizeof(u_int32_t), &ea->ea_nvaddrs, 267 (void **)&ea->ea_vaddrs); 268 if (rv != ENOENT) { 269 if (rv) 270 return (rv); 271 272 if (ea->ea_nregs != ea->ea_nvaddrs) 273 printf("ebus loses: device %s: %d regs and %d addrs\n", 274 ea->ea_name, ea->ea_nregs, ea->ea_nvaddrs); 275 } else 276 ea->ea_nvaddrs = 0; 277 278 if (getprop(node, "interrupts", sizeof(u_int32_t), &ea->ea_nintrs, 279 (void **)&ea->ea_intrs)) 280 ea->ea_nintrs = 0; 281 else 282 ebus_find_ino(sc, ea); 283 284 return (0); 285 } 286 287 void 288 ebus_destroy_attach_args(ea) 289 struct ebus_attach_args *ea; 290 { 291 292 if (ea->ea_name) 293 free((void *)ea->ea_name, M_DEVBUF); 294 if (ea->ea_regs) 295 free((void *)ea->ea_regs, M_DEVBUF); 296 if (ea->ea_intrs) 297 free((void *)ea->ea_intrs, M_DEVBUF); 298 if (ea->ea_vaddrs) 299 free((void *)ea->ea_vaddrs, M_DEVBUF); 300 } 301 302 int 303 ebus_print(aux, p) 304 void *aux; 305 const char *p; 306 { 307 struct ebus_attach_args *ea = aux; 308 int i; 309 310 if (p) 311 printf("%s at %s", ea->ea_name, p); 312 for (i = 0; i < ea->ea_nregs; i++) 313 printf("%s %x-%x", i == 0 ? " addr" : ",", 314 ea->ea_regs[i].lo, 315 ea->ea_regs[i].lo + ea->ea_regs[i].size - 1); 316 for (i = 0; i < ea->ea_nintrs; i++) 317 printf(" ipl %d", ea->ea_intrs[i]); 318 return (UNCONF); 319 } 320 321 322 /* 323 * find the INO values for each interrupt and fill them in. 324 * 325 * for each "reg" property of this device, mask it's hi and lo 326 * values with the "interrupt-map-mask"'s hi/lo values, and also 327 * mask the interrupt number with the interrupt mask. search the 328 * "interrupt-map" list for matching values of hi, lo and interrupt 329 * to give the INO for this interrupt. 330 */ 331 void 332 ebus_find_ino(sc, ea) 333 struct ebus_softc *sc; 334 struct ebus_attach_args *ea; 335 { 336 u_int32_t hi, lo, intr; 337 int i, j, k; 338 339 if (sc->sc_nintmap == 0) { 340 for (i = 0; i < ea->ea_nintrs; i++) { 341 OF_mapintr(ea->ea_node, &ea->ea_intrs[i], 342 sizeof(ea->ea_intrs[0]), 343 sizeof(ea->ea_intrs[0])); 344 } 345 return; 346 } 347 348 DPRINTF(EDB_INTRMAP, 349 ("ebus_find_ino: searching %d interrupts", ea->ea_nintrs)); 350 351 for (j = 0; j < ea->ea_nintrs; j++) { 352 353 intr = ea->ea_intrs[j] & sc->sc_intmapmask.intr; 354 355 DPRINTF(EDB_INTRMAP, 356 ("; intr %x masked to %x", ea->ea_intrs[j], intr)); 357 for (i = 0; i < ea->ea_nregs; i++) { 358 hi = ea->ea_regs[i].hi & sc->sc_intmapmask.hi; 359 lo = ea->ea_regs[i].lo & sc->sc_intmapmask.lo; 360 361 DPRINTF(EDB_INTRMAP, 362 ("; reg hi.lo %08x.%08x masked to %08x.%08x", 363 ea->ea_regs[i].hi, ea->ea_regs[i].lo, hi, lo)); 364 for (k = 0; k < sc->sc_nintmap; k++) { 365 DPRINTF(EDB_INTRMAP, 366 ("; checking hi.lo %08x.%08x intr %x", 367 sc->sc_intmap[k].hi, sc->sc_intmap[k].lo, 368 sc->sc_intmap[k].intr)); 369 if (hi == sc->sc_intmap[k].hi && 370 lo == sc->sc_intmap[k].lo && 371 intr == sc->sc_intmap[k].intr) { 372 ea->ea_intrs[j] = 373 sc->sc_intmap[k].cintr; 374 DPRINTF(EDB_INTRMAP, 375 ("; FOUND IT! changing to %d\n", 376 sc->sc_intmap[k].cintr)); 377 goto next_intr; 378 } 379 } 380 } 381 next_intr:; 382 } 383 } 384 385 386 /* 387 * bus space and bus dma below here 388 */ 389 bus_space_tag_t 390 ebus_alloc_bus_tag(sc, type) 391 struct ebus_softc *sc; 392 int type; 393 { 394 bus_space_tag_t bt; 395 396 bt = (bus_space_tag_t) 397 malloc(sizeof(struct sparc_bus_space_tag), M_DEVBUF, M_NOWAIT); 398 if (bt == NULL) 399 panic("could not allocate ebus bus tag"); 400 401 bzero(bt, sizeof *bt); 402 bt->cookie = sc; 403 bt->parent = sc->sc_memtag; 404 bt->type = type; 405 bt->sparc_bus_map = _ebus_bus_map; 406 bt->sparc_bus_mmap = ebus_bus_mmap; 407 bt->sparc_intr_establish = ebus_intr_establish; 408 return (bt); 409 } 410 411 /* XXX? */ 412 bus_dma_tag_t 413 ebus_alloc_dma_tag(sc, pdt) 414 struct ebus_softc *sc; 415 bus_dma_tag_t pdt; 416 { 417 bus_dma_tag_t dt; 418 419 dt = (bus_dma_tag_t) 420 malloc(sizeof(struct sparc_bus_dma_tag), M_DEVBUF, M_NOWAIT); 421 if (dt == NULL) 422 panic("could not allocate ebus dma tag"); 423 424 bzero(dt, sizeof *dt); 425 dt->_cookie = sc; 426 dt->_parent = pdt; 427 #define PCOPY(x) dt->x = pdt->x 428 PCOPY(_dmamap_create); 429 PCOPY(_dmamap_destroy); 430 dt->_dmamap_load = ebus_dmamap_load; 431 PCOPY(_dmamap_load_mbuf); 432 PCOPY(_dmamap_load_uio); 433 PCOPY(_dmamap_load_raw); 434 dt->_dmamap_unload = ebus_dmamap_unload; 435 dt->_dmamap_sync = ebus_dmamap_sync; 436 dt->_dmamem_alloc = ebus_dmamem_alloc; 437 dt->_dmamem_free = ebus_dmamem_free; 438 dt->_dmamem_map = ebus_dmamem_map; 439 dt->_dmamem_unmap = ebus_dmamem_unmap; 440 PCOPY(_dmamem_mmap); 441 #undef PCOPY 442 return (dt); 443 } 444 445 /* 446 * bus space support. <sparc64/dev/psychoreg.h> has a discussion 447 * about PCI physical addresses, which also applies to ebus. 448 */ 449 static int 450 _ebus_bus_map(t, btype, offset, size, flags, vaddr, hp) 451 bus_space_tag_t t; 452 bus_type_t btype; 453 bus_addr_t offset; 454 bus_size_t size; 455 int flags; 456 vaddr_t vaddr; 457 bus_space_handle_t *hp; 458 { 459 struct ebus_softc *sc = t->cookie; 460 bus_addr_t hi, lo; 461 int i, ss; 462 463 DPRINTF(EDB_BUSMAP, 464 ("\n_ebus_bus_map: type %d off %016llx sz %x flags %d va %p", 465 (int)t->type, (unsigned long long)offset, (int)size, (int)flags, 466 (void *)vaddr)); 467 468 hi = offset >> 32UL; 469 lo = offset & 0xffffffff; 470 DPRINTF(EDB_BUSMAP, (" (hi %08x lo %08x)", (u_int)hi, (u_int)lo)); 471 for (i = 0; i < sc->sc_nrange; i++) { 472 bus_addr_t pciaddr; 473 474 if (hi != sc->sc_range[i].child_hi) 475 continue; 476 if (lo < sc->sc_range[i].child_lo || 477 (lo + size) > 478 (sc->sc_range[i].child_lo + sc->sc_range[i].size)) 479 continue; 480 481 /* Isolate address space and find the right tag */ 482 ss = (sc->sc_range[i].phys_hi>>24)&3; 483 switch (ss) { 484 case 1: /* I/O space */ 485 t = sc->sc_iotag; 486 break; 487 case 2: /* Memory space */ 488 t = sc->sc_memtag; 489 break; 490 case 0: /* Config space */ 491 case 3: /* 64-bit Memory space */ 492 default: /* WTF? */ 493 /* We don't handle these */ 494 panic("_ebus_bus_map: illegal space %x", ss); 495 break; 496 } 497 pciaddr = ((bus_addr_t)sc->sc_range[i].phys_mid << 32UL) | 498 sc->sc_range[i].phys_lo; 499 pciaddr += lo; 500 DPRINTF(EDB_BUSMAP, 501 ("\n_ebus_bus_map: mapping space %x paddr offset %qx pciaddr %qx\n", 502 ss, (unsigned long long)offset, (unsigned long long)pciaddr)); 503 /* pass it onto the psycho */ 504 return (bus_space_map2(t, sc->sc_range[i].phys_hi, 505 pciaddr, size, flags, vaddr, hp)); 506 } 507 DPRINTF(EDB_BUSMAP, (": FAILED\n")); 508 return (EINVAL); 509 } 510 511 static int 512 ebus_bus_mmap(t, btype, paddr, flags, hp) 513 bus_space_tag_t t; 514 bus_type_t btype; 515 bus_addr_t paddr; 516 int flags; 517 bus_space_handle_t *hp; 518 { 519 bus_addr_t offset = paddr; 520 struct ebus_softc *sc = t->cookie; 521 int i; 522 523 for (i = 0; i < sc->sc_nrange; i++) { 524 bus_addr_t paddr = ((bus_addr_t)sc->sc_range[i].child_hi << 32) | 525 sc->sc_range[i].child_lo; 526 527 if (offset != paddr) 528 continue; 529 530 DPRINTF(EDB_BUSMAP, ("\n_ebus_bus_mmap: mapping paddr %qx\n", 531 (unsigned long long)paddr)); 532 return (bus_space_mmap(sc->sc_memtag, 0, paddr, 533 flags, hp)); 534 } 535 536 return (-1); 537 } 538 539 /* 540 * install an interrupt handler for a PCI device 541 */ 542 void * 543 ebus_intr_establish(t, pri, level, flags, handler, arg) 544 bus_space_tag_t t; 545 int pri; 546 int level; 547 int flags; 548 int (*handler) __P((void *)); 549 void *arg; 550 { 551 return (bus_intr_establish(t->parent, pri, level, flags, handler, arg)); 552 } 553 554 /* 555 * bus dma support 556 */ 557 int 558 ebus_dmamap_load(t, map, buf, buflen, p, flags) 559 bus_dma_tag_t t; 560 bus_dmamap_t map; 561 void *buf; 562 bus_size_t buflen; 563 struct proc *p; 564 int flags; 565 { 566 struct ebus_softc *sc = t->_cookie; 567 568 return (iommu_dvmamap_load(t, sc->sc_parent->sc_is, map, buf, buflen, 569 p, flags)); 570 } 571 572 void 573 ebus_dmamap_unload(t, map) 574 bus_dma_tag_t t; 575 bus_dmamap_t map; 576 { 577 struct ebus_softc *sc = t->_cookie; 578 579 iommu_dvmamap_unload(t, sc->sc_parent->sc_is, map); 580 } 581 582 void 583 ebus_dmamap_sync(t, map, offset, len, ops) 584 bus_dma_tag_t t; 585 bus_dmamap_t map; 586 bus_addr_t offset; 587 bus_size_t len; 588 int ops; 589 { 590 struct ebus_softc *sc = t->_cookie; 591 592 iommu_dvmamap_sync(t, sc->sc_parent->sc_is, map, offset, len, ops); 593 bus_dmamap_sync(t->_parent, map, offset, len, ops); 594 } 595 596 int 597 ebus_dmamem_alloc(t, size, alignment, boundary, segs, nsegs, rsegs, flags) 598 bus_dma_tag_t t; 599 bus_size_t size; 600 bus_size_t alignment; 601 bus_size_t boundary; 602 bus_dma_segment_t *segs; 603 int nsegs; 604 int *rsegs; 605 int flags; 606 { 607 struct ebus_softc *sc = t->_cookie; 608 609 return (iommu_dvmamem_alloc(t, sc->sc_parent->sc_is, size, alignment, 610 boundary, segs, nsegs, rsegs, flags)); 611 } 612 613 void 614 ebus_dmamem_free(t, segs, nsegs) 615 bus_dma_tag_t t; 616 bus_dma_segment_t *segs; 617 int nsegs; 618 { 619 struct ebus_softc *sc = t->_cookie; 620 621 iommu_dvmamem_free(t, sc->sc_parent->sc_is, segs, nsegs); 622 } 623 624 int 625 ebus_dmamem_map(t, segs, nsegs, size, kvap, flags) 626 bus_dma_tag_t t; 627 bus_dma_segment_t *segs; 628 int nsegs; 629 size_t size; 630 caddr_t *kvap; 631 int flags; 632 { 633 struct ebus_softc *sc = t->_cookie; 634 635 return (iommu_dvmamem_map(t, sc->sc_parent->sc_is, segs, nsegs, 636 size, kvap, flags)); 637 } 638 639 void 640 ebus_dmamem_unmap(t, kva, size) 641 bus_dma_tag_t t; 642 caddr_t kva; 643 size_t size; 644 { 645 struct ebus_softc *sc = t->_cookie; 646 647 iommu_dvmamem_unmap(t, sc->sc_parent->sc_is, kva, size); 648 } 649
Indexes created Fri Oct 03 02:09:57 GMT 2025