ebus_mainbus.c revision 1.11
11.11Smartin/* $NetBSD: ebus_mainbus.c,v 1.11 2013/09/12 19:51:09 martin Exp $ */ 21.1Smrg/* $OpenBSD: ebus_mainbus.c,v 1.7 2010/11/11 17:58:23 miod Exp $ */ 31.1Smrg 41.1Smrg/* 51.1Smrg * Copyright (c) 2007 Mark Kettenis 61.1Smrg * 71.1Smrg * Permission to use, copy, modify, and distribute this software for any 81.1Smrg * purpose with or without fee is hereby granted, provided that the above 91.1Smrg * copyright notice and this permission notice appear in all copies. 101.1Smrg * 111.1Smrg * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 121.1Smrg * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 131.1Smrg * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 141.1Smrg * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 151.1Smrg * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 161.1Smrg * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 171.1Smrg * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 181.1Smrg */ 191.1Smrg 201.9Smrg#include <sys/cdefs.h> 211.11Smartin__KERNEL_RCSID(0, "$NetBSD: ebus_mainbus.c,v 1.11 2013/09/12 19:51:09 martin Exp $"); 221.9Smrg 231.1Smrg#ifdef DEBUG 241.1Smrg#define EDB_PROM 0x01 251.1Smrg#define EDB_CHILD 0x02 261.1Smrg#define EDB_INTRMAP 0x04 271.1Smrg#define EDB_BUSMAP 0x08 281.1Smrg#define EDB_BUSDMA 0x10 291.1Smrg#define EDB_INTR 0x20 301.1Smrgextern int ebus_debug; 311.1Smrg#define DPRINTF(l, s) do { if (ebus_debug & l) printf s; } while (0) 321.1Smrg#else 331.1Smrg#define DPRINTF(l, s) 341.1Smrg#endif 351.1Smrg 361.1Smrg#include <sys/param.h> 371.1Smrg#include <sys/conf.h> 381.1Smrg#include <sys/device.h> 391.1Smrg#include <sys/errno.h> 401.1Smrg#include <sys/extent.h> 411.1Smrg#include <sys/malloc.h> 421.1Smrg#include <sys/systm.h> 431.1Smrg#include <sys/time.h> 441.1Smrg 451.1Smrg#define _SPARC_BUS_DMA_PRIVATE 461.5Sdyoung#include <sys/bus.h> 471.1Smrg#include <machine/autoconf.h> 481.1Smrg#include <machine/openfirm.h> 491.1Smrg 501.1Smrg#include <dev/pci/pcivar.h> 511.1Smrg 521.1Smrg#include <sparc64/dev/iommureg.h> 531.2Smrg#include <sparc64/dev/iommuvar.h> 541.2Smrg#include <sparc64/dev/pyrovar.h> 551.2Smrg#include <dev/ebus/ebusreg.h> 561.2Smrg#include <dev/ebus/ebusvar.h> 571.1Smrg#include <sparc64/dev/ebusvar.h> 581.1Smrg 591.4Schristosint ebus_mainbus_match(device_t, cfdata_t, void *); 601.4Schristosvoid ebus_mainbus_attach(device_t, device_t, void *); 611.1Smrg 621.4SchristosCFATTACH_DECL_NEW(ebus_mainbus, sizeof(struct ebus_softc), 631.2Smrg ebus_mainbus_match, ebus_mainbus_attach, NULL, NULL); 641.1Smrg 651.7Smrgstatic int ebus_mainbus_bus_map(bus_space_tag_t, bus_addr_t, bus_size_t, int, 661.7Smrg vaddr_t, bus_space_handle_t *); 671.7Smrgstatic void *ebus_mainbus_intr_establish(bus_space_tag_t, int, int, 681.2Smrg int (*)(void *), void *, void (*)(void)); 691.7Smrgstatic bus_space_tag_t ebus_mainbus_alloc_bus_tag(struct ebus_softc *, 701.7Smrg bus_space_tag_t, int); 711.7Smrg#ifdef SUN4V 721.7Smrgstatic void ebus_mainbus_intr_ack(struct intrhand *); 731.7Smrg#endif 741.1Smrg 751.1Smrgint 761.10Schsebus_mainbus_match(device_t parent, cfdata_t cf, void *aux) 771.1Smrg{ 781.1Smrg struct mainbus_attach_args *ma = aux; 791.1Smrg 801.1Smrg if (strcmp(ma->ma_name, "ebus") == 0) 811.1Smrg return (1); 821.1Smrg return (0); 831.1Smrg} 841.1Smrg 851.1Smrgvoid 861.10Schsebus_mainbus_attach(device_t parent, device_t self, void *aux) 871.1Smrg{ 881.4Schristos struct ebus_softc *sc = device_private(self); 891.1Smrg struct mainbus_attach_args *ma = aux; 901.1Smrg struct ebus_attach_args eba; 911.1Smrg struct ebus_interrupt_map_mask *immp; 921.1Smrg int node, nmapmask, error; 931.1Smrg struct pyro_softc *psc; 941.1Smrg int i; 951.1Smrg 961.4Schristos sc->sc_dev = self; 971.1Smrg sc->sc_node = node = ma->ma_node; 981.1Smrg sc->sc_ign = INTIGN((ma->ma_upaid) << INTMAP_IGN_SHIFT); 991.1Smrg 1001.1Smrg if (CPU_ISSUN4U) { 1011.1Smrg printf(": ign %x", sc->sc_ign); 1021.2Smrg /* XXX */ 1031.2Smrg extern struct cfdriver pyro_cd; 1041.1Smrg 1051.1Smrg for (i = 0; i < pyro_cd.cd_ndevs; i++) { 1061.2Smrg device_t dt = pyro_cd.cd_devs[i]; 1071.6Smrg psc = device_private(dt); 1081.1Smrg if (psc && psc->sc_ign == sc->sc_ign) { 1091.2Smrg sc->sc_bust = psc->sc_bustag; 1101.1Smrg sc->sc_csr = psc->sc_csr; 1111.1Smrg sc->sc_csrh = psc->sc_csrh; 1121.1Smrg break; 1131.1Smrg } 1141.1Smrg } 1151.1Smrg 1161.1Smrg if (sc->sc_csr == 0) { 1171.1Smrg printf(": can't find matching host bridge leaf\n"); 1181.1Smrg return; 1191.1Smrg } 1201.1Smrg } 1211.1Smrg 1221.1Smrg printf("\n"); 1231.1Smrg 1241.7Smrg sc->sc_memtag = ebus_mainbus_alloc_bus_tag(sc, ma->ma_bustag, 1251.7Smrg PCI_MEMORY_BUS_SPACE); 1261.7Smrg sc->sc_iotag = ebus_mainbus_alloc_bus_tag(sc, ma->ma_bustag, 1271.7Smrg PCI_IO_BUS_SPACE); 1281.2Smrg sc->sc_childbustag = sc->sc_memtag; 1291.2Smrg sc->sc_dmatag = ma->ma_dmatag; 1301.1Smrg 1311.1Smrg /* 1321.1Smrg * fill in our softc with information from the prom 1331.1Smrg */ 1341.1Smrg sc->sc_intmap = NULL; 1351.1Smrg sc->sc_range = NULL; 1361.2Smrg error = prom_getprop(node, "interrupt-map", 1371.1Smrg sizeof(struct ebus_interrupt_map), 1381.1Smrg &sc->sc_nintmap, (void **)&sc->sc_intmap); 1391.1Smrg switch (error) { 1401.1Smrg case 0: 1411.1Smrg immp = &sc->sc_intmapmask; 1421.7Smrg nmapmask = 1; 1431.2Smrg error = prom_getprop(node, "interrupt-map-mask", 1441.1Smrg sizeof(struct ebus_interrupt_map_mask), &nmapmask, 1451.1Smrg (void **)&immp); 1461.1Smrg if (error) 1471.7Smrg panic("could not get ebus interrupt-map-mask: error %d", 1481.7Smrg error); 1491.1Smrg if (nmapmask != 1) 1501.1Smrg panic("ebus interrupt-map-mask is broken"); 1511.1Smrg break; 1521.1Smrg case ENOENT: 1531.1Smrg break; 1541.1Smrg default: 1551.1Smrg panic("ebus interrupt-map: error %d", error); 1561.1Smrg break; 1571.1Smrg } 1581.1Smrg 1591.2Smrg error = prom_getprop(node, "ranges", sizeof(struct ebus_mainbus_ranges), 1601.1Smrg &sc->sc_nrange, (void **)&sc->sc_range); 1611.1Smrg if (error) 1621.1Smrg panic("ebus ranges: error %d", error); 1631.1Smrg 1641.1Smrg /* 1651.1Smrg * now attach all our children 1661.1Smrg */ 1671.1Smrg DPRINTF(EDB_CHILD, ("ebus node %08x, searching children...\n", node)); 1681.1Smrg for (node = firstchild(node); node; node = nextsibling(node)) { 1691.1Smrg if (ebus_setup_attach_args(sc, node, &eba) != 0) { 1701.1Smrg DPRINTF(EDB_CHILD, 1711.1Smrg ("ebus_mainbus_attach: %s: incomplete\n", 1721.2Smrg prom_getpropstring(node, "name"))); 1731.1Smrg continue; 1741.1Smrg } else { 1751.1Smrg DPRINTF(EDB_CHILD, ("- found child `%s', attaching\n", 1761.1Smrg eba.ea_name)); 1771.1Smrg (void)config_found(self, &eba, ebus_print); 1781.1Smrg } 1791.1Smrg ebus_destroy_attach_args(&eba); 1801.1Smrg } 1811.1Smrg} 1821.1Smrg 1831.7Smrgstatic bus_space_tag_t 1841.7Smrgebus_mainbus_alloc_bus_tag(struct ebus_softc *sc, 1851.7Smrg bus_space_tag_t parent, 1861.7Smrg int type) 1871.1Smrg{ 1881.1Smrg struct sparc_bus_space_tag *bt; 1891.1Smrg 1901.1Smrg bt = malloc(sizeof(*bt), M_DEVBUF, M_NOWAIT | M_ZERO); 1911.1Smrg if (bt == NULL) 1921.1Smrg panic("could not allocate ebus bus tag"); 1931.1Smrg 1941.1Smrg bt->cookie = sc; 1951.1Smrg bt->parent = parent; 1961.2Smrg bt->type = type; 1971.1Smrg bt->sparc_bus_map = ebus_mainbus_bus_map; 1981.2Smrg bt->sparc_bus_mmap = ebus_bus_mmap; 1991.1Smrg bt->sparc_intr_establish = ebus_mainbus_intr_establish; 2001.1Smrg 2011.1Smrg return (bt); 2021.1Smrg} 2031.1Smrg 2041.1Smrgint 2051.2Smrgebus_mainbus_bus_map(bus_space_tag_t t, bus_addr_t offset, bus_size_t size, 2061.2Smrg int flags, vaddr_t va, bus_space_handle_t *hp) 2071.1Smrg{ 2081.1Smrg struct ebus_softc *sc = t->cookie; 2091.1Smrg struct ebus_mainbus_ranges *range; 2101.1Smrg bus_addr_t hi, lo; 2111.11Smartin int i; 2121.11Smartin#if 0 2131.11Smartin int ss; 2141.11Smartin#endif 2151.1Smrg 2161.1Smrg DPRINTF(EDB_BUSMAP, 2171.1Smrg ("\n_ebus_mainbus_bus_map: off %016llx sz %x flags %d", 2181.1Smrg (unsigned long long)offset, (int)size, (int)flags)); 2191.1Smrg 2201.1Smrg if (t->parent == 0 || t->parent->sparc_bus_map == 0) { 2211.1Smrg printf("\n_ebus_mainbus_bus_map: invalid parent"); 2221.1Smrg return (EINVAL); 2231.1Smrg } 2241.1Smrg 2251.1Smrg t = t->parent; 2261.1Smrg 2271.1Smrg hi = offset >> 32UL; 2281.1Smrg lo = offset & 0xffffffff; 2291.1Smrg range = (struct ebus_mainbus_ranges *)sc->sc_range; 2301.1Smrg 2311.1Smrg DPRINTF(EDB_BUSMAP, (" (hi %08x lo %08x)", (u_int)hi, (u_int)lo)); 2321.1Smrg for (i = 0; i < sc->sc_nrange; i++) { 2331.1Smrg bus_addr_t addr; 2341.1Smrg 2351.1Smrg if (hi != range[i].child_hi) 2361.1Smrg continue; 2371.1Smrg if (lo < range[i].child_lo || 2381.1Smrg (lo + size) > (range[i].child_lo + range[i].size)) 2391.1Smrg continue; 2401.1Smrg 2411.2Smrg#if 0 2421.2Smrg /* Isolate address space and find the right tag */ 2431.2Smrg ss = (range[i].phys_hi>>24)&3; 2441.2Smrg switch (ss) { 2451.2Smrg case 1: /* I/O space */ 2461.2Smrg t = sc->sc_iotag; 2471.2Smrg break; 2481.2Smrg case 2: /* Memory space */ 2491.2Smrg t = sc->sc_memtag; 2501.2Smrg break; 2511.2Smrg case 0: /* Config space */ 2521.2Smrg case 3: /* 64-bit Memory space */ 2531.2Smrg default: /* WTF? */ 2541.2Smrg /* We don't handle these */ 2551.2Smrg panic("ebus_mainbus_bus_map: illegal space %x", ss); 2561.2Smrg break; 2571.2Smrg } 2581.2Smrg#endif 2591.2Smrg 2601.1Smrg addr = ((bus_addr_t)range[i].phys_hi << 32UL) | 2611.1Smrg range[i].phys_lo; 2621.1Smrg addr += lo; 2631.1Smrg DPRINTF(EDB_BUSMAP, 2641.1Smrg ("\n_ebus_mainbus_bus_map: paddr offset %qx addr %qx\n", 2651.1Smrg (unsigned long long)offset, (unsigned long long)addr)); 2661.2Smrg return (bus_space_map(t, addr, size, flags, hp)); 2671.1Smrg } 2681.1Smrg DPRINTF(EDB_BUSMAP, (": FAILED\n")); 2691.1Smrg return (EINVAL); 2701.1Smrg} 2711.1Smrg 2721.7Smrgstatic void * 2731.2Smrgebus_mainbus_intr_establish(bus_space_tag_t t, int ihandle, int level, 2741.2Smrg int (*handler)(void *), void *arg, void (*fastvec)(void) /* ignored */) 2751.1Smrg{ 2761.1Smrg struct ebus_softc *sc = t->cookie; 2771.1Smrg struct intrhand *ih = NULL; 2781.1Smrg volatile u_int64_t *intrmapptr = NULL, *intrclrptr = NULL; 2791.2Smrg u_int64_t *imap, *iclr; 2801.1Smrg int ino; 2811.1Smrg 2821.1Smrg#ifdef SUN4V 2831.1Smrg if (CPU_ISSUN4V) { 2841.1Smrg struct upa_reg reg; 2851.1Smrg u_int64_t devhandle, devino = INTINO(ihandle); 2861.1Smrg u_int64_t sysino; 2871.1Smrg int node = -1; 2881.1Smrg int i, err; 2891.1Smrg 2901.1Smrg for (i = 0; i < sc->sc_nintmap; i++) { 2911.1Smrg if (sc->sc_intmap[i].cintr == ihandle) { 2921.1Smrg node = sc->sc_intmap[i].cnode; 2931.1Smrg break; 2941.1Smrg } 2951.1Smrg } 2961.1Smrg if (node == -1) 2971.1Smrg return (NULL); 2981.1Smrg 2991.1Smrg if (OF_getprop(node, "reg", ®, sizeof(reg)) != sizeof(reg)) 3001.1Smrg return (NULL); 3011.1Smrg devhandle = (reg.ur_paddr >> 32) & 0x0fffffff; 3021.1Smrg 3031.1Smrg err = hv_intr_devino_to_sysino(devhandle, devino, &sysino); 3041.1Smrg if (err != H_EOK) 3051.1Smrg return (NULL); 3061.1Smrg 3071.1Smrg KASSERT(sysino == INTVEC(sysino)); 3081.1Smrg ih = bus_intr_allocate(t0, handler, arg, sysino, level, 3091.1Smrg NULL, NULL, what); 3101.1Smrg if (ih == NULL) 3111.1Smrg return (NULL); 3121.1Smrg 3131.1Smrg intr_establish(ih->ih_pil, ih); 3141.1Smrg ih->ih_ack = ebus_mainbus_intr_ack; 3151.1Smrg 3161.1Smrg err = hv_intr_settarget(sysino, cpus->ci_upaid); 3171.1Smrg if (err != H_EOK) 3181.1Smrg return (NULL); 3191.1Smrg 3201.1Smrg /* Clear pending interrupts. */ 3211.1Smrg err = hv_intr_setstate(sysino, INTR_IDLE); 3221.1Smrg if (err != H_EOK) 3231.1Smrg return (NULL); 3241.1Smrg 3251.1Smrg err = hv_intr_setenabled(sysino, INTR_ENABLED); 3261.1Smrg if (err != H_EOK) 3271.1Smrg return (NULL); 3281.1Smrg 3291.1Smrg return (ih); 3301.1Smrg } 3311.1Smrg#endif 3321.1Smrg 3331.1Smrg ihandle |= sc->sc_ign; 3341.1Smrg ino = INTINO(ihandle); 3351.1Smrg 3361.2Smrg /* XXX */ 3371.2Smrg imap = (uint64_t *)((uintptr_t)bus_space_vaddr(sc->sc_bustag, sc->sc_csrh) + 0x1000); 3381.2Smrg iclr = (uint64_t *)((uintptr_t)bus_space_vaddr(sc->sc_bustag, sc->sc_csrh) + 0x1400); 3391.2Smrg intrmapptr = &imap[ino]; 3401.2Smrg intrclrptr = &iclr[ino]; 3411.2Smrg ino |= INTVEC(ihandle); 3421.1Smrg 3431.2Smrg ih = malloc(sizeof *ih, M_DEVBUF, M_NOWAIT); 3441.1Smrg if (ih == NULL) 3451.1Smrg return (NULL); 3461.1Smrg 3471.2Smrg /* Register the map and clear intr registers */ 3481.2Smrg ih->ih_map = intrmapptr; 3491.2Smrg ih->ih_clr = intrclrptr; 3501.2Smrg 3511.8Smrg ih->ih_ivec = ihandle; 3521.2Smrg ih->ih_fun = handler; 3531.2Smrg ih->ih_arg = arg; 3541.2Smrg ih->ih_pil = level; 3551.2Smrg ih->ih_number = ino; 3561.7Smrg ih->ih_pending = 0; 3571.2Smrg 3581.2Smrg intr_establish(ih->ih_pil, level != IPL_VM, ih); 3591.1Smrg 3601.1Smrg if (intrmapptr != NULL) { 3611.2Smrg u_int64_t imapval; 3621.1Smrg 3631.2Smrg imapval = *intrmapptr; 3641.2Smrg imapval |= (1LL << 6); 3651.2Smrg imapval |= INTMAP_V; 3661.2Smrg *intrmapptr = imapval; 3671.2Smrg imapval = *intrmapptr; 3681.2Smrg ih->ih_number |= imapval & INTMAP_INR; 3691.1Smrg } 3701.1Smrg 3711.1Smrg return (ih); 3721.1Smrg} 3731.1Smrg 3741.1Smrg#ifdef SUN4V 3751.1Smrg 3761.7Smrgstatic void 3771.1Smrgebus_mainbus_intr_ack(struct intrhand *ih) 3781.1Smrg{ 3791.1Smrg hv_intr_setstate(ih->ih_number, INTR_IDLE); 3801.1Smrg} 3811.1Smrg 3821.1Smrg#endif 383