ebus_mainbus.c revision 1.21 
1/*	$NetBSD: ebus_mainbus.c,v 1.21 2021/08/07 16:19:05 thorpej Exp $	*/
2/*	$OpenBSD: ebus_mainbus.c,v 1.7 2010/11/11 17:58:23 miod Exp $	*/
3
4/*
5 * Copyright (c) 2007 Mark Kettenis
6 *
7 * Permission to use, copy, modify, and distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 */
19
20#include <sys/cdefs.h>
21__KERNEL_RCSID(0, "$NetBSD: ebus_mainbus.c,v 1.21 2021/08/07 16:19:05 thorpej Exp $");
22
23#ifdef DEBUG
24#define	EDB_PROM	0x01
25#define EDB_CHILD	0x02
26#define	EDB_INTRMAP	0x04
27#define EDB_BUSMAP	0x08
28#define EDB_BUSDMA	0x10
29#define EDB_INTR	0x20
30extern int ebus_debug;
31#define DPRINTF(l, s)   do { if (ebus_debug & l) printf s; } while (0)
32#else
33#define DPRINTF(l, s)
34#endif
35
36#include <sys/param.h>
37#include <sys/conf.h>
38#include <sys/device.h>
39#include <sys/errno.h>
40#include <sys/extent.h>
41#include <sys/kmem.h>
42#include <sys/systm.h>
43#include <sys/time.h>
44
45#define _SPARC_BUS_DMA_PRIVATE
46#include <sys/bus.h>
47#include <machine/autoconf.h>
48#include <machine/openfirm.h>
49
50#include <dev/pci/pcivar.h>
51
52#include <sparc64/dev/iommureg.h>
53#include <sparc64/dev/iommuvar.h>
54#include <sparc64/dev/pyrovar.h>
55#include <dev/ebus/ebusreg.h>
56#include <dev/ebus/ebusvar.h>
57#include <sparc64/dev/ebusvar.h>
58
59#include "ioconf.h"
60
61int	ebus_mainbus_match(device_t, cfdata_t, void *);
62void	ebus_mainbus_attach(device_t, device_t, void *);
63
64CFATTACH_DECL_NEW(ebus_mainbus, sizeof(struct ebus_softc),
65    ebus_mainbus_match, ebus_mainbus_attach, NULL, NULL);
66
67static int ebus_mainbus_bus_map(bus_space_tag_t, bus_addr_t, bus_size_t, int,
68	vaddr_t, bus_space_handle_t *);
69static void *ebus_mainbus_intr_establish(bus_space_tag_t, int, int,
70	int (*)(void *), void *, void (*)(void));
71static bus_space_tag_t ebus_mainbus_alloc_bus_tag(struct ebus_softc *,
72	bus_space_tag_t, int);
73#ifdef SUN4V
74#if 0
75XXX
76static void ebus_mainbus_intr_ack(struct intrhand *);
77#endif
78#endif
79int
80ebus_mainbus_match(device_t parent, cfdata_t cf, void *aux)
81{
82	struct mainbus_attach_args *ma = aux;
83
84	if (strcmp(ma->ma_name, "ebus") == 0)
85		return (1);
86	return (0);
87}
88
89void
90ebus_mainbus_attach(device_t parent, device_t self, void *aux)
91{
92	struct ebus_softc *sc = device_private(self);
93	struct mainbus_attach_args *ma = aux;
94	struct ebus_attach_args eba;
95	struct ebus_interrupt_map_mask *immp;
96	int node, nmapmask, error;
97	struct pyro_softc *psc;
98	int i, j;
99
100	sc->sc_dev = self;
101
102	printf("\n");
103
104	sc->sc_memtag = ebus_mainbus_alloc_bus_tag(sc, ma->ma_bustag,
105						   PCI_MEMORY_BUS_SPACE);
106	sc->sc_iotag = ebus_mainbus_alloc_bus_tag(sc, ma->ma_bustag,
107						  PCI_IO_BUS_SPACE);
108	sc->sc_childbustag = sc->sc_memtag;
109	sc->sc_dmatag = ma->ma_dmatag;
110
111	sc->sc_node = node = ma->ma_node;
112
113	/*
114	 * fill in our softc with information from the prom
115	 */
116	sc->sc_intmap = NULL;
117	sc->sc_range = NULL;
118	error = prom_getprop(node, "interrupt-map",
119			sizeof(struct ebus_interrupt_map),
120			&sc->sc_nintmap, (void **)&sc->sc_intmap);
121	switch (error) {
122	case 0:
123		immp = &sc->sc_intmapmask;
124		nmapmask = 1;
125		error = prom_getprop(node, "interrupt-map-mask",
126			    sizeof(struct ebus_interrupt_map_mask), &nmapmask,
127			    (void **)&immp);
128		if (error)
129			panic("could not get ebus interrupt-map-mask: error %d",
130			      error);
131		if (nmapmask != 1)
132			panic("ebus interrupt-map-mask is broken");
133		break;
134	case ENOENT:
135		break;
136	default:
137		panic("ebus interrupt-map: error %d", error);
138		break;
139	}
140
141	/*
142	 * Ebus interrupts may be connected to any of the PCI Express
143	 * leafs.  Here we add the appropriate IGN to the interrupt
144	 * mappings such that we can use it to distingish between
145	 * interrupts connected to PCIE-A and PCIE-B.
146	 */
147	for (i = 0; i < sc->sc_nintmap; i++) {
148		for (j = 0; j < pyro_cd.cd_ndevs; j++) {
149			device_t dt = device_lookup(&pyro_cd, j);
150			psc = device_private(dt);
151			if (psc && psc->sc_node == sc->sc_intmap[i].cnode) {
152				sc->sc_intmap[i].cintr |= psc->sc_ign;
153				break;
154			}
155		}
156	}
157
158	error = prom_getprop(node, "ranges", sizeof(struct ebus_mainbus_ranges),
159	    &sc->sc_nrange, (void **)&sc->sc_range);
160	if (error)
161		panic("ebus ranges: error %d", error);
162
163	/*
164	 * now attach all our children
165	 */
166	DPRINTF(EDB_CHILD, ("ebus node %08x, searching children...\n", node));
167	for (node = firstchild(node); node; node = nextsibling(node)) {
168		if (ebus_setup_attach_args(sc, node, &eba) != 0) {
169			DPRINTF(EDB_CHILD,
170			    ("ebus_mainbus_attach: %s: incomplete\n",
171			    prom_getpropstring(node, "name")));
172			continue;
173		} else {
174			DPRINTF(EDB_CHILD, ("- found child `%s', attaching\n",
175			    eba.ea_name));
176			(void)config_found(self, &eba, ebus_print,
177			    CFARGS(.devhandle = prom_node_to_devhandle(node)));
178		}
179		ebus_destroy_attach_args(&eba);
180	}
181}
182
183static bus_space_tag_t
184ebus_mainbus_alloc_bus_tag(struct ebus_softc *sc,
185			   bus_space_tag_t parent,
186			   int type)
187{
188	struct sparc_bus_space_tag *bt;
189
190	bt = kmem_zalloc(sizeof(*bt), KM_SLEEP);
191	bt->cookie = sc;
192	bt->parent = parent;
193	bt->type = type;
194	bt->sparc_bus_map = ebus_mainbus_bus_map;
195	bt->sparc_bus_mmap = ebus_bus_mmap;
196	bt->sparc_intr_establish = ebus_mainbus_intr_establish;
197
198	return (bt);
199}
200
201int
202ebus_mainbus_bus_map(bus_space_tag_t t, bus_addr_t offset, bus_size_t size,
203	int flags, vaddr_t va, bus_space_handle_t *hp)
204{
205	struct ebus_softc *sc = t->cookie;
206	struct ebus_mainbus_ranges *range;
207	bus_addr_t hi, lo;
208	int i;
209#if 0
210	int ss;
211#endif
212
213	DPRINTF(EDB_BUSMAP,
214	    ("\n_ebus_mainbus_bus_map: off %016llx sz %x flags %d",
215	    (unsigned long long)offset, (int)size, (int)flags));
216
217	if (t->parent == 0 || t->parent->sparc_bus_map == 0) {
218		printf("\n_ebus_mainbus_bus_map: invalid parent");
219		return (EINVAL);
220	}
221
222	t = t->parent;
223
224	hi = offset >> 32UL;
225	lo = offset & 0xffffffff;
226	range = (struct ebus_mainbus_ranges *)sc->sc_range;
227
228	DPRINTF(EDB_BUSMAP, (" (hi %08x lo %08x)", (u_int)hi, (u_int)lo));
229	for (i = 0; i < sc->sc_nrange; i++) {
230		bus_addr_t addr;
231
232		if (hi != range[i].child_hi)
233			continue;
234		if (lo < range[i].child_lo ||
235		    (lo + size) > (range[i].child_lo + range[i].size))
236			continue;
237
238#if 0
239		/* Isolate address space and find the right tag */
240		ss = (range[i].phys_hi>>24)&3;
241		switch (ss) {
242		case 1:	/* I/O space */
243			t = sc->sc_iotag;
244			break;
245		case 2:	/* Memory space */
246			t = sc->sc_memtag;
247			break;
248		case 0:	/* Config space */
249		case 3:	/* 64-bit Memory space */
250		default: /* WTF? */
251			/* We don't handle these */
252			panic("ebus_mainbus_bus_map: illegal space %x", ss);
253			break;
254		}
255#endif
256
257		addr = ((bus_addr_t)range[i].phys_hi << 32UL) |
258				    range[i].phys_lo;
259		addr += lo;
260		DPRINTF(EDB_BUSMAP,
261		    ("\n_ebus_mainbus_bus_map: paddr offset %qx addr %qx\n",
262		    (unsigned long long)offset, (unsigned long long)addr));
263		return (bus_space_map(t, addr, size, flags, hp));
264	}
265	DPRINTF(EDB_BUSMAP, (": FAILED\n"));
266	return (EINVAL);
267}
268
269static void *
270ebus_mainbus_intr_establish(bus_space_tag_t t, int ihandle, int level,
271	int (*handler)(void *), void *arg, void (*fastvec)(void) /* ignored */)
272{
273	struct intrhand *ih = NULL;
274	volatile u_int64_t *intrmapptr = NULL, *intrclrptr = NULL;
275	u_int64_t *imap, *iclr;
276	int ino;
277
278#if 0
279XXX
280	if (CPU_ISSUN4V) {
281		struct upa_reg reg;
282		u_int64_t devhandle, devino = INTINO(ihandle);
283		u_int64_t sysino;
284		int node = -1;
285		int i, err;
286
287		for (i = 0; i < sc->sc_nintmap; i++) {
288			if (sc->sc_intmap[i].cintr == ihandle) {
289				node = sc->sc_intmap[i].cnode;
290				break;
291			}
292		}
293		if (node == -1)
294			return (NULL);
295
296		if (OF_getprop(node, "reg", &reg, sizeof(reg)) != sizeof(reg))
297			return (NULL);
298		devhandle = (reg.ur_paddr >> 32) & 0x0fffffff;
299
300		err = hv_intr_devino_to_sysino(devhandle, devino, &sysino);
301		if (err != H_EOK)
302			return (NULL);
303
304		KASSERT(sysino == INTVEC(sysino));
305		ih = bus_intr_allocate(t0, handler, arg, sysino, level,
306		    NULL, NULL, what);
307		if (ih == NULL)
308			return (NULL);
309
310		intr_establish(ih->ih_pil, ih);
311		ih->ih_ack = ebus_mainbus_intr_ack;
312
313		err = hv_intr_settarget(sysino, cpus->ci_upaid);
314		if (err != H_EOK)
315			return (NULL);
316
317		/* Clear pending interrupts. */
318		err = hv_intr_setstate(sysino, INTR_IDLE);
319		if (err != H_EOK)
320			return (NULL);
321
322		err = hv_intr_setenabled(sysino, INTR_ENABLED);
323		if (err != H_EOK)
324			return (NULL);
325
326		return (ih);
327	}
328#endif
329
330	ino = INTINO(ihandle);
331
332	struct pyro_softc *psc = NULL;
333	int i;
334
335	for (i = 0; i < pyro_cd.cd_ndevs; i++) {
336		device_t dt = device_lookup(&pyro_cd, i);
337		psc = device_private(dt);
338		if (psc && psc->sc_ign == INTIGN(ihandle)) {
339			break;
340		}
341	}
342	if (psc == NULL)
343		return (NULL);
344
345	imap = (uint64_t *)((uintptr_t)bus_space_vaddr(psc->sc_bustag, psc->sc_csrh) + 0x1000);
346	iclr = (uint64_t *)((uintptr_t)bus_space_vaddr(psc->sc_bustag, psc->sc_csrh) + 0x1400);
347	intrmapptr = &imap[ino];
348	intrclrptr = &iclr[ino];
349	ino |= INTVEC(ihandle);
350
351	ih = intrhand_alloc();
352
353	/* Register the map and clear intr registers */
354	ih->ih_map = intrmapptr;
355	ih->ih_clr = intrclrptr;
356
357	ih->ih_ivec = ihandle;
358	ih->ih_fun = handler;
359	ih->ih_arg = arg;
360	ih->ih_pil = level;
361	ih->ih_number = ino;
362	ih->ih_pending = 0;
363
364	intr_establish(ih->ih_pil, level != IPL_VM, ih);
365
366	if (intrmapptr != NULL) {
367		u_int64_t imapval;
368
369		imapval = *intrmapptr;
370		imapval |= (1LL << 6);
371		imapval |= INTMAP_V;
372		*intrmapptr = imapval;
373		imapval = *intrmapptr;
374		ih->ih_number |= imapval & INTMAP_INR;
375	}
376
377	return (ih);
378}
379
380#ifdef SUN4V
381#if 0
382XXX
383static void
384ebus_mainbus_intr_ack(struct intrhand *ih)
385{
386	hv_intr_setstate(ih->ih_number, INTR_IDLE);
387}
388#endif
389#endif
390