ffb.c revision 1.38.2.1
1 /* $NetBSD: ffb.c,v 1.38.2.1 2011/06/06 09:06:49 jruoho Exp $ */ 2 /* $OpenBSD: creator.c,v 1.20 2002/07/30 19:48:15 jason Exp $ */ 3 4 /* 5 * Copyright (c) 2002 Jason L. Wright (jason (at) thought.net) 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Jason L. Wright 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 25 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 26 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 27 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 30 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 31 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32 * POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: ffb.c,v 1.38.2.1 2011/06/06 09:06:49 jruoho Exp $"); 37 38 #include <sys/types.h> 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/kernel.h> 42 #include <sys/device.h> 43 #include <sys/conf.h> 44 #include <sys/ioctl.h> 45 #include <sys/malloc.h> 46 #include <sys/mman.h> 47 48 #include <machine/bus.h> 49 #include <machine/autoconf.h> 50 #include <machine/openfirm.h> 51 #include <machine/vmparam.h> 52 53 #include <dev/wscons/wsconsio.h> 54 #include <dev/sun/fbio.h> 55 #include <dev/sun/fbvar.h> 56 57 #include <dev/wsfont/wsfont.h> 58 #include <dev/wscons/wsdisplay_vconsvar.h> 59 60 #include <dev/i2c/i2cvar.h> 61 #include <dev/i2c/i2c_bitbang.h> 62 #include <dev/i2c/ddcvar.h> 63 64 #include <sparc64/dev/ffbreg.h> 65 #include <sparc64/dev/ffbvar.h> 66 67 #include "opt_wsdisplay_compat.h" 68 #include "opt_ffb.h" 69 70 #ifndef WS_DEFAULT_BG 71 /* Sun -> background should be white */ 72 #define WS_DEFAULT_BG 0xf 73 #endif 74 75 #ifdef FFB_SYNC 76 #define SYNC ffb_ras_wait(sc) 77 #else 78 #define SYNC 79 #endif 80 81 /* Debugging */ 82 #if !defined FFB_DEBUG 83 #define FFB_DEBUG 0 84 #endif 85 #define DPRINTF(x) if (ffb_debug) printf x 86 /* Patchable */ 87 extern int ffb_debug; 88 #if FFB_DEBUG > 0 89 int ffb_debug = 1; 90 #else 91 int ffb_debug = 0; 92 #endif 93 94 extern struct cfdriver ffb_cd; 95 96 struct wsscreen_descr ffb_stdscreen = { 97 "sunffb", 98 0, 0, /* will be filled in -- XXX shouldn't, it's global. */ 99 0, 100 0, 0, 101 WSSCREEN_REVERSE | WSSCREEN_WSCOLORS, 102 NULL /* modecookie */ 103 }; 104 105 const struct wsscreen_descr *ffb_scrlist[] = { 106 &ffb_stdscreen, 107 /* XXX other formats? */ 108 }; 109 110 struct wsscreen_list ffb_screenlist = { 111 sizeof(ffb_scrlist) / sizeof(struct wsscreen_descr *), 112 ffb_scrlist 113 }; 114 115 static struct vcons_screen ffb_console_screen; 116 117 int ffb_ioctl(void *, void *, u_long, void *, int, struct lwp *); 118 static int ffb_blank(struct ffb_softc *, u_long, u_int *); 119 paddr_t ffb_mmap(void *, void *, off_t, int); 120 void ffb_ras_fifo_wait(struct ffb_softc *, int); 121 void ffb_ras_wait(struct ffb_softc *); 122 void ffb_ras_init(struct ffb_softc *); 123 void ffb_ras_copyrows(void *, int, int, int); 124 void ffb_ras_erasecols(void *, int, int, int, long int); 125 void ffb_ras_eraserows(void *, int, int, long int); 126 void ffb_ras_do_cursor(struct rasops_info *); 127 void ffb_ras_fill(struct ffb_softc *); 128 static void ffb_ras_setfg(struct ffb_softc *, int32_t); 129 static void ffb_ras_setbg(struct ffb_softc *, int32_t); 130 131 void ffb_clearscreen(struct ffb_softc *); 132 int ffb_load_font(void *, void *, struct wsdisplay_font *); 133 void ffb_init_screen(void *, struct vcons_screen *, int, 134 long *); 135 int ffb_allocattr(void *, int, int, int, long *); 136 void ffb_putchar(void *, int, int, u_int, long); 137 void ffb_cursor(void *, int, int, int); 138 139 /* frame buffer generic driver */ 140 static void ffbfb_unblank(device_t); 141 dev_type_open(ffbfb_open); 142 dev_type_close(ffbfb_close); 143 dev_type_ioctl(ffbfb_ioctl); 144 dev_type_mmap(ffbfb_mmap); 145 146 static struct fbdriver ffb_fbdriver = { 147 ffbfb_unblank, ffbfb_open, ffbfb_close, ffbfb_ioctl, nopoll, 148 ffbfb_mmap, nokqfilter 149 }; 150 151 struct wsdisplay_accessops ffb_accessops = { 152 .ioctl = ffb_ioctl, 153 .mmap = ffb_mmap, 154 }; 155 156 /* I2C glue */ 157 static int ffb_i2c_acquire_bus(void *, int); 158 static void ffb_i2c_release_bus(void *, int); 159 static int ffb_i2c_send_start(void *, int); 160 static int ffb_i2c_send_stop(void *, int); 161 static int ffb_i2c_initiate_xfer(void *, i2c_addr_t, int); 162 static int ffb_i2c_read_byte(void *, uint8_t *, int); 163 static int ffb_i2c_write_byte(void *, uint8_t, int); 164 165 /* I2C bitbang glue */ 166 static void ffb_i2cbb_set_bits(void *, uint32_t); 167 static void ffb_i2cbb_set_dir(void *, uint32_t); 168 static uint32_t ffb_i2cbb_read(void *); 169 170 static const struct i2c_bitbang_ops ffb_i2cbb_ops = { 171 ffb_i2cbb_set_bits, 172 ffb_i2cbb_set_dir, 173 ffb_i2cbb_read, 174 { 175 FFB_DAC_CFG_MPDATA_SDA, 176 FFB_DAC_CFG_MPDATA_SCL, 177 0, 178 0 179 } 180 }; 181 182 void ffb_attach_i2c(struct ffb_softc *); 183 184 /* Video mode setting */ 185 int ffb_tgc_disable(struct ffb_softc *); 186 void ffb_get_pclk(int, uint32_t *, int *); 187 int ffb_set_vmode(struct ffb_softc *, struct videomode *, int, int *, int *); 188 189 190 void 191 ffb_attach(struct ffb_softc *sc) 192 { 193 struct wsemuldisplaydev_attach_args waa; 194 struct rasops_info *ri; 195 long defattr; 196 const char *model, *out_dev; 197 int btype; 198 uint32_t dac; 199 int maxrow, maxcol; 200 u_int blank = WSDISPLAYIO_VIDEO_ON; 201 char buf[6+1]; 202 int i, try_edid; 203 204 printf(":"); 205 206 if (sc->sc_type == FFB_CREATOR) { 207 btype = prom_getpropint(sc->sc_node, "board_type", 0); 208 if ((btype & 7) == 3) 209 printf(" Creator3D"); 210 else 211 printf(" Creator"); 212 } else { 213 printf(" Elite3D"); 214 btype = 0; 215 } 216 217 model = prom_getpropstring(sc->sc_node, "model"); 218 if (model == NULL || strlen(model) == 0) 219 model = "unknown"; 220 221 sc->sc_depth = 24; 222 sc->sc_linebytes = 8192; 223 /* We might alter these during EDID mode setting */ 224 sc->sc_height = prom_getpropint(sc->sc_node, "height", 0); 225 sc->sc_width = prom_getpropint(sc->sc_node, "width", 0); 226 227 sc->sc_locked = 0; 228 sc->sc_mode = WSDISPLAYIO_MODE_EMUL; 229 230 maxcol = (prom_getoption("screen-#columns", buf, sizeof buf) == 0) 231 ? strtoul(buf, NULL, 10) 232 : 80; 233 234 maxrow = (prom_getoption("screen-#rows", buf, sizeof buf) != 0) 235 ? strtoul(buf, NULL, 10) 236 : 34; 237 238 /* collect DAC version, as Elite3D cursor enable bit is reversed */ 239 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_DEVID); 240 dac = DAC_READ(sc, FFB_DAC_VALUE); 241 sc->sc_dacrev = (dac >> 28) & 0xf; 242 243 if (sc->sc_type == FFB_AFB) { 244 sc->sc_dacrev = 10; 245 sc->sc_needredraw = 0; 246 } else { 247 /* see what kind of DAC we have */ 248 int pnum = (dac & 0x0ffff000) >> 12; 249 if (pnum == 0x236e) { 250 sc->sc_needredraw = 0; 251 } else { 252 sc->sc_needredraw = 1; 253 } 254 } 255 printf(", model %s, dac %u\n", model, sc->sc_dacrev); 256 if (sc->sc_needredraw) 257 printf("%s: found old DAC, enabling redraw on unblank\n", 258 device_xname(sc->sc_dev)); 259 260 /* Check if a console resolution "<device>:r<res>" is set. */ 261 if (sc->sc_console) { 262 out_dev = prom_getpropstring(sc->sc_node, "output_device"); 263 if (out_dev != NULL && strlen(out_dev) != 0 && 264 strstr(out_dev, ":r") != NULL) 265 try_edid = 0; 266 else 267 try_edid = 1; 268 } else 269 try_edid = 1; 270 271 ffb_attach_i2c(sc); 272 273 /* Need to set asynchronous blank during DDC write/read */ 274 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_USR_CTRL); 275 dac = DAC_READ(sc, FFB_DAC_VALUE); 276 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_USR_CTRL); 277 DAC_WRITE(sc, FFB_DAC_VALUE, dac | FFB_DAC_USR_CTRL_BLANK); 278 279 /* Some monitors don't respond first time */ 280 i = 0; 281 while (sc->sc_edid_data[1] == 0 && i++ < 3) 282 ddc_read_edid(&sc->sc_i2c, sc->sc_edid_data, EDID_DATA_LEN); 283 284 /* Remove asynchronous blank */ 285 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_USR_CTRL); 286 DAC_WRITE(sc, FFB_DAC_VALUE, dac); 287 288 if (edid_parse(&sc->sc_edid_data[0], &sc->sc_edid_info) != -1) { 289 sort_modes(sc->sc_edid_info.edid_modes, 290 &sc->sc_edid_info.edid_preferred_mode, 291 sc->sc_edid_info.edid_nmodes); 292 DPRINTF(("%s: EDID data:\n ", device_xname(sc->sc_dev))); 293 for (i = 0; i < EDID_DATA_LEN; i++) { 294 if (i && !(i % 32)) 295 DPRINTF(("\n ")); 296 if (i && !(i % 4)) 297 DPRINTF((" ")); 298 DPRINTF(("%02x", sc->sc_edid_data[i])); 299 } 300 DPRINTF(("\n")); 301 if (ffb_debug) 302 edid_print(&sc->sc_edid_info); 303 304 if (try_edid) 305 for (i = 0; i < sc->sc_edid_info.edid_nmodes; i++) { 306 if (ffb_set_vmode(sc, 307 &(sc->sc_edid_info.edid_modes[i]), btype, 308 &(sc->sc_width), &(sc->sc_height))) 309 break; 310 } 311 } else { 312 DPRINTF(("%s: No EDID data.\n", device_xname(sc->sc_dev))); 313 } 314 315 ffb_ras_init(sc); 316 317 ffb_blank(sc, WSDISPLAYIO_SVIDEO, &blank); 318 319 sc->sc_accel = ((device_cfdata(sc->sc_dev)->cf_flags & 320 FFB_CFFLAG_NOACCEL) == 0); 321 322 wsfont_init(); 323 324 vcons_init(&sc->vd, sc, &ffb_stdscreen, &ffb_accessops); 325 sc->vd.init_screen = ffb_init_screen; 326 327 /* we mess with ffb_console_screen only once */ 328 if (sc->sc_console) { 329 vcons_init_screen(&sc->vd, &ffb_console_screen, 1, &defattr); 330 SCREEN_VISIBLE((&ffb_console_screen)); 331 /* 332 * XXX we shouldn't use a global variable for the console 333 * screen 334 */ 335 sc->vd.active = &ffb_console_screen; 336 ffb_console_screen.scr_flags = VCONS_SCREEN_IS_STATIC; 337 } else { 338 if (ffb_console_screen.scr_ri.ri_rows == 0) { 339 /* do some minimal setup to avoid weirdnesses later */ 340 vcons_init_screen(&sc->vd, &ffb_console_screen, 1, &defattr); 341 } 342 } 343 ri = &ffb_console_screen.scr_ri; 344 345 ffb_stdscreen.nrows = ri->ri_rows; 346 ffb_stdscreen.ncols = ri->ri_cols; 347 ffb_stdscreen.textops = &ri->ri_ops; 348 ffb_stdscreen.capabilities = ri->ri_caps; 349 350 sc->sc_fb.fb_driver = &ffb_fbdriver; 351 sc->sc_fb.fb_type.fb_cmsize = 0; 352 sc->sc_fb.fb_type.fb_size = maxrow * sc->sc_linebytes; 353 sc->sc_fb.fb_type.fb_type = FBTYPE_CREATOR; 354 sc->sc_fb.fb_type.fb_width = sc->sc_width; 355 sc->sc_fb.fb_type.fb_depth = sc->sc_depth; 356 sc->sc_fb.fb_type.fb_height = sc->sc_height; 357 sc->sc_fb.fb_device = sc->sc_dev; 358 fb_attach(&sc->sc_fb, sc->sc_console); 359 360 ffb_clearscreen(sc); 361 362 if (sc->sc_console) { 363 wsdisplay_cnattach(&ffb_stdscreen, ri, 0, 0, defattr); 364 vcons_replay_msgbuf(&ffb_console_screen); 365 } 366 367 waa.console = sc->sc_console; 368 waa.scrdata = &ffb_screenlist; 369 waa.accessops = &ffb_accessops; 370 waa.accesscookie = &sc->vd; 371 config_found(sc->sc_dev, &waa, wsemuldisplaydevprint); 372 } 373 374 void 375 ffb_attach_i2c(struct ffb_softc *sc) 376 { 377 378 /* Fill in the i2c tag */ 379 sc->sc_i2c.ic_cookie = sc; 380 sc->sc_i2c.ic_acquire_bus = ffb_i2c_acquire_bus; 381 sc->sc_i2c.ic_release_bus = ffb_i2c_release_bus; 382 sc->sc_i2c.ic_send_start = ffb_i2c_send_start; 383 sc->sc_i2c.ic_send_stop = ffb_i2c_send_stop; 384 sc->sc_i2c.ic_initiate_xfer = ffb_i2c_initiate_xfer; 385 sc->sc_i2c.ic_read_byte = ffb_i2c_read_byte; 386 sc->sc_i2c.ic_write_byte = ffb_i2c_write_byte; 387 sc->sc_i2c.ic_exec = NULL; 388 } 389 390 int 391 ffb_ioctl(void *v, void *vs, u_long cmd, void *data, int flags, struct lwp *l) 392 { 393 struct vcons_data *vd = v; 394 struct ffb_softc *sc = vd->cookie; 395 struct wsdisplay_fbinfo *wdf; 396 struct vcons_screen *ms = vd->active; 397 398 DPRINTF(("ffb_ioctl: %s cmd _IO%s%s('%c', %lu)\n", 399 device_xname(sc->sc_dev), 400 (cmd & IOC_IN) ? "W" : "", (cmd & IOC_OUT) ? "R" : "", 401 (char)IOCGROUP(cmd), cmd & 0xff)); 402 403 switch (cmd) { 404 case FBIOGTYPE: 405 *(struct fbtype *)data = sc->sc_fb.fb_type; 406 break; 407 case FBIOGATTR: 408 #define fba ((struct fbgattr *)data) 409 fba->real_type = sc->sc_fb.fb_type.fb_type; 410 fba->owner = 0; /* XXX ??? */ 411 fba->fbtype = sc->sc_fb.fb_type; 412 fba->sattr.flags = 0; 413 fba->sattr.emu_type = sc->sc_fb.fb_type.fb_type; 414 fba->sattr.dev_specific[0] = -1; 415 fba->emu_types[0] = sc->sc_fb.fb_type.fb_type; 416 fba->emu_types[1] = -1; 417 #undef fba 418 break; 419 420 case FBIOGETCMAP: 421 case FBIOPUTCMAP: 422 return EIO; 423 424 case FBIOGVIDEO: 425 case FBIOSVIDEO: 426 return ffb_blank(sc, cmd == FBIOGVIDEO? 427 WSDISPLAYIO_GVIDEO : WSDISPLAYIO_SVIDEO, 428 (u_int *)data); 429 break; 430 case FBIOGCURSOR: 431 case FBIOSCURSOR: 432 /* the console driver is not using the hardware cursor */ 433 break; 434 case FBIOGCURPOS: 435 printf("%s: FBIOGCURPOS not implemented\n", 436 device_xname(sc->sc_dev)); 437 return EIO; 438 case FBIOSCURPOS: 439 printf("%s: FBIOSCURPOS not implemented\n", 440 device_xname(sc->sc_dev)); 441 return EIO; 442 case FBIOGCURMAX: 443 printf("%s: FBIOGCURMAX not implemented\n", 444 device_xname(sc->sc_dev)); 445 return EIO; 446 447 case WSDISPLAYIO_GTYPE: 448 *(u_int *)data = WSDISPLAY_TYPE_SUNFFB; 449 break; 450 case WSDISPLAYIO_SMODE: 451 { 452 if (sc->sc_mode != *(u_int *)data) { 453 sc->sc_mode = *(u_int *)data; 454 if ((sc->sc_mode == WSDISPLAYIO_MODE_EMUL) && 455 (sc->sc_locked == 0)) { 456 ffb_ras_init(sc); 457 vcons_redraw_screen(ms); 458 } 459 } 460 } 461 break; 462 case WSDISPLAYIO_GINFO: 463 wdf = (void *)data; 464 wdf->height = sc->sc_height; 465 wdf->width = sc->sc_width; 466 wdf->depth = 32; 467 wdf->cmsize = 256; /* XXX */ 468 break; 469 #ifdef WSDISPLAYIO_LINEBYTES 470 case WSDISPLAYIO_LINEBYTES: 471 *(u_int *)data = sc->sc_linebytes; 472 break; 473 #endif 474 case WSDISPLAYIO_GETCMAP: 475 break;/* XXX */ 476 477 case WSDISPLAYIO_PUTCMAP: 478 break;/* XXX */ 479 480 case WSDISPLAYIO_SVIDEO: 481 case WSDISPLAYIO_GVIDEO: 482 return(ffb_blank(sc, cmd, (u_int *)data)); 483 break; 484 case WSDISPLAYIO_GCURPOS: 485 case WSDISPLAYIO_SCURPOS: 486 case WSDISPLAYIO_GCURMAX: 487 case WSDISPLAYIO_GCURSOR: 488 case WSDISPLAYIO_SCURSOR: 489 return EIO; /* not supported yet */ 490 default: 491 return EPASSTHROUGH; 492 } 493 494 return (0); 495 } 496 497 /* blank/unblank the screen */ 498 static int 499 ffb_blank(struct ffb_softc *sc, u_long cmd, u_int *data) 500 { 501 struct vcons_screen *ms = sc->vd.active; 502 u_int val; 503 504 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_TGC); 505 val = DAC_READ(sc, FFB_DAC_VALUE); 506 507 switch (cmd) { 508 case WSDISPLAYIO_GVIDEO: 509 *data = val & 1; 510 return(0); 511 break; 512 case WSDISPLAYIO_SVIDEO: 513 if (*data == WSDISPLAYIO_VIDEO_OFF) 514 val &= ~1; 515 else if (*data == WSDISPLAYIO_VIDEO_ON) 516 val |= 1; 517 else 518 return(EINVAL); 519 break; 520 default: 521 return(EINVAL); 522 } 523 524 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_TGC); 525 DAC_WRITE(sc, FFB_DAC_VALUE, val); 526 527 if ((val & 1) && sc->sc_needredraw) { 528 if (ms != NULL) { 529 if ((sc->sc_mode == WSDISPLAYIO_MODE_EMUL) && 530 (sc->sc_locked == 0)) { 531 ffb_ras_init(sc); 532 vcons_redraw_screen(ms); 533 } 534 } 535 } 536 537 return(0); 538 } 539 540 paddr_t 541 ffb_mmap(void *vsc, void *vs, off_t off, int prot) 542 { 543 struct vcons_data *vd = vsc; 544 struct ffb_softc *sc = vd->cookie; 545 int i; 546 547 switch (sc->sc_mode) { 548 case WSDISPLAYIO_MODE_MAPPED: 549 for (i = 0; i < sc->sc_nreg; i++) { 550 /* Before this set? */ 551 if (off < sc->sc_addrs[i]) 552 continue; 553 /* After this set? */ 554 if (off >= (sc->sc_addrs[i] + sc->sc_sizes[i])) 555 continue; 556 557 return (bus_space_mmap(sc->sc_bt, sc->sc_addrs[i], 558 off - sc->sc_addrs[i], prot, BUS_SPACE_MAP_LINEAR)); 559 } 560 break; 561 #ifdef WSDISPLAYIO_MODE_DUMBFB 562 case WSDISPLAYIO_MODE_DUMBFB: 563 if (sc->sc_nreg < FFB_REG_DFB24) 564 break; 565 if (off >= 0 && off < sc->sc_sizes[FFB_REG_DFB24]) 566 return (bus_space_mmap(sc->sc_bt, 567 sc->sc_addrs[FFB_REG_DFB24], off, prot, 568 BUS_SPACE_MAP_LINEAR)); 569 break; 570 #endif 571 } 572 return (-1); 573 } 574 575 void 576 ffb_ras_fifo_wait(struct ffb_softc *sc, int n) 577 { 578 int32_t cache = sc->sc_fifo_cache; 579 580 if (cache < n) { 581 do { 582 cache = FBC_READ(sc, FFB_FBC_UCSR); 583 cache = (cache & FBC_UCSR_FIFO_MASK) - 8; 584 } while (cache < n); 585 } 586 sc->sc_fifo_cache = cache - n; 587 } 588 589 void 590 ffb_ras_wait(struct ffb_softc *sc) 591 { 592 uint32_t ucsr, r; 593 594 while (1) { 595 ucsr = FBC_READ(sc, FFB_FBC_UCSR); 596 if ((ucsr & (FBC_UCSR_FB_BUSY|FBC_UCSR_RP_BUSY)) == 0) 597 break; 598 r = ucsr & (FBC_UCSR_READ_ERR | FBC_UCSR_FIFO_OVFL); 599 if (r != 0) 600 FBC_WRITE(sc, FFB_FBC_UCSR, r); 601 } 602 } 603 604 void 605 ffb_ras_init(struct ffb_softc *sc) 606 { 607 uint32_t fbc; 608 609 if (sc->sc_width > 1280) { 610 DPRINTF(("ffb_ras_init: high resolution.\n")); 611 fbc = FFB_FBC_WB_B | FFB_FBC_WM_COMBINED | FFB_FBC_WE_FORCEON | 612 FFB_FBC_ZE_OFF | FFB_FBC_YE_OFF | FFB_FBC_XE_ON; 613 } else { 614 DPRINTF(("ffb_ras_init: standard resolution.\n")); 615 fbc = FFB_FBC_XE_OFF; 616 } 617 ffb_ras_fifo_wait(sc, 7); 618 FBC_WRITE(sc, FFB_FBC_PPC, 619 FBC_PPC_VCE_DIS | FBC_PPC_TBE_OPAQUE | FBC_PPC_ACE_DIS | 620 FBC_PPC_APE_DIS | FBC_PPC_DCE_DIS | FBC_PPC_CS_CONST); 621 FBC_WRITE(sc, FFB_FBC_FBC, 622 FFB_FBC_WB_A | FFB_FBC_RB_A | FFB_FBC_SB_BOTH | 623 FFB_FBC_RGBE_MASK | fbc); 624 FBC_WRITE(sc, FFB_FBC_ROP, FBC_ROP_NEW); 625 FBC_WRITE(sc, FFB_FBC_DRAWOP, FBC_DRAWOP_RECTANGLE); 626 FBC_WRITE(sc, FFB_FBC_PMASK, 0xffffffff); 627 FBC_WRITE(sc, FFB_FBC_FONTINC, 0x10000); 628 sc->sc_fg_cache = 0; 629 FBC_WRITE(sc, FFB_FBC_FG, sc->sc_fg_cache); 630 ffb_ras_wait(sc); 631 } 632 633 void 634 ffb_ras_eraserows(void *cookie, int row, int n, long attr) 635 { 636 struct rasops_info *ri = cookie; 637 struct vcons_screen *scr = ri->ri_hw; 638 struct ffb_softc *sc = scr->scr_cookie; 639 640 if (row < 0) { 641 n += row; 642 row = 0; 643 } 644 if (row + n > ri->ri_rows) 645 n = ri->ri_rows - row; 646 if (n <= 0) 647 return; 648 649 ffb_ras_fill(sc); 650 ffb_ras_setfg(sc, ri->ri_devcmap[(attr >> 16) & 0xf]); 651 ffb_ras_fifo_wait(sc, 4); 652 if ((n == ri->ri_rows) && (ri->ri_flg & RI_FULLCLEAR)) { 653 FBC_WRITE(sc, FFB_FBC_BY, 0); 654 FBC_WRITE(sc, FFB_FBC_BX, 0); 655 FBC_WRITE(sc, FFB_FBC_BH, ri->ri_height); 656 FBC_WRITE(sc, FFB_FBC_BW, ri->ri_width); 657 } else { 658 row *= ri->ri_font->fontheight; 659 FBC_WRITE(sc, FFB_FBC_BY, ri->ri_yorigin + row); 660 FBC_WRITE(sc, FFB_FBC_BX, ri->ri_xorigin); 661 FBC_WRITE(sc, FFB_FBC_BH, n * ri->ri_font->fontheight); 662 FBC_WRITE(sc, FFB_FBC_BW, ri->ri_emuwidth); 663 } 664 SYNC; 665 } 666 667 void 668 ffb_ras_erasecols(void *cookie, int row, int col, int n, long attr) 669 { 670 struct rasops_info *ri = cookie; 671 struct vcons_screen *scr = ri->ri_hw; 672 struct ffb_softc *sc = scr->scr_cookie; 673 674 if ((row < 0) || (row >= ri->ri_rows)) 675 return; 676 if (col < 0) { 677 n += col; 678 col = 0; 679 } 680 if (col + n > ri->ri_cols) 681 n = ri->ri_cols - col; 682 if (n <= 0) 683 return; 684 n *= ri->ri_font->fontwidth; 685 col *= ri->ri_font->fontwidth; 686 row *= ri->ri_font->fontheight; 687 688 ffb_ras_fill(sc); 689 ffb_ras_setfg(sc, ri->ri_devcmap[(attr >> 16) & 0xf]); 690 ffb_ras_fifo_wait(sc, 4); 691 FBC_WRITE(sc, FFB_FBC_BY, ri->ri_yorigin + row); 692 FBC_WRITE(sc, FFB_FBC_BX, ri->ri_xorigin + col); 693 FBC_WRITE(sc, FFB_FBC_BH, ri->ri_font->fontheight); 694 FBC_WRITE(sc, FFB_FBC_BW, n - 1); 695 SYNC; 696 } 697 698 void 699 ffb_ras_fill(struct ffb_softc *sc) 700 { 701 ffb_ras_fifo_wait(sc, 2); 702 FBC_WRITE(sc, FFB_FBC_ROP, FBC_ROP_NEW); 703 FBC_WRITE(sc, FFB_FBC_DRAWOP, FBC_DRAWOP_RECTANGLE); 704 SYNC; 705 } 706 707 void 708 ffb_ras_copyrows(void *cookie, int src, int dst, int n) 709 { 710 struct rasops_info *ri = cookie; 711 struct vcons_screen *scr = ri->ri_hw; 712 struct ffb_softc *sc = scr->scr_cookie; 713 714 if (dst == src) 715 return; 716 if (src < 0) { 717 n += src; 718 src = 0; 719 } 720 if ((src + n) > ri->ri_rows) 721 n = ri->ri_rows - src; 722 if (dst < 0) { 723 n += dst; 724 dst = 0; 725 } 726 if ((dst + n) > ri->ri_rows) 727 n = ri->ri_rows - dst; 728 if (n <= 0) 729 return; 730 n *= ri->ri_font->fontheight; 731 src *= ri->ri_font->fontheight; 732 dst *= ri->ri_font->fontheight; 733 734 ffb_ras_fifo_wait(sc, 8); 735 FBC_WRITE(sc, FFB_FBC_ROP, FBC_ROP_OLD | (FBC_ROP_OLD << 8)); 736 FBC_WRITE(sc, FFB_FBC_DRAWOP, FBC_DRAWOP_VSCROLL); 737 FBC_WRITE(sc, FFB_FBC_BY, ri->ri_yorigin + src); 738 FBC_WRITE(sc, FFB_FBC_BX, ri->ri_xorigin); 739 FBC_WRITE(sc, FFB_FBC_DY, ri->ri_yorigin + dst); 740 FBC_WRITE(sc, FFB_FBC_DX, ri->ri_xorigin); 741 FBC_WRITE(sc, FFB_FBC_BH, n); 742 FBC_WRITE(sc, FFB_FBC_BW, ri->ri_emuwidth); 743 SYNC; 744 } 745 746 static void 747 ffb_ras_setfg(struct ffb_softc *sc, int32_t fg) 748 { 749 ffb_ras_fifo_wait(sc, 1); 750 if (fg == sc->sc_fg_cache) 751 return; 752 sc->sc_fg_cache = fg; 753 FBC_WRITE(sc, FFB_FBC_FG, fg); 754 SYNC; 755 } 756 757 static void 758 ffb_ras_setbg(struct ffb_softc *sc, int32_t bg) 759 { 760 ffb_ras_fifo_wait(sc, 1); 761 if (bg == sc->sc_bg_cache) 762 return; 763 sc->sc_bg_cache = bg; 764 FBC_WRITE(sc, FFB_FBC_BG, bg); 765 SYNC; 766 } 767 768 /* frame buffer generic driver support functions */ 769 static void 770 ffbfb_unblank(device_t dev) 771 { 772 struct ffb_softc *sc = device_private(dev); 773 struct vcons_screen *ms = sc->vd.active; 774 u_int on = 1; 775 int redraw = 0; 776 777 ffb_ras_init(sc); 778 if (sc->sc_locked) { 779 sc->sc_locked = 0; 780 redraw = 1; 781 } 782 783 ffb_blank(sc, WSDISPLAYIO_SVIDEO, &on); 784 #if 0 785 if ((sc->vd.active != &ffb_console_screen) && 786 (ffb_console_screen.scr_flags & VCONS_SCREEN_IS_STATIC)) { 787 /* 788 * force-switch to the console screen. 789 * Caveat: the higher layer will think we're still on the 790 * other screen 791 */ 792 793 SCREEN_INVISIBLE(sc->vd.active); 794 sc->vd.active = &ffb_console_screen; 795 SCREEN_VISIBLE(sc->vd.active); 796 ms = sc->vd.active; 797 redraw = 1; 798 } 799 #endif 800 if (redraw) { 801 vcons_redraw_screen(ms); 802 } 803 } 804 805 int 806 ffbfb_open(dev_t dev, int flags, int mode, struct lwp *l) 807 { 808 struct ffb_softc *sc; 809 810 sc = device_lookup_private(&ffb_cd, minor(dev)); 811 if (sc == NULL) 812 return ENXIO; 813 814 sc->sc_locked = 1; 815 return 0; 816 } 817 818 int 819 ffbfb_close(dev_t dev, int flags, int mode, struct lwp *l) 820 { 821 struct ffb_softc *sc = device_lookup_private(&ffb_cd, minor(dev)); 822 struct vcons_screen *ms = sc->vd.active; 823 824 sc->sc_locked = 0; 825 if (ms != NULL) { 826 if ((sc->sc_mode == WSDISPLAYIO_MODE_EMUL) && 827 (sc->sc_locked == 0)) { 828 ffb_ras_init(sc); 829 vcons_redraw_screen(ms); 830 } 831 } 832 return 0; 833 } 834 835 int 836 ffbfb_ioctl(dev_t dev, u_long cmd, void *data, int flags, struct lwp *l) 837 { 838 struct ffb_softc *sc = device_lookup_private(&ffb_cd, minor(dev)); 839 840 return ffb_ioctl(&sc->vd, NULL, cmd, data, flags, l); 841 } 842 843 paddr_t 844 ffbfb_mmap(dev_t dev, off_t off, int prot) 845 { 846 struct ffb_softc *sc = device_lookup_private(&ffb_cd, minor(dev)); 847 uint64_t size; 848 int i, reg; 849 off_t o; 850 851 /* 852 * off is a magic cookie (see xfree86/drivers/sunffb/ffb.h), 853 * which we map to an index into the "reg" property, and use 854 * our copy of the firmware data as arguments for the real 855 * mapping. 856 */ 857 static struct { unsigned long voff; int reg; } map[] = { 858 { 0x00000000, FFB_REG_SFB8R }, 859 { 0x00400000, FFB_REG_SFB8G }, 860 { 0x00800000, FFB_REG_SFB8B }, 861 { 0x00c00000, FFB_REG_SFB8X }, 862 { 0x01000000, FFB_REG_SFB32 }, 863 { 0x02000000, FFB_REG_SFB64 }, 864 { 0x04000000, FFB_REG_FBC }, 865 { 0x04004000, FFB_REG_DFB8R }, 866 { 0x04404000, FFB_REG_DFB8G }, 867 { 0x04804000, FFB_REG_DFB8B }, 868 { 0x04c04000, FFB_REG_DFB8X }, 869 { 0x05004000, FFB_REG_DFB24 }, 870 { 0x06004000, FFB_REG_DFB32 }, 871 { 0x07004000, FFB_REG_DFB422A }, 872 { 0x0bc06000, FFB_REG_DAC }, 873 { 0x0bc08000, FFB_REG_PROM }, 874 { 0x0bc18000, 0 } 875 }; 876 877 /* special value "FFB_EXP_VOFF" - not backed by any "reg" entry */ 878 if (off == 0x0bc18000) 879 return bus_space_mmap(sc->sc_bt, sc->sc_addrs[FFB_REG_PROM], 880 0x00200000, prot, BUS_SPACE_MAP_LINEAR); 881 882 /* 883 * FFB_VOFF_FBC_KREGS - used by afbinit to upload firmware. We should 884 * probably mmap them only on afb boards 885 */ 886 if ((off >= 0x0bc04000) && (off < 0x0bc06000)) 887 return bus_space_mmap(sc->sc_bt, sc->sc_addrs[FFB_REG_PROM], 888 0x00610000 + (off - 0x0bc04000), prot, 889 BUS_SPACE_MAP_LINEAR); 890 891 #define NELEMS(arr) (sizeof(arr)/sizeof((arr)[0])) 892 893 /* the map is ordered by voff */ 894 for (i = 0; i < NELEMS(map)-1; i++) { 895 reg = map[i].reg; 896 /* the number of entries in reg seems to vary */ 897 if (reg < sc->sc_nreg) { 898 size = min((map[i + 1].voff - map[i].voff), 899 sc->sc_sizes[reg]); 900 if ((off >= map[i].voff) && 901 (off < (map[i].voff + size))) { 902 o = off - map[i].voff; 903 return bus_space_mmap(sc->sc_bt, 904 sc->sc_addrs[reg], o, prot, 905 BUS_SPACE_MAP_LINEAR); 906 } 907 } 908 } 909 910 return -1; 911 } 912 913 void 914 ffb_clearscreen(struct ffb_softc *sc) 915 { 916 struct rasops_info *ri = &ffb_console_screen.scr_ri; 917 ffb_ras_fill(sc); 918 ffb_ras_setfg(sc, ri->ri_devcmap[WS_DEFAULT_BG]); 919 ffb_ras_fifo_wait(sc, 4); 920 FBC_WRITE(sc, FFB_FBC_BY, 0); 921 FBC_WRITE(sc, FFB_FBC_BX, 0); 922 FBC_WRITE(sc, FFB_FBC_BH, sc->sc_height); 923 FBC_WRITE(sc, FFB_FBC_BW, sc->sc_width); 924 } 925 926 void 927 ffb_cursor(void *cookie, int on, int row, int col) 928 { 929 struct rasops_info *ri = cookie; 930 struct vcons_screen *scr; 931 struct ffb_softc *sc; 932 int x, y, wi, he, coffset; 933 934 if (cookie != NULL) { 935 scr = ri->ri_hw; 936 sc = scr->scr_cookie; 937 938 wi = ri->ri_font->fontwidth; 939 he = ri->ri_font->fontheight; 940 941 if (sc->sc_mode == WSDISPLAYIO_MODE_EMUL) { 942 x = ri->ri_ccol * wi + ri->ri_xorigin; 943 y = ri->ri_crow * he + ri->ri_yorigin; 944 945 if (ri->ri_flg & RI_CURSOR) { 946 /* remove cursor */ 947 coffset = ri->ri_ccol + (ri->ri_crow * 948 ri->ri_cols); 949 #ifdef WSDISPLAY_SCROLLSUPPORT 950 coffset += scr->scr_offset_to_zero; 951 #endif 952 ffb_ras_wait(sc); 953 ffb_putchar(cookie, ri->ri_crow, 954 ri->ri_ccol, scr->scr_chars[coffset], 955 scr->scr_attrs[coffset]); 956 ri->ri_flg &= ~RI_CURSOR; 957 } 958 ri->ri_crow = row; 959 ri->ri_ccol = col; 960 if (on) 961 { 962 long attr, revattr; 963 x = ri->ri_ccol * wi + ri->ri_xorigin; 964 y = ri->ri_crow * he + ri->ri_yorigin; 965 coffset = col + (row * ri->ri_cols); 966 #ifdef WSDISPLAY_SCROLLSUPPORT 967 coffset += scr->scr_offset_to_zero; 968 #endif 969 attr = scr->scr_attrs[coffset]; 970 #ifdef FFB_CURSOR_SWAP_COLOURS 971 revattr=((attr >> 8 ) & 0x000f0000) | ((attr & 972 0x000f0000)<<8) | (attr & 0x0000ffff); 973 #else 974 revattr = attr ^ 0xffff0000; 975 #endif 976 ffb_ras_wait(sc); 977 ffb_putchar(cookie, ri->ri_crow, ri->ri_ccol, 978 scr->scr_chars[coffset], revattr); 979 ri->ri_flg |= RI_CURSOR; 980 } 981 } else { 982 ri->ri_crow = row; 983 ri->ri_ccol = col; 984 ri->ri_flg &= ~RI_CURSOR; 985 } 986 } 987 } 988 989 void 990 ffb_putchar(void *cookie, int row, int col, u_int c, long attr) 991 { 992 struct rasops_info *ri = cookie; 993 struct vcons_screen *scr = ri->ri_hw; 994 struct wsdisplay_font *font = PICK_FONT(ri, c); 995 struct ffb_softc *sc = scr->scr_cookie; 996 997 if (sc->sc_mode == WSDISPLAYIO_MODE_EMUL) { 998 void *data; 999 uint32_t fg, bg; 1000 int uc, i; 1001 int x, y, wi, he; 1002 1003 wi = font->fontwidth; 1004 he = font->fontheight; 1005 1006 if (!CHAR_IN_FONT(c, font)) 1007 return; 1008 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 1009 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 1010 x = ri->ri_xorigin + col * wi; 1011 y = ri->ri_yorigin + row * he; 1012 1013 uc = c - font->firstchar; 1014 data = (uint8_t *)font->data + uc * ri->ri_fontscale; 1015 1016 ffb_ras_setbg(sc, bg); 1017 ffb_ras_setfg(sc, fg); 1018 ffb_ras_fifo_wait(sc, 3); 1019 FBC_WRITE(sc, FFB_FBC_ROP, FBC_ROP_NEW); 1020 FBC_WRITE(sc, FFB_FBC_FONTXY, (y << 16) | x); 1021 FBC_WRITE(sc, FFB_FBC_FONTW, wi); 1022 1023 switch (ri->ri_font->stride) { 1024 case 1: { 1025 uint8_t *data8 = data; 1026 uint32_t reg; 1027 for (i = 0; i < he; i++) { 1028 reg = *data8; 1029 FBC_WRITE(sc, FFB_FBC_FONT, reg << 24); 1030 data8++; 1031 } 1032 break; 1033 } 1034 case 2: { 1035 uint16_t *data16 = data; 1036 uint32_t reg; 1037 for (i = 0; i < he; i++) { 1038 reg = *data16; 1039 FBC_WRITE(sc, FFB_FBC_FONT, reg << 16); 1040 data16++; 1041 } 1042 break; 1043 } 1044 } 1045 } 1046 } 1047 1048 int 1049 ffb_allocattr(void *cookie, int fg, int bg, int flags, long *attrp) 1050 { 1051 if ((fg == 0) && (bg == 0)) 1052 { 1053 fg = WS_DEFAULT_FG; 1054 bg = WS_DEFAULT_BG; 1055 } 1056 if (flags & WSATTR_REVERSE) { 1057 *attrp = (bg & 0xff) << 24 | (fg & 0xff) << 16 | 1058 (flags & 0xff); 1059 } else 1060 *attrp = (fg & 0xff) << 24 | (bg & 0xff) << 16 | 1061 (flags & 0xff); 1062 return 0; 1063 } 1064 1065 void 1066 ffb_init_screen(void *cookie, struct vcons_screen *scr, 1067 int existing, long *defattr) 1068 { 1069 struct ffb_softc *sc = cookie; 1070 struct rasops_info *ri = &scr->scr_ri; 1071 1072 ri->ri_depth = 32; 1073 ri->ri_width = sc->sc_width; 1074 ri->ri_height = sc->sc_height; 1075 ri->ri_stride = sc->sc_linebytes; 1076 ri->ri_flg = RI_CENTER; 1077 1078 /* 1079 * we can't accelerate copycols() so instead of falling back to 1080 * software use vcons' putchar() based implementation 1081 */ 1082 scr->scr_flags |= VCONS_NO_COPYCOLS; 1083 1084 DPRINTF(("ffb_init_screen: addr: %08lx\n",(ulong)ri->ri_bits)); 1085 1086 rasops_init(ri, sc->sc_height/8, sc->sc_width/8); 1087 ri->ri_caps = WSSCREEN_WSCOLORS; 1088 rasops_reconfig(ri, sc->sc_height / ri->ri_font->fontheight, 1089 sc->sc_width / ri->ri_font->fontwidth); 1090 1091 /* enable acceleration */ 1092 ri->ri_ops.copyrows = ffb_ras_copyrows; 1093 ri->ri_ops.eraserows = ffb_ras_eraserows; 1094 ri->ri_ops.erasecols = ffb_ras_erasecols; 1095 ri->ri_ops.cursor = ffb_cursor; 1096 ri->ri_ops.allocattr = ffb_allocattr; 1097 ri->ri_ops.putchar = ffb_putchar; 1098 } 1099 1100 /* I2C bitbanging */ 1101 static void ffb_i2cbb_set_bits(void *cookie, uint32_t bits) 1102 { 1103 struct ffb_softc *sc = cookie; 1104 1105 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_CFG_MPDATA); 1106 DAC_WRITE(sc, FFB_DAC_VALUE, bits); 1107 } 1108 1109 static void ffb_i2cbb_set_dir(void *cookie, uint32_t dir) 1110 { 1111 /* Nothing to do */ 1112 } 1113 1114 static uint32_t ffb_i2cbb_read(void *cookie) 1115 { 1116 struct ffb_softc *sc = cookie; 1117 uint32_t bits; 1118 1119 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_CFG_MPSENSE); 1120 bits = DAC_READ(sc, FFB_DAC_VALUE); 1121 1122 return bits; 1123 } 1124 1125 /* higher level I2C stuff */ 1126 static int 1127 ffb_i2c_acquire_bus(void *cookie, int flags) 1128 { 1129 /* private bus */ 1130 return (0); 1131 } 1132 1133 static void 1134 ffb_i2c_release_bus(void *cookie, int flags) 1135 { 1136 /* private bus */ 1137 } 1138 1139 static int 1140 ffb_i2c_send_start(void *cookie, int flags) 1141 { 1142 return (i2c_bitbang_send_start(cookie, flags, &ffb_i2cbb_ops)); 1143 } 1144 1145 static int 1146 ffb_i2c_send_stop(void *cookie, int flags) 1147 { 1148 1149 return (i2c_bitbang_send_stop(cookie, flags, &ffb_i2cbb_ops)); 1150 } 1151 1152 static int 1153 ffb_i2c_initiate_xfer(void *cookie, i2c_addr_t addr, int flags) 1154 { 1155 /* 1156 * for some reason i2c_bitbang_initiate_xfer left-shifts 1157 * the I2C-address and then sets the direction bit 1158 */ 1159 return (i2c_bitbang_initiate_xfer(cookie, addr, flags, 1160 &ffb_i2cbb_ops)); 1161 } 1162 1163 static int 1164 ffb_i2c_read_byte(void *cookie, uint8_t *valp, int flags) 1165 { 1166 return (i2c_bitbang_read_byte(cookie, valp, flags, &ffb_i2cbb_ops)); 1167 } 1168 1169 static int 1170 ffb_i2c_write_byte(void *cookie, uint8_t val, int flags) 1171 { 1172 return (i2c_bitbang_write_byte(cookie, val, flags, &ffb_i2cbb_ops)); 1173 } 1174 1175 1176 #define TVC_READ_LIMIT 100000 1177 int 1178 ffb_tgc_disable(struct ffb_softc *sc) 1179 { 1180 int i; 1181 1182 /* Is the timing generator disabled? */ 1183 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_TGC); 1184 if (!(DAC_READ(sc, FFB_DAC_VALUE) & FFB_DAC_TGC_TIMING_ENABLE)) 1185 return 1; 1186 1187 /* If not, disable it when the vertical counter reaches 0 */ 1188 for (i = 0; i < TVC_READ_LIMIT; i++) { 1189 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_TVC); 1190 if (!DAC_READ(sc, FFB_DAC_VALUE)) { 1191 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_TGC); 1192 DAC_WRITE(sc, FFB_DAC_VALUE, 0); 1193 return 1; 1194 } 1195 } 1196 return 0; 1197 } 1198 1199 /* 1200 * PLL Control Register values: 1201 * M)ultiplier = bits 0:6 + 1 1202 * D)ivisor = bits 7:10 + 1 1203 * P)ost divisor = bits 11:13 (000 = 1, 001 = 2, 010 = 4, 011 = 8) 1204 * Frequency = 13.5 * M / D / P 1205 */ 1206 #define FFB_PLL_FREQ 13500000 1207 void 1208 ffb_get_pclk(int request, uint32_t *pll, int *diff) 1209 { 1210 int m, d, p, f, hex = 0, curdiff; 1211 1212 *diff = 100000000; 1213 1214 for (m = 32; m <= 80; m++) { 1215 for (d = 4; d <= 11; d++) { 1216 for (p = 1; p <= 8; p = p << 1) { 1217 switch (p) { 1218 case 1: 1219 hex = 0x4000 + (d << 7) + m; 1220 break; 1221 case 2: 1222 hex = 0x4800 + (d << 7) + m; 1223 break; 1224 case 4: 1225 hex = 0x5000 + (d << 7) + m; 1226 break; 1227 case 8: 1228 hex = 0x6000 + (d << 7) + m; 1229 break; 1230 } 1231 f = 13500000 * m / d / p; 1232 if (f == request) { 1233 *diff = 0; 1234 *pll = hex; 1235 return; 1236 } else { 1237 curdiff = abs(request - f); 1238 if (curdiff < *diff) { 1239 *diff = curdiff; 1240 *pll = hex; 1241 } 1242 } 1243 } 1244 } 1245 } 1246 } 1247 1248 /* 1249 * Details of the FFB RAMDAC are contained in the Brooktree BT497/498 1250 * and in the Connexant BT497A/498A documentation. 1251 * 1252 * VESA timings to FFB register conversion: 1253 * If interleave = 4/2:1 then x = 2, if interleave = 8/2:1 then x = 4 1254 * VBE = VBS - vres = (sync pulse - 1) + back porch 1255 * VBS = VSS - front porch = (sync pulse - 1) + back porch + vres 1256 * VSE = sync pulse - 1 1257 * VSS = (sync pulse - 1) + back porch + vres + front porch 1258 * HRE = HSS - HSE - 1 1259 * HBE = (sync pulse + back porch) / x - 1 1260 * HBS = (sync pulse + back porch + hres) / x - 1 1261 * HSE = sync pulse / x - 1 1262 * HSS = (sync pulse + back porch + hres + front porch) / x - 1 1263 * HCE = HBS - 4 1264 * HCS = HBE - 4 1265 * EPE = EIE = EIS = 0 (for all non-interlaced modes) 1266 * 1267 * Note, that 8/2:1 Single Buffered Interleaving is only supported by the 1268 * double-buffered FFB (Creator3D), and at higher resolutions than 1280x1024 1269 * 1270 * Note, that the timing generator should be disabled and re-enabled when the 1271 * the timing parameter registers are being programmed. Stopping the timing 1272 * generator should only be done when the vertical counter is zero. 1273 */ 1274 #define DIVIDE(x,y) (((x) + ((y) / 2)) / (y)) 1275 int 1276 ffb_set_vmode(struct ffb_softc *sc, struct videomode *mode, int btype, 1277 int *hres, int *vres) 1278 { 1279 int diff; 1280 uint32_t fp, sp, bp, x; 1281 uint32_t pll, pfc, ucl, dcl, tgc; 1282 uint32_t vbe, vbs, vse, vss, hre, hbe, hbs, hse, hss, hce, hcs; 1283 uint32_t epe, eie, eis; 1284 uint32_t fbcfg0; 1285 1286 DPRINTF(("ffb_set_vmode: %dx%d@%d", mode->hdisplay, mode->vdisplay, 1287 DIVIDE(DIVIDE(mode->dot_clock * 1000, 1288 mode->htotal), mode->vtotal))); 1289 DPRINTF((" (%d %d %d %d %d %d %d", 1290 mode->dot_clock, mode->hsync_start, mode->hsync_end, mode->htotal, 1291 mode->vsync_start, mode->vsync_end, mode->vtotal)); 1292 DPRINTF((" %s%sH %s%sV)\n", 1293 mode->flags & VID_PHSYNC ? "+" : "", 1294 mode->flags & VID_NHSYNC ? "-" : "", 1295 mode->flags & VID_PVSYNC ? "+" : "", 1296 mode->flags & VID_NVSYNC ? "-" : "")); 1297 1298 /* We don't handle interlaced or doublescan (yet) */ 1299 if ((mode->flags & VID_INTERLACE) || (mode->flags & VID_DBLSCAN)) 1300 return 0; 1301 1302 /* Only Creator3D can be set to > 1280x1024 */ 1303 if(((sc->sc_type == FFB_CREATOR && !((btype & 7) == 3)) || 1304 sc->sc_type == FFB_AFB) 1305 && (mode->hdisplay > 1280 || mode->vdisplay > 1024)) 1306 return 0; 1307 /* Creator3D can be set to <= 1920x1360 */ 1308 if (mode->hdisplay > 1920 || mode->vdisplay > 1360) 1309 return 0; 1310 1311 /* 1312 * Look for a matching pixel clock and set PLL Control. 1313 * XXX: 640x480@60 is 25175000 in modelines but 25125000 in the 1314 * FFB PROM, and the closest match to 25175000 (0x4da9/25159090) 1315 * does not work. So, use the PROM value instead. 1316 */ 1317 if (mode->hdisplay == 640 && mode->vdisplay == 480 && 1318 mode->dot_clock == 25175) { 1319 DPRINTF(("ffb_set_vmode: 640x480@60: adjusted dot clock\n")); 1320 mode->dot_clock = 25125; 1321 } 1322 ffb_get_pclk(mode->dot_clock * 1000, &pll, &diff); 1323 if (diff > 250000) 1324 return 0; 1325 1326 /* Pixel Format Control, User Control and FBC Configuration. */ 1327 if (mode->hdisplay > 1280) { 1328 pfc = FFB_DAC_PIX_FMT_821; 1329 ucl = FFB_DAC_USR_CTRL_OVERLAY | FFB_DAC_USR_CTRL_WMODE_C; 1330 x = 4; 1331 fbcfg0 = FBC_READ(sc, FFB_FBC_FBCFG0) | FBC_CFG0_DOUBLE_BUF; 1332 } else { 1333 pfc = FFB_DAC_PIX_FMT_421; 1334 /* Only Creator3D and Elite3D can have double-buffer */ 1335 if ((sc->sc_type == FFB_CREATOR && !((btype & 7) == 3))) 1336 ucl = 0; 1337 else 1338 ucl = FFB_DAC_USR_CTRL_DOUBLE; 1339 ucl |= (FFB_DAC_USR_CTRL_OVERLAY | FFB_DAC_USR_CTRL_WMODE_S8); 1340 x = 2; 1341 fbcfg0 = FBC_READ(sc, FFB_FBC_FBCFG0) | FBC_CFG0_SINGLE_BUF; 1342 } 1343 1344 /* DAC Control and Timing Generator Control */ 1345 if (mode->flags & VID_PHSYNC) { 1346 dcl = FFB_DAC_DAC_CTRL_POS_SYNC; 1347 if (mode->flags & VID_NVSYNC) { 1348 dcl |= FFB_DAC_DAC_CTRL_VSYNC_REV; 1349 tgc = 0; 1350 } else { 1351 tgc = FFB_DAC_TGC_EQUAL_DISABLE; 1352 } 1353 } else { 1354 dcl = 0; 1355 if (mode->flags & VID_PVSYNC) { 1356 dcl |= FFB_DAC_DAC_CTRL_VSYNC_REV; 1357 tgc = 0; 1358 } else { 1359 tgc = FFB_DAC_TGC_EQUAL_DISABLE; 1360 } 1361 } 1362 #define EDID_VID_INP sc->sc_edid_info.edid_video_input 1363 if (!(EDID_VID_INP & EDID_VIDEO_INPUT_COMPOSITE_SYNC)) { 1364 dcl |= FFB_DAC_DAC_CTRL_SYNC_G; 1365 if (EDID_VID_INP & EDID_VIDEO_INPUT_SEPARATE_SYNCS) 1366 tgc |= FFB_DAC_TGC_VSYNC_DISABLE; 1367 } 1368 if (EDID_VID_INP & EDID_VIDEO_INPUT_BLANK_TO_BLACK) 1369 dcl |= FFB_DAC_DAC_CTRL_PED_ENABLE; 1370 tgc |= (FFB_DAC_TGC_VIDEO_ENABLE | FFB_DAC_TGC_TIMING_ENABLE | 1371 FFB_DAC_TGC_MASTER_ENABLE); 1372 1373 /* Vertical timing */ 1374 fp = mode->vsync_start - mode->vdisplay; 1375 sp = mode->vsync_end - mode->vsync_start; 1376 bp = mode->vtotal - mode->vsync_end; 1377 1378 vbe = sp - 1 + bp; 1379 vbs = sp - 1 + bp + mode->vdisplay; 1380 vse = sp - 1; 1381 vss = sp - 1 + bp + mode->vdisplay + fp; 1382 1383 /* Horizontal timing */ 1384 fp = mode->hsync_start - mode->hdisplay; 1385 sp = mode->hsync_end - mode->hsync_start; 1386 bp = mode->htotal - mode->hsync_end; 1387 1388 hbe = (sp + bp) / x - 1; 1389 hbs = (sp + bp + mode->hdisplay) / x - 1; 1390 hse = sp / x - 1; 1391 hss = (sp + bp + mode->hdisplay + fp) / x -1; 1392 hre = hss - hse - 1; 1393 hce = hbs - 4; 1394 hcs = hbe - 4; 1395 1396 /* Equalisation (interlaced modes) */ 1397 epe = 0; 1398 eie = 0; 1399 eis = 0; 1400 1401 DPRINTF(("ffb_set_vmode: 0x%04x 0x%04x 0x%04x 0x%04x 0x%04x\n", 1402 pll, pfc, ucl, dcl, tgc)); 1403 DPRINTF(("\t0x%04x 0x%04x 0x%04x 0x%04x\n", vbe, vbs, vse, vss)); 1404 DPRINTF(("\t0x%04x 0x%04x 0x%04x 0x%04x 0x%04x 0x%04x 0x%04x\n", 1405 hre, hbe, hbs, hse, hss, hce, hcs)); 1406 DPRINTF(("\t0x%04x 0x%04x 0x%04x\n", epe, eie, eis)); 1407 1408 if (!ffb_tgc_disable(sc)) { 1409 DPRINTF(("ffb_set_vmode: failed to disable TGC register\n")); 1410 return 0; 1411 } 1412 1413 /* 1414 * Program the mode registers. 1415 * Program the timing generator last, as that re-enables output. 1416 * Note, that a read to/write from a register increments the 1417 * register address to the next register automatically. 1418 */ 1419 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_PLL_CTRL); 1420 DAC_WRITE(sc, FFB_DAC_VALUE, pll); 1421 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_PIX_FMT); 1422 DAC_WRITE(sc, FFB_DAC_VALUE, pfc); 1423 DAC_WRITE(sc, FFB_DAC_VALUE, ucl); 1424 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_DAC_CTRL); 1425 DAC_WRITE(sc, FFB_DAC_VALUE, dcl); 1426 1427 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_VBE); 1428 DAC_WRITE(sc, FFB_DAC_VALUE, vbe); 1429 DAC_WRITE(sc, FFB_DAC_VALUE, vbs); 1430 DAC_WRITE(sc, FFB_DAC_VALUE, vse); 1431 DAC_WRITE(sc, FFB_DAC_VALUE, vss); 1432 1433 DAC_WRITE(sc, FFB_DAC_VALUE, hre); 1434 DAC_WRITE(sc, FFB_DAC_VALUE, hbe); 1435 DAC_WRITE(sc, FFB_DAC_VALUE, hbs); 1436 DAC_WRITE(sc, FFB_DAC_VALUE, hse); 1437 DAC_WRITE(sc, FFB_DAC_VALUE, hss); 1438 DAC_WRITE(sc, FFB_DAC_VALUE, hce); 1439 DAC_WRITE(sc, FFB_DAC_VALUE, hcs); 1440 1441 DAC_WRITE(sc, FFB_DAC_VALUE, epe); 1442 DAC_WRITE(sc, FFB_DAC_VALUE, eie); 1443 DAC_WRITE(sc, FFB_DAC_VALUE, eis); 1444 1445 FBC_WRITE(sc, FFB_FBC_FBCFG0, fbcfg0); 1446 1447 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_TGC); 1448 DAC_WRITE(sc, FFB_DAC_VALUE, tgc); 1449 1450 *hres = mode->hdisplay; 1451 *vres = mode->vdisplay; 1452 1453 printf("%s: video mode set to %d x %d @ %dHz\n", 1454 device_xname(sc->sc_dev), 1455 mode->hdisplay, mode->vdisplay, 1456 DIVIDE(DIVIDE(mode->dot_clock * 1000, 1457 mode->htotal), mode->vtotal)); 1458 1459 return 1; 1460 } 1461
Indexes created Sun Oct 12 02:09:55 GMT 2025