ffb.c revision 1.48.2.2
1 /* $NetBSD: ffb.c,v 1.48.2.2 2012/10/30 17:20:23 yamt Exp $ */ 2 /* $OpenBSD: creator.c,v 1.20 2002/07/30 19:48:15 jason Exp $ */ 3 4 /* 5 * Copyright (c) 2002 Jason L. Wright (jason (at) thought.net) 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Jason L. Wright 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 25 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 26 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 27 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 30 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 31 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32 * POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: ffb.c,v 1.48.2.2 2012/10/30 17:20:23 yamt Exp $"); 37 38 #include <sys/types.h> 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/kernel.h> 42 #include <sys/device.h> 43 #include <sys/conf.h> 44 #include <sys/ioctl.h> 45 #include <sys/malloc.h> 46 #include <sys/mman.h> 47 48 #include <sys/bus.h> 49 #include <machine/autoconf.h> 50 #include <machine/openfirm.h> 51 #include <machine/vmparam.h> 52 53 #include <dev/wscons/wsconsio.h> 54 #include <dev/sun/fbio.h> 55 #include <dev/sun/fbvar.h> 56 57 #include <dev/wsfont/wsfont.h> 58 #include <dev/wscons/wsdisplay_vconsvar.h> 59 60 #include <prop/proplib.h> 61 62 #include <dev/i2c/i2cvar.h> 63 #include <dev/i2c/i2c_bitbang.h> 64 #include <dev/i2c/ddcvar.h> 65 66 #include <sparc64/dev/ffbreg.h> 67 #include <sparc64/dev/ffbvar.h> 68 69 #include "opt_wsdisplay_compat.h" 70 #include "opt_ffb.h" 71 72 #ifndef WS_DEFAULT_BG 73 /* Sun -> background should be white */ 74 #define WS_DEFAULT_BG 0xf 75 #endif 76 77 #ifdef FFB_SYNC 78 #define SYNC ffb_ras_wait(sc) 79 #else 80 #define SYNC 81 #endif 82 83 /* Debugging */ 84 #if !defined FFB_DEBUG 85 #define FFB_DEBUG 0 86 #endif 87 #define DPRINTF(x) if (ffb_debug) printf x 88 /* Patchable */ 89 extern int ffb_debug; 90 #if FFB_DEBUG > 0 91 int ffb_debug = 1; 92 #else 93 int ffb_debug = 0; 94 #endif 95 96 extern struct cfdriver ffb_cd; 97 98 struct wsscreen_descr ffb_stdscreen = { 99 "sunffb", 100 0, 0, /* will be filled in -- XXX shouldn't, it's global. */ 101 0, 102 0, 0, 103 WSSCREEN_REVERSE | WSSCREEN_WSCOLORS, 104 NULL /* modecookie */ 105 }; 106 107 const struct wsscreen_descr *ffb_scrlist[] = { 108 &ffb_stdscreen, 109 /* XXX other formats? */ 110 }; 111 112 struct wsscreen_list ffb_screenlist = { 113 sizeof(ffb_scrlist) / sizeof(struct wsscreen_descr *), 114 ffb_scrlist 115 }; 116 117 static struct vcons_screen ffb_console_screen; 118 119 int ffb_ioctl(void *, void *, u_long, void *, int, struct lwp *); 120 static int ffb_blank(struct ffb_softc *, u_long, u_int *); 121 paddr_t ffb_mmap(void *, void *, off_t, int); 122 void ffb_ras_fifo_wait(struct ffb_softc *, int); 123 void ffb_ras_wait(struct ffb_softc *); 124 void ffb_ras_init(struct ffb_softc *); 125 void ffb_ras_copyrows(void *, int, int, int); 126 void ffb_ras_erasecols(void *, int, int, int, long int); 127 void ffb_ras_eraserows(void *, int, int, long int); 128 void ffb_ras_do_cursor(struct rasops_info *); 129 void ffb_ras_fill(struct ffb_softc *); 130 void ffb_ras_invert(struct ffb_softc *); 131 static void ffb_ras_setfg(struct ffb_softc *, int32_t); 132 static void ffb_ras_setbg(struct ffb_softc *, int32_t); 133 134 void ffb_clearscreen(struct ffb_softc *); 135 int ffb_load_font(void *, void *, struct wsdisplay_font *); 136 void ffb_init_screen(void *, struct vcons_screen *, int, 137 long *); 138 int ffb_allocattr(void *, int, int, int, long *); 139 void ffb_putchar_mono(void *, int, int, u_int, long); 140 void ffb_putchar_aa(void *, int, int, u_int, long); 141 void ffb_cursor(void *, int, int, int); 142 143 /* frame buffer generic driver */ 144 static void ffbfb_unblank(device_t); 145 dev_type_open(ffbfb_open); 146 dev_type_close(ffbfb_close); 147 dev_type_ioctl(ffbfb_ioctl); 148 dev_type_mmap(ffbfb_mmap); 149 150 static struct fbdriver ffb_fbdriver = { 151 ffbfb_unblank, ffbfb_open, ffbfb_close, ffbfb_ioctl, nopoll, 152 ffbfb_mmap, nokqfilter 153 }; 154 155 struct wsdisplay_accessops ffb_accessops = { 156 .ioctl = ffb_ioctl, 157 .mmap = ffb_mmap, 158 }; 159 160 /* I2C glue */ 161 static int ffb_i2c_acquire_bus(void *, int); 162 static void ffb_i2c_release_bus(void *, int); 163 static int ffb_i2c_send_start(void *, int); 164 static int ffb_i2c_send_stop(void *, int); 165 static int ffb_i2c_initiate_xfer(void *, i2c_addr_t, int); 166 static int ffb_i2c_read_byte(void *, uint8_t *, int); 167 static int ffb_i2c_write_byte(void *, uint8_t, int); 168 169 /* I2C bitbang glue */ 170 static void ffb_i2cbb_set_bits(void *, uint32_t); 171 static void ffb_i2cbb_set_dir(void *, uint32_t); 172 static uint32_t ffb_i2cbb_read(void *); 173 174 static const struct i2c_bitbang_ops ffb_i2cbb_ops = { 175 ffb_i2cbb_set_bits, 176 ffb_i2cbb_set_dir, 177 ffb_i2cbb_read, 178 { 179 FFB_DAC_CFG_MPDATA_SDA, 180 FFB_DAC_CFG_MPDATA_SCL, 181 0, 182 0 183 } 184 }; 185 186 void ffb_attach_i2c(struct ffb_softc *); 187 188 /* Video mode setting */ 189 int ffb_tgc_disable(struct ffb_softc *); 190 void ffb_get_pclk(int, uint32_t *, int *); 191 int ffb_set_vmode(struct ffb_softc *, struct videomode *, int, int *, int *); 192 193 194 void 195 ffb_attach(device_t self) 196 { 197 struct ffb_softc *sc = device_private(self); 198 struct wsemuldisplaydev_attach_args waa; 199 struct rasops_info *ri; 200 long defattr; 201 const char *model, *out_dev; 202 int btype; 203 uint32_t dac; 204 int maxrow, maxcol; 205 u_int blank = WSDISPLAYIO_VIDEO_ON; 206 char buf[6+1]; 207 int i, try_edid; 208 prop_data_t data; 209 210 printf(":"); 211 212 if (sc->sc_type == FFB_CREATOR) { 213 btype = prom_getpropint(sc->sc_node, "board_type", 0); 214 if ((btype & 7) == 3) 215 printf(" Creator3D"); 216 else 217 printf(" Creator"); 218 } else { 219 printf(" Elite3D"); 220 btype = 0; 221 } 222 223 model = prom_getpropstring(sc->sc_node, "model"); 224 if (model == NULL || strlen(model) == 0) 225 model = "unknown"; 226 227 sc->sc_depth = 24; 228 sc->sc_linebytes = 8192; 229 /* We might alter these during EDID mode setting */ 230 sc->sc_height = prom_getpropint(sc->sc_node, "height", 0); 231 sc->sc_width = prom_getpropint(sc->sc_node, "width", 0); 232 233 sc->sc_locked = 0; 234 sc->sc_mode = WSDISPLAYIO_MODE_EMUL; 235 236 maxcol = (prom_getoption("screen-#columns", buf, sizeof buf) == 0) 237 ? strtoul(buf, NULL, 10) 238 : 80; 239 240 maxrow = (prom_getoption("screen-#rows", buf, sizeof buf) != 0) 241 ? strtoul(buf, NULL, 10) 242 : 34; 243 244 /* collect DAC version, as Elite3D cursor enable bit is reversed */ 245 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_DEVID); 246 dac = DAC_READ(sc, FFB_DAC_VALUE); 247 sc->sc_dacrev = (dac >> 28) & 0xf; 248 249 if (sc->sc_type == FFB_AFB) { 250 sc->sc_dacrev = 10; 251 sc->sc_needredraw = 0; 252 } else { 253 /* see what kind of DAC we have */ 254 int pnum = (dac & 0x0ffff000) >> 12; 255 if (pnum == 0x236e) { 256 sc->sc_needredraw = 0; 257 } else { 258 sc->sc_needredraw = 1; 259 } 260 } 261 printf(", model %s, dac %u\n", model, sc->sc_dacrev); 262 if (sc->sc_needredraw) 263 printf("%s: found old DAC, enabling redraw on unblank\n", 264 device_xname(sc->sc_dev)); 265 266 /* Check if a console resolution "<device>:r<res>" is set. */ 267 if (sc->sc_console) { 268 out_dev = prom_getpropstring(sc->sc_node, "output_device"); 269 if (out_dev != NULL && strlen(out_dev) != 0 && 270 strstr(out_dev, ":r") != NULL) 271 try_edid = 0; 272 else 273 try_edid = 1; 274 } else 275 try_edid = 1; 276 277 #if FFB_DEBUG > 0 278 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_TGC); 279 printf("tgc: %08x\n", DAC_READ(sc, FFB_DAC_VALUE)); 280 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_DAC_CTRL); 281 printf("dcl: %08x\n", DAC_READ(sc, FFB_DAC_VALUE)); 282 #endif 283 ffb_attach_i2c(sc); 284 285 /* Need to set asynchronous blank during DDC write/read */ 286 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_USR_CTRL); 287 dac = DAC_READ(sc, FFB_DAC_VALUE); 288 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_USR_CTRL); 289 DAC_WRITE(sc, FFB_DAC_VALUE, dac | FFB_DAC_USR_CTRL_BLANK); 290 291 /* Some monitors don't respond first time */ 292 i = 0; 293 while (sc->sc_edid_data[1] == 0 && i++ < 3) 294 ddc_read_edid(&sc->sc_i2c, sc->sc_edid_data, EDID_DATA_LEN); 295 296 /* Remove asynchronous blank */ 297 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_USR_CTRL); 298 DAC_WRITE(sc, FFB_DAC_VALUE, dac); 299 300 if (edid_parse(&sc->sc_edid_data[0], &sc->sc_edid_info) != -1) { 301 sort_modes(sc->sc_edid_info.edid_modes, 302 &sc->sc_edid_info.edid_preferred_mode, 303 sc->sc_edid_info.edid_nmodes); 304 DPRINTF(("%s: EDID data:\n ", device_xname(sc->sc_dev))); 305 for (i = 0; i < EDID_DATA_LEN; i++) { 306 if (i && !(i % 32)) 307 DPRINTF(("\n ")); 308 if (i && !(i % 4)) 309 DPRINTF((" ")); 310 DPRINTF(("%02x", sc->sc_edid_data[i])); 311 } 312 DPRINTF(("\n")); 313 if (ffb_debug) 314 edid_print(&sc->sc_edid_info); 315 316 data = prop_data_create_data(sc->sc_edid_data, EDID_DATA_LEN); 317 prop_dictionary_set(device_properties(self), "EDID", data); 318 prop_object_release(data); 319 320 if (try_edid) 321 for (i = 0; i < sc->sc_edid_info.edid_nmodes; i++) { 322 if (ffb_set_vmode(sc, 323 &(sc->sc_edid_info.edid_modes[i]), btype, 324 &(sc->sc_width), &(sc->sc_height))) 325 break; 326 } 327 } else { 328 DPRINTF(("%s: No EDID data.\n", device_xname(sc->sc_dev))); 329 } 330 331 ffb_ras_init(sc); 332 333 ffb_blank(sc, WSDISPLAYIO_SVIDEO, &blank); 334 335 sc->sc_accel = ((device_cfdata(sc->sc_dev)->cf_flags & 336 FFB_CFFLAG_NOACCEL) == 0); 337 338 wsfont_init(); 339 340 vcons_init(&sc->vd, sc, &ffb_stdscreen, &ffb_accessops); 341 sc->vd.init_screen = ffb_init_screen; 342 343 /* we mess with ffb_console_screen only once */ 344 if (sc->sc_console) { 345 vcons_init_screen(&sc->vd, &ffb_console_screen, 1, &defattr); 346 SCREEN_VISIBLE((&ffb_console_screen)); 347 /* 348 * XXX we shouldn't use a global variable for the console 349 * screen 350 */ 351 sc->vd.active = &ffb_console_screen; 352 ffb_console_screen.scr_flags = VCONS_SCREEN_IS_STATIC; 353 } else { 354 if (ffb_console_screen.scr_ri.ri_rows == 0) { 355 /* do some minimal setup to avoid weirdnesses later */ 356 vcons_init_screen(&sc->vd, &ffb_console_screen, 1, &defattr); 357 } 358 } 359 ri = &ffb_console_screen.scr_ri; 360 361 ffb_stdscreen.nrows = ri->ri_rows; 362 ffb_stdscreen.ncols = ri->ri_cols; 363 ffb_stdscreen.textops = &ri->ri_ops; 364 ffb_stdscreen.capabilities = ri->ri_caps; 365 366 sc->sc_fb.fb_driver = &ffb_fbdriver; 367 sc->sc_fb.fb_type.fb_cmsize = 0; 368 sc->sc_fb.fb_type.fb_size = maxrow * sc->sc_linebytes; 369 sc->sc_fb.fb_type.fb_type = FBTYPE_CREATOR; 370 sc->sc_fb.fb_type.fb_width = sc->sc_width; 371 sc->sc_fb.fb_type.fb_depth = sc->sc_depth; 372 sc->sc_fb.fb_type.fb_height = sc->sc_height; 373 sc->sc_fb.fb_device = sc->sc_dev; 374 fb_attach(&sc->sc_fb, sc->sc_console); 375 376 ffb_clearscreen(sc); 377 378 if (sc->sc_console) { 379 wsdisplay_cnattach(&ffb_stdscreen, ri, 0, 0, defattr); 380 vcons_replay_msgbuf(&ffb_console_screen); 381 } 382 383 waa.console = sc->sc_console; 384 waa.scrdata = &ffb_screenlist; 385 waa.accessops = &ffb_accessops; 386 waa.accesscookie = &sc->vd; 387 config_found(sc->sc_dev, &waa, wsemuldisplaydevprint); 388 } 389 390 void 391 ffb_attach_i2c(struct ffb_softc *sc) 392 { 393 394 /* Fill in the i2c tag */ 395 sc->sc_i2c.ic_cookie = sc; 396 sc->sc_i2c.ic_acquire_bus = ffb_i2c_acquire_bus; 397 sc->sc_i2c.ic_release_bus = ffb_i2c_release_bus; 398 sc->sc_i2c.ic_send_start = ffb_i2c_send_start; 399 sc->sc_i2c.ic_send_stop = ffb_i2c_send_stop; 400 sc->sc_i2c.ic_initiate_xfer = ffb_i2c_initiate_xfer; 401 sc->sc_i2c.ic_read_byte = ffb_i2c_read_byte; 402 sc->sc_i2c.ic_write_byte = ffb_i2c_write_byte; 403 sc->sc_i2c.ic_exec = NULL; 404 } 405 406 int 407 ffb_ioctl(void *v, void *vs, u_long cmd, void *data, int flags, struct lwp *l) 408 { 409 struct vcons_data *vd = v; 410 struct ffb_softc *sc = vd->cookie; 411 struct wsdisplay_fbinfo *wdf; 412 struct vcons_screen *ms = vd->active; 413 414 DPRINTF(("ffb_ioctl: %s cmd _IO%s%s('%c', %lu)\n", 415 device_xname(sc->sc_dev), 416 (cmd & IOC_IN) ? "W" : "", (cmd & IOC_OUT) ? "R" : "", 417 (char)IOCGROUP(cmd), cmd & 0xff)); 418 419 switch (cmd) { 420 case FBIOGTYPE: 421 *(struct fbtype *)data = sc->sc_fb.fb_type; 422 break; 423 case FBIOGATTR: 424 #define fba ((struct fbgattr *)data) 425 fba->real_type = sc->sc_fb.fb_type.fb_type; 426 fba->owner = 0; /* XXX ??? */ 427 fba->fbtype = sc->sc_fb.fb_type; 428 fba->sattr.flags = 0; 429 fba->sattr.emu_type = sc->sc_fb.fb_type.fb_type; 430 fba->sattr.dev_specific[0] = -1; 431 fba->emu_types[0] = sc->sc_fb.fb_type.fb_type; 432 fba->emu_types[1] = -1; 433 #undef fba 434 break; 435 436 case FBIOGETCMAP: 437 case FBIOPUTCMAP: 438 return EIO; 439 440 case FBIOGVIDEO: 441 case FBIOSVIDEO: 442 return ffb_blank(sc, cmd == FBIOGVIDEO? 443 WSDISPLAYIO_GVIDEO : WSDISPLAYIO_SVIDEO, 444 (u_int *)data); 445 break; 446 case FBIOGCURSOR: 447 case FBIOSCURSOR: 448 /* the console driver is not using the hardware cursor */ 449 break; 450 case FBIOGCURPOS: 451 printf("%s: FBIOGCURPOS not implemented\n", 452 device_xname(sc->sc_dev)); 453 return EIO; 454 case FBIOSCURPOS: 455 printf("%s: FBIOSCURPOS not implemented\n", 456 device_xname(sc->sc_dev)); 457 return EIO; 458 case FBIOGCURMAX: 459 printf("%s: FBIOGCURMAX not implemented\n", 460 device_xname(sc->sc_dev)); 461 return EIO; 462 463 case WSDISPLAYIO_GTYPE: 464 *(u_int *)data = WSDISPLAY_TYPE_SUNFFB; 465 break; 466 case WSDISPLAYIO_SMODE: 467 { 468 if (sc->sc_mode != *(u_int *)data) { 469 sc->sc_mode = *(u_int *)data; 470 if ((sc->sc_mode == WSDISPLAYIO_MODE_EMUL) && 471 (sc->sc_locked == 0)) { 472 ffb_ras_init(sc); 473 vcons_redraw_screen(ms); 474 } 475 } 476 } 477 break; 478 case WSDISPLAYIO_GINFO: 479 wdf = (void *)data; 480 wdf->height = sc->sc_height; 481 wdf->width = sc->sc_width; 482 wdf->depth = 32; 483 wdf->cmsize = 256; /* XXX */ 484 break; 485 #ifdef WSDISPLAYIO_LINEBYTES 486 case WSDISPLAYIO_LINEBYTES: 487 *(u_int *)data = sc->sc_linebytes; 488 break; 489 #endif 490 case WSDISPLAYIO_GETCMAP: 491 break;/* XXX */ 492 493 case WSDISPLAYIO_PUTCMAP: 494 break;/* XXX */ 495 496 case WSDISPLAYIO_SVIDEO: 497 case WSDISPLAYIO_GVIDEO: 498 return(ffb_blank(sc, cmd, (u_int *)data)); 499 break; 500 case WSDISPLAYIO_GCURPOS: 501 case WSDISPLAYIO_SCURPOS: 502 case WSDISPLAYIO_GCURMAX: 503 case WSDISPLAYIO_GCURSOR: 504 case WSDISPLAYIO_SCURSOR: 505 return EIO; /* not supported yet */ 506 break; 507 case WSDISPLAYIO_GET_EDID: { 508 struct wsdisplayio_edid_info *d = data; 509 return wsdisplayio_get_edid(sc->sc_dev, d); 510 } 511 default: 512 return EPASSTHROUGH; 513 } 514 515 return (0); 516 } 517 518 /* blank/unblank the screen */ 519 static int 520 ffb_blank(struct ffb_softc *sc, u_long cmd, u_int *data) 521 { 522 struct vcons_screen *ms = sc->vd.active; 523 u_int val; 524 525 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_TGC); 526 val = DAC_READ(sc, FFB_DAC_VALUE); 527 528 switch (cmd) { 529 case WSDISPLAYIO_GVIDEO: 530 *data = val & 1; 531 return(0); 532 break; 533 case WSDISPLAYIO_SVIDEO: 534 if (*data == WSDISPLAYIO_VIDEO_OFF) 535 val &= ~1; 536 else if (*data == WSDISPLAYIO_VIDEO_ON) 537 val |= 1; 538 else 539 return(EINVAL); 540 break; 541 default: 542 return(EINVAL); 543 } 544 545 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_TGC); 546 DAC_WRITE(sc, FFB_DAC_VALUE, val); 547 548 if ((val & 1) && sc->sc_needredraw) { 549 if (ms != NULL) { 550 if ((sc->sc_mode == WSDISPLAYIO_MODE_EMUL) && 551 (sc->sc_locked == 0)) { 552 ffb_ras_init(sc); 553 vcons_redraw_screen(ms); 554 } 555 } 556 } 557 558 return(0); 559 } 560 561 paddr_t 562 ffb_mmap(void *vsc, void *vs, off_t off, int prot) 563 { 564 struct vcons_data *vd = vsc; 565 struct ffb_softc *sc = vd->cookie; 566 int i; 567 568 switch (sc->sc_mode) { 569 case WSDISPLAYIO_MODE_MAPPED: 570 for (i = 0; i < sc->sc_nreg; i++) { 571 /* Before this set? */ 572 if (off < sc->sc_addrs[i]) 573 continue; 574 /* After this set? */ 575 if (off >= (sc->sc_addrs[i] + sc->sc_sizes[i])) 576 continue; 577 578 return (bus_space_mmap(sc->sc_bt, sc->sc_addrs[i], 579 off - sc->sc_addrs[i], prot, BUS_SPACE_MAP_LINEAR)); 580 } 581 break; 582 #ifdef WSDISPLAYIO_MODE_DUMBFB 583 case WSDISPLAYIO_MODE_DUMBFB: 584 if (sc->sc_nreg < FFB_REG_DFB24) 585 break; 586 if (off >= 0 && off < sc->sc_sizes[FFB_REG_DFB24]) 587 return (bus_space_mmap(sc->sc_bt, 588 sc->sc_addrs[FFB_REG_DFB24], off, prot, 589 BUS_SPACE_MAP_LINEAR)); 590 break; 591 #endif 592 } 593 return (-1); 594 } 595 596 void 597 ffb_ras_fifo_wait(struct ffb_softc *sc, int n) 598 { 599 int32_t cache = sc->sc_fifo_cache; 600 601 if (cache < n) { 602 do { 603 cache = FBC_READ(sc, FFB_FBC_UCSR); 604 cache = (cache & FBC_UCSR_FIFO_MASK) - 8; 605 } while (cache < n); 606 } 607 sc->sc_fifo_cache = cache - n; 608 } 609 610 void 611 ffb_ras_wait(struct ffb_softc *sc) 612 { 613 uint32_t ucsr, r; 614 615 while (1) { 616 ucsr = FBC_READ(sc, FFB_FBC_UCSR); 617 if ((ucsr & (FBC_UCSR_FB_BUSY|FBC_UCSR_RP_BUSY)) == 0) 618 break; 619 r = ucsr & (FBC_UCSR_READ_ERR | FBC_UCSR_FIFO_OVFL); 620 if (r != 0) 621 FBC_WRITE(sc, FFB_FBC_UCSR, r); 622 } 623 } 624 625 void 626 ffb_ras_init(struct ffb_softc *sc) 627 { 628 uint32_t fbc; 629 630 if (sc->sc_width > 1280) { 631 DPRINTF(("ffb_ras_init: high resolution.\n")); 632 fbc = FFB_FBC_WM_COMBINED | FFB_FBC_WE_FORCEON | 633 FFB_FBC_ZE_OFF | FFB_FBC_YE_OFF | FFB_FBC_XE_ON; 634 } else { 635 DPRINTF(("ffb_ras_init: standard resolution.\n")); 636 fbc = FFB_FBC_XE_OFF; 637 } 638 ffb_ras_fifo_wait(sc, 11); 639 DPRINTF(("WID: %08x\n", FBC_READ(sc, FFB_FBC_WID))); 640 FBC_WRITE(sc, FFB_FBC_WID, 0x0); 641 FBC_WRITE(sc, FFB_FBC_PPC, 642 FBC_PPC_VCE_DIS | FBC_PPC_TBE_OPAQUE | FBC_PPC_ACE_DIS | 643 FBC_PPC_APE_DIS | FBC_PPC_DCE_DIS | FBC_PPC_CS_CONST | 644 FBC_PPC_ABE_DIS | FBC_PPC_XS_WID); 645 646 fbc |= FFB_FBC_WB_A | FFB_FBC_RB_A | FFB_FBC_SB_BOTH | 647 FFB_FBC_RGBE_MASK; 648 DPRINTF(("%s: fbc is %08x\n", __func__, fbc)); 649 FBC_WRITE(sc, FFB_FBC_FBC, fbc); 650 FBC_WRITE(sc, FFB_FBC_ROP, FBC_ROP_NEW); 651 FBC_WRITE(sc, FFB_FBC_DRAWOP, FBC_DRAWOP_RECTANGLE); 652 FBC_WRITE(sc, FFB_FBC_PMASK, 0xffffffff); 653 FBC_WRITE(sc, FFB_FBC_FONTINC, 0x10000); 654 sc->sc_fg_cache = 0; 655 FBC_WRITE(sc, FFB_FBC_FG, sc->sc_fg_cache); 656 FBC_WRITE(sc, FFB_FBC_BLENDC, FFB_BLENDC_FORCE_ONE | 657 FFB_BLENDC_DF_ONE_M_A | 658 FFB_BLENDC_SF_A); 659 FBC_WRITE(sc, FFB_FBC_BLENDC1, 0); 660 FBC_WRITE(sc, FFB_FBC_BLENDC2, 0); 661 ffb_ras_wait(sc); 662 } 663 664 void 665 ffb_ras_eraserows(void *cookie, int row, int n, long attr) 666 { 667 struct rasops_info *ri = cookie; 668 struct vcons_screen *scr = ri->ri_hw; 669 struct ffb_softc *sc = scr->scr_cookie; 670 671 if (row < 0) { 672 n += row; 673 row = 0; 674 } 675 if (row + n > ri->ri_rows) 676 n = ri->ri_rows - row; 677 if (n <= 0) 678 return; 679 680 ffb_ras_fill(sc); 681 ffb_ras_setfg(sc, ri->ri_devcmap[(attr >> 16) & 0xf]); 682 ffb_ras_fifo_wait(sc, 4); 683 if ((n == ri->ri_rows) && (ri->ri_flg & RI_FULLCLEAR)) { 684 FBC_WRITE(sc, FFB_FBC_BY, 0); 685 FBC_WRITE(sc, FFB_FBC_BX, 0); 686 FBC_WRITE(sc, FFB_FBC_BH, ri->ri_height); 687 FBC_WRITE(sc, FFB_FBC_BW, ri->ri_width); 688 } else { 689 row *= ri->ri_font->fontheight; 690 FBC_WRITE(sc, FFB_FBC_BY, ri->ri_yorigin + row); 691 FBC_WRITE(sc, FFB_FBC_BX, ri->ri_xorigin); 692 FBC_WRITE(sc, FFB_FBC_BH, n * ri->ri_font->fontheight); 693 FBC_WRITE(sc, FFB_FBC_BW, ri->ri_emuwidth); 694 } 695 SYNC; 696 } 697 698 void 699 ffb_ras_erasecols(void *cookie, int row, int col, int n, long attr) 700 { 701 struct rasops_info *ri = cookie; 702 struct vcons_screen *scr = ri->ri_hw; 703 struct ffb_softc *sc = scr->scr_cookie; 704 705 if ((row < 0) || (row >= ri->ri_rows)) 706 return; 707 if (col < 0) { 708 n += col; 709 col = 0; 710 } 711 if (col + n > ri->ri_cols) 712 n = ri->ri_cols - col; 713 if (n <= 0) 714 return; 715 n *= ri->ri_font->fontwidth; 716 col *= ri->ri_font->fontwidth; 717 row *= ri->ri_font->fontheight; 718 719 ffb_ras_fill(sc); 720 ffb_ras_setfg(sc, ri->ri_devcmap[(attr >> 16) & 0xf]); 721 ffb_ras_fifo_wait(sc, 4); 722 FBC_WRITE(sc, FFB_FBC_BY, ri->ri_yorigin + row); 723 FBC_WRITE(sc, FFB_FBC_BX, ri->ri_xorigin + col); 724 FBC_WRITE(sc, FFB_FBC_BH, ri->ri_font->fontheight); 725 FBC_WRITE(sc, FFB_FBC_BW, n - 1); 726 SYNC; 727 } 728 729 void 730 ffb_ras_fill(struct ffb_softc *sc) 731 { 732 ffb_ras_fifo_wait(sc, 3); 733 FBC_WRITE(sc, FFB_FBC_PPC, 734 FBC_PPC_VCE_DIS | FBC_PPC_TBE_OPAQUE | FBC_PPC_ACE_DIS | 735 FBC_PPC_APE_DIS | FBC_PPC_DCE_DIS | FBC_PPC_CS_CONST | 736 FBC_PPC_ABE_DIS | FBC_PPC_XS_WID); 737 FBC_WRITE(sc, FFB_FBC_ROP, FBC_ROP_NEW); 738 FBC_WRITE(sc, FFB_FBC_DRAWOP, FBC_DRAWOP_RECTANGLE); 739 SYNC; 740 } 741 742 void 743 ffb_ras_invert(struct ffb_softc *sc) 744 { 745 ffb_ras_fifo_wait(sc, 3); 746 FBC_WRITE(sc, FFB_FBC_PPC, 747 FBC_PPC_VCE_DIS | FBC_PPC_TBE_OPAQUE | FBC_PPC_ACE_DIS | 748 FBC_PPC_APE_DIS | FBC_PPC_DCE_DIS | FBC_PPC_CS_CONST | 749 FBC_PPC_ABE_DIS | FBC_PPC_XS_WID); 750 FBC_WRITE(sc, FFB_FBC_ROP, FBC_ROP_INVERT); 751 FBC_WRITE(sc, FFB_FBC_DRAWOP, FBC_DRAWOP_RECTANGLE); 752 SYNC; 753 } 754 755 void 756 ffb_ras_copyrows(void *cookie, int src, int dst, int n) 757 { 758 struct rasops_info *ri = cookie; 759 struct vcons_screen *scr = ri->ri_hw; 760 struct ffb_softc *sc = scr->scr_cookie; 761 762 if (dst == src) 763 return; 764 if (src < 0) { 765 n += src; 766 src = 0; 767 } 768 if ((src + n) > ri->ri_rows) 769 n = ri->ri_rows - src; 770 if (dst < 0) { 771 n += dst; 772 dst = 0; 773 } 774 if ((dst + n) > ri->ri_rows) 775 n = ri->ri_rows - dst; 776 if (n <= 0) 777 return; 778 n *= ri->ri_font->fontheight; 779 src *= ri->ri_font->fontheight; 780 dst *= ri->ri_font->fontheight; 781 782 ffb_ras_fifo_wait(sc, 9); 783 FBC_WRITE(sc, FFB_FBC_PPC, 784 FBC_PPC_VCE_DIS | FBC_PPC_TBE_OPAQUE | FBC_PPC_ACE_DIS | 785 FBC_PPC_APE_DIS | FBC_PPC_DCE_DIS | FBC_PPC_CS_CONST | 786 FBC_PPC_ABE_DIS | FBC_PPC_XS_WID); 787 FBC_WRITE(sc, FFB_FBC_ROP, FBC_ROP_OLD | (FBC_ROP_OLD << 8)); 788 FBC_WRITE(sc, FFB_FBC_DRAWOP, FBC_DRAWOP_VSCROLL); 789 FBC_WRITE(sc, FFB_FBC_BY, ri->ri_yorigin + src); 790 FBC_WRITE(sc, FFB_FBC_BX, ri->ri_xorigin); 791 FBC_WRITE(sc, FFB_FBC_DY, ri->ri_yorigin + dst); 792 FBC_WRITE(sc, FFB_FBC_DX, ri->ri_xorigin); 793 FBC_WRITE(sc, FFB_FBC_BH, n); 794 FBC_WRITE(sc, FFB_FBC_BW, ri->ri_emuwidth); 795 SYNC; 796 } 797 798 static void 799 ffb_ras_setfg(struct ffb_softc *sc, int32_t fg) 800 { 801 ffb_ras_fifo_wait(sc, 1); 802 if (fg == sc->sc_fg_cache) 803 return; 804 sc->sc_fg_cache = fg; 805 FBC_WRITE(sc, FFB_FBC_FG, fg); 806 SYNC; 807 } 808 809 static void 810 ffb_ras_setbg(struct ffb_softc *sc, int32_t bg) 811 { 812 ffb_ras_fifo_wait(sc, 1); 813 if (bg == sc->sc_bg_cache) 814 return; 815 sc->sc_bg_cache = bg; 816 FBC_WRITE(sc, FFB_FBC_BG, bg); 817 SYNC; 818 } 819 820 /* frame buffer generic driver support functions */ 821 static void 822 ffbfb_unblank(device_t dev) 823 { 824 struct ffb_softc *sc = device_private(dev); 825 struct vcons_screen *ms = sc->vd.active; 826 u_int on = 1; 827 int redraw = 0; 828 829 ffb_ras_init(sc); 830 if (sc->sc_locked) { 831 sc->sc_locked = 0; 832 redraw = 1; 833 } 834 835 ffb_blank(sc, WSDISPLAYIO_SVIDEO, &on); 836 #if 0 837 if ((sc->vd.active != &ffb_console_screen) && 838 (ffb_console_screen.scr_flags & VCONS_SCREEN_IS_STATIC)) { 839 /* 840 * force-switch to the console screen. 841 * Caveat: the higher layer will think we're still on the 842 * other screen 843 */ 844 845 SCREEN_INVISIBLE(sc->vd.active); 846 sc->vd.active = &ffb_console_screen; 847 SCREEN_VISIBLE(sc->vd.active); 848 ms = sc->vd.active; 849 redraw = 1; 850 } 851 #endif 852 if (redraw) { 853 vcons_redraw_screen(ms); 854 } 855 } 856 857 int 858 ffbfb_open(dev_t dev, int flags, int mode, struct lwp *l) 859 { 860 struct ffb_softc *sc; 861 862 sc = device_lookup_private(&ffb_cd, minor(dev)); 863 if (sc == NULL) 864 return ENXIO; 865 866 sc->sc_locked = 1; 867 return 0; 868 } 869 870 int 871 ffbfb_close(dev_t dev, int flags, int mode, struct lwp *l) 872 { 873 struct ffb_softc *sc = device_lookup_private(&ffb_cd, minor(dev)); 874 struct vcons_screen *ms = sc->vd.active; 875 876 sc->sc_locked = 0; 877 if (ms != NULL) { 878 if ((sc->sc_mode == WSDISPLAYIO_MODE_EMUL) && 879 (sc->sc_locked == 0)) { 880 ffb_ras_init(sc); 881 vcons_redraw_screen(ms); 882 } 883 } 884 return 0; 885 } 886 887 int 888 ffbfb_ioctl(dev_t dev, u_long cmd, void *data, int flags, struct lwp *l) 889 { 890 struct ffb_softc *sc = device_lookup_private(&ffb_cd, minor(dev)); 891 892 return ffb_ioctl(&sc->vd, NULL, cmd, data, flags, l); 893 } 894 895 paddr_t 896 ffbfb_mmap(dev_t dev, off_t off, int prot) 897 { 898 struct ffb_softc *sc = device_lookup_private(&ffb_cd, minor(dev)); 899 uint64_t size; 900 int i, reg; 901 off_t o; 902 903 /* 904 * off is a magic cookie (see xfree86/drivers/sunffb/ffb.h), 905 * which we map to an index into the "reg" property, and use 906 * our copy of the firmware data as arguments for the real 907 * mapping. 908 */ 909 static struct { unsigned long voff; int reg; } map[] = { 910 { 0x00000000, FFB_REG_SFB8R }, 911 { 0x00400000, FFB_REG_SFB8G }, 912 { 0x00800000, FFB_REG_SFB8B }, 913 { 0x00c00000, FFB_REG_SFB8X }, 914 { 0x01000000, FFB_REG_SFB32 }, 915 { 0x02000000, FFB_REG_SFB64 }, 916 { 0x04000000, FFB_REG_FBC }, 917 { 0x04004000, FFB_REG_DFB8R }, 918 { 0x04404000, FFB_REG_DFB8G }, 919 { 0x04804000, FFB_REG_DFB8B }, 920 { 0x04c04000, FFB_REG_DFB8X }, 921 { 0x05004000, FFB_REG_DFB24 }, 922 { 0x06004000, FFB_REG_DFB32 }, 923 { 0x07004000, FFB_REG_DFB422A }, 924 { 0x0bc06000, FFB_REG_DAC }, 925 { 0x0bc08000, FFB_REG_PROM }, 926 { 0x0bc18000, 0 } 927 }; 928 929 /* special value "FFB_EXP_VOFF" - not backed by any "reg" entry */ 930 if (off == 0x0bc18000) 931 return bus_space_mmap(sc->sc_bt, sc->sc_addrs[FFB_REG_PROM], 932 0x00200000, prot, BUS_SPACE_MAP_LINEAR); 933 934 /* 935 * FFB_VOFF_FBC_KREGS - used by afbinit to upload firmware. We should 936 * probably mmap them only on afb boards 937 */ 938 if ((off >= 0x0bc04000) && (off < 0x0bc06000)) 939 return bus_space_mmap(sc->sc_bt, sc->sc_addrs[FFB_REG_PROM], 940 0x00610000 + (off - 0x0bc04000), prot, 941 BUS_SPACE_MAP_LINEAR); 942 943 #define NELEMS(arr) (sizeof(arr)/sizeof((arr)[0])) 944 945 /* the map is ordered by voff */ 946 for (i = 0; i < NELEMS(map)-1; i++) { 947 reg = map[i].reg; 948 /* the number of entries in reg seems to vary */ 949 if (reg < sc->sc_nreg) { 950 size = min((map[i + 1].voff - map[i].voff), 951 sc->sc_sizes[reg]); 952 if ((off >= map[i].voff) && 953 (off < (map[i].voff + size))) { 954 o = off - map[i].voff; 955 return bus_space_mmap(sc->sc_bt, 956 sc->sc_addrs[reg], o, prot, 957 BUS_SPACE_MAP_LINEAR); 958 } 959 } 960 } 961 962 return -1; 963 } 964 965 void 966 ffb_clearscreen(struct ffb_softc *sc) 967 { 968 struct rasops_info *ri = &ffb_console_screen.scr_ri; 969 ffb_ras_fill(sc); 970 ffb_ras_setfg(sc, ri->ri_devcmap[WS_DEFAULT_BG]); 971 ffb_ras_fifo_wait(sc, 4); 972 FBC_WRITE(sc, FFB_FBC_BY, 0); 973 FBC_WRITE(sc, FFB_FBC_BX, 0); 974 FBC_WRITE(sc, FFB_FBC_BH, sc->sc_height); 975 FBC_WRITE(sc, FFB_FBC_BW, sc->sc_width); 976 } 977 978 void 979 ffb_cursor(void *cookie, int on, int row, int col) 980 { 981 struct rasops_info *ri = cookie; 982 struct vcons_screen *scr; 983 struct ffb_softc *sc; 984 int x, y, wi, he; 985 986 if (cookie != NULL) { 987 scr = ri->ri_hw; 988 sc = scr->scr_cookie; 989 990 wi = ri->ri_font->fontwidth; 991 he = ri->ri_font->fontheight; 992 993 if (sc->sc_mode == WSDISPLAYIO_MODE_EMUL) { 994 995 if (ri->ri_flg & RI_CURSOR) { 996 997 /* remove cursor */ 998 x = ri->ri_ccol * wi + ri->ri_xorigin; 999 y = ri->ri_crow * he + ri->ri_yorigin; 1000 1001 ffb_ras_invert(sc); 1002 ffb_ras_fifo_wait(sc, 4); 1003 FBC_WRITE(sc, FFB_FBC_BY, y); 1004 FBC_WRITE(sc, FFB_FBC_BX, x); 1005 FBC_WRITE(sc, FFB_FBC_BH, he); 1006 FBC_WRITE(sc, FFB_FBC_BW, wi); 1007 1008 ri->ri_flg &= ~RI_CURSOR; 1009 } 1010 ri->ri_crow = row; 1011 ri->ri_ccol = col; 1012 if (on) 1013 { 1014 x = ri->ri_ccol * wi + ri->ri_xorigin; 1015 y = ri->ri_crow * he + ri->ri_yorigin; 1016 1017 ffb_ras_invert(sc); 1018 ffb_ras_fifo_wait(sc, 4); 1019 FBC_WRITE(sc, FFB_FBC_BY, y); 1020 FBC_WRITE(sc, FFB_FBC_BX, x); 1021 FBC_WRITE(sc, FFB_FBC_BH, he); 1022 FBC_WRITE(sc, FFB_FBC_BW, wi); 1023 1024 ri->ri_flg |= RI_CURSOR; 1025 } 1026 } else { 1027 ri->ri_crow = row; 1028 ri->ri_ccol = col; 1029 ri->ri_flg &= ~RI_CURSOR; 1030 } 1031 } 1032 } 1033 1034 /* mono bitmap font */ 1035 void 1036 ffb_putchar_mono(void *cookie, int row, int col, u_int c, long attr) 1037 { 1038 struct rasops_info *ri = cookie; 1039 struct vcons_screen *scr = ri->ri_hw; 1040 struct wsdisplay_font *font = PICK_FONT(ri, c); 1041 struct ffb_softc *sc = scr->scr_cookie; 1042 void *data; 1043 uint32_t fg, bg; 1044 int i; 1045 int x, y, wi, he; 1046 1047 if (sc->sc_mode != WSDISPLAYIO_MODE_EMUL) 1048 return; 1049 1050 wi = font->fontwidth; 1051 he = font->fontheight; 1052 1053 if (!CHAR_IN_FONT(c, font)) 1054 return; 1055 1056 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 1057 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 1058 x = ri->ri_xorigin + col * wi; 1059 y = ri->ri_yorigin + row * he; 1060 1061 data = WSFONT_GLYPH(c, font); 1062 1063 ffb_ras_setbg(sc, bg); 1064 ffb_ras_setfg(sc, fg); 1065 ffb_ras_fifo_wait(sc, 4); 1066 FBC_WRITE(sc, FFB_FBC_ROP, FBC_ROP_NEW); 1067 FBC_WRITE(sc, FFB_FBC_FONTXY, (y << 16) | x); 1068 FBC_WRITE(sc, FFB_FBC_FONTW, wi); 1069 FBC_WRITE(sc, FFB_FBC_PPC, 1070 FBC_PPC_VCE_DIS | FBC_PPC_TBE_OPAQUE | FBC_PPC_ACE_DIS | 1071 FBC_PPC_APE_DIS | FBC_PPC_DCE_DIS | FBC_PPC_CS_CONST | 1072 FBC_PPC_ABE_DIS | FBC_PPC_XS_WID); 1073 1074 switch (font->stride) { 1075 case 1: { 1076 uint8_t *data8 = data; 1077 uint32_t reg; 1078 for (i = 0; i < he; i++) { 1079 reg = *data8; 1080 FBC_WRITE(sc, FFB_FBC_FONT, reg << 24); 1081 data8++; 1082 } 1083 break; 1084 } 1085 case 2: { 1086 uint16_t *data16 = data; 1087 uint32_t reg; 1088 for (i = 0; i < he; i++) { 1089 reg = *data16; 1090 FBC_WRITE(sc, FFB_FBC_FONT, reg << 16); 1091 data16++; 1092 } 1093 break; 1094 } 1095 } 1096 } 1097 1098 /* alpha font */ 1099 void 1100 ffb_putchar_aa(void *cookie, int row, int col, u_int c, long attr) 1101 { 1102 struct rasops_info *ri = cookie; 1103 struct vcons_screen *scr = ri->ri_hw; 1104 struct wsdisplay_font *font = PICK_FONT(ri, c); 1105 struct ffb_softc *sc = scr->scr_cookie; 1106 volatile uint32_t *dest, *ddest; 1107 uint8_t *data8; 1108 uint32_t fg, bg; 1109 int i; 1110 int x, y, wi, he; 1111 uint32_t alpha = 0x80; 1112 int j; 1113 1114 if (sc->sc_mode != WSDISPLAYIO_MODE_EMUL) 1115 return; 1116 1117 wi = font->fontwidth; 1118 he = font->fontheight; 1119 1120 if (!CHAR_IN_FONT(c, font)) 1121 return; 1122 1123 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 1124 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 1125 x = ri->ri_xorigin + col * wi; 1126 y = ri->ri_yorigin + row * he; 1127 1128 data8 = WSFONT_GLYPH(c, font); 1129 1130 /* first we erase the background */ 1131 ffb_ras_fill(sc); 1132 ffb_ras_setfg(sc, bg); 1133 ffb_ras_fifo_wait(sc, 4); 1134 FBC_WRITE(sc, FFB_FBC_BY, y); 1135 FBC_WRITE(sc, FFB_FBC_BX, x); 1136 FBC_WRITE(sc, FFB_FBC_BH, he); 1137 FBC_WRITE(sc, FFB_FBC_BW, wi); 1138 1139 /* if we draw a space we're done */ 1140 if (c == ' ') return; 1141 1142 /* now enable alpha blending */ 1143 ffb_ras_setfg(sc, fg); 1144 ffb_ras_fifo_wait(sc, 2); 1145 FBC_WRITE(sc, FFB_FBC_ROP, FBC_ROP_NEW); 1146 1147 FBC_WRITE(sc, FFB_FBC_PPC, 1148 FBC_PPC_VCE_DIS | FBC_PPC_TBE_OPAQUE | FBC_PPC_ACE_DIS | 1149 FBC_PPC_APE_DIS | FBC_PPC_DCE_DIS | FBC_PPC_CS_CONST | 1150 FBC_PPC_ABE_ENA | FBC_PPC_XS_VAR); 1151 /* 1152 * we have to wait for both the rectangle drawing op above and the 1153 * FFB_FBC_PPC write to finish before mucking around in the SFB aperture 1154 */ 1155 ffb_ras_wait(sc); 1156 1157 /* ... and draw the character */ 1158 dest = sc->sc_sfb32 + (y << 11) + x; 1159 for (i = 0; i < he; i++) { 1160 ddest = dest; 1161 for (j = 0; j < wi; j++) { 1162 alpha = *data8; 1163 /* 1164 * We set the colour source to constant above so we only 1165 * have to write the alpha channel here and the colour 1166 * comes from the FG register. It would be nice if we 1167 * could just use the SFB8X aperture and memcpy() the 1168 * alpha map line by line but for some strange reason 1169 * that will take colour info from the framebuffer even 1170 * if we set the FBC_PPC_CS_CONST bit above. 1171 */ 1172 *ddest = alpha << 24; 1173 data8++; 1174 ddest++; 1175 } 1176 dest += 2048; 1177 } 1178 } 1179 1180 int 1181 ffb_allocattr(void *cookie, int fg, int bg, int flags, long *attrp) 1182 { 1183 if ((fg == 0) && (bg == 0)) 1184 { 1185 fg = WS_DEFAULT_FG; 1186 bg = WS_DEFAULT_BG; 1187 } 1188 if (flags & WSATTR_REVERSE) { 1189 *attrp = (bg & 0xff) << 24 | (fg & 0xff) << 16 | 1190 (flags & 0xff); 1191 } else 1192 *attrp = (fg & 0xff) << 24 | (bg & 0xff) << 16 | 1193 (flags & 0xff); 1194 return 0; 1195 } 1196 1197 void 1198 ffb_init_screen(void *cookie, struct vcons_screen *scr, 1199 int existing, long *defattr) 1200 { 1201 struct ffb_softc *sc = cookie; 1202 struct rasops_info *ri = &scr->scr_ri; 1203 1204 ri->ri_depth = 32; 1205 ri->ri_width = sc->sc_width; 1206 ri->ri_height = sc->sc_height; 1207 ri->ri_stride = sc->sc_linebytes; 1208 ri->ri_flg = RI_CENTER | RI_ENABLE_ALPHA; 1209 1210 /* 1211 * we can't accelerate copycols() so instead of falling back to 1212 * software use vcons' putchar() based implementation 1213 */ 1214 scr->scr_flags |= VCONS_NO_COPYCOLS; 1215 #ifdef VCONS_DRAW_INTR 1216 scr->scr_flags |= VCONS_DONT_READ; 1217 #endif 1218 DPRINTF(("ffb_init_screen: addr: %08lx\n",(ulong)ri->ri_bits)); 1219 1220 /* explicitly request BGR in case the default changes */ 1221 ri->ri_rnum = 8; 1222 ri->ri_gnum = 8; 1223 ri->ri_bnum = 8; 1224 ri->ri_rpos = 0; 1225 ri->ri_gpos = 8; 1226 ri->ri_bpos = 16; 1227 1228 rasops_init(ri, 0, 0); 1229 ri->ri_caps = WSSCREEN_WSCOLORS; 1230 rasops_reconfig(ri, sc->sc_height / ri->ri_font->fontheight, 1231 sc->sc_width / ri->ri_font->fontwidth); 1232 1233 /* enable acceleration */ 1234 ri->ri_ops.copyrows = ffb_ras_copyrows; 1235 ri->ri_ops.eraserows = ffb_ras_eraserows; 1236 ri->ri_ops.erasecols = ffb_ras_erasecols; 1237 ri->ri_ops.cursor = ffb_cursor; 1238 ri->ri_ops.allocattr = ffb_allocattr; 1239 if (FONT_IS_ALPHA(ri->ri_font)) { 1240 ri->ri_ops.putchar = ffb_putchar_aa; 1241 } else 1242 ri->ri_ops.putchar = ffb_putchar_mono; 1243 } 1244 1245 /* I2C bitbanging */ 1246 static void ffb_i2cbb_set_bits(void *cookie, uint32_t bits) 1247 { 1248 struct ffb_softc *sc = cookie; 1249 1250 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_CFG_MPDATA); 1251 DAC_WRITE(sc, FFB_DAC_VALUE, bits); 1252 } 1253 1254 static void ffb_i2cbb_set_dir(void *cookie, uint32_t dir) 1255 { 1256 /* Nothing to do */ 1257 } 1258 1259 static uint32_t ffb_i2cbb_read(void *cookie) 1260 { 1261 struct ffb_softc *sc = cookie; 1262 uint32_t bits; 1263 1264 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_CFG_MPSENSE); 1265 bits = DAC_READ(sc, FFB_DAC_VALUE); 1266 1267 return bits; 1268 } 1269 1270 /* higher level I2C stuff */ 1271 static int 1272 ffb_i2c_acquire_bus(void *cookie, int flags) 1273 { 1274 /* private bus */ 1275 return (0); 1276 } 1277 1278 static void 1279 ffb_i2c_release_bus(void *cookie, int flags) 1280 { 1281 /* private bus */ 1282 } 1283 1284 static int 1285 ffb_i2c_send_start(void *cookie, int flags) 1286 { 1287 return (i2c_bitbang_send_start(cookie, flags, &ffb_i2cbb_ops)); 1288 } 1289 1290 static int 1291 ffb_i2c_send_stop(void *cookie, int flags) 1292 { 1293 1294 return (i2c_bitbang_send_stop(cookie, flags, &ffb_i2cbb_ops)); 1295 } 1296 1297 static int 1298 ffb_i2c_initiate_xfer(void *cookie, i2c_addr_t addr, int flags) 1299 { 1300 /* 1301 * for some reason i2c_bitbang_initiate_xfer left-shifts 1302 * the I2C-address and then sets the direction bit 1303 */ 1304 return (i2c_bitbang_initiate_xfer(cookie, addr, flags, 1305 &ffb_i2cbb_ops)); 1306 } 1307 1308 static int 1309 ffb_i2c_read_byte(void *cookie, uint8_t *valp, int flags) 1310 { 1311 return (i2c_bitbang_read_byte(cookie, valp, flags, &ffb_i2cbb_ops)); 1312 } 1313 1314 static int 1315 ffb_i2c_write_byte(void *cookie, uint8_t val, int flags) 1316 { 1317 return (i2c_bitbang_write_byte(cookie, val, flags, &ffb_i2cbb_ops)); 1318 } 1319 1320 1321 #define TVC_READ_LIMIT 100000 1322 int 1323 ffb_tgc_disable(struct ffb_softc *sc) 1324 { 1325 int i; 1326 1327 /* Is the timing generator disabled? */ 1328 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_TGC); 1329 if (!(DAC_READ(sc, FFB_DAC_VALUE) & FFB_DAC_TGC_TIMING_ENABLE)) 1330 return 1; 1331 1332 /* If not, disable it when the vertical counter reaches 0 */ 1333 for (i = 0; i < TVC_READ_LIMIT; i++) { 1334 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_TVC); 1335 if (!DAC_READ(sc, FFB_DAC_VALUE)) { 1336 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_TGC); 1337 DAC_WRITE(sc, FFB_DAC_VALUE, 0); 1338 return 1; 1339 } 1340 } 1341 return 0; 1342 } 1343 1344 /* 1345 * PLL Control Register values: 1346 * M)ultiplier = bits 0:6 + 1 1347 * D)ivisor = bits 7:10 + 1 1348 * P)ost divisor = bits 11:13 (000 = 1, 001 = 2, 010 = 4, 011 = 8) 1349 * Frequency = 13.5 * M / D / P 1350 */ 1351 #define FFB_PLL_FREQ 13500000 1352 void 1353 ffb_get_pclk(int request, uint32_t *pll, int *diff) 1354 { 1355 int m, d, p, f, hex = 0, curdiff; 1356 1357 *diff = 100000000; 1358 1359 for (m = 32; m <= 80; m++) { 1360 for (d = 4; d <= 11; d++) { 1361 for (p = 1; p <= 8; p = p << 1) { 1362 switch (p) { 1363 case 1: 1364 hex = 0x4000 + (d << 7) + m; 1365 break; 1366 case 2: 1367 hex = 0x4800 + (d << 7) + m; 1368 break; 1369 case 4: 1370 hex = 0x5000 + (d << 7) + m; 1371 break; 1372 case 8: 1373 hex = 0x6000 + (d << 7) + m; 1374 break; 1375 } 1376 f = 13500000 * m / d / p; 1377 if (f == request) { 1378 *diff = 0; 1379 *pll = hex; 1380 return; 1381 } else { 1382 curdiff = abs(request - f); 1383 if (curdiff < *diff) { 1384 *diff = curdiff; 1385 *pll = hex; 1386 } 1387 } 1388 } 1389 } 1390 } 1391 } 1392 1393 /* 1394 * Details of the FFB RAMDAC are contained in the Brooktree BT497/498 1395 * and in the Connexant BT497A/498A documentation. 1396 * 1397 * VESA timings to FFB register conversion: 1398 * If interleave = 4/2:1 then x = 2, if interleave = 8/2:1 then x = 4 1399 * VBE = VBS - vres = (sync pulse - 1) + back porch 1400 * VBS = VSS - front porch = (sync pulse - 1) + back porch + vres 1401 * VSE = sync pulse - 1 1402 * VSS = (sync pulse - 1) + back porch + vres + front porch 1403 * HRE = HSS - HSE - 1 1404 * HBE = (sync pulse + back porch) / x - 1 1405 * HBS = (sync pulse + back porch + hres) / x - 1 1406 * HSE = sync pulse / x - 1 1407 * HSS = (sync pulse + back porch + hres + front porch) / x - 1 1408 * HCE = HBS - 4 1409 * HCS = HBE - 4 1410 * EPE = EIE = EIS = 0 (for all non-interlaced modes) 1411 * 1412 * Note, that 8/2:1 Single Buffered Interleaving is only supported by the 1413 * double-buffered FFB (Creator3D), and at higher resolutions than 1280x1024 1414 * 1415 * Note, that the timing generator should be disabled and re-enabled when the 1416 * the timing parameter registers are being programmed. Stopping the timing 1417 * generator should only be done when the vertical counter is zero. 1418 */ 1419 #define DIVIDE(x,y) (((x) + ((y) / 2)) / (y)) 1420 int 1421 ffb_set_vmode(struct ffb_softc *sc, struct videomode *mode, int btype, 1422 int *hres, int *vres) 1423 { 1424 int diff; 1425 uint32_t fp, sp, bp, x; 1426 uint32_t pll, pfc, ucl, dcl, tgc; 1427 uint32_t vbe, vbs, vse, vss, hre, hbe, hbs, hse, hss, hce, hcs; 1428 uint32_t epe, eie, eis; 1429 uint32_t fbcfg0; 1430 1431 DPRINTF(("ffb_set_vmode: %dx%d@%d", mode->hdisplay, mode->vdisplay, 1432 DIVIDE(DIVIDE(mode->dot_clock * 1000, 1433 mode->htotal), mode->vtotal))); 1434 DPRINTF((" (%d %d %d %d %d %d %d", 1435 mode->dot_clock, mode->hsync_start, mode->hsync_end, mode->htotal, 1436 mode->vsync_start, mode->vsync_end, mode->vtotal)); 1437 DPRINTF((" %s%sH %s%sV)\n", 1438 mode->flags & VID_PHSYNC ? "+" : "", 1439 mode->flags & VID_NHSYNC ? "-" : "", 1440 mode->flags & VID_PVSYNC ? "+" : "", 1441 mode->flags & VID_NVSYNC ? "-" : "")); 1442 1443 /* We don't handle interlaced or doublescan (yet) */ 1444 if ((mode->flags & VID_INTERLACE) || (mode->flags & VID_DBLSCAN)) 1445 return 0; 1446 1447 /* Only Creator3D can be set to > 1280x1024 */ 1448 if(((sc->sc_type == FFB_CREATOR && !((btype & 7) == 3)) || 1449 sc->sc_type == FFB_AFB) 1450 && (mode->hdisplay > 1280 || mode->vdisplay > 1024)) 1451 return 0; 1452 /* Creator3D can be set to <= 1920x1360 */ 1453 if (mode->hdisplay > 1920 || mode->vdisplay > 1360) 1454 return 0; 1455 1456 /* 1457 * Look for a matching pixel clock and set PLL Control. 1458 * XXX: 640x480@60 is 25175000 in modelines but 25125000 in the 1459 * FFB PROM, and the closest match to 25175000 (0x4da9/25159090) 1460 * does not work. So, use the PROM value instead. 1461 */ 1462 if (mode->hdisplay == 640 && mode->vdisplay == 480 && 1463 mode->dot_clock == 25175) { 1464 DPRINTF(("ffb_set_vmode: 640x480@60: adjusted dot clock\n")); 1465 mode->dot_clock = 25125; 1466 } 1467 ffb_get_pclk(mode->dot_clock * 1000, &pll, &diff); 1468 if (diff > 250000) 1469 return 0; 1470 1471 /* Pixel Format Control, User Control and FBC Configuration. */ 1472 if (mode->hdisplay > 1280) { 1473 pfc = FFB_DAC_PIX_FMT_821; 1474 ucl = FFB_DAC_USR_CTRL_OVERLAY | FFB_DAC_USR_CTRL_WMODE_C; 1475 x = 4; 1476 fbcfg0 = FBC_READ(sc, FFB_FBC_FBCFG0) | FBC_CFG0_DOUBLE_BUF; 1477 } else { 1478 pfc = FFB_DAC_PIX_FMT_421; 1479 /* Only Creator3D and Elite3D can have double-buffer */ 1480 if ((sc->sc_type == FFB_CREATOR && !((btype & 7) == 3))) 1481 ucl = 0; 1482 else 1483 ucl = FFB_DAC_USR_CTRL_DOUBLE; 1484 ucl |= (FFB_DAC_USR_CTRL_OVERLAY | FFB_DAC_USR_CTRL_WMODE_S8); 1485 x = 2; 1486 fbcfg0 = FBC_READ(sc, FFB_FBC_FBCFG0) | FBC_CFG0_SINGLE_BUF; 1487 } 1488 1489 /* DAC Control and Timing Generator Control */ 1490 if (mode->flags & VID_PVSYNC) 1491 dcl = FFB_DAC_DAC_CTRL_POS_VSYNC; 1492 else 1493 dcl = 0; 1494 tgc = 0; 1495 #define EDID_VID_INP sc->sc_edid_info.edid_video_input 1496 if ((EDID_VID_INP & EDID_VIDEO_INPUT_COMPOSITE_SYNC)) { 1497 dcl |= FFB_DAC_DAC_CTRL_VSYNC_DIS; 1498 tgc = FFB_DAC_TGC_EQUAL_DISABLE; 1499 } else { 1500 dcl |= FFB_DAC_DAC_CTRL_SYNC_G; 1501 if (EDID_VID_INP & EDID_VIDEO_INPUT_SEPARATE_SYNCS) 1502 tgc |= FFB_DAC_TGC_VSYNC_DISABLE; 1503 else 1504 tgc = FFB_DAC_TGC_EQUAL_DISABLE; 1505 } 1506 if (EDID_VID_INP & EDID_VIDEO_INPUT_BLANK_TO_BLACK) 1507 dcl |= FFB_DAC_DAC_CTRL_PED_ENABLE; 1508 tgc |= (FFB_DAC_TGC_VIDEO_ENABLE | FFB_DAC_TGC_TIMING_ENABLE | 1509 FFB_DAC_TGC_MASTER_ENABLE); 1510 1511 /* Vertical timing */ 1512 fp = mode->vsync_start - mode->vdisplay; 1513 sp = mode->vsync_end - mode->vsync_start; 1514 bp = mode->vtotal - mode->vsync_end; 1515 1516 vbe = sp - 1 + bp; 1517 vbs = sp - 1 + bp + mode->vdisplay; 1518 vse = sp - 1; 1519 vss = sp - 1 + bp + mode->vdisplay + fp; 1520 1521 /* Horizontal timing */ 1522 fp = mode->hsync_start - mode->hdisplay; 1523 sp = mode->hsync_end - mode->hsync_start; 1524 bp = mode->htotal - mode->hsync_end; 1525 1526 hbe = (sp + bp) / x - 1; 1527 hbs = (sp + bp + mode->hdisplay) / x - 1; 1528 hse = sp / x - 1; 1529 hss = (sp + bp + mode->hdisplay + fp) / x -1; 1530 hre = hss - hse - 1; 1531 hce = hbs - 4; 1532 hcs = hbe - 4; 1533 1534 /* Equalisation (interlaced modes) */ 1535 epe = 0; 1536 eie = 0; 1537 eis = 0; 1538 1539 DPRINTF(("ffb_set_vmode: 0x%04x 0x%04x 0x%04x 0x%04x 0x%04x\n", 1540 pll, pfc, ucl, dcl, tgc)); 1541 DPRINTF(("\t0x%04x 0x%04x 0x%04x 0x%04x\n", vbe, vbs, vse, vss)); 1542 DPRINTF(("\t0x%04x 0x%04x 0x%04x 0x%04x 0x%04x 0x%04x 0x%04x\n", 1543 hre, hbe, hbs, hse, hss, hce, hcs)); 1544 DPRINTF(("\t0x%04x 0x%04x 0x%04x\n", epe, eie, eis)); 1545 1546 if (!ffb_tgc_disable(sc)) { 1547 DPRINTF(("ffb_set_vmode: failed to disable TGC register\n")); 1548 return 0; 1549 } 1550 1551 /* 1552 * Program the mode registers. 1553 * Program the timing generator last, as that re-enables output. 1554 * Note, that a read to/write from a register increments the 1555 * register address to the next register automatically. 1556 */ 1557 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_PLL_CTRL); 1558 DAC_WRITE(sc, FFB_DAC_VALUE, pll); 1559 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_PIX_FMT); 1560 DAC_WRITE(sc, FFB_DAC_VALUE, pfc); 1561 DAC_WRITE(sc, FFB_DAC_VALUE, ucl); 1562 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_DAC_CTRL); 1563 DAC_WRITE(sc, FFB_DAC_VALUE, dcl); 1564 1565 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_VBE); 1566 DAC_WRITE(sc, FFB_DAC_VALUE, vbe); 1567 DAC_WRITE(sc, FFB_DAC_VALUE, vbs); 1568 DAC_WRITE(sc, FFB_DAC_VALUE, vse); 1569 DAC_WRITE(sc, FFB_DAC_VALUE, vss); 1570 1571 DAC_WRITE(sc, FFB_DAC_VALUE, hre); 1572 DAC_WRITE(sc, FFB_DAC_VALUE, hbe); 1573 DAC_WRITE(sc, FFB_DAC_VALUE, hbs); 1574 DAC_WRITE(sc, FFB_DAC_VALUE, hse); 1575 DAC_WRITE(sc, FFB_DAC_VALUE, hss); 1576 DAC_WRITE(sc, FFB_DAC_VALUE, hce); 1577 DAC_WRITE(sc, FFB_DAC_VALUE, hcs); 1578 1579 DAC_WRITE(sc, FFB_DAC_VALUE, epe); 1580 DAC_WRITE(sc, FFB_DAC_VALUE, eie); 1581 DAC_WRITE(sc, FFB_DAC_VALUE, eis); 1582 1583 FBC_WRITE(sc, FFB_FBC_FBCFG0, fbcfg0); 1584 1585 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_TGC); 1586 DAC_WRITE(sc, FFB_DAC_VALUE, tgc); 1587 DPRINTF(("new tgc: %08x\n", tgc)); 1588 1589 *hres = mode->hdisplay; 1590 *vres = mode->vdisplay; 1591 1592 printf("%s: video mode set to %d x %d @ %dHz\n", 1593 device_xname(sc->sc_dev), 1594 mode->hdisplay, mode->vdisplay, 1595 DIVIDE(DIVIDE(mode->dot_clock * 1000, 1596 mode->htotal), mode->vtotal)); 1597 1598 return 1; 1599 } 1600
Indexes created Sun Oct 12 05:10:08 GMT 2025