ffb.c revision 1.51
1 /* $NetBSD: ffb.c,v 1.51 2012/04/12 19:09:18 macallan Exp $ */ 2 /* $OpenBSD: creator.c,v 1.20 2002/07/30 19:48:15 jason Exp $ */ 3 4 /* 5 * Copyright (c) 2002 Jason L. Wright (jason (at) thought.net) 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Jason L. Wright 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 25 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 26 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 27 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 30 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 31 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32 * POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: ffb.c,v 1.51 2012/04/12 19:09:18 macallan Exp $"); 37 38 #include <sys/types.h> 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/kernel.h> 42 #include <sys/device.h> 43 #include <sys/conf.h> 44 #include <sys/ioctl.h> 45 #include <sys/malloc.h> 46 #include <sys/mman.h> 47 48 #include <sys/bus.h> 49 #include <machine/autoconf.h> 50 #include <machine/openfirm.h> 51 #include <machine/vmparam.h> 52 53 #include <dev/wscons/wsconsio.h> 54 #include <dev/sun/fbio.h> 55 #include <dev/sun/fbvar.h> 56 57 #include <dev/wsfont/wsfont.h> 58 #include <dev/wscons/wsdisplay_vconsvar.h> 59 60 #include <prop/proplib.h> 61 62 #include <dev/i2c/i2cvar.h> 63 #include <dev/i2c/i2c_bitbang.h> 64 #include <dev/i2c/ddcvar.h> 65 66 #include <sparc64/dev/ffbreg.h> 67 #include <sparc64/dev/ffbvar.h> 68 69 #include "opt_wsdisplay_compat.h" 70 #include "opt_ffb.h" 71 72 #ifndef WS_DEFAULT_BG 73 /* Sun -> background should be white */ 74 #define WS_DEFAULT_BG 0xf 75 #endif 76 77 #ifdef FFB_SYNC 78 #define SYNC ffb_ras_wait(sc) 79 #else 80 #define SYNC 81 #endif 82 83 /* Debugging */ 84 #if !defined FFB_DEBUG 85 #define FFB_DEBUG 0 86 #endif 87 #define DPRINTF(x) if (ffb_debug) printf x 88 /* Patchable */ 89 extern int ffb_debug; 90 #if FFB_DEBUG > 0 91 int ffb_debug = 1; 92 #else 93 int ffb_debug = 0; 94 #endif 95 96 extern struct cfdriver ffb_cd; 97 98 struct wsscreen_descr ffb_stdscreen = { 99 "sunffb", 100 0, 0, /* will be filled in -- XXX shouldn't, it's global. */ 101 0, 102 0, 0, 103 WSSCREEN_REVERSE | WSSCREEN_WSCOLORS, 104 NULL /* modecookie */ 105 }; 106 107 const struct wsscreen_descr *ffb_scrlist[] = { 108 &ffb_stdscreen, 109 /* XXX other formats? */ 110 }; 111 112 struct wsscreen_list ffb_screenlist = { 113 sizeof(ffb_scrlist) / sizeof(struct wsscreen_descr *), 114 ffb_scrlist 115 }; 116 117 static struct vcons_screen ffb_console_screen; 118 119 int ffb_ioctl(void *, void *, u_long, void *, int, struct lwp *); 120 static int ffb_blank(struct ffb_softc *, u_long, u_int *); 121 paddr_t ffb_mmap(void *, void *, off_t, int); 122 void ffb_ras_fifo_wait(struct ffb_softc *, int); 123 void ffb_ras_wait(struct ffb_softc *); 124 void ffb_ras_init(struct ffb_softc *); 125 void ffb_ras_copyrows(void *, int, int, int); 126 void ffb_ras_erasecols(void *, int, int, int, long int); 127 void ffb_ras_eraserows(void *, int, int, long int); 128 void ffb_ras_do_cursor(struct rasops_info *); 129 void ffb_ras_fill(struct ffb_softc *); 130 static void ffb_ras_setfg(struct ffb_softc *, int32_t); 131 static void ffb_ras_setbg(struct ffb_softc *, int32_t); 132 133 void ffb_clearscreen(struct ffb_softc *); 134 int ffb_load_font(void *, void *, struct wsdisplay_font *); 135 void ffb_init_screen(void *, struct vcons_screen *, int, 136 long *); 137 int ffb_allocattr(void *, int, int, int, long *); 138 void ffb_putchar(void *, int, int, u_int, long); 139 void ffb_cursor(void *, int, int, int); 140 141 /* frame buffer generic driver */ 142 static void ffbfb_unblank(device_t); 143 dev_type_open(ffbfb_open); 144 dev_type_close(ffbfb_close); 145 dev_type_ioctl(ffbfb_ioctl); 146 dev_type_mmap(ffbfb_mmap); 147 148 static struct fbdriver ffb_fbdriver = { 149 ffbfb_unblank, ffbfb_open, ffbfb_close, ffbfb_ioctl, nopoll, 150 ffbfb_mmap, nokqfilter 151 }; 152 153 struct wsdisplay_accessops ffb_accessops = { 154 .ioctl = ffb_ioctl, 155 .mmap = ffb_mmap, 156 }; 157 158 /* I2C glue */ 159 static int ffb_i2c_acquire_bus(void *, int); 160 static void ffb_i2c_release_bus(void *, int); 161 static int ffb_i2c_send_start(void *, int); 162 static int ffb_i2c_send_stop(void *, int); 163 static int ffb_i2c_initiate_xfer(void *, i2c_addr_t, int); 164 static int ffb_i2c_read_byte(void *, uint8_t *, int); 165 static int ffb_i2c_write_byte(void *, uint8_t, int); 166 167 /* I2C bitbang glue */ 168 static void ffb_i2cbb_set_bits(void *, uint32_t); 169 static void ffb_i2cbb_set_dir(void *, uint32_t); 170 static uint32_t ffb_i2cbb_read(void *); 171 172 static const struct i2c_bitbang_ops ffb_i2cbb_ops = { 173 ffb_i2cbb_set_bits, 174 ffb_i2cbb_set_dir, 175 ffb_i2cbb_read, 176 { 177 FFB_DAC_CFG_MPDATA_SDA, 178 FFB_DAC_CFG_MPDATA_SCL, 179 0, 180 0 181 } 182 }; 183 184 void ffb_attach_i2c(struct ffb_softc *); 185 186 /* Video mode setting */ 187 int ffb_tgc_disable(struct ffb_softc *); 188 void ffb_get_pclk(int, uint32_t *, int *); 189 int ffb_set_vmode(struct ffb_softc *, struct videomode *, int, int *, int *); 190 191 192 void 193 ffb_attach(device_t self) 194 { 195 struct ffb_softc *sc = device_private(self); 196 struct wsemuldisplaydev_attach_args waa; 197 struct rasops_info *ri; 198 long defattr; 199 const char *model, *out_dev; 200 int btype; 201 uint32_t dac; 202 int maxrow, maxcol; 203 u_int blank = WSDISPLAYIO_VIDEO_ON; 204 char buf[6+1]; 205 int i, try_edid; 206 prop_data_t data; 207 208 printf(":"); 209 210 if (sc->sc_type == FFB_CREATOR) { 211 btype = prom_getpropint(sc->sc_node, "board_type", 0); 212 if ((btype & 7) == 3) 213 printf(" Creator3D"); 214 else 215 printf(" Creator"); 216 } else { 217 printf(" Elite3D"); 218 btype = 0; 219 } 220 221 model = prom_getpropstring(sc->sc_node, "model"); 222 if (model == NULL || strlen(model) == 0) 223 model = "unknown"; 224 225 sc->sc_depth = 24; 226 sc->sc_linebytes = 8192; 227 /* We might alter these during EDID mode setting */ 228 sc->sc_height = prom_getpropint(sc->sc_node, "height", 0); 229 sc->sc_width = prom_getpropint(sc->sc_node, "width", 0); 230 231 sc->sc_locked = 0; 232 sc->sc_mode = WSDISPLAYIO_MODE_EMUL; 233 234 maxcol = (prom_getoption("screen-#columns", buf, sizeof buf) == 0) 235 ? strtoul(buf, NULL, 10) 236 : 80; 237 238 maxrow = (prom_getoption("screen-#rows", buf, sizeof buf) != 0) 239 ? strtoul(buf, NULL, 10) 240 : 34; 241 242 /* collect DAC version, as Elite3D cursor enable bit is reversed */ 243 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_DEVID); 244 dac = DAC_READ(sc, FFB_DAC_VALUE); 245 sc->sc_dacrev = (dac >> 28) & 0xf; 246 247 if (sc->sc_type == FFB_AFB) { 248 sc->sc_dacrev = 10; 249 sc->sc_needredraw = 0; 250 } else { 251 /* see what kind of DAC we have */ 252 int pnum = (dac & 0x0ffff000) >> 12; 253 if (pnum == 0x236e) { 254 sc->sc_needredraw = 0; 255 } else { 256 sc->sc_needredraw = 1; 257 } 258 } 259 printf(", model %s, dac %u\n", model, sc->sc_dacrev); 260 if (sc->sc_needredraw) 261 printf("%s: found old DAC, enabling redraw on unblank\n", 262 device_xname(sc->sc_dev)); 263 264 /* Check if a console resolution "<device>:r<res>" is set. */ 265 if (sc->sc_console) { 266 out_dev = prom_getpropstring(sc->sc_node, "output_device"); 267 if (out_dev != NULL && strlen(out_dev) != 0 && 268 strstr(out_dev, ":r") != NULL) 269 try_edid = 0; 270 else 271 try_edid = 1; 272 } else 273 try_edid = 1; 274 275 #if FFB_DEBUG > 0 276 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_TGC); 277 printf("tgc: %08x\n", DAC_READ(sc, FFB_DAC_VALUE)); 278 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_DAC_CTRL); 279 printf("dcl: %08x\n", DAC_READ(sc, FFB_DAC_VALUE)); 280 #endif 281 ffb_attach_i2c(sc); 282 283 /* Need to set asynchronous blank during DDC write/read */ 284 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_USR_CTRL); 285 dac = DAC_READ(sc, FFB_DAC_VALUE); 286 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_USR_CTRL); 287 DAC_WRITE(sc, FFB_DAC_VALUE, dac | FFB_DAC_USR_CTRL_BLANK); 288 289 /* Some monitors don't respond first time */ 290 i = 0; 291 while (sc->sc_edid_data[1] == 0 && i++ < 3) 292 ddc_read_edid(&sc->sc_i2c, sc->sc_edid_data, EDID_DATA_LEN); 293 294 /* Remove asynchronous blank */ 295 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_USR_CTRL); 296 DAC_WRITE(sc, FFB_DAC_VALUE, dac); 297 298 if (edid_parse(&sc->sc_edid_data[0], &sc->sc_edid_info) != -1) { 299 sort_modes(sc->sc_edid_info.edid_modes, 300 &sc->sc_edid_info.edid_preferred_mode, 301 sc->sc_edid_info.edid_nmodes); 302 DPRINTF(("%s: EDID data:\n ", device_xname(sc->sc_dev))); 303 for (i = 0; i < EDID_DATA_LEN; i++) { 304 if (i && !(i % 32)) 305 DPRINTF(("\n ")); 306 if (i && !(i % 4)) 307 DPRINTF((" ")); 308 DPRINTF(("%02x", sc->sc_edid_data[i])); 309 } 310 DPRINTF(("\n")); 311 if (ffb_debug) 312 edid_print(&sc->sc_edid_info); 313 314 data = prop_data_create_data(sc->sc_edid_data, EDID_DATA_LEN); 315 prop_dictionary_set(device_properties(self), "EDID", data); 316 prop_object_release(data); 317 318 if (try_edid) 319 for (i = 0; i < sc->sc_edid_info.edid_nmodes; i++) { 320 if (ffb_set_vmode(sc, 321 &(sc->sc_edid_info.edid_modes[i]), btype, 322 &(sc->sc_width), &(sc->sc_height))) 323 break; 324 } 325 } else { 326 DPRINTF(("%s: No EDID data.\n", device_xname(sc->sc_dev))); 327 } 328 329 ffb_ras_init(sc); 330 331 ffb_blank(sc, WSDISPLAYIO_SVIDEO, &blank); 332 333 sc->sc_accel = ((device_cfdata(sc->sc_dev)->cf_flags & 334 FFB_CFFLAG_NOACCEL) == 0); 335 336 wsfont_init(); 337 338 vcons_init(&sc->vd, sc, &ffb_stdscreen, &ffb_accessops); 339 sc->vd.init_screen = ffb_init_screen; 340 341 /* we mess with ffb_console_screen only once */ 342 if (sc->sc_console) { 343 vcons_init_screen(&sc->vd, &ffb_console_screen, 1, &defattr); 344 SCREEN_VISIBLE((&ffb_console_screen)); 345 /* 346 * XXX we shouldn't use a global variable for the console 347 * screen 348 */ 349 sc->vd.active = &ffb_console_screen; 350 ffb_console_screen.scr_flags = VCONS_SCREEN_IS_STATIC; 351 } else { 352 if (ffb_console_screen.scr_ri.ri_rows == 0) { 353 /* do some minimal setup to avoid weirdnesses later */ 354 vcons_init_screen(&sc->vd, &ffb_console_screen, 1, &defattr); 355 } 356 } 357 ri = &ffb_console_screen.scr_ri; 358 359 ffb_stdscreen.nrows = ri->ri_rows; 360 ffb_stdscreen.ncols = ri->ri_cols; 361 ffb_stdscreen.textops = &ri->ri_ops; 362 ffb_stdscreen.capabilities = ri->ri_caps; 363 364 sc->sc_fb.fb_driver = &ffb_fbdriver; 365 sc->sc_fb.fb_type.fb_cmsize = 0; 366 sc->sc_fb.fb_type.fb_size = maxrow * sc->sc_linebytes; 367 sc->sc_fb.fb_type.fb_type = FBTYPE_CREATOR; 368 sc->sc_fb.fb_type.fb_width = sc->sc_width; 369 sc->sc_fb.fb_type.fb_depth = sc->sc_depth; 370 sc->sc_fb.fb_type.fb_height = sc->sc_height; 371 sc->sc_fb.fb_device = sc->sc_dev; 372 fb_attach(&sc->sc_fb, sc->sc_console); 373 374 ffb_clearscreen(sc); 375 376 if (sc->sc_console) { 377 wsdisplay_cnattach(&ffb_stdscreen, ri, 0, 0, defattr); 378 vcons_replay_msgbuf(&ffb_console_screen); 379 } 380 381 waa.console = sc->sc_console; 382 waa.scrdata = &ffb_screenlist; 383 waa.accessops = &ffb_accessops; 384 waa.accesscookie = &sc->vd; 385 config_found(sc->sc_dev, &waa, wsemuldisplaydevprint); 386 } 387 388 void 389 ffb_attach_i2c(struct ffb_softc *sc) 390 { 391 392 /* Fill in the i2c tag */ 393 sc->sc_i2c.ic_cookie = sc; 394 sc->sc_i2c.ic_acquire_bus = ffb_i2c_acquire_bus; 395 sc->sc_i2c.ic_release_bus = ffb_i2c_release_bus; 396 sc->sc_i2c.ic_send_start = ffb_i2c_send_start; 397 sc->sc_i2c.ic_send_stop = ffb_i2c_send_stop; 398 sc->sc_i2c.ic_initiate_xfer = ffb_i2c_initiate_xfer; 399 sc->sc_i2c.ic_read_byte = ffb_i2c_read_byte; 400 sc->sc_i2c.ic_write_byte = ffb_i2c_write_byte; 401 sc->sc_i2c.ic_exec = NULL; 402 } 403 404 int 405 ffb_ioctl(void *v, void *vs, u_long cmd, void *data, int flags, struct lwp *l) 406 { 407 struct vcons_data *vd = v; 408 struct ffb_softc *sc = vd->cookie; 409 struct wsdisplay_fbinfo *wdf; 410 struct vcons_screen *ms = vd->active; 411 412 DPRINTF(("ffb_ioctl: %s cmd _IO%s%s('%c', %lu)\n", 413 device_xname(sc->sc_dev), 414 (cmd & IOC_IN) ? "W" : "", (cmd & IOC_OUT) ? "R" : "", 415 (char)IOCGROUP(cmd), cmd & 0xff)); 416 417 switch (cmd) { 418 case FBIOGTYPE: 419 *(struct fbtype *)data = sc->sc_fb.fb_type; 420 break; 421 case FBIOGATTR: 422 #define fba ((struct fbgattr *)data) 423 fba->real_type = sc->sc_fb.fb_type.fb_type; 424 fba->owner = 0; /* XXX ??? */ 425 fba->fbtype = sc->sc_fb.fb_type; 426 fba->sattr.flags = 0; 427 fba->sattr.emu_type = sc->sc_fb.fb_type.fb_type; 428 fba->sattr.dev_specific[0] = -1; 429 fba->emu_types[0] = sc->sc_fb.fb_type.fb_type; 430 fba->emu_types[1] = -1; 431 #undef fba 432 break; 433 434 case FBIOGETCMAP: 435 case FBIOPUTCMAP: 436 return EIO; 437 438 case FBIOGVIDEO: 439 case FBIOSVIDEO: 440 return ffb_blank(sc, cmd == FBIOGVIDEO? 441 WSDISPLAYIO_GVIDEO : WSDISPLAYIO_SVIDEO, 442 (u_int *)data); 443 break; 444 case FBIOGCURSOR: 445 case FBIOSCURSOR: 446 /* the console driver is not using the hardware cursor */ 447 break; 448 case FBIOGCURPOS: 449 printf("%s: FBIOGCURPOS not implemented\n", 450 device_xname(sc->sc_dev)); 451 return EIO; 452 case FBIOSCURPOS: 453 printf("%s: FBIOSCURPOS not implemented\n", 454 device_xname(sc->sc_dev)); 455 return EIO; 456 case FBIOGCURMAX: 457 printf("%s: FBIOGCURMAX not implemented\n", 458 device_xname(sc->sc_dev)); 459 return EIO; 460 461 case WSDISPLAYIO_GTYPE: 462 *(u_int *)data = WSDISPLAY_TYPE_SUNFFB; 463 break; 464 case WSDISPLAYIO_SMODE: 465 { 466 if (sc->sc_mode != *(u_int *)data) { 467 sc->sc_mode = *(u_int *)data; 468 if ((sc->sc_mode == WSDISPLAYIO_MODE_EMUL) && 469 (sc->sc_locked == 0)) { 470 ffb_ras_init(sc); 471 vcons_redraw_screen(ms); 472 } 473 } 474 } 475 break; 476 case WSDISPLAYIO_GINFO: 477 wdf = (void *)data; 478 wdf->height = sc->sc_height; 479 wdf->width = sc->sc_width; 480 wdf->depth = 32; 481 wdf->cmsize = 256; /* XXX */ 482 break; 483 #ifdef WSDISPLAYIO_LINEBYTES 484 case WSDISPLAYIO_LINEBYTES: 485 *(u_int *)data = sc->sc_linebytes; 486 break; 487 #endif 488 case WSDISPLAYIO_GETCMAP: 489 break;/* XXX */ 490 491 case WSDISPLAYIO_PUTCMAP: 492 break;/* XXX */ 493 494 case WSDISPLAYIO_SVIDEO: 495 case WSDISPLAYIO_GVIDEO: 496 return(ffb_blank(sc, cmd, (u_int *)data)); 497 break; 498 case WSDISPLAYIO_GCURPOS: 499 case WSDISPLAYIO_SCURPOS: 500 case WSDISPLAYIO_GCURMAX: 501 case WSDISPLAYIO_GCURSOR: 502 case WSDISPLAYIO_SCURSOR: 503 return EIO; /* not supported yet */ 504 break; 505 case WSDISPLAYIO_GET_EDID: { 506 struct wsdisplayio_edid_info *d = data; 507 return wsdisplayio_get_edid(sc->sc_dev, d); 508 } 509 default: 510 return EPASSTHROUGH; 511 } 512 513 return (0); 514 } 515 516 /* blank/unblank the screen */ 517 static int 518 ffb_blank(struct ffb_softc *sc, u_long cmd, u_int *data) 519 { 520 struct vcons_screen *ms = sc->vd.active; 521 u_int val; 522 523 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_TGC); 524 val = DAC_READ(sc, FFB_DAC_VALUE); 525 526 switch (cmd) { 527 case WSDISPLAYIO_GVIDEO: 528 *data = val & 1; 529 return(0); 530 break; 531 case WSDISPLAYIO_SVIDEO: 532 if (*data == WSDISPLAYIO_VIDEO_OFF) 533 val &= ~1; 534 else if (*data == WSDISPLAYIO_VIDEO_ON) 535 val |= 1; 536 else 537 return(EINVAL); 538 break; 539 default: 540 return(EINVAL); 541 } 542 543 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_TGC); 544 DAC_WRITE(sc, FFB_DAC_VALUE, val); 545 546 if ((val & 1) && sc->sc_needredraw) { 547 if (ms != NULL) { 548 if ((sc->sc_mode == WSDISPLAYIO_MODE_EMUL) && 549 (sc->sc_locked == 0)) { 550 ffb_ras_init(sc); 551 vcons_redraw_screen(ms); 552 } 553 } 554 } 555 556 return(0); 557 } 558 559 paddr_t 560 ffb_mmap(void *vsc, void *vs, off_t off, int prot) 561 { 562 struct vcons_data *vd = vsc; 563 struct ffb_softc *sc = vd->cookie; 564 int i; 565 566 switch (sc->sc_mode) { 567 case WSDISPLAYIO_MODE_MAPPED: 568 for (i = 0; i < sc->sc_nreg; i++) { 569 /* Before this set? */ 570 if (off < sc->sc_addrs[i]) 571 continue; 572 /* After this set? */ 573 if (off >= (sc->sc_addrs[i] + sc->sc_sizes[i])) 574 continue; 575 576 return (bus_space_mmap(sc->sc_bt, sc->sc_addrs[i], 577 off - sc->sc_addrs[i], prot, BUS_SPACE_MAP_LINEAR)); 578 } 579 break; 580 #ifdef WSDISPLAYIO_MODE_DUMBFB 581 case WSDISPLAYIO_MODE_DUMBFB: 582 if (sc->sc_nreg < FFB_REG_DFB24) 583 break; 584 if (off >= 0 && off < sc->sc_sizes[FFB_REG_DFB24]) 585 return (bus_space_mmap(sc->sc_bt, 586 sc->sc_addrs[FFB_REG_DFB24], off, prot, 587 BUS_SPACE_MAP_LINEAR)); 588 break; 589 #endif 590 } 591 return (-1); 592 } 593 594 void 595 ffb_ras_fifo_wait(struct ffb_softc *sc, int n) 596 { 597 int32_t cache = sc->sc_fifo_cache; 598 599 if (cache < n) { 600 do { 601 cache = FBC_READ(sc, FFB_FBC_UCSR); 602 cache = (cache & FBC_UCSR_FIFO_MASK) - 8; 603 } while (cache < n); 604 } 605 sc->sc_fifo_cache = cache - n; 606 } 607 608 void 609 ffb_ras_wait(struct ffb_softc *sc) 610 { 611 uint32_t ucsr, r; 612 613 while (1) { 614 ucsr = FBC_READ(sc, FFB_FBC_UCSR); 615 if ((ucsr & (FBC_UCSR_FB_BUSY|FBC_UCSR_RP_BUSY)) == 0) 616 break; 617 r = ucsr & (FBC_UCSR_READ_ERR | FBC_UCSR_FIFO_OVFL); 618 if (r != 0) 619 FBC_WRITE(sc, FFB_FBC_UCSR, r); 620 } 621 } 622 623 void 624 ffb_ras_init(struct ffb_softc *sc) 625 { 626 uint32_t fbc; 627 628 if (sc->sc_width > 1280) { 629 DPRINTF(("ffb_ras_init: high resolution.\n")); 630 fbc = FFB_FBC_WM_COMBINED | FFB_FBC_WE_FORCEON | 631 FFB_FBC_ZE_OFF | FFB_FBC_YE_OFF | FFB_FBC_XE_ON; 632 } else { 633 DPRINTF(("ffb_ras_init: standard resolution.\n")); 634 fbc = FFB_FBC_XE_OFF; 635 } 636 ffb_ras_fifo_wait(sc, 11); 637 DPRINTF(("WID: %08x\n", FBC_READ(sc, FFB_FBC_WID))); 638 FBC_WRITE(sc, FFB_FBC_WID, 0x0); 639 FBC_WRITE(sc, FFB_FBC_PPC, 640 FBC_PPC_VCE_DIS | FBC_PPC_TBE_OPAQUE | FBC_PPC_ACE_DIS | 641 FBC_PPC_APE_DIS | FBC_PPC_DCE_DIS | FBC_PPC_CS_CONST | 642 FBC_PPC_ABE_DIS | FBC_PPC_XS_WID); 643 644 fbc |= FFB_FBC_WB_A | FFB_FBC_RB_A | FFB_FBC_SB_BOTH | 645 FFB_FBC_RGBE_MASK; 646 DPRINTF(("%s: fbc is %08x\n", __func__, fbc)); 647 FBC_WRITE(sc, FFB_FBC_FBC, fbc); 648 FBC_WRITE(sc, FFB_FBC_ROP, FBC_ROP_NEW); 649 FBC_WRITE(sc, FFB_FBC_DRAWOP, FBC_DRAWOP_RECTANGLE); 650 FBC_WRITE(sc, FFB_FBC_PMASK, 0xffffffff); 651 FBC_WRITE(sc, FFB_FBC_FONTINC, 0x10000); 652 sc->sc_fg_cache = 0; 653 FBC_WRITE(sc, FFB_FBC_FG, sc->sc_fg_cache); 654 FBC_WRITE(sc, FFB_FBC_BLENDC, FFB_BLENDC_FORCE_ONE | 655 FFB_BLENDC_DF_ONE_M_A | 656 FFB_BLENDC_SF_A); 657 FBC_WRITE(sc, FFB_FBC_BLENDC1, 0); 658 FBC_WRITE(sc, FFB_FBC_BLENDC2, 0); 659 ffb_ras_wait(sc); 660 } 661 662 void 663 ffb_ras_eraserows(void *cookie, int row, int n, long attr) 664 { 665 struct rasops_info *ri = cookie; 666 struct vcons_screen *scr = ri->ri_hw; 667 struct ffb_softc *sc = scr->scr_cookie; 668 669 if (row < 0) { 670 n += row; 671 row = 0; 672 } 673 if (row + n > ri->ri_rows) 674 n = ri->ri_rows - row; 675 if (n <= 0) 676 return; 677 678 ffb_ras_fill(sc); 679 ffb_ras_setfg(sc, ri->ri_devcmap[(attr >> 16) & 0xf]); 680 ffb_ras_fifo_wait(sc, 4); 681 if ((n == ri->ri_rows) && (ri->ri_flg & RI_FULLCLEAR)) { 682 FBC_WRITE(sc, FFB_FBC_BY, 0); 683 FBC_WRITE(sc, FFB_FBC_BX, 0); 684 FBC_WRITE(sc, FFB_FBC_BH, ri->ri_height); 685 FBC_WRITE(sc, FFB_FBC_BW, ri->ri_width); 686 } else { 687 row *= ri->ri_font->fontheight; 688 FBC_WRITE(sc, FFB_FBC_BY, ri->ri_yorigin + row); 689 FBC_WRITE(sc, FFB_FBC_BX, ri->ri_xorigin); 690 FBC_WRITE(sc, FFB_FBC_BH, n * ri->ri_font->fontheight); 691 FBC_WRITE(sc, FFB_FBC_BW, ri->ri_emuwidth); 692 } 693 SYNC; 694 } 695 696 void 697 ffb_ras_erasecols(void *cookie, int row, int col, int n, long attr) 698 { 699 struct rasops_info *ri = cookie; 700 struct vcons_screen *scr = ri->ri_hw; 701 struct ffb_softc *sc = scr->scr_cookie; 702 703 if ((row < 0) || (row >= ri->ri_rows)) 704 return; 705 if (col < 0) { 706 n += col; 707 col = 0; 708 } 709 if (col + n > ri->ri_cols) 710 n = ri->ri_cols - col; 711 if (n <= 0) 712 return; 713 n *= ri->ri_font->fontwidth; 714 col *= ri->ri_font->fontwidth; 715 row *= ri->ri_font->fontheight; 716 717 ffb_ras_fill(sc); 718 ffb_ras_setfg(sc, ri->ri_devcmap[(attr >> 16) & 0xf]); 719 ffb_ras_fifo_wait(sc, 4); 720 FBC_WRITE(sc, FFB_FBC_BY, ri->ri_yorigin + row); 721 FBC_WRITE(sc, FFB_FBC_BX, ri->ri_xorigin + col); 722 FBC_WRITE(sc, FFB_FBC_BH, ri->ri_font->fontheight); 723 FBC_WRITE(sc, FFB_FBC_BW, n - 1); 724 SYNC; 725 } 726 727 void 728 ffb_ras_fill(struct ffb_softc *sc) 729 { 730 ffb_ras_fifo_wait(sc, 3); 731 FBC_WRITE(sc, FFB_FBC_PPC, 732 FBC_PPC_VCE_DIS | FBC_PPC_TBE_OPAQUE | FBC_PPC_ACE_DIS | 733 FBC_PPC_APE_DIS | FBC_PPC_DCE_DIS | FBC_PPC_CS_CONST | 734 FBC_PPC_ABE_DIS | FBC_PPC_XS_WID); 735 FBC_WRITE(sc, FFB_FBC_ROP, FBC_ROP_NEW); 736 FBC_WRITE(sc, FFB_FBC_DRAWOP, FBC_DRAWOP_RECTANGLE); 737 SYNC; 738 } 739 740 void 741 ffb_ras_copyrows(void *cookie, int src, int dst, int n) 742 { 743 struct rasops_info *ri = cookie; 744 struct vcons_screen *scr = ri->ri_hw; 745 struct ffb_softc *sc = scr->scr_cookie; 746 747 if (dst == src) 748 return; 749 if (src < 0) { 750 n += src; 751 src = 0; 752 } 753 if ((src + n) > ri->ri_rows) 754 n = ri->ri_rows - src; 755 if (dst < 0) { 756 n += dst; 757 dst = 0; 758 } 759 if ((dst + n) > ri->ri_rows) 760 n = ri->ri_rows - dst; 761 if (n <= 0) 762 return; 763 n *= ri->ri_font->fontheight; 764 src *= ri->ri_font->fontheight; 765 dst *= ri->ri_font->fontheight; 766 767 ffb_ras_fifo_wait(sc, 9); 768 FBC_WRITE(sc, FFB_FBC_PPC, 769 FBC_PPC_VCE_DIS | FBC_PPC_TBE_OPAQUE | FBC_PPC_ACE_DIS | 770 FBC_PPC_APE_DIS | FBC_PPC_DCE_DIS | FBC_PPC_CS_CONST | 771 FBC_PPC_ABE_DIS | FBC_PPC_XS_WID); 772 FBC_WRITE(sc, FFB_FBC_ROP, FBC_ROP_OLD | (FBC_ROP_OLD << 8)); 773 FBC_WRITE(sc, FFB_FBC_DRAWOP, FBC_DRAWOP_VSCROLL); 774 FBC_WRITE(sc, FFB_FBC_BY, ri->ri_yorigin + src); 775 FBC_WRITE(sc, FFB_FBC_BX, ri->ri_xorigin); 776 FBC_WRITE(sc, FFB_FBC_DY, ri->ri_yorigin + dst); 777 FBC_WRITE(sc, FFB_FBC_DX, ri->ri_xorigin); 778 FBC_WRITE(sc, FFB_FBC_BH, n); 779 FBC_WRITE(sc, FFB_FBC_BW, ri->ri_emuwidth); 780 SYNC; 781 } 782 783 static void 784 ffb_ras_setfg(struct ffb_softc *sc, int32_t fg) 785 { 786 ffb_ras_fifo_wait(sc, 1); 787 if (fg == sc->sc_fg_cache) 788 return; 789 sc->sc_fg_cache = fg; 790 FBC_WRITE(sc, FFB_FBC_FG, fg); 791 SYNC; 792 } 793 794 static void 795 ffb_ras_setbg(struct ffb_softc *sc, int32_t bg) 796 { 797 ffb_ras_fifo_wait(sc, 1); 798 if (bg == sc->sc_bg_cache) 799 return; 800 sc->sc_bg_cache = bg; 801 FBC_WRITE(sc, FFB_FBC_BG, bg); 802 SYNC; 803 } 804 805 /* frame buffer generic driver support functions */ 806 static void 807 ffbfb_unblank(device_t dev) 808 { 809 struct ffb_softc *sc = device_private(dev); 810 struct vcons_screen *ms = sc->vd.active; 811 u_int on = 1; 812 int redraw = 0; 813 814 ffb_ras_init(sc); 815 if (sc->sc_locked) { 816 sc->sc_locked = 0; 817 redraw = 1; 818 } 819 820 ffb_blank(sc, WSDISPLAYIO_SVIDEO, &on); 821 #if 0 822 if ((sc->vd.active != &ffb_console_screen) && 823 (ffb_console_screen.scr_flags & VCONS_SCREEN_IS_STATIC)) { 824 /* 825 * force-switch to the console screen. 826 * Caveat: the higher layer will think we're still on the 827 * other screen 828 */ 829 830 SCREEN_INVISIBLE(sc->vd.active); 831 sc->vd.active = &ffb_console_screen; 832 SCREEN_VISIBLE(sc->vd.active); 833 ms = sc->vd.active; 834 redraw = 1; 835 } 836 #endif 837 if (redraw) { 838 vcons_redraw_screen(ms); 839 } 840 } 841 842 int 843 ffbfb_open(dev_t dev, int flags, int mode, struct lwp *l) 844 { 845 struct ffb_softc *sc; 846 847 sc = device_lookup_private(&ffb_cd, minor(dev)); 848 if (sc == NULL) 849 return ENXIO; 850 851 sc->sc_locked = 1; 852 return 0; 853 } 854 855 int 856 ffbfb_close(dev_t dev, int flags, int mode, struct lwp *l) 857 { 858 struct ffb_softc *sc = device_lookup_private(&ffb_cd, minor(dev)); 859 struct vcons_screen *ms = sc->vd.active; 860 861 sc->sc_locked = 0; 862 if (ms != NULL) { 863 if ((sc->sc_mode == WSDISPLAYIO_MODE_EMUL) && 864 (sc->sc_locked == 0)) { 865 ffb_ras_init(sc); 866 vcons_redraw_screen(ms); 867 } 868 } 869 return 0; 870 } 871 872 int 873 ffbfb_ioctl(dev_t dev, u_long cmd, void *data, int flags, struct lwp *l) 874 { 875 struct ffb_softc *sc = device_lookup_private(&ffb_cd, minor(dev)); 876 877 return ffb_ioctl(&sc->vd, NULL, cmd, data, flags, l); 878 } 879 880 paddr_t 881 ffbfb_mmap(dev_t dev, off_t off, int prot) 882 { 883 struct ffb_softc *sc = device_lookup_private(&ffb_cd, minor(dev)); 884 uint64_t size; 885 int i, reg; 886 off_t o; 887 888 /* 889 * off is a magic cookie (see xfree86/drivers/sunffb/ffb.h), 890 * which we map to an index into the "reg" property, and use 891 * our copy of the firmware data as arguments for the real 892 * mapping. 893 */ 894 static struct { unsigned long voff; int reg; } map[] = { 895 { 0x00000000, FFB_REG_SFB8R }, 896 { 0x00400000, FFB_REG_SFB8G }, 897 { 0x00800000, FFB_REG_SFB8B }, 898 { 0x00c00000, FFB_REG_SFB8X }, 899 { 0x01000000, FFB_REG_SFB32 }, 900 { 0x02000000, FFB_REG_SFB64 }, 901 { 0x04000000, FFB_REG_FBC }, 902 { 0x04004000, FFB_REG_DFB8R }, 903 { 0x04404000, FFB_REG_DFB8G }, 904 { 0x04804000, FFB_REG_DFB8B }, 905 { 0x04c04000, FFB_REG_DFB8X }, 906 { 0x05004000, FFB_REG_DFB24 }, 907 { 0x06004000, FFB_REG_DFB32 }, 908 { 0x07004000, FFB_REG_DFB422A }, 909 { 0x0bc06000, FFB_REG_DAC }, 910 { 0x0bc08000, FFB_REG_PROM }, 911 { 0x0bc18000, 0 } 912 }; 913 914 /* special value "FFB_EXP_VOFF" - not backed by any "reg" entry */ 915 if (off == 0x0bc18000) 916 return bus_space_mmap(sc->sc_bt, sc->sc_addrs[FFB_REG_PROM], 917 0x00200000, prot, BUS_SPACE_MAP_LINEAR); 918 919 /* 920 * FFB_VOFF_FBC_KREGS - used by afbinit to upload firmware. We should 921 * probably mmap them only on afb boards 922 */ 923 if ((off >= 0x0bc04000) && (off < 0x0bc06000)) 924 return bus_space_mmap(sc->sc_bt, sc->sc_addrs[FFB_REG_PROM], 925 0x00610000 + (off - 0x0bc04000), prot, 926 BUS_SPACE_MAP_LINEAR); 927 928 #define NELEMS(arr) (sizeof(arr)/sizeof((arr)[0])) 929 930 /* the map is ordered by voff */ 931 for (i = 0; i < NELEMS(map)-1; i++) { 932 reg = map[i].reg; 933 /* the number of entries in reg seems to vary */ 934 if (reg < sc->sc_nreg) { 935 size = min((map[i + 1].voff - map[i].voff), 936 sc->sc_sizes[reg]); 937 if ((off >= map[i].voff) && 938 (off < (map[i].voff + size))) { 939 o = off - map[i].voff; 940 return bus_space_mmap(sc->sc_bt, 941 sc->sc_addrs[reg], o, prot, 942 BUS_SPACE_MAP_LINEAR); 943 } 944 } 945 } 946 947 return -1; 948 } 949 950 void 951 ffb_clearscreen(struct ffb_softc *sc) 952 { 953 struct rasops_info *ri = &ffb_console_screen.scr_ri; 954 ffb_ras_fill(sc); 955 ffb_ras_setfg(sc, ri->ri_devcmap[WS_DEFAULT_BG]); 956 ffb_ras_fifo_wait(sc, 4); 957 FBC_WRITE(sc, FFB_FBC_BY, 0); 958 FBC_WRITE(sc, FFB_FBC_BX, 0); 959 FBC_WRITE(sc, FFB_FBC_BH, sc->sc_height); 960 FBC_WRITE(sc, FFB_FBC_BW, sc->sc_width); 961 } 962 963 void 964 ffb_cursor(void *cookie, int on, int row, int col) 965 { 966 struct rasops_info *ri = cookie; 967 struct vcons_screen *scr; 968 struct ffb_softc *sc; 969 int x, y, wi, he, coffset; 970 971 if (cookie != NULL) { 972 scr = ri->ri_hw; 973 sc = scr->scr_cookie; 974 975 wi = ri->ri_font->fontwidth; 976 he = ri->ri_font->fontheight; 977 978 if (sc->sc_mode == WSDISPLAYIO_MODE_EMUL) { 979 x = ri->ri_ccol * wi + ri->ri_xorigin; 980 y = ri->ri_crow * he + ri->ri_yorigin; 981 982 if (ri->ri_flg & RI_CURSOR) { 983 /* remove cursor */ 984 coffset = ri->ri_ccol + (ri->ri_crow * 985 ri->ri_cols); 986 #ifdef WSDISPLAY_SCROLLSUPPORT 987 coffset += scr->scr_offset_to_zero; 988 #endif 989 ffb_ras_wait(sc); 990 ffb_putchar(cookie, ri->ri_crow, 991 ri->ri_ccol, scr->scr_chars[coffset], 992 scr->scr_attrs[coffset]); 993 ri->ri_flg &= ~RI_CURSOR; 994 } 995 ri->ri_crow = row; 996 ri->ri_ccol = col; 997 if (on) 998 { 999 long attr, revattr; 1000 x = ri->ri_ccol * wi + ri->ri_xorigin; 1001 y = ri->ri_crow * he + ri->ri_yorigin; 1002 coffset = col + (row * ri->ri_cols); 1003 #ifdef WSDISPLAY_SCROLLSUPPORT 1004 coffset += scr->scr_offset_to_zero; 1005 #endif 1006 attr = scr->scr_attrs[coffset]; 1007 #ifdef FFB_CURSOR_SWAP_COLOURS 1008 revattr=((attr >> 8 ) & 0x000f0000) | ((attr & 1009 0x000f0000)<<8) | (attr & 0x0000ffff); 1010 #else 1011 revattr = attr ^ 0xffff0000; 1012 #endif 1013 ffb_ras_wait(sc); 1014 ffb_putchar(cookie, ri->ri_crow, ri->ri_ccol, 1015 scr->scr_chars[coffset], revattr); 1016 ri->ri_flg |= RI_CURSOR; 1017 } 1018 } else { 1019 ri->ri_crow = row; 1020 ri->ri_ccol = col; 1021 ri->ri_flg &= ~RI_CURSOR; 1022 } 1023 } 1024 } 1025 1026 void 1027 ffb_putchar(void *cookie, int row, int col, u_int c, long attr) 1028 { 1029 struct rasops_info *ri = cookie; 1030 struct vcons_screen *scr = ri->ri_hw; 1031 struct wsdisplay_font *font = PICK_FONT(ri, c); 1032 struct ffb_softc *sc = scr->scr_cookie; 1033 void *data; 1034 uint32_t fg, bg; 1035 int uc, i; 1036 int x, y, wi, he; 1037 1038 if (sc->sc_mode != WSDISPLAYIO_MODE_EMUL) 1039 return; 1040 1041 wi = font->fontwidth; 1042 he = font->fontheight; 1043 1044 if (!CHAR_IN_FONT(c, font)) 1045 return; 1046 1047 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 1048 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 1049 x = ri->ri_xorigin + col * wi; 1050 y = ri->ri_yorigin + row * he; 1051 1052 uc = c - font->firstchar; 1053 data = (uint8_t *)font->data + uc * ri->ri_fontscale; 1054 1055 if (font->stride < wi) { 1056 /* mono bitmap font */ 1057 ffb_ras_setbg(sc, bg); 1058 ffb_ras_setfg(sc, fg); 1059 ffb_ras_fifo_wait(sc, 4); 1060 FBC_WRITE(sc, FFB_FBC_ROP, FBC_ROP_NEW); 1061 FBC_WRITE(sc, FFB_FBC_FONTXY, (y << 16) | x); 1062 FBC_WRITE(sc, FFB_FBC_FONTW, wi); 1063 FBC_WRITE(sc, FFB_FBC_PPC, 1064 FBC_PPC_VCE_DIS | FBC_PPC_TBE_OPAQUE | FBC_PPC_ACE_DIS | 1065 FBC_PPC_APE_DIS | FBC_PPC_DCE_DIS | FBC_PPC_CS_CONST | 1066 FBC_PPC_ABE_DIS | FBC_PPC_XS_WID); 1067 1068 switch (font->stride) { 1069 case 1: { 1070 uint8_t *data8 = data; 1071 uint32_t reg; 1072 for (i = 0; i < he; i++) { 1073 reg = *data8; 1074 FBC_WRITE(sc, FFB_FBC_FONT, reg << 24); 1075 data8++; 1076 } 1077 break; 1078 } 1079 case 2: { 1080 uint16_t *data16 = data; 1081 uint32_t reg; 1082 for (i = 0; i < he; i++) { 1083 reg = *data16; 1084 FBC_WRITE(sc, FFB_FBC_FONT, reg << 16); 1085 data16++; 1086 } 1087 break; 1088 } 1089 } 1090 } else { 1091 /* alpha font */ 1092 volatile uint32_t *dest, *ddest; 1093 uint32_t alpha = 0x80; 1094 uint8_t *data8 = data; 1095 int j; 1096 1097 /* first we erase the background */ 1098 ffb_ras_fill(sc); 1099 ffb_ras_setfg(sc, bg); 1100 ffb_ras_fifo_wait(sc, 4); 1101 FBC_WRITE(sc, FFB_FBC_BY, y); 1102 FBC_WRITE(sc, FFB_FBC_BX, x); 1103 FBC_WRITE(sc, FFB_FBC_BH, he); 1104 FBC_WRITE(sc, FFB_FBC_BW, wi); 1105 1106 /* if we draw a space we're done */ 1107 if (c == ' ') return; 1108 1109 /* now enable alpha blending */ 1110 ffb_ras_setfg(sc, fg); 1111 ffb_ras_fifo_wait(sc, 2); 1112 FBC_WRITE(sc, FFB_FBC_ROP, FBC_ROP_NEW); 1113 1114 FBC_WRITE(sc, FFB_FBC_PPC, 1115 FBC_PPC_VCE_DIS | FBC_PPC_TBE_OPAQUE | FBC_PPC_ACE_DIS | 1116 FBC_PPC_APE_DIS | FBC_PPC_DCE_DIS | FBC_PPC_CS_CONST | 1117 FBC_PPC_ABE_ENA | FBC_PPC_XS_VAR); 1118 /* 1119 * we have to wait for both the rectangle drawing op above and 1120 * the FFB_FBC_PPC write to finish before mucking around in 1121 * the SFB aperture 1122 */ 1123 ffb_ras_wait(sc); 1124 1125 /* ... and draw the character */ 1126 dest = sc->sc_sfb32 + 2048 * y + x; 1127 for (i = 0; i < he; i++) { 1128 ddest = dest; 1129 for (j = 0; j < wi; j++) { 1130 alpha = *data8; 1131 /* 1132 * We set the colour source to constant above 1133 * so we only have to write the alpha channel 1134 * here and the colour comes from the FG 1135 * register. It would be nice if we could 1136 * just use the SFB8X aperture and memcpy() 1137 * the alpha map line by line but for some 1138 * strange reason that will take colour info 1139 * from the framebuffer even if we set the 1140 * FBC_PPC_CS_CONST bit above. 1141 */ 1142 *ddest = alpha << 24; 1143 data8++; 1144 ddest++; 1145 } 1146 dest += 2048; 1147 } 1148 } 1149 } 1150 1151 int 1152 ffb_allocattr(void *cookie, int fg, int bg, int flags, long *attrp) 1153 { 1154 if ((fg == 0) && (bg == 0)) 1155 { 1156 fg = WS_DEFAULT_FG; 1157 bg = WS_DEFAULT_BG; 1158 } 1159 if (flags & WSATTR_REVERSE) { 1160 *attrp = (bg & 0xff) << 24 | (fg & 0xff) << 16 | 1161 (flags & 0xff); 1162 } else 1163 *attrp = (fg & 0xff) << 24 | (bg & 0xff) << 16 | 1164 (flags & 0xff); 1165 return 0; 1166 } 1167 1168 void 1169 ffb_init_screen(void *cookie, struct vcons_screen *scr, 1170 int existing, long *defattr) 1171 { 1172 struct ffb_softc *sc = cookie; 1173 struct rasops_info *ri = &scr->scr_ri; 1174 1175 ri->ri_depth = 32; 1176 ri->ri_width = sc->sc_width; 1177 ri->ri_height = sc->sc_height; 1178 ri->ri_stride = sc->sc_linebytes; 1179 ri->ri_flg = RI_CENTER | RI_ENABLE_ALPHA; 1180 1181 /* 1182 * we can't accelerate copycols() so instead of falling back to 1183 * software use vcons' putchar() based implementation 1184 */ 1185 scr->scr_flags |= VCONS_NO_COPYCOLS; 1186 #ifdef VCONS_DRAW_INTR 1187 scr->scr_flags |= VCONS_DONT_READ; 1188 #endif 1189 DPRINTF(("ffb_init_screen: addr: %08lx\n",(ulong)ri->ri_bits)); 1190 1191 /* explicitly request BGR in case the default changes */ 1192 ri->ri_rnum = 8; 1193 ri->ri_gnum = 8; 1194 ri->ri_bnum = 8; 1195 ri->ri_rpos = 0; 1196 ri->ri_gpos = 8; 1197 ri->ri_bpos = 16; 1198 1199 rasops_init(ri, 0, 0); 1200 ri->ri_caps = WSSCREEN_WSCOLORS; 1201 rasops_reconfig(ri, sc->sc_height / ri->ri_font->fontheight, 1202 sc->sc_width / ri->ri_font->fontwidth); 1203 1204 /* enable acceleration */ 1205 ri->ri_ops.copyrows = ffb_ras_copyrows; 1206 ri->ri_ops.eraserows = ffb_ras_eraserows; 1207 ri->ri_ops.erasecols = ffb_ras_erasecols; 1208 ri->ri_ops.cursor = ffb_cursor; 1209 ri->ri_ops.allocattr = ffb_allocattr; 1210 ri->ri_ops.putchar = ffb_putchar; 1211 } 1212 1213 /* I2C bitbanging */ 1214 static void ffb_i2cbb_set_bits(void *cookie, uint32_t bits) 1215 { 1216 struct ffb_softc *sc = cookie; 1217 1218 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_CFG_MPDATA); 1219 DAC_WRITE(sc, FFB_DAC_VALUE, bits); 1220 } 1221 1222 static void ffb_i2cbb_set_dir(void *cookie, uint32_t dir) 1223 { 1224 /* Nothing to do */ 1225 } 1226 1227 static uint32_t ffb_i2cbb_read(void *cookie) 1228 { 1229 struct ffb_softc *sc = cookie; 1230 uint32_t bits; 1231 1232 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_CFG_MPSENSE); 1233 bits = DAC_READ(sc, FFB_DAC_VALUE); 1234 1235 return bits; 1236 } 1237 1238 /* higher level I2C stuff */ 1239 static int 1240 ffb_i2c_acquire_bus(void *cookie, int flags) 1241 { 1242 /* private bus */ 1243 return (0); 1244 } 1245 1246 static void 1247 ffb_i2c_release_bus(void *cookie, int flags) 1248 { 1249 /* private bus */ 1250 } 1251 1252 static int 1253 ffb_i2c_send_start(void *cookie, int flags) 1254 { 1255 return (i2c_bitbang_send_start(cookie, flags, &ffb_i2cbb_ops)); 1256 } 1257 1258 static int 1259 ffb_i2c_send_stop(void *cookie, int flags) 1260 { 1261 1262 return (i2c_bitbang_send_stop(cookie, flags, &ffb_i2cbb_ops)); 1263 } 1264 1265 static int 1266 ffb_i2c_initiate_xfer(void *cookie, i2c_addr_t addr, int flags) 1267 { 1268 /* 1269 * for some reason i2c_bitbang_initiate_xfer left-shifts 1270 * the I2C-address and then sets the direction bit 1271 */ 1272 return (i2c_bitbang_initiate_xfer(cookie, addr, flags, 1273 &ffb_i2cbb_ops)); 1274 } 1275 1276 static int 1277 ffb_i2c_read_byte(void *cookie, uint8_t *valp, int flags) 1278 { 1279 return (i2c_bitbang_read_byte(cookie, valp, flags, &ffb_i2cbb_ops)); 1280 } 1281 1282 static int 1283 ffb_i2c_write_byte(void *cookie, uint8_t val, int flags) 1284 { 1285 return (i2c_bitbang_write_byte(cookie, val, flags, &ffb_i2cbb_ops)); 1286 } 1287 1288 1289 #define TVC_READ_LIMIT 100000 1290 int 1291 ffb_tgc_disable(struct ffb_softc *sc) 1292 { 1293 int i; 1294 1295 /* Is the timing generator disabled? */ 1296 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_TGC); 1297 if (!(DAC_READ(sc, FFB_DAC_VALUE) & FFB_DAC_TGC_TIMING_ENABLE)) 1298 return 1; 1299 1300 /* If not, disable it when the vertical counter reaches 0 */ 1301 for (i = 0; i < TVC_READ_LIMIT; i++) { 1302 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_TVC); 1303 if (!DAC_READ(sc, FFB_DAC_VALUE)) { 1304 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_TGC); 1305 DAC_WRITE(sc, FFB_DAC_VALUE, 0); 1306 return 1; 1307 } 1308 } 1309 return 0; 1310 } 1311 1312 /* 1313 * PLL Control Register values: 1314 * M)ultiplier = bits 0:6 + 1 1315 * D)ivisor = bits 7:10 + 1 1316 * P)ost divisor = bits 11:13 (000 = 1, 001 = 2, 010 = 4, 011 = 8) 1317 * Frequency = 13.5 * M / D / P 1318 */ 1319 #define FFB_PLL_FREQ 13500000 1320 void 1321 ffb_get_pclk(int request, uint32_t *pll, int *diff) 1322 { 1323 int m, d, p, f, hex = 0, curdiff; 1324 1325 *diff = 100000000; 1326 1327 for (m = 32; m <= 80; m++) { 1328 for (d = 4; d <= 11; d++) { 1329 for (p = 1; p <= 8; p = p << 1) { 1330 switch (p) { 1331 case 1: 1332 hex = 0x4000 + (d << 7) + m; 1333 break; 1334 case 2: 1335 hex = 0x4800 + (d << 7) + m; 1336 break; 1337 case 4: 1338 hex = 0x5000 + (d << 7) + m; 1339 break; 1340 case 8: 1341 hex = 0x6000 + (d << 7) + m; 1342 break; 1343 } 1344 f = 13500000 * m / d / p; 1345 if (f == request) { 1346 *diff = 0; 1347 *pll = hex; 1348 return; 1349 } else { 1350 curdiff = abs(request - f); 1351 if (curdiff < *diff) { 1352 *diff = curdiff; 1353 *pll = hex; 1354 } 1355 } 1356 } 1357 } 1358 } 1359 } 1360 1361 /* 1362 * Details of the FFB RAMDAC are contained in the Brooktree BT497/498 1363 * and in the Connexant BT497A/498A documentation. 1364 * 1365 * VESA timings to FFB register conversion: 1366 * If interleave = 4/2:1 then x = 2, if interleave = 8/2:1 then x = 4 1367 * VBE = VBS - vres = (sync pulse - 1) + back porch 1368 * VBS = VSS - front porch = (sync pulse - 1) + back porch + vres 1369 * VSE = sync pulse - 1 1370 * VSS = (sync pulse - 1) + back porch + vres + front porch 1371 * HRE = HSS - HSE - 1 1372 * HBE = (sync pulse + back porch) / x - 1 1373 * HBS = (sync pulse + back porch + hres) / x - 1 1374 * HSE = sync pulse / x - 1 1375 * HSS = (sync pulse + back porch + hres + front porch) / x - 1 1376 * HCE = HBS - 4 1377 * HCS = HBE - 4 1378 * EPE = EIE = EIS = 0 (for all non-interlaced modes) 1379 * 1380 * Note, that 8/2:1 Single Buffered Interleaving is only supported by the 1381 * double-buffered FFB (Creator3D), and at higher resolutions than 1280x1024 1382 * 1383 * Note, that the timing generator should be disabled and re-enabled when the 1384 * the timing parameter registers are being programmed. Stopping the timing 1385 * generator should only be done when the vertical counter is zero. 1386 */ 1387 #define DIVIDE(x,y) (((x) + ((y) / 2)) / (y)) 1388 int 1389 ffb_set_vmode(struct ffb_softc *sc, struct videomode *mode, int btype, 1390 int *hres, int *vres) 1391 { 1392 int diff; 1393 uint32_t fp, sp, bp, x; 1394 uint32_t pll, pfc, ucl, dcl, tgc; 1395 uint32_t vbe, vbs, vse, vss, hre, hbe, hbs, hse, hss, hce, hcs; 1396 uint32_t epe, eie, eis; 1397 uint32_t fbcfg0; 1398 1399 DPRINTF(("ffb_set_vmode: %dx%d@%d", mode->hdisplay, mode->vdisplay, 1400 DIVIDE(DIVIDE(mode->dot_clock * 1000, 1401 mode->htotal), mode->vtotal))); 1402 DPRINTF((" (%d %d %d %d %d %d %d", 1403 mode->dot_clock, mode->hsync_start, mode->hsync_end, mode->htotal, 1404 mode->vsync_start, mode->vsync_end, mode->vtotal)); 1405 DPRINTF((" %s%sH %s%sV)\n", 1406 mode->flags & VID_PHSYNC ? "+" : "", 1407 mode->flags & VID_NHSYNC ? "-" : "", 1408 mode->flags & VID_PVSYNC ? "+" : "", 1409 mode->flags & VID_NVSYNC ? "-" : "")); 1410 1411 /* We don't handle interlaced or doublescan (yet) */ 1412 if ((mode->flags & VID_INTERLACE) || (mode->flags & VID_DBLSCAN)) 1413 return 0; 1414 1415 /* Only Creator3D can be set to > 1280x1024 */ 1416 if(((sc->sc_type == FFB_CREATOR && !((btype & 7) == 3)) || 1417 sc->sc_type == FFB_AFB) 1418 && (mode->hdisplay > 1280 || mode->vdisplay > 1024)) 1419 return 0; 1420 /* Creator3D can be set to <= 1920x1360 */ 1421 if (mode->hdisplay > 1920 || mode->vdisplay > 1360) 1422 return 0; 1423 1424 /* 1425 * Look for a matching pixel clock and set PLL Control. 1426 * XXX: 640x480@60 is 25175000 in modelines but 25125000 in the 1427 * FFB PROM, and the closest match to 25175000 (0x4da9/25159090) 1428 * does not work. So, use the PROM value instead. 1429 */ 1430 if (mode->hdisplay == 640 && mode->vdisplay == 480 && 1431 mode->dot_clock == 25175) { 1432 DPRINTF(("ffb_set_vmode: 640x480@60: adjusted dot clock\n")); 1433 mode->dot_clock = 25125; 1434 } 1435 ffb_get_pclk(mode->dot_clock * 1000, &pll, &diff); 1436 if (diff > 250000) 1437 return 0; 1438 1439 /* Pixel Format Control, User Control and FBC Configuration. */ 1440 if (mode->hdisplay > 1280) { 1441 pfc = FFB_DAC_PIX_FMT_821; 1442 ucl = FFB_DAC_USR_CTRL_OVERLAY | FFB_DAC_USR_CTRL_WMODE_C; 1443 x = 4; 1444 fbcfg0 = FBC_READ(sc, FFB_FBC_FBCFG0) | FBC_CFG0_DOUBLE_BUF; 1445 } else { 1446 pfc = FFB_DAC_PIX_FMT_421; 1447 /* Only Creator3D and Elite3D can have double-buffer */ 1448 if ((sc->sc_type == FFB_CREATOR && !((btype & 7) == 3))) 1449 ucl = 0; 1450 else 1451 ucl = FFB_DAC_USR_CTRL_DOUBLE; 1452 ucl |= (FFB_DAC_USR_CTRL_OVERLAY | FFB_DAC_USR_CTRL_WMODE_S8); 1453 x = 2; 1454 fbcfg0 = FBC_READ(sc, FFB_FBC_FBCFG0) | FBC_CFG0_SINGLE_BUF; 1455 } 1456 1457 /* DAC Control and Timing Generator Control */ 1458 if (mode->flags & VID_PVSYNC) 1459 dcl = FFB_DAC_DAC_CTRL_POS_VSYNC; 1460 else 1461 dcl = 0; 1462 tgc = 0; 1463 #define EDID_VID_INP sc->sc_edid_info.edid_video_input 1464 if ((EDID_VID_INP & EDID_VIDEO_INPUT_COMPOSITE_SYNC)) { 1465 dcl |= FFB_DAC_DAC_CTRL_VSYNC_DIS; 1466 tgc = FFB_DAC_TGC_EQUAL_DISABLE; 1467 } else { 1468 dcl |= FFB_DAC_DAC_CTRL_SYNC_G; 1469 if (EDID_VID_INP & EDID_VIDEO_INPUT_SEPARATE_SYNCS) 1470 tgc |= FFB_DAC_TGC_VSYNC_DISABLE; 1471 else 1472 tgc = FFB_DAC_TGC_EQUAL_DISABLE; 1473 } 1474 if (EDID_VID_INP & EDID_VIDEO_INPUT_BLANK_TO_BLACK) 1475 dcl |= FFB_DAC_DAC_CTRL_PED_ENABLE; 1476 tgc |= (FFB_DAC_TGC_VIDEO_ENABLE | FFB_DAC_TGC_TIMING_ENABLE | 1477 FFB_DAC_TGC_MASTER_ENABLE); 1478 1479 /* Vertical timing */ 1480 fp = mode->vsync_start - mode->vdisplay; 1481 sp = mode->vsync_end - mode->vsync_start; 1482 bp = mode->vtotal - mode->vsync_end; 1483 1484 vbe = sp - 1 + bp; 1485 vbs = sp - 1 + bp + mode->vdisplay; 1486 vse = sp - 1; 1487 vss = sp - 1 + bp + mode->vdisplay + fp; 1488 1489 /* Horizontal timing */ 1490 fp = mode->hsync_start - mode->hdisplay; 1491 sp = mode->hsync_end - mode->hsync_start; 1492 bp = mode->htotal - mode->hsync_end; 1493 1494 hbe = (sp + bp) / x - 1; 1495 hbs = (sp + bp + mode->hdisplay) / x - 1; 1496 hse = sp / x - 1; 1497 hss = (sp + bp + mode->hdisplay + fp) / x -1; 1498 hre = hss - hse - 1; 1499 hce = hbs - 4; 1500 hcs = hbe - 4; 1501 1502 /* Equalisation (interlaced modes) */ 1503 epe = 0; 1504 eie = 0; 1505 eis = 0; 1506 1507 DPRINTF(("ffb_set_vmode: 0x%04x 0x%04x 0x%04x 0x%04x 0x%04x\n", 1508 pll, pfc, ucl, dcl, tgc)); 1509 DPRINTF(("\t0x%04x 0x%04x 0x%04x 0x%04x\n", vbe, vbs, vse, vss)); 1510 DPRINTF(("\t0x%04x 0x%04x 0x%04x 0x%04x 0x%04x 0x%04x 0x%04x\n", 1511 hre, hbe, hbs, hse, hss, hce, hcs)); 1512 DPRINTF(("\t0x%04x 0x%04x 0x%04x\n", epe, eie, eis)); 1513 1514 if (!ffb_tgc_disable(sc)) { 1515 DPRINTF(("ffb_set_vmode: failed to disable TGC register\n")); 1516 return 0; 1517 } 1518 1519 /* 1520 * Program the mode registers. 1521 * Program the timing generator last, as that re-enables output. 1522 * Note, that a read to/write from a register increments the 1523 * register address to the next register automatically. 1524 */ 1525 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_PLL_CTRL); 1526 DAC_WRITE(sc, FFB_DAC_VALUE, pll); 1527 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_PIX_FMT); 1528 DAC_WRITE(sc, FFB_DAC_VALUE, pfc); 1529 DAC_WRITE(sc, FFB_DAC_VALUE, ucl); 1530 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_DAC_CTRL); 1531 DAC_WRITE(sc, FFB_DAC_VALUE, dcl); 1532 1533 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_VBE); 1534 DAC_WRITE(sc, FFB_DAC_VALUE, vbe); 1535 DAC_WRITE(sc, FFB_DAC_VALUE, vbs); 1536 DAC_WRITE(sc, FFB_DAC_VALUE, vse); 1537 DAC_WRITE(sc, FFB_DAC_VALUE, vss); 1538 1539 DAC_WRITE(sc, FFB_DAC_VALUE, hre); 1540 DAC_WRITE(sc, FFB_DAC_VALUE, hbe); 1541 DAC_WRITE(sc, FFB_DAC_VALUE, hbs); 1542 DAC_WRITE(sc, FFB_DAC_VALUE, hse); 1543 DAC_WRITE(sc, FFB_DAC_VALUE, hss); 1544 DAC_WRITE(sc, FFB_DAC_VALUE, hce); 1545 DAC_WRITE(sc, FFB_DAC_VALUE, hcs); 1546 1547 DAC_WRITE(sc, FFB_DAC_VALUE, epe); 1548 DAC_WRITE(sc, FFB_DAC_VALUE, eie); 1549 DAC_WRITE(sc, FFB_DAC_VALUE, eis); 1550 1551 FBC_WRITE(sc, FFB_FBC_FBCFG0, fbcfg0); 1552 1553 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_TGC); 1554 DAC_WRITE(sc, FFB_DAC_VALUE, tgc); 1555 DPRINTF(("new tgc: %08x\n", tgc)); 1556 1557 *hres = mode->hdisplay; 1558 *vres = mode->vdisplay; 1559 1560 printf("%s: video mode set to %d x %d @ %dHz\n", 1561 device_xname(sc->sc_dev), 1562 mode->hdisplay, mode->vdisplay, 1563 DIVIDE(DIVIDE(mode->dot_clock * 1000, 1564 mode->htotal), mode->vtotal)); 1565 1566 return 1; 1567 } 1568
Indexes created Fri Sep 26 08:10:20 GMT 2025