ffb.c revision 1.53
1 /* $NetBSD: ffb.c,v 1.53 2013/07/30 19:16:50 macallan Exp $ */ 2 /* $OpenBSD: creator.c,v 1.20 2002/07/30 19:48:15 jason Exp $ */ 3 4 /* 5 * Copyright (c) 2002 Jason L. Wright (jason (at) thought.net) 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Jason L. Wright 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 25 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 26 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 27 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 30 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 31 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32 * POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: ffb.c,v 1.53 2013/07/30 19:16:50 macallan Exp $"); 37 38 #include <sys/types.h> 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/kernel.h> 42 #include <sys/device.h> 43 #include <sys/conf.h> 44 #include <sys/ioctl.h> 45 #include <sys/malloc.h> 46 #include <sys/mman.h> 47 48 #include <sys/bus.h> 49 #include <machine/autoconf.h> 50 #include <machine/openfirm.h> 51 #include <machine/vmparam.h> 52 53 #include <dev/wscons/wsconsio.h> 54 #include <dev/sun/fbio.h> 55 #include <dev/sun/fbvar.h> 56 57 #include <dev/wsfont/wsfont.h> 58 #include <dev/wscons/wsdisplay_vconsvar.h> 59 60 #include <prop/proplib.h> 61 62 #include <dev/i2c/i2cvar.h> 63 #include <dev/i2c/i2c_bitbang.h> 64 #include <dev/i2c/ddcvar.h> 65 66 #include <sparc64/dev/ffbreg.h> 67 #include <sparc64/dev/ffbvar.h> 68 69 #include "opt_wsdisplay_compat.h" 70 #include "opt_ffb.h" 71 72 #ifndef WS_DEFAULT_BG 73 /* Sun -> background should be white */ 74 #define WS_DEFAULT_BG 0xf 75 #endif 76 77 #ifdef FFB_SYNC 78 #define SYNC ffb_ras_wait(sc) 79 #else 80 #define SYNC 81 #endif 82 83 /* Debugging */ 84 #if !defined FFB_DEBUG 85 #define FFB_DEBUG 0 86 #endif 87 #define DPRINTF(x) if (ffb_debug) printf x 88 /* Patchable */ 89 extern int ffb_debug; 90 #if FFB_DEBUG > 0 91 int ffb_debug = 1; 92 #else 93 int ffb_debug = 0; 94 #endif 95 96 extern struct cfdriver ffb_cd; 97 98 struct wsscreen_descr ffb_stdscreen = { 99 "sunffb", 100 0, 0, /* will be filled in -- XXX shouldn't, it's global. */ 101 0, 102 0, 0, 103 WSSCREEN_REVERSE | WSSCREEN_WSCOLORS, 104 NULL /* modecookie */ 105 }; 106 107 const struct wsscreen_descr *ffb_scrlist[] = { 108 &ffb_stdscreen, 109 /* XXX other formats? */ 110 }; 111 112 struct wsscreen_list ffb_screenlist = { 113 sizeof(ffb_scrlist) / sizeof(struct wsscreen_descr *), 114 ffb_scrlist 115 }; 116 117 static struct vcons_screen ffb_console_screen; 118 119 int ffb_ioctl(void *, void *, u_long, void *, int, struct lwp *); 120 static int ffb_blank(struct ffb_softc *, u_long, u_int *); 121 paddr_t ffb_mmap(void *, void *, off_t, int); 122 void ffb_ras_fifo_wait(struct ffb_softc *, int); 123 void ffb_ras_wait(struct ffb_softc *); 124 void ffb_ras_init(struct ffb_softc *); 125 void ffb_ras_copyrows(void *, int, int, int); 126 void ffb_ras_erasecols(void *, int, int, int, long int); 127 void ffb_ras_eraserows(void *, int, int, long int); 128 void ffb_ras_do_cursor(struct rasops_info *); 129 void ffb_ras_fill(struct ffb_softc *); 130 void ffb_ras_invert(struct ffb_softc *); 131 static void ffb_ras_setfg(struct ffb_softc *, int32_t); 132 static void ffb_ras_setbg(struct ffb_softc *, int32_t); 133 134 void ffb_clearscreen(struct ffb_softc *); 135 int ffb_load_font(void *, void *, struct wsdisplay_font *); 136 void ffb_init_screen(void *, struct vcons_screen *, int, 137 long *); 138 int ffb_allocattr(void *, int, int, int, long *); 139 void ffb_putchar_mono(void *, int, int, u_int, long); 140 void ffb_putchar_aa(void *, int, int, u_int, long); 141 void ffb_cursor(void *, int, int, int); 142 143 /* frame buffer generic driver */ 144 static void ffbfb_unblank(device_t); 145 dev_type_open(ffbfb_open); 146 dev_type_close(ffbfb_close); 147 dev_type_ioctl(ffbfb_ioctl); 148 dev_type_mmap(ffbfb_mmap); 149 150 static struct fbdriver ffb_fbdriver = { 151 ffbfb_unblank, ffbfb_open, ffbfb_close, ffbfb_ioctl, nopoll, 152 ffbfb_mmap, nokqfilter 153 }; 154 155 struct wsdisplay_accessops ffb_accessops = { 156 .ioctl = ffb_ioctl, 157 .mmap = ffb_mmap, 158 }; 159 160 /* I2C glue */ 161 static int ffb_i2c_acquire_bus(void *, int); 162 static void ffb_i2c_release_bus(void *, int); 163 static int ffb_i2c_send_start(void *, int); 164 static int ffb_i2c_send_stop(void *, int); 165 static int ffb_i2c_initiate_xfer(void *, i2c_addr_t, int); 166 static int ffb_i2c_read_byte(void *, uint8_t *, int); 167 static int ffb_i2c_write_byte(void *, uint8_t, int); 168 169 /* I2C bitbang glue */ 170 static void ffb_i2cbb_set_bits(void *, uint32_t); 171 static void ffb_i2cbb_set_dir(void *, uint32_t); 172 static uint32_t ffb_i2cbb_read(void *); 173 174 static const struct i2c_bitbang_ops ffb_i2cbb_ops = { 175 ffb_i2cbb_set_bits, 176 ffb_i2cbb_set_dir, 177 ffb_i2cbb_read, 178 { 179 FFB_DAC_CFG_MPDATA_SDA, 180 FFB_DAC_CFG_MPDATA_SCL, 181 0, 182 0 183 } 184 }; 185 186 void ffb_attach_i2c(struct ffb_softc *); 187 188 /* Video mode setting */ 189 int ffb_tgc_disable(struct ffb_softc *); 190 void ffb_get_pclk(int, uint32_t *, int *); 191 int ffb_set_vmode(struct ffb_softc *, struct videomode *, int, int *, int *); 192 193 194 void 195 ffb_attach(device_t self) 196 { 197 struct ffb_softc *sc = device_private(self); 198 struct wsemuldisplaydev_attach_args waa; 199 struct rasops_info *ri; 200 long defattr; 201 const char *model, *out_dev; 202 int btype; 203 uint32_t dac; 204 int maxrow, maxcol; 205 u_int blank = WSDISPLAYIO_VIDEO_ON; 206 char buf[6+1]; 207 int i, try_edid; 208 prop_data_t data; 209 210 printf(":"); 211 212 if (sc->sc_type == FFB_CREATOR) { 213 btype = prom_getpropint(sc->sc_node, "board_type", 0); 214 if ((btype & 7) == 3) 215 printf(" Creator3D"); 216 else 217 printf(" Creator"); 218 } else { 219 printf(" Elite3D"); 220 btype = 0; 221 } 222 223 model = prom_getpropstring(sc->sc_node, "model"); 224 if (model == NULL || strlen(model) == 0) 225 model = "unknown"; 226 227 sc->sc_depth = 24; 228 sc->sc_linebytes = 8192; 229 /* We might alter these during EDID mode setting */ 230 sc->sc_height = prom_getpropint(sc->sc_node, "height", 0); 231 sc->sc_width = prom_getpropint(sc->sc_node, "width", 0); 232 233 sc->sc_locked = 0; 234 sc->sc_mode = WSDISPLAYIO_MODE_EMUL; 235 236 maxcol = (prom_getoption("screen-#columns", buf, sizeof buf) == 0) 237 ? strtoul(buf, NULL, 10) 238 : 80; 239 240 maxrow = (prom_getoption("screen-#rows", buf, sizeof buf) != 0) 241 ? strtoul(buf, NULL, 10) 242 : 34; 243 244 /* collect DAC version, as Elite3D cursor enable bit is reversed */ 245 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_DEVID); 246 dac = DAC_READ(sc, FFB_DAC_VALUE); 247 sc->sc_dacrev = (dac >> 28) & 0xf; 248 249 if (sc->sc_type == FFB_AFB) { 250 sc->sc_dacrev = 10; 251 sc->sc_needredraw = 0; 252 } else { 253 /* see what kind of DAC we have */ 254 int pnum = (dac & 0x0ffff000) >> 12; 255 if (pnum == 0x236e) { 256 sc->sc_needredraw = 0; 257 } else { 258 sc->sc_needredraw = 1; 259 } 260 } 261 printf(", model %s, dac %u\n", model, sc->sc_dacrev); 262 if (sc->sc_needredraw) 263 printf("%s: found old DAC, enabling redraw on unblank\n", 264 device_xname(sc->sc_dev)); 265 266 /* Check if a console resolution "<device>:r<res>" is set. */ 267 if (sc->sc_console) { 268 out_dev = prom_getpropstring(sc->sc_node, "output_device"); 269 if (out_dev != NULL && strlen(out_dev) != 0 && 270 strstr(out_dev, ":r") != NULL) 271 try_edid = 0; 272 else 273 try_edid = 1; 274 } else 275 try_edid = 1; 276 277 #if FFB_DEBUG > 0 278 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_TGC); 279 printf("tgc: %08x\n", DAC_READ(sc, FFB_DAC_VALUE)); 280 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_DAC_CTRL); 281 printf("dcl: %08x\n", DAC_READ(sc, FFB_DAC_VALUE)); 282 #endif 283 ffb_attach_i2c(sc); 284 285 /* Need to set asynchronous blank during DDC write/read */ 286 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_USR_CTRL); 287 dac = DAC_READ(sc, FFB_DAC_VALUE); 288 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_USR_CTRL); 289 DAC_WRITE(sc, FFB_DAC_VALUE, dac | FFB_DAC_USR_CTRL_BLANK); 290 291 /* Some monitors don't respond first time */ 292 i = 0; 293 while (sc->sc_edid_data[1] == 0 && i++ < 3) 294 ddc_read_edid(&sc->sc_i2c, sc->sc_edid_data, EDID_DATA_LEN); 295 296 /* Remove asynchronous blank */ 297 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_USR_CTRL); 298 DAC_WRITE(sc, FFB_DAC_VALUE, dac); 299 300 if (edid_parse(&sc->sc_edid_data[0], &sc->sc_edid_info) != -1) { 301 sort_modes(sc->sc_edid_info.edid_modes, 302 &sc->sc_edid_info.edid_preferred_mode, 303 sc->sc_edid_info.edid_nmodes); 304 DPRINTF(("%s: EDID data:\n ", device_xname(sc->sc_dev))); 305 for (i = 0; i < EDID_DATA_LEN; i++) { 306 if (i && !(i % 32)) 307 DPRINTF(("\n ")); 308 if (i && !(i % 4)) 309 DPRINTF((" ")); 310 DPRINTF(("%02x", sc->sc_edid_data[i])); 311 } 312 DPRINTF(("\n")); 313 if (ffb_debug) 314 edid_print(&sc->sc_edid_info); 315 316 data = prop_data_create_data(sc->sc_edid_data, EDID_DATA_LEN); 317 prop_dictionary_set(device_properties(self), "EDID", data); 318 prop_object_release(data); 319 320 if (try_edid) 321 for (i = 0; i < sc->sc_edid_info.edid_nmodes; i++) { 322 if (ffb_set_vmode(sc, 323 &(sc->sc_edid_info.edid_modes[i]), btype, 324 &(sc->sc_width), &(sc->sc_height))) 325 break; 326 } 327 } else { 328 DPRINTF(("%s: No EDID data.\n", device_xname(sc->sc_dev))); 329 } 330 331 ffb_ras_init(sc); 332 333 ffb_blank(sc, WSDISPLAYIO_SVIDEO, &blank); 334 335 sc->sc_accel = ((device_cfdata(sc->sc_dev)->cf_flags & 336 FFB_CFFLAG_NOACCEL) == 0); 337 338 wsfont_init(); 339 340 vcons_init(&sc->vd, sc, &ffb_stdscreen, &ffb_accessops); 341 sc->vd.init_screen = ffb_init_screen; 342 ri = &ffb_console_screen.scr_ri; 343 344 /* we mess with ffb_console_screen only once */ 345 if (sc->sc_console) { 346 vcons_init_screen(&sc->vd, &ffb_console_screen, 1, &defattr); 347 SCREEN_VISIBLE((&ffb_console_screen)); 348 /* 349 * XXX we shouldn't use a global variable for the console 350 * screen 351 */ 352 sc->vd.active = &ffb_console_screen; 353 ffb_console_screen.scr_flags = VCONS_SCREEN_IS_STATIC; 354 } else { 355 if (ffb_console_screen.scr_ri.ri_rows == 0) { 356 /* do some minimal setup to avoid weirdnesses later */ 357 vcons_init_screen(&sc->vd, &ffb_console_screen, 1, &defattr); 358 } else 359 (*ri->ri_ops.allocattr)(ri, 0, 0, 0, &defattr); 360 } 361 362 ffb_stdscreen.nrows = ri->ri_rows; 363 ffb_stdscreen.ncols = ri->ri_cols; 364 ffb_stdscreen.textops = &ri->ri_ops; 365 ffb_stdscreen.capabilities = ri->ri_caps; 366 367 sc->sc_fb.fb_driver = &ffb_fbdriver; 368 sc->sc_fb.fb_type.fb_cmsize = 0; 369 sc->sc_fb.fb_type.fb_size = maxrow * sc->sc_linebytes; 370 sc->sc_fb.fb_type.fb_type = FBTYPE_CREATOR; 371 sc->sc_fb.fb_type.fb_width = sc->sc_width; 372 sc->sc_fb.fb_type.fb_depth = sc->sc_depth; 373 sc->sc_fb.fb_type.fb_height = sc->sc_height; 374 sc->sc_fb.fb_device = sc->sc_dev; 375 fb_attach(&sc->sc_fb, sc->sc_console); 376 377 ffb_clearscreen(sc); 378 379 if (sc->sc_console) { 380 wsdisplay_cnattach(&ffb_stdscreen, ri, 0, 0, defattr); 381 vcons_replay_msgbuf(&ffb_console_screen); 382 } 383 384 waa.console = sc->sc_console; 385 waa.scrdata = &ffb_screenlist; 386 waa.accessops = &ffb_accessops; 387 waa.accesscookie = &sc->vd; 388 config_found(sc->sc_dev, &waa, wsemuldisplaydevprint); 389 } 390 391 void 392 ffb_attach_i2c(struct ffb_softc *sc) 393 { 394 395 /* Fill in the i2c tag */ 396 sc->sc_i2c.ic_cookie = sc; 397 sc->sc_i2c.ic_acquire_bus = ffb_i2c_acquire_bus; 398 sc->sc_i2c.ic_release_bus = ffb_i2c_release_bus; 399 sc->sc_i2c.ic_send_start = ffb_i2c_send_start; 400 sc->sc_i2c.ic_send_stop = ffb_i2c_send_stop; 401 sc->sc_i2c.ic_initiate_xfer = ffb_i2c_initiate_xfer; 402 sc->sc_i2c.ic_read_byte = ffb_i2c_read_byte; 403 sc->sc_i2c.ic_write_byte = ffb_i2c_write_byte; 404 sc->sc_i2c.ic_exec = NULL; 405 } 406 407 int 408 ffb_ioctl(void *v, void *vs, u_long cmd, void *data, int flags, struct lwp *l) 409 { 410 struct vcons_data *vd = v; 411 struct ffb_softc *sc = vd->cookie; 412 struct wsdisplay_fbinfo *wdf; 413 struct vcons_screen *ms = vd->active; 414 415 DPRINTF(("ffb_ioctl: %s cmd _IO%s%s('%c', %lu)\n", 416 device_xname(sc->sc_dev), 417 (cmd & IOC_IN) ? "W" : "", (cmd & IOC_OUT) ? "R" : "", 418 (char)IOCGROUP(cmd), cmd & 0xff)); 419 420 switch (cmd) { 421 case FBIOGTYPE: 422 *(struct fbtype *)data = sc->sc_fb.fb_type; 423 break; 424 case FBIOGATTR: 425 #define fba ((struct fbgattr *)data) 426 fba->real_type = sc->sc_fb.fb_type.fb_type; 427 fba->owner = 0; /* XXX ??? */ 428 fba->fbtype = sc->sc_fb.fb_type; 429 fba->sattr.flags = 0; 430 fba->sattr.emu_type = sc->sc_fb.fb_type.fb_type; 431 fba->sattr.dev_specific[0] = -1; 432 fba->emu_types[0] = sc->sc_fb.fb_type.fb_type; 433 fba->emu_types[1] = -1; 434 #undef fba 435 break; 436 437 case FBIOGETCMAP: 438 case FBIOPUTCMAP: 439 return EIO; 440 441 case FBIOGVIDEO: 442 case FBIOSVIDEO: 443 return ffb_blank(sc, cmd == FBIOGVIDEO? 444 WSDISPLAYIO_GVIDEO : WSDISPLAYIO_SVIDEO, 445 (u_int *)data); 446 break; 447 case FBIOGCURSOR: 448 case FBIOSCURSOR: 449 /* the console driver is not using the hardware cursor */ 450 break; 451 case FBIOGCURPOS: 452 printf("%s: FBIOGCURPOS not implemented\n", 453 device_xname(sc->sc_dev)); 454 return EIO; 455 case FBIOSCURPOS: 456 printf("%s: FBIOSCURPOS not implemented\n", 457 device_xname(sc->sc_dev)); 458 return EIO; 459 case FBIOGCURMAX: 460 printf("%s: FBIOGCURMAX not implemented\n", 461 device_xname(sc->sc_dev)); 462 return EIO; 463 464 case WSDISPLAYIO_GTYPE: 465 *(u_int *)data = WSDISPLAY_TYPE_SUNFFB; 466 break; 467 case WSDISPLAYIO_SMODE: 468 { 469 if (sc->sc_mode != *(u_int *)data) { 470 sc->sc_mode = *(u_int *)data; 471 if ((sc->sc_mode == WSDISPLAYIO_MODE_EMUL) && 472 (sc->sc_locked == 0)) { 473 ffb_ras_init(sc); 474 vcons_redraw_screen(ms); 475 } 476 } 477 } 478 break; 479 case WSDISPLAYIO_GINFO: 480 wdf = (void *)data; 481 wdf->height = sc->sc_height; 482 wdf->width = sc->sc_width; 483 wdf->depth = 32; 484 wdf->cmsize = 256; /* XXX */ 485 break; 486 #ifdef WSDISPLAYIO_LINEBYTES 487 case WSDISPLAYIO_LINEBYTES: 488 *(u_int *)data = sc->sc_linebytes; 489 break; 490 #endif 491 case WSDISPLAYIO_GETCMAP: 492 break;/* XXX */ 493 494 case WSDISPLAYIO_PUTCMAP: 495 break;/* XXX */ 496 497 case WSDISPLAYIO_SVIDEO: 498 case WSDISPLAYIO_GVIDEO: 499 return(ffb_blank(sc, cmd, (u_int *)data)); 500 break; 501 case WSDISPLAYIO_GCURPOS: 502 case WSDISPLAYIO_SCURPOS: 503 case WSDISPLAYIO_GCURMAX: 504 case WSDISPLAYIO_GCURSOR: 505 case WSDISPLAYIO_SCURSOR: 506 return EIO; /* not supported yet */ 507 break; 508 case WSDISPLAYIO_GET_EDID: { 509 struct wsdisplayio_edid_info *d = data; 510 return wsdisplayio_get_edid(sc->sc_dev, d); 511 } 512 default: 513 return EPASSTHROUGH; 514 } 515 516 return (0); 517 } 518 519 /* blank/unblank the screen */ 520 static int 521 ffb_blank(struct ffb_softc *sc, u_long cmd, u_int *data) 522 { 523 struct vcons_screen *ms = sc->vd.active; 524 u_int val; 525 526 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_TGC); 527 val = DAC_READ(sc, FFB_DAC_VALUE); 528 529 switch (cmd) { 530 case WSDISPLAYIO_GVIDEO: 531 *data = val & 1; 532 return(0); 533 break; 534 case WSDISPLAYIO_SVIDEO: 535 if (*data == WSDISPLAYIO_VIDEO_OFF) 536 val &= ~1; 537 else if (*data == WSDISPLAYIO_VIDEO_ON) 538 val |= 1; 539 else 540 return(EINVAL); 541 break; 542 default: 543 return(EINVAL); 544 } 545 546 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_TGC); 547 DAC_WRITE(sc, FFB_DAC_VALUE, val); 548 549 if ((val & 1) && sc->sc_needredraw) { 550 if (ms != NULL) { 551 if ((sc->sc_mode == WSDISPLAYIO_MODE_EMUL) && 552 (sc->sc_locked == 0)) { 553 ffb_ras_init(sc); 554 vcons_redraw_screen(ms); 555 } 556 } 557 } 558 559 return(0); 560 } 561 562 paddr_t 563 ffb_mmap(void *vsc, void *vs, off_t off, int prot) 564 { 565 struct vcons_data *vd = vsc; 566 struct ffb_softc *sc = vd->cookie; 567 int i; 568 569 switch (sc->sc_mode) { 570 case WSDISPLAYIO_MODE_MAPPED: 571 for (i = 0; i < sc->sc_nreg; i++) { 572 /* Before this set? */ 573 if (off < sc->sc_addrs[i]) 574 continue; 575 /* After this set? */ 576 if (off >= (sc->sc_addrs[i] + sc->sc_sizes[i])) 577 continue; 578 579 return (bus_space_mmap(sc->sc_bt, sc->sc_addrs[i], 580 off - sc->sc_addrs[i], prot, BUS_SPACE_MAP_LINEAR)); 581 } 582 break; 583 #ifdef WSDISPLAYIO_MODE_DUMBFB 584 case WSDISPLAYIO_MODE_DUMBFB: 585 if (sc->sc_nreg < FFB_REG_DFB24) 586 break; 587 if (off >= 0 && off < sc->sc_sizes[FFB_REG_DFB24]) 588 return (bus_space_mmap(sc->sc_bt, 589 sc->sc_addrs[FFB_REG_DFB24], off, prot, 590 BUS_SPACE_MAP_LINEAR)); 591 break; 592 #endif 593 } 594 return (-1); 595 } 596 597 void 598 ffb_ras_fifo_wait(struct ffb_softc *sc, int n) 599 { 600 int32_t cache = sc->sc_fifo_cache; 601 602 if (cache < n) { 603 do { 604 cache = FBC_READ(sc, FFB_FBC_UCSR); 605 cache = (cache & FBC_UCSR_FIFO_MASK) - 8; 606 } while (cache < n); 607 } 608 sc->sc_fifo_cache = cache - n; 609 } 610 611 void 612 ffb_ras_wait(struct ffb_softc *sc) 613 { 614 uint32_t ucsr, r; 615 616 while (1) { 617 ucsr = FBC_READ(sc, FFB_FBC_UCSR); 618 if ((ucsr & (FBC_UCSR_FB_BUSY|FBC_UCSR_RP_BUSY)) == 0) 619 break; 620 r = ucsr & (FBC_UCSR_READ_ERR | FBC_UCSR_FIFO_OVFL); 621 if (r != 0) 622 FBC_WRITE(sc, FFB_FBC_UCSR, r); 623 } 624 } 625 626 void 627 ffb_ras_init(struct ffb_softc *sc) 628 { 629 uint32_t fbc; 630 631 if (sc->sc_width > 1280) { 632 DPRINTF(("ffb_ras_init: high resolution.\n")); 633 fbc = FFB_FBC_WM_COMBINED | FFB_FBC_WE_FORCEON | 634 FFB_FBC_ZE_OFF | FFB_FBC_YE_OFF | FFB_FBC_XE_ON; 635 } else { 636 DPRINTF(("ffb_ras_init: standard resolution.\n")); 637 fbc = FFB_FBC_XE_OFF; 638 } 639 ffb_ras_fifo_wait(sc, 11); 640 DPRINTF(("WID: %08x\n", FBC_READ(sc, FFB_FBC_WID))); 641 FBC_WRITE(sc, FFB_FBC_WID, 0x0); 642 FBC_WRITE(sc, FFB_FBC_PPC, 643 FBC_PPC_VCE_DIS | FBC_PPC_TBE_OPAQUE | FBC_PPC_ACE_DIS | 644 FBC_PPC_APE_DIS | FBC_PPC_DCE_DIS | FBC_PPC_CS_CONST | 645 FBC_PPC_ABE_DIS | FBC_PPC_XS_WID); 646 647 fbc |= FFB_FBC_WB_A | FFB_FBC_RB_A | FFB_FBC_SB_BOTH | 648 FFB_FBC_RGBE_MASK; 649 DPRINTF(("%s: fbc is %08x\n", __func__, fbc)); 650 FBC_WRITE(sc, FFB_FBC_FBC, fbc); 651 FBC_WRITE(sc, FFB_FBC_ROP, FBC_ROP_NEW); 652 FBC_WRITE(sc, FFB_FBC_DRAWOP, FBC_DRAWOP_RECTANGLE); 653 FBC_WRITE(sc, FFB_FBC_PMASK, 0xffffffff); 654 FBC_WRITE(sc, FFB_FBC_FONTINC, 0x10000); 655 sc->sc_fg_cache = 0; 656 FBC_WRITE(sc, FFB_FBC_FG, sc->sc_fg_cache); 657 FBC_WRITE(sc, FFB_FBC_BLENDC, FFB_BLENDC_FORCE_ONE | 658 FFB_BLENDC_DF_ONE_M_A | 659 FFB_BLENDC_SF_A); 660 FBC_WRITE(sc, FFB_FBC_BLENDC1, 0); 661 FBC_WRITE(sc, FFB_FBC_BLENDC2, 0); 662 ffb_ras_wait(sc); 663 } 664 665 void 666 ffb_ras_eraserows(void *cookie, int row, int n, long attr) 667 { 668 struct rasops_info *ri = cookie; 669 struct vcons_screen *scr = ri->ri_hw; 670 struct ffb_softc *sc = scr->scr_cookie; 671 672 if (row < 0) { 673 n += row; 674 row = 0; 675 } 676 if (row + n > ri->ri_rows) 677 n = ri->ri_rows - row; 678 if (n <= 0) 679 return; 680 681 ffb_ras_fill(sc); 682 ffb_ras_setfg(sc, ri->ri_devcmap[(attr >> 16) & 0xf]); 683 ffb_ras_fifo_wait(sc, 4); 684 if ((n == ri->ri_rows) && (ri->ri_flg & RI_FULLCLEAR)) { 685 FBC_WRITE(sc, FFB_FBC_BY, 0); 686 FBC_WRITE(sc, FFB_FBC_BX, 0); 687 FBC_WRITE(sc, FFB_FBC_BH, ri->ri_height); 688 FBC_WRITE(sc, FFB_FBC_BW, ri->ri_width); 689 } else { 690 row *= ri->ri_font->fontheight; 691 FBC_WRITE(sc, FFB_FBC_BY, ri->ri_yorigin + row); 692 FBC_WRITE(sc, FFB_FBC_BX, ri->ri_xorigin); 693 FBC_WRITE(sc, FFB_FBC_BH, n * ri->ri_font->fontheight); 694 FBC_WRITE(sc, FFB_FBC_BW, ri->ri_emuwidth); 695 } 696 SYNC; 697 } 698 699 void 700 ffb_ras_erasecols(void *cookie, int row, int col, int n, long attr) 701 { 702 struct rasops_info *ri = cookie; 703 struct vcons_screen *scr = ri->ri_hw; 704 struct ffb_softc *sc = scr->scr_cookie; 705 706 if ((row < 0) || (row >= ri->ri_rows)) 707 return; 708 if (col < 0) { 709 n += col; 710 col = 0; 711 } 712 if (col + n > ri->ri_cols) 713 n = ri->ri_cols - col; 714 if (n <= 0) 715 return; 716 n *= ri->ri_font->fontwidth; 717 col *= ri->ri_font->fontwidth; 718 row *= ri->ri_font->fontheight; 719 720 ffb_ras_fill(sc); 721 ffb_ras_setfg(sc, ri->ri_devcmap[(attr >> 16) & 0xf]); 722 ffb_ras_fifo_wait(sc, 4); 723 FBC_WRITE(sc, FFB_FBC_BY, ri->ri_yorigin + row); 724 FBC_WRITE(sc, FFB_FBC_BX, ri->ri_xorigin + col); 725 FBC_WRITE(sc, FFB_FBC_BH, ri->ri_font->fontheight); 726 FBC_WRITE(sc, FFB_FBC_BW, n - 1); 727 SYNC; 728 } 729 730 void 731 ffb_ras_fill(struct ffb_softc *sc) 732 { 733 ffb_ras_fifo_wait(sc, 3); 734 FBC_WRITE(sc, FFB_FBC_PPC, 735 FBC_PPC_VCE_DIS | FBC_PPC_TBE_OPAQUE | FBC_PPC_ACE_DIS | 736 FBC_PPC_APE_DIS | FBC_PPC_DCE_DIS | FBC_PPC_CS_CONST | 737 FBC_PPC_ABE_DIS | FBC_PPC_XS_WID); 738 FBC_WRITE(sc, FFB_FBC_ROP, FBC_ROP_NEW); 739 FBC_WRITE(sc, FFB_FBC_DRAWOP, FBC_DRAWOP_RECTANGLE); 740 SYNC; 741 } 742 743 void 744 ffb_ras_invert(struct ffb_softc *sc) 745 { 746 ffb_ras_fifo_wait(sc, 3); 747 FBC_WRITE(sc, FFB_FBC_PPC, 748 FBC_PPC_VCE_DIS | FBC_PPC_TBE_OPAQUE | FBC_PPC_ACE_DIS | 749 FBC_PPC_APE_DIS | FBC_PPC_DCE_DIS | FBC_PPC_CS_CONST | 750 FBC_PPC_ABE_DIS | FBC_PPC_XS_WID); 751 FBC_WRITE(sc, FFB_FBC_ROP, FBC_ROP_INVERT); 752 FBC_WRITE(sc, FFB_FBC_DRAWOP, FBC_DRAWOP_RECTANGLE); 753 SYNC; 754 } 755 756 void 757 ffb_ras_copyrows(void *cookie, int src, int dst, int n) 758 { 759 struct rasops_info *ri = cookie; 760 struct vcons_screen *scr = ri->ri_hw; 761 struct ffb_softc *sc = scr->scr_cookie; 762 763 if (dst == src) 764 return; 765 if (src < 0) { 766 n += src; 767 src = 0; 768 } 769 if ((src + n) > ri->ri_rows) 770 n = ri->ri_rows - src; 771 if (dst < 0) { 772 n += dst; 773 dst = 0; 774 } 775 if ((dst + n) > ri->ri_rows) 776 n = ri->ri_rows - dst; 777 if (n <= 0) 778 return; 779 n *= ri->ri_font->fontheight; 780 src *= ri->ri_font->fontheight; 781 dst *= ri->ri_font->fontheight; 782 783 ffb_ras_fifo_wait(sc, 9); 784 FBC_WRITE(sc, FFB_FBC_PPC, 785 FBC_PPC_VCE_DIS | FBC_PPC_TBE_OPAQUE | FBC_PPC_ACE_DIS | 786 FBC_PPC_APE_DIS | FBC_PPC_DCE_DIS | FBC_PPC_CS_CONST | 787 FBC_PPC_ABE_DIS | FBC_PPC_XS_WID); 788 FBC_WRITE(sc, FFB_FBC_ROP, FBC_ROP_OLD | (FBC_ROP_OLD << 8)); 789 FBC_WRITE(sc, FFB_FBC_DRAWOP, FBC_DRAWOP_VSCROLL); 790 FBC_WRITE(sc, FFB_FBC_BY, ri->ri_yorigin + src); 791 FBC_WRITE(sc, FFB_FBC_BX, ri->ri_xorigin); 792 FBC_WRITE(sc, FFB_FBC_DY, ri->ri_yorigin + dst); 793 FBC_WRITE(sc, FFB_FBC_DX, ri->ri_xorigin); 794 FBC_WRITE(sc, FFB_FBC_BH, n); 795 FBC_WRITE(sc, FFB_FBC_BW, ri->ri_emuwidth); 796 SYNC; 797 } 798 799 static void 800 ffb_ras_setfg(struct ffb_softc *sc, int32_t fg) 801 { 802 ffb_ras_fifo_wait(sc, 1); 803 if (fg == sc->sc_fg_cache) 804 return; 805 sc->sc_fg_cache = fg; 806 FBC_WRITE(sc, FFB_FBC_FG, fg); 807 SYNC; 808 } 809 810 static void 811 ffb_ras_setbg(struct ffb_softc *sc, int32_t bg) 812 { 813 ffb_ras_fifo_wait(sc, 1); 814 if (bg == sc->sc_bg_cache) 815 return; 816 sc->sc_bg_cache = bg; 817 FBC_WRITE(sc, FFB_FBC_BG, bg); 818 SYNC; 819 } 820 821 /* frame buffer generic driver support functions */ 822 static void 823 ffbfb_unblank(device_t dev) 824 { 825 struct ffb_softc *sc = device_private(dev); 826 struct vcons_screen *ms = sc->vd.active; 827 u_int on = 1; 828 int redraw = 0; 829 830 ffb_ras_init(sc); 831 if (sc->sc_locked) { 832 sc->sc_locked = 0; 833 redraw = 1; 834 } 835 836 ffb_blank(sc, WSDISPLAYIO_SVIDEO, &on); 837 #if 0 838 if ((sc->vd.active != &ffb_console_screen) && 839 (ffb_console_screen.scr_flags & VCONS_SCREEN_IS_STATIC)) { 840 /* 841 * force-switch to the console screen. 842 * Caveat: the higher layer will think we're still on the 843 * other screen 844 */ 845 846 SCREEN_INVISIBLE(sc->vd.active); 847 sc->vd.active = &ffb_console_screen; 848 SCREEN_VISIBLE(sc->vd.active); 849 ms = sc->vd.active; 850 redraw = 1; 851 } 852 #endif 853 if (redraw) { 854 vcons_redraw_screen(ms); 855 } 856 } 857 858 int 859 ffbfb_open(dev_t dev, int flags, int mode, struct lwp *l) 860 { 861 struct ffb_softc *sc; 862 863 sc = device_lookup_private(&ffb_cd, minor(dev)); 864 if (sc == NULL) 865 return ENXIO; 866 867 sc->sc_locked = 1; 868 return 0; 869 } 870 871 int 872 ffbfb_close(dev_t dev, int flags, int mode, struct lwp *l) 873 { 874 struct ffb_softc *sc = device_lookup_private(&ffb_cd, minor(dev)); 875 struct vcons_screen *ms = sc->vd.active; 876 877 sc->sc_locked = 0; 878 if (ms != NULL) { 879 if ((sc->sc_mode == WSDISPLAYIO_MODE_EMUL) && 880 (sc->sc_locked == 0)) { 881 ffb_ras_init(sc); 882 vcons_redraw_screen(ms); 883 } 884 } 885 return 0; 886 } 887 888 int 889 ffbfb_ioctl(dev_t dev, u_long cmd, void *data, int flags, struct lwp *l) 890 { 891 struct ffb_softc *sc = device_lookup_private(&ffb_cd, minor(dev)); 892 893 return ffb_ioctl(&sc->vd, NULL, cmd, data, flags, l); 894 } 895 896 paddr_t 897 ffbfb_mmap(dev_t dev, off_t off, int prot) 898 { 899 struct ffb_softc *sc = device_lookup_private(&ffb_cd, minor(dev)); 900 uint64_t size; 901 int i, reg; 902 off_t o; 903 904 /* 905 * off is a magic cookie (see xfree86/drivers/sunffb/ffb.h), 906 * which we map to an index into the "reg" property, and use 907 * our copy of the firmware data as arguments for the real 908 * mapping. 909 */ 910 static struct { unsigned long voff; int reg; } map[] = { 911 { 0x00000000, FFB_REG_SFB8R }, 912 { 0x00400000, FFB_REG_SFB8G }, 913 { 0x00800000, FFB_REG_SFB8B }, 914 { 0x00c00000, FFB_REG_SFB8X }, 915 { 0x01000000, FFB_REG_SFB32 }, 916 { 0x02000000, FFB_REG_SFB64 }, 917 { 0x04000000, FFB_REG_FBC }, 918 { 0x04004000, FFB_REG_DFB8R }, 919 { 0x04404000, FFB_REG_DFB8G }, 920 { 0x04804000, FFB_REG_DFB8B }, 921 { 0x04c04000, FFB_REG_DFB8X }, 922 { 0x05004000, FFB_REG_DFB24 }, 923 { 0x06004000, FFB_REG_DFB32 }, 924 { 0x07004000, FFB_REG_DFB422A }, 925 { 0x0bc06000, FFB_REG_DAC }, 926 { 0x0bc08000, FFB_REG_PROM }, 927 { 0x0bc18000, 0 } 928 }; 929 930 /* special value "FFB_EXP_VOFF" - not backed by any "reg" entry */ 931 if (off == 0x0bc18000) 932 return bus_space_mmap(sc->sc_bt, sc->sc_addrs[FFB_REG_PROM], 933 0x00200000, prot, BUS_SPACE_MAP_LINEAR); 934 935 /* 936 * FFB_VOFF_FBC_KREGS - used by afbinit to upload firmware. We should 937 * probably mmap them only on afb boards 938 */ 939 if ((off >= 0x0bc04000) && (off < 0x0bc06000)) 940 return bus_space_mmap(sc->sc_bt, sc->sc_addrs[FFB_REG_PROM], 941 0x00610000 + (off - 0x0bc04000), prot, 942 BUS_SPACE_MAP_LINEAR); 943 944 #define NELEMS(arr) (sizeof(arr)/sizeof((arr)[0])) 945 946 /* the map is ordered by voff */ 947 for (i = 0; i < NELEMS(map)-1; i++) { 948 reg = map[i].reg; 949 /* the number of entries in reg seems to vary */ 950 if (reg < sc->sc_nreg) { 951 size = min((map[i + 1].voff - map[i].voff), 952 sc->sc_sizes[reg]); 953 if ((off >= map[i].voff) && 954 (off < (map[i].voff + size))) { 955 o = off - map[i].voff; 956 return bus_space_mmap(sc->sc_bt, 957 sc->sc_addrs[reg], o, prot, 958 BUS_SPACE_MAP_LINEAR); 959 } 960 } 961 } 962 963 return -1; 964 } 965 966 void 967 ffb_clearscreen(struct ffb_softc *sc) 968 { 969 struct rasops_info *ri = &ffb_console_screen.scr_ri; 970 ffb_ras_fill(sc); 971 ffb_ras_setfg(sc, ri->ri_devcmap[WS_DEFAULT_BG]); 972 ffb_ras_fifo_wait(sc, 4); 973 FBC_WRITE(sc, FFB_FBC_BY, 0); 974 FBC_WRITE(sc, FFB_FBC_BX, 0); 975 FBC_WRITE(sc, FFB_FBC_BH, sc->sc_height); 976 FBC_WRITE(sc, FFB_FBC_BW, sc->sc_width); 977 } 978 979 void 980 ffb_cursor(void *cookie, int on, int row, int col) 981 { 982 struct rasops_info *ri = cookie; 983 struct vcons_screen *scr; 984 struct ffb_softc *sc; 985 int x, y, wi, he; 986 987 if (cookie != NULL) { 988 scr = ri->ri_hw; 989 sc = scr->scr_cookie; 990 991 wi = ri->ri_font->fontwidth; 992 he = ri->ri_font->fontheight; 993 994 if (sc->sc_mode == WSDISPLAYIO_MODE_EMUL) { 995 996 if (ri->ri_flg & RI_CURSOR) { 997 998 /* remove cursor */ 999 x = ri->ri_ccol * wi + ri->ri_xorigin; 1000 y = ri->ri_crow * he + ri->ri_yorigin; 1001 1002 ffb_ras_invert(sc); 1003 ffb_ras_fifo_wait(sc, 4); 1004 FBC_WRITE(sc, FFB_FBC_BY, y); 1005 FBC_WRITE(sc, FFB_FBC_BX, x); 1006 FBC_WRITE(sc, FFB_FBC_BH, he); 1007 FBC_WRITE(sc, FFB_FBC_BW, wi); 1008 1009 ri->ri_flg &= ~RI_CURSOR; 1010 } 1011 ri->ri_crow = row; 1012 ri->ri_ccol = col; 1013 if (on) 1014 { 1015 x = ri->ri_ccol * wi + ri->ri_xorigin; 1016 y = ri->ri_crow * he + ri->ri_yorigin; 1017 1018 ffb_ras_invert(sc); 1019 ffb_ras_fifo_wait(sc, 4); 1020 FBC_WRITE(sc, FFB_FBC_BY, y); 1021 FBC_WRITE(sc, FFB_FBC_BX, x); 1022 FBC_WRITE(sc, FFB_FBC_BH, he); 1023 FBC_WRITE(sc, FFB_FBC_BW, wi); 1024 1025 ri->ri_flg |= RI_CURSOR; 1026 } 1027 } else { 1028 ri->ri_crow = row; 1029 ri->ri_ccol = col; 1030 ri->ri_flg &= ~RI_CURSOR; 1031 } 1032 } 1033 } 1034 1035 /* mono bitmap font */ 1036 void 1037 ffb_putchar_mono(void *cookie, int row, int col, u_int c, long attr) 1038 { 1039 struct rasops_info *ri = cookie; 1040 struct vcons_screen *scr = ri->ri_hw; 1041 struct wsdisplay_font *font = PICK_FONT(ri, c); 1042 struct ffb_softc *sc = scr->scr_cookie; 1043 void *data; 1044 uint32_t fg, bg; 1045 int i; 1046 int x, y, wi, he; 1047 1048 if (sc->sc_mode != WSDISPLAYIO_MODE_EMUL) 1049 return; 1050 1051 wi = font->fontwidth; 1052 he = font->fontheight; 1053 1054 if (!CHAR_IN_FONT(c, font)) 1055 return; 1056 1057 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 1058 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 1059 x = ri->ri_xorigin + col * wi; 1060 y = ri->ri_yorigin + row * he; 1061 1062 data = WSFONT_GLYPH(c, font); 1063 1064 ffb_ras_setbg(sc, bg); 1065 ffb_ras_setfg(sc, fg); 1066 ffb_ras_fifo_wait(sc, 4); 1067 FBC_WRITE(sc, FFB_FBC_ROP, FBC_ROP_NEW); 1068 FBC_WRITE(sc, FFB_FBC_FONTXY, (y << 16) | x); 1069 FBC_WRITE(sc, FFB_FBC_FONTW, wi); 1070 FBC_WRITE(sc, FFB_FBC_PPC, 1071 FBC_PPC_VCE_DIS | FBC_PPC_TBE_OPAQUE | FBC_PPC_ACE_DIS | 1072 FBC_PPC_APE_DIS | FBC_PPC_DCE_DIS | FBC_PPC_CS_CONST | 1073 FBC_PPC_ABE_DIS | FBC_PPC_XS_WID); 1074 1075 switch (font->stride) { 1076 case 1: { 1077 uint8_t *data8 = data; 1078 uint32_t reg; 1079 for (i = 0; i < he; i++) { 1080 reg = *data8; 1081 FBC_WRITE(sc, FFB_FBC_FONT, reg << 24); 1082 data8++; 1083 } 1084 break; 1085 } 1086 case 2: { 1087 uint16_t *data16 = data; 1088 uint32_t reg; 1089 for (i = 0; i < he; i++) { 1090 reg = *data16; 1091 FBC_WRITE(sc, FFB_FBC_FONT, reg << 16); 1092 data16++; 1093 } 1094 break; 1095 } 1096 } 1097 } 1098 1099 /* alpha font */ 1100 void 1101 ffb_putchar_aa(void *cookie, int row, int col, u_int c, long attr) 1102 { 1103 struct rasops_info *ri = cookie; 1104 struct vcons_screen *scr = ri->ri_hw; 1105 struct wsdisplay_font *font = PICK_FONT(ri, c); 1106 struct ffb_softc *sc = scr->scr_cookie; 1107 volatile uint32_t *dest, *ddest; 1108 uint8_t *data8; 1109 uint32_t fg, bg; 1110 int i; 1111 int x, y, wi, he; 1112 uint32_t alpha = 0x80; 1113 int j; 1114 1115 if (sc->sc_mode != WSDISPLAYIO_MODE_EMUL) 1116 return; 1117 1118 wi = font->fontwidth; 1119 he = font->fontheight; 1120 1121 if (!CHAR_IN_FONT(c, font)) 1122 return; 1123 1124 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 1125 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 1126 x = ri->ri_xorigin + col * wi; 1127 y = ri->ri_yorigin + row * he; 1128 1129 data8 = WSFONT_GLYPH(c, font); 1130 1131 /* first we erase the background */ 1132 ffb_ras_fill(sc); 1133 ffb_ras_setfg(sc, bg); 1134 ffb_ras_fifo_wait(sc, 4); 1135 FBC_WRITE(sc, FFB_FBC_BY, y); 1136 FBC_WRITE(sc, FFB_FBC_BX, x); 1137 FBC_WRITE(sc, FFB_FBC_BH, he); 1138 FBC_WRITE(sc, FFB_FBC_BW, wi); 1139 1140 /* if we draw a space we're done */ 1141 if (c == ' ') return; 1142 1143 /* now enable alpha blending */ 1144 ffb_ras_setfg(sc, fg); 1145 ffb_ras_fifo_wait(sc, 2); 1146 FBC_WRITE(sc, FFB_FBC_ROP, FBC_ROP_NEW); 1147 1148 FBC_WRITE(sc, FFB_FBC_PPC, 1149 FBC_PPC_VCE_DIS | FBC_PPC_TBE_OPAQUE | FBC_PPC_ACE_DIS | 1150 FBC_PPC_APE_DIS | FBC_PPC_DCE_DIS | FBC_PPC_CS_CONST | 1151 FBC_PPC_ABE_ENA | FBC_PPC_XS_VAR); 1152 /* 1153 * we have to wait for both the rectangle drawing op above and the 1154 * FFB_FBC_PPC write to finish before mucking around in the SFB aperture 1155 */ 1156 ffb_ras_wait(sc); 1157 1158 /* ... and draw the character */ 1159 dest = sc->sc_sfb32 + (y << 11) + x; 1160 for (i = 0; i < he; i++) { 1161 ddest = dest; 1162 for (j = 0; j < wi; j++) { 1163 alpha = *data8; 1164 /* 1165 * We set the colour source to constant above so we only 1166 * have to write the alpha channel here and the colour 1167 * comes from the FG register. It would be nice if we 1168 * could just use the SFB8X aperture and memcpy() the 1169 * alpha map line by line but for some strange reason 1170 * that will take colour info from the framebuffer even 1171 * if we set the FBC_PPC_CS_CONST bit above. 1172 */ 1173 *ddest = alpha << 24; 1174 data8++; 1175 ddest++; 1176 } 1177 dest += 2048; 1178 } 1179 } 1180 1181 int 1182 ffb_allocattr(void *cookie, int fg, int bg, int flags, long *attrp) 1183 { 1184 if ((fg == 0) && (bg == 0)) 1185 { 1186 fg = WS_DEFAULT_FG; 1187 bg = WS_DEFAULT_BG; 1188 } 1189 if (flags & WSATTR_REVERSE) { 1190 *attrp = (bg & 0xff) << 24 | (fg & 0xff) << 16 | 1191 (flags & 0xff); 1192 } else 1193 *attrp = (fg & 0xff) << 24 | (bg & 0xff) << 16 | 1194 (flags & 0xff); 1195 return 0; 1196 } 1197 1198 void 1199 ffb_init_screen(void *cookie, struct vcons_screen *scr, 1200 int existing, long *defattr) 1201 { 1202 struct ffb_softc *sc = cookie; 1203 struct rasops_info *ri = &scr->scr_ri; 1204 1205 ri->ri_depth = 32; 1206 ri->ri_width = sc->sc_width; 1207 ri->ri_height = sc->sc_height; 1208 ri->ri_stride = sc->sc_linebytes; 1209 ri->ri_flg = RI_CENTER | RI_ENABLE_ALPHA; 1210 1211 /* 1212 * we can't accelerate copycols() so instead of falling back to 1213 * software use vcons' putchar() based implementation 1214 */ 1215 scr->scr_flags |= VCONS_NO_COPYCOLS; 1216 #ifdef VCONS_DRAW_INTR 1217 scr->scr_flags |= VCONS_DONT_READ; 1218 #endif 1219 DPRINTF(("ffb_init_screen: addr: %08lx\n",(ulong)ri->ri_bits)); 1220 1221 /* explicitly request BGR in case the default changes */ 1222 ri->ri_rnum = 8; 1223 ri->ri_gnum = 8; 1224 ri->ri_bnum = 8; 1225 ri->ri_rpos = 0; 1226 ri->ri_gpos = 8; 1227 ri->ri_bpos = 16; 1228 1229 rasops_init(ri, 0, 0); 1230 ri->ri_caps = WSSCREEN_WSCOLORS; 1231 rasops_reconfig(ri, sc->sc_height / ri->ri_font->fontheight, 1232 sc->sc_width / ri->ri_font->fontwidth); 1233 1234 /* enable acceleration */ 1235 ri->ri_ops.copyrows = ffb_ras_copyrows; 1236 ri->ri_ops.eraserows = ffb_ras_eraserows; 1237 ri->ri_ops.erasecols = ffb_ras_erasecols; 1238 ri->ri_ops.cursor = ffb_cursor; 1239 ri->ri_ops.allocattr = ffb_allocattr; 1240 if (FONT_IS_ALPHA(ri->ri_font)) { 1241 ri->ri_ops.putchar = ffb_putchar_aa; 1242 } else 1243 ri->ri_ops.putchar = ffb_putchar_mono; 1244 } 1245 1246 /* I2C bitbanging */ 1247 static void ffb_i2cbb_set_bits(void *cookie, uint32_t bits) 1248 { 1249 struct ffb_softc *sc = cookie; 1250 1251 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_CFG_MPDATA); 1252 DAC_WRITE(sc, FFB_DAC_VALUE, bits); 1253 } 1254 1255 static void ffb_i2cbb_set_dir(void *cookie, uint32_t dir) 1256 { 1257 /* Nothing to do */ 1258 } 1259 1260 static uint32_t ffb_i2cbb_read(void *cookie) 1261 { 1262 struct ffb_softc *sc = cookie; 1263 uint32_t bits; 1264 1265 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_CFG_MPSENSE); 1266 bits = DAC_READ(sc, FFB_DAC_VALUE); 1267 1268 return bits; 1269 } 1270 1271 /* higher level I2C stuff */ 1272 static int 1273 ffb_i2c_acquire_bus(void *cookie, int flags) 1274 { 1275 /* private bus */ 1276 return (0); 1277 } 1278 1279 static void 1280 ffb_i2c_release_bus(void *cookie, int flags) 1281 { 1282 /* private bus */ 1283 } 1284 1285 static int 1286 ffb_i2c_send_start(void *cookie, int flags) 1287 { 1288 return (i2c_bitbang_send_start(cookie, flags, &ffb_i2cbb_ops)); 1289 } 1290 1291 static int 1292 ffb_i2c_send_stop(void *cookie, int flags) 1293 { 1294 1295 return (i2c_bitbang_send_stop(cookie, flags, &ffb_i2cbb_ops)); 1296 } 1297 1298 static int 1299 ffb_i2c_initiate_xfer(void *cookie, i2c_addr_t addr, int flags) 1300 { 1301 /* 1302 * for some reason i2c_bitbang_initiate_xfer left-shifts 1303 * the I2C-address and then sets the direction bit 1304 */ 1305 return (i2c_bitbang_initiate_xfer(cookie, addr, flags, 1306 &ffb_i2cbb_ops)); 1307 } 1308 1309 static int 1310 ffb_i2c_read_byte(void *cookie, uint8_t *valp, int flags) 1311 { 1312 return (i2c_bitbang_read_byte(cookie, valp, flags, &ffb_i2cbb_ops)); 1313 } 1314 1315 static int 1316 ffb_i2c_write_byte(void *cookie, uint8_t val, int flags) 1317 { 1318 return (i2c_bitbang_write_byte(cookie, val, flags, &ffb_i2cbb_ops)); 1319 } 1320 1321 1322 #define TVC_READ_LIMIT 100000 1323 int 1324 ffb_tgc_disable(struct ffb_softc *sc) 1325 { 1326 int i; 1327 1328 /* Is the timing generator disabled? */ 1329 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_TGC); 1330 if (!(DAC_READ(sc, FFB_DAC_VALUE) & FFB_DAC_TGC_TIMING_ENABLE)) 1331 return 1; 1332 1333 /* If not, disable it when the vertical counter reaches 0 */ 1334 for (i = 0; i < TVC_READ_LIMIT; i++) { 1335 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_TVC); 1336 if (!DAC_READ(sc, FFB_DAC_VALUE)) { 1337 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_TGC); 1338 DAC_WRITE(sc, FFB_DAC_VALUE, 0); 1339 return 1; 1340 } 1341 } 1342 return 0; 1343 } 1344 1345 /* 1346 * PLL Control Register values: 1347 * M)ultiplier = bits 0:6 + 1 1348 * D)ivisor = bits 7:10 + 1 1349 * P)ost divisor = bits 11:13 (000 = 1, 001 = 2, 010 = 4, 011 = 8) 1350 * Frequency = 13.5 * M / D / P 1351 */ 1352 #define FFB_PLL_FREQ 13500000 1353 void 1354 ffb_get_pclk(int request, uint32_t *pll, int *diff) 1355 { 1356 int m, d, p, f, hex = 0, curdiff; 1357 1358 *diff = 100000000; 1359 1360 for (m = 32; m <= 80; m++) { 1361 for (d = 4; d <= 11; d++) { 1362 for (p = 1; p <= 8; p = p << 1) { 1363 switch (p) { 1364 case 1: 1365 hex = 0x4000 + (d << 7) + m; 1366 break; 1367 case 2: 1368 hex = 0x4800 + (d << 7) + m; 1369 break; 1370 case 4: 1371 hex = 0x5000 + (d << 7) + m; 1372 break; 1373 case 8: 1374 hex = 0x6000 + (d << 7) + m; 1375 break; 1376 } 1377 f = 13500000 * m / d / p; 1378 if (f == request) { 1379 *diff = 0; 1380 *pll = hex; 1381 return; 1382 } else { 1383 curdiff = abs(request - f); 1384 if (curdiff < *diff) { 1385 *diff = curdiff; 1386 *pll = hex; 1387 } 1388 } 1389 } 1390 } 1391 } 1392 } 1393 1394 /* 1395 * Details of the FFB RAMDAC are contained in the Brooktree BT497/498 1396 * and in the Connexant BT497A/498A documentation. 1397 * 1398 * VESA timings to FFB register conversion: 1399 * If interleave = 4/2:1 then x = 2, if interleave = 8/2:1 then x = 4 1400 * VBE = VBS - vres = (sync pulse - 1) + back porch 1401 * VBS = VSS - front porch = (sync pulse - 1) + back porch + vres 1402 * VSE = sync pulse - 1 1403 * VSS = (sync pulse - 1) + back porch + vres + front porch 1404 * HRE = HSS - HSE - 1 1405 * HBE = (sync pulse + back porch) / x - 1 1406 * HBS = (sync pulse + back porch + hres) / x - 1 1407 * HSE = sync pulse / x - 1 1408 * HSS = (sync pulse + back porch + hres + front porch) / x - 1 1409 * HCE = HBS - 4 1410 * HCS = HBE - 4 1411 * EPE = EIE = EIS = 0 (for all non-interlaced modes) 1412 * 1413 * Note, that 8/2:1 Single Buffered Interleaving is only supported by the 1414 * double-buffered FFB (Creator3D), and at higher resolutions than 1280x1024 1415 * 1416 * Note, that the timing generator should be disabled and re-enabled when the 1417 * the timing parameter registers are being programmed. Stopping the timing 1418 * generator should only be done when the vertical counter is zero. 1419 */ 1420 #define DIVIDE(x,y) (((x) + ((y) / 2)) / (y)) 1421 int 1422 ffb_set_vmode(struct ffb_softc *sc, struct videomode *mode, int btype, 1423 int *hres, int *vres) 1424 { 1425 int diff; 1426 uint32_t fp, sp, bp, x; 1427 uint32_t pll, pfc, ucl, dcl, tgc; 1428 uint32_t vbe, vbs, vse, vss, hre, hbe, hbs, hse, hss, hce, hcs; 1429 uint32_t epe, eie, eis; 1430 uint32_t fbcfg0; 1431 1432 DPRINTF(("ffb_set_vmode: %dx%d@%d", mode->hdisplay, mode->vdisplay, 1433 DIVIDE(DIVIDE(mode->dot_clock * 1000, 1434 mode->htotal), mode->vtotal))); 1435 DPRINTF((" (%d %d %d %d %d %d %d", 1436 mode->dot_clock, mode->hsync_start, mode->hsync_end, mode->htotal, 1437 mode->vsync_start, mode->vsync_end, mode->vtotal)); 1438 DPRINTF((" %s%sH %s%sV)\n", 1439 mode->flags & VID_PHSYNC ? "+" : "", 1440 mode->flags & VID_NHSYNC ? "-" : "", 1441 mode->flags & VID_PVSYNC ? "+" : "", 1442 mode->flags & VID_NVSYNC ? "-" : "")); 1443 1444 /* We don't handle interlaced or doublescan (yet) */ 1445 if ((mode->flags & VID_INTERLACE) || (mode->flags & VID_DBLSCAN)) 1446 return 0; 1447 1448 /* Only Creator3D can be set to > 1280x1024 */ 1449 if(((sc->sc_type == FFB_CREATOR && !((btype & 7) == 3)) || 1450 sc->sc_type == FFB_AFB) 1451 && (mode->hdisplay > 1280 || mode->vdisplay > 1024)) 1452 return 0; 1453 /* Creator3D can be set to <= 1920x1360 */ 1454 if (mode->hdisplay > 1920 || mode->vdisplay > 1360) 1455 return 0; 1456 1457 /* 1458 * Look for a matching pixel clock and set PLL Control. 1459 * XXX: 640x480@60 is 25175000 in modelines but 25125000 in the 1460 * FFB PROM, and the closest match to 25175000 (0x4da9/25159090) 1461 * does not work. So, use the PROM value instead. 1462 */ 1463 if (mode->hdisplay == 640 && mode->vdisplay == 480 && 1464 mode->dot_clock == 25175) { 1465 DPRINTF(("ffb_set_vmode: 640x480@60: adjusted dot clock\n")); 1466 mode->dot_clock = 25125; 1467 } 1468 ffb_get_pclk(mode->dot_clock * 1000, &pll, &diff); 1469 if (diff > 250000) 1470 return 0; 1471 1472 /* Pixel Format Control, User Control and FBC Configuration. */ 1473 if (mode->hdisplay > 1280) { 1474 pfc = FFB_DAC_PIX_FMT_821; 1475 ucl = FFB_DAC_USR_CTRL_OVERLAY | FFB_DAC_USR_CTRL_WMODE_C; 1476 x = 4; 1477 fbcfg0 = FBC_READ(sc, FFB_FBC_FBCFG0) | FBC_CFG0_DOUBLE_BUF; 1478 } else { 1479 pfc = FFB_DAC_PIX_FMT_421; 1480 /* Only Creator3D and Elite3D can have double-buffer */ 1481 if ((sc->sc_type == FFB_CREATOR && !((btype & 7) == 3))) 1482 ucl = 0; 1483 else 1484 ucl = FFB_DAC_USR_CTRL_DOUBLE; 1485 ucl |= (FFB_DAC_USR_CTRL_OVERLAY | FFB_DAC_USR_CTRL_WMODE_S8); 1486 x = 2; 1487 fbcfg0 = FBC_READ(sc, FFB_FBC_FBCFG0) | FBC_CFG0_SINGLE_BUF; 1488 } 1489 1490 /* DAC Control and Timing Generator Control */ 1491 if (mode->flags & VID_PVSYNC) 1492 dcl = FFB_DAC_DAC_CTRL_POS_VSYNC; 1493 else 1494 dcl = 0; 1495 tgc = 0; 1496 #define EDID_VID_INP sc->sc_edid_info.edid_video_input 1497 if ((EDID_VID_INP & EDID_VIDEO_INPUT_COMPOSITE_SYNC)) { 1498 dcl |= FFB_DAC_DAC_CTRL_VSYNC_DIS; 1499 tgc = FFB_DAC_TGC_EQUAL_DISABLE; 1500 } else { 1501 dcl |= FFB_DAC_DAC_CTRL_SYNC_G; 1502 if (EDID_VID_INP & EDID_VIDEO_INPUT_SEPARATE_SYNCS) 1503 tgc |= FFB_DAC_TGC_VSYNC_DISABLE; 1504 else 1505 tgc = FFB_DAC_TGC_EQUAL_DISABLE; 1506 } 1507 if (EDID_VID_INP & EDID_VIDEO_INPUT_BLANK_TO_BLACK) 1508 dcl |= FFB_DAC_DAC_CTRL_PED_ENABLE; 1509 tgc |= (FFB_DAC_TGC_VIDEO_ENABLE | FFB_DAC_TGC_TIMING_ENABLE | 1510 FFB_DAC_TGC_MASTER_ENABLE); 1511 1512 /* Vertical timing */ 1513 fp = mode->vsync_start - mode->vdisplay; 1514 sp = mode->vsync_end - mode->vsync_start; 1515 bp = mode->vtotal - mode->vsync_end; 1516 1517 vbe = sp - 1 + bp; 1518 vbs = sp - 1 + bp + mode->vdisplay; 1519 vse = sp - 1; 1520 vss = sp - 1 + bp + mode->vdisplay + fp; 1521 1522 /* Horizontal timing */ 1523 fp = mode->hsync_start - mode->hdisplay; 1524 sp = mode->hsync_end - mode->hsync_start; 1525 bp = mode->htotal - mode->hsync_end; 1526 1527 hbe = (sp + bp) / x - 1; 1528 hbs = (sp + bp + mode->hdisplay) / x - 1; 1529 hse = sp / x - 1; 1530 hss = (sp + bp + mode->hdisplay + fp) / x -1; 1531 hre = hss - hse - 1; 1532 hce = hbs - 4; 1533 hcs = hbe - 4; 1534 1535 /* Equalisation (interlaced modes) */ 1536 epe = 0; 1537 eie = 0; 1538 eis = 0; 1539 1540 DPRINTF(("ffb_set_vmode: 0x%04x 0x%04x 0x%04x 0x%04x 0x%04x\n", 1541 pll, pfc, ucl, dcl, tgc)); 1542 DPRINTF(("\t0x%04x 0x%04x 0x%04x 0x%04x\n", vbe, vbs, vse, vss)); 1543 DPRINTF(("\t0x%04x 0x%04x 0x%04x 0x%04x 0x%04x 0x%04x 0x%04x\n", 1544 hre, hbe, hbs, hse, hss, hce, hcs)); 1545 DPRINTF(("\t0x%04x 0x%04x 0x%04x\n", epe, eie, eis)); 1546 1547 if (!ffb_tgc_disable(sc)) { 1548 DPRINTF(("ffb_set_vmode: failed to disable TGC register\n")); 1549 return 0; 1550 } 1551 1552 /* 1553 * Program the mode registers. 1554 * Program the timing generator last, as that re-enables output. 1555 * Note, that a read to/write from a register increments the 1556 * register address to the next register automatically. 1557 */ 1558 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_PLL_CTRL); 1559 DAC_WRITE(sc, FFB_DAC_VALUE, pll); 1560 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_PIX_FMT); 1561 DAC_WRITE(sc, FFB_DAC_VALUE, pfc); 1562 DAC_WRITE(sc, FFB_DAC_VALUE, ucl); 1563 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_DAC_CTRL); 1564 DAC_WRITE(sc, FFB_DAC_VALUE, dcl); 1565 1566 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_VBE); 1567 DAC_WRITE(sc, FFB_DAC_VALUE, vbe); 1568 DAC_WRITE(sc, FFB_DAC_VALUE, vbs); 1569 DAC_WRITE(sc, FFB_DAC_VALUE, vse); 1570 DAC_WRITE(sc, FFB_DAC_VALUE, vss); 1571 1572 DAC_WRITE(sc, FFB_DAC_VALUE, hre); 1573 DAC_WRITE(sc, FFB_DAC_VALUE, hbe); 1574 DAC_WRITE(sc, FFB_DAC_VALUE, hbs); 1575 DAC_WRITE(sc, FFB_DAC_VALUE, hse); 1576 DAC_WRITE(sc, FFB_DAC_VALUE, hss); 1577 DAC_WRITE(sc, FFB_DAC_VALUE, hce); 1578 DAC_WRITE(sc, FFB_DAC_VALUE, hcs); 1579 1580 DAC_WRITE(sc, FFB_DAC_VALUE, epe); 1581 DAC_WRITE(sc, FFB_DAC_VALUE, eie); 1582 DAC_WRITE(sc, FFB_DAC_VALUE, eis); 1583 1584 FBC_WRITE(sc, FFB_FBC_FBCFG0, fbcfg0); 1585 1586 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_TGC); 1587 DAC_WRITE(sc, FFB_DAC_VALUE, tgc); 1588 DPRINTF(("new tgc: %08x\n", tgc)); 1589 1590 *hres = mode->hdisplay; 1591 *vres = mode->vdisplay; 1592 1593 printf("%s: video mode set to %d x %d @ %dHz\n", 1594 device_xname(sc->sc_dev), 1595 mode->hdisplay, mode->vdisplay, 1596 DIVIDE(DIVIDE(mode->dot_clock * 1000, 1597 mode->htotal), mode->vtotal)); 1598 1599 return 1; 1600 } 1601
Indexes created Mon Sep 29 15:09:53 GMT 2025