ffb.c revision 1.54
1 /* $NetBSD: ffb.c,v 1.54 2013/09/12 19:57:43 martin Exp $ */ 2 /* $OpenBSD: creator.c,v 1.20 2002/07/30 19:48:15 jason Exp $ */ 3 4 /* 5 * Copyright (c) 2002 Jason L. Wright (jason (at) thought.net) 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Jason L. Wright 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 25 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 26 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 27 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 30 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 31 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32 * POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: ffb.c,v 1.54 2013/09/12 19:57:43 martin Exp $"); 37 38 #include <sys/types.h> 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/kernel.h> 42 #include <sys/device.h> 43 #include <sys/conf.h> 44 #include <sys/ioctl.h> 45 #include <sys/malloc.h> 46 #include <sys/mman.h> 47 48 #include <sys/bus.h> 49 #include <machine/autoconf.h> 50 #include <machine/openfirm.h> 51 #include <machine/vmparam.h> 52 53 #include <dev/wscons/wsconsio.h> 54 #include <dev/sun/fbio.h> 55 #include <dev/sun/fbvar.h> 56 57 #include <dev/wsfont/wsfont.h> 58 #include <dev/wscons/wsdisplay_vconsvar.h> 59 60 #include <prop/proplib.h> 61 62 #include <dev/i2c/i2cvar.h> 63 #include <dev/i2c/i2c_bitbang.h> 64 #include <dev/i2c/ddcvar.h> 65 66 #include <sparc64/dev/ffbreg.h> 67 #include <sparc64/dev/ffbvar.h> 68 69 #include "opt_wsdisplay_compat.h" 70 #include "opt_ffb.h" 71 72 #ifndef WS_DEFAULT_BG 73 /* Sun -> background should be white */ 74 #define WS_DEFAULT_BG 0xf 75 #endif 76 77 #ifdef FFB_SYNC 78 #define SYNC ffb_ras_wait(sc) 79 #else 80 #define SYNC 81 #endif 82 83 /* Debugging */ 84 #if !defined FFB_DEBUG 85 #define FFB_DEBUG 0 86 #endif 87 #define DPRINTF(x) if (ffb_debug) printf x 88 /* Patchable */ 89 extern int ffb_debug; 90 #if FFB_DEBUG > 0 91 int ffb_debug = 1; 92 #else 93 int ffb_debug = 0; 94 #endif 95 96 extern struct cfdriver ffb_cd; 97 98 struct wsscreen_descr ffb_stdscreen = { 99 "sunffb", 100 0, 0, /* will be filled in -- XXX shouldn't, it's global. */ 101 0, 102 0, 0, 103 WSSCREEN_REVERSE | WSSCREEN_WSCOLORS, 104 NULL /* modecookie */ 105 }; 106 107 const struct wsscreen_descr *ffb_scrlist[] = { 108 &ffb_stdscreen, 109 /* XXX other formats? */ 110 }; 111 112 struct wsscreen_list ffb_screenlist = { 113 sizeof(ffb_scrlist) / sizeof(struct wsscreen_descr *), 114 ffb_scrlist 115 }; 116 117 static struct vcons_screen ffb_console_screen; 118 119 int ffb_ioctl(void *, void *, u_long, void *, int, struct lwp *); 120 static int ffb_blank(struct ffb_softc *, u_long, u_int *); 121 paddr_t ffb_mmap(void *, void *, off_t, int); 122 void ffb_ras_fifo_wait(struct ffb_softc *, int); 123 void ffb_ras_wait(struct ffb_softc *); 124 void ffb_ras_init(struct ffb_softc *); 125 void ffb_ras_copyrows(void *, int, int, int); 126 void ffb_ras_erasecols(void *, int, int, int, long int); 127 void ffb_ras_eraserows(void *, int, int, long int); 128 void ffb_ras_do_cursor(struct rasops_info *); 129 void ffb_ras_fill(struct ffb_softc *); 130 void ffb_ras_invert(struct ffb_softc *); 131 static void ffb_ras_setfg(struct ffb_softc *, int32_t); 132 static void ffb_ras_setbg(struct ffb_softc *, int32_t); 133 134 void ffb_clearscreen(struct ffb_softc *); 135 int ffb_load_font(void *, void *, struct wsdisplay_font *); 136 void ffb_init_screen(void *, struct vcons_screen *, int, 137 long *); 138 int ffb_allocattr(void *, int, int, int, long *); 139 void ffb_putchar_mono(void *, int, int, u_int, long); 140 void ffb_putchar_aa(void *, int, int, u_int, long); 141 void ffb_cursor(void *, int, int, int); 142 143 /* frame buffer generic driver */ 144 static void ffbfb_unblank(device_t); 145 dev_type_open(ffbfb_open); 146 dev_type_close(ffbfb_close); 147 dev_type_ioctl(ffbfb_ioctl); 148 dev_type_mmap(ffbfb_mmap); 149 150 static struct fbdriver ffb_fbdriver = { 151 ffbfb_unblank, ffbfb_open, ffbfb_close, ffbfb_ioctl, nopoll, 152 ffbfb_mmap, nokqfilter 153 }; 154 155 struct wsdisplay_accessops ffb_accessops = { 156 .ioctl = ffb_ioctl, 157 .mmap = ffb_mmap, 158 }; 159 160 /* I2C glue */ 161 static int ffb_i2c_acquire_bus(void *, int); 162 static void ffb_i2c_release_bus(void *, int); 163 static int ffb_i2c_send_start(void *, int); 164 static int ffb_i2c_send_stop(void *, int); 165 static int ffb_i2c_initiate_xfer(void *, i2c_addr_t, int); 166 static int ffb_i2c_read_byte(void *, uint8_t *, int); 167 static int ffb_i2c_write_byte(void *, uint8_t, int); 168 169 /* I2C bitbang glue */ 170 static void ffb_i2cbb_set_bits(void *, uint32_t); 171 static void ffb_i2cbb_set_dir(void *, uint32_t); 172 static uint32_t ffb_i2cbb_read(void *); 173 174 static const struct i2c_bitbang_ops ffb_i2cbb_ops = { 175 ffb_i2cbb_set_bits, 176 ffb_i2cbb_set_dir, 177 ffb_i2cbb_read, 178 { 179 FFB_DAC_CFG_MPDATA_SDA, 180 FFB_DAC_CFG_MPDATA_SCL, 181 0, 182 0 183 } 184 }; 185 186 void ffb_attach_i2c(struct ffb_softc *); 187 188 /* Video mode setting */ 189 int ffb_tgc_disable(struct ffb_softc *); 190 void ffb_get_pclk(int, uint32_t *, int *); 191 int ffb_set_vmode(struct ffb_softc *, struct videomode *, int, int *, int *); 192 193 194 void 195 ffb_attach(device_t self) 196 { 197 struct ffb_softc *sc = device_private(self); 198 struct wsemuldisplaydev_attach_args waa; 199 struct rasops_info *ri; 200 long defattr; 201 const char *model, *out_dev; 202 int btype; 203 uint32_t dac; 204 int maxrow; 205 u_int blank = WSDISPLAYIO_VIDEO_ON; 206 char buf[6+1]; 207 int i, try_edid; 208 prop_data_t data; 209 210 printf(":"); 211 212 if (sc->sc_type == FFB_CREATOR) { 213 btype = prom_getpropint(sc->sc_node, "board_type", 0); 214 if ((btype & 7) == 3) 215 printf(" Creator3D"); 216 else 217 printf(" Creator"); 218 } else { 219 printf(" Elite3D"); 220 btype = 0; 221 } 222 223 model = prom_getpropstring(sc->sc_node, "model"); 224 if (model == NULL || strlen(model) == 0) 225 model = "unknown"; 226 227 sc->sc_depth = 24; 228 sc->sc_linebytes = 8192; 229 /* We might alter these during EDID mode setting */ 230 sc->sc_height = prom_getpropint(sc->sc_node, "height", 0); 231 sc->sc_width = prom_getpropint(sc->sc_node, "width", 0); 232 233 sc->sc_locked = 0; 234 sc->sc_mode = WSDISPLAYIO_MODE_EMUL; 235 236 maxrow = (prom_getoption("screen-#rows", buf, sizeof buf) != 0) 237 ? strtoul(buf, NULL, 10) 238 : 34; 239 240 /* collect DAC version, as Elite3D cursor enable bit is reversed */ 241 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_DEVID); 242 dac = DAC_READ(sc, FFB_DAC_VALUE); 243 sc->sc_dacrev = (dac >> 28) & 0xf; 244 245 if (sc->sc_type == FFB_AFB) { 246 sc->sc_dacrev = 10; 247 sc->sc_needredraw = 0; 248 } else { 249 /* see what kind of DAC we have */ 250 int pnum = (dac & 0x0ffff000) >> 12; 251 if (pnum == 0x236e) { 252 sc->sc_needredraw = 0; 253 } else { 254 sc->sc_needredraw = 1; 255 } 256 } 257 printf(", model %s, dac %u\n", model, sc->sc_dacrev); 258 if (sc->sc_needredraw) 259 printf("%s: found old DAC, enabling redraw on unblank\n", 260 device_xname(sc->sc_dev)); 261 262 /* Check if a console resolution "<device>:r<res>" is set. */ 263 if (sc->sc_console) { 264 out_dev = prom_getpropstring(sc->sc_node, "output_device"); 265 if (out_dev != NULL && strlen(out_dev) != 0 && 266 strstr(out_dev, ":r") != NULL) 267 try_edid = 0; 268 else 269 try_edid = 1; 270 } else 271 try_edid = 1; 272 273 #if FFB_DEBUG > 0 274 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_TGC); 275 printf("tgc: %08x\n", DAC_READ(sc, FFB_DAC_VALUE)); 276 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_DAC_CTRL); 277 printf("dcl: %08x\n", DAC_READ(sc, FFB_DAC_VALUE)); 278 #endif 279 ffb_attach_i2c(sc); 280 281 /* Need to set asynchronous blank during DDC write/read */ 282 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_USR_CTRL); 283 dac = DAC_READ(sc, FFB_DAC_VALUE); 284 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_USR_CTRL); 285 DAC_WRITE(sc, FFB_DAC_VALUE, dac | FFB_DAC_USR_CTRL_BLANK); 286 287 /* Some monitors don't respond first time */ 288 i = 0; 289 while (sc->sc_edid_data[1] == 0 && i++ < 3) 290 ddc_read_edid(&sc->sc_i2c, sc->sc_edid_data, EDID_DATA_LEN); 291 292 /* Remove asynchronous blank */ 293 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_USR_CTRL); 294 DAC_WRITE(sc, FFB_DAC_VALUE, dac); 295 296 if (edid_parse(&sc->sc_edid_data[0], &sc->sc_edid_info) != -1) { 297 sort_modes(sc->sc_edid_info.edid_modes, 298 &sc->sc_edid_info.edid_preferred_mode, 299 sc->sc_edid_info.edid_nmodes); 300 DPRINTF(("%s: EDID data:\n ", device_xname(sc->sc_dev))); 301 for (i = 0; i < EDID_DATA_LEN; i++) { 302 if (i && !(i % 32)) 303 DPRINTF(("\n ")); 304 if (i && !(i % 4)) 305 DPRINTF((" ")); 306 DPRINTF(("%02x", sc->sc_edid_data[i])); 307 } 308 DPRINTF(("\n")); 309 if (ffb_debug) 310 edid_print(&sc->sc_edid_info); 311 312 data = prop_data_create_data(sc->sc_edid_data, EDID_DATA_LEN); 313 prop_dictionary_set(device_properties(self), "EDID", data); 314 prop_object_release(data); 315 316 if (try_edid) 317 for (i = 0; i < sc->sc_edid_info.edid_nmodes; i++) { 318 if (ffb_set_vmode(sc, 319 &(sc->sc_edid_info.edid_modes[i]), btype, 320 &(sc->sc_width), &(sc->sc_height))) 321 break; 322 } 323 } else { 324 DPRINTF(("%s: No EDID data.\n", device_xname(sc->sc_dev))); 325 } 326 327 ffb_ras_init(sc); 328 329 ffb_blank(sc, WSDISPLAYIO_SVIDEO, &blank); 330 331 sc->sc_accel = ((device_cfdata(sc->sc_dev)->cf_flags & 332 FFB_CFFLAG_NOACCEL) == 0); 333 334 wsfont_init(); 335 336 vcons_init(&sc->vd, sc, &ffb_stdscreen, &ffb_accessops); 337 sc->vd.init_screen = ffb_init_screen; 338 ri = &ffb_console_screen.scr_ri; 339 340 /* we mess with ffb_console_screen only once */ 341 if (sc->sc_console) { 342 vcons_init_screen(&sc->vd, &ffb_console_screen, 1, &defattr); 343 SCREEN_VISIBLE((&ffb_console_screen)); 344 /* 345 * XXX we shouldn't use a global variable for the console 346 * screen 347 */ 348 sc->vd.active = &ffb_console_screen; 349 ffb_console_screen.scr_flags = VCONS_SCREEN_IS_STATIC; 350 } else { 351 if (ffb_console_screen.scr_ri.ri_rows == 0) { 352 /* do some minimal setup to avoid weirdnesses later */ 353 vcons_init_screen(&sc->vd, &ffb_console_screen, 1, &defattr); 354 } else 355 (*ri->ri_ops.allocattr)(ri, 0, 0, 0, &defattr); 356 } 357 358 ffb_stdscreen.nrows = ri->ri_rows; 359 ffb_stdscreen.ncols = ri->ri_cols; 360 ffb_stdscreen.textops = &ri->ri_ops; 361 ffb_stdscreen.capabilities = ri->ri_caps; 362 363 sc->sc_fb.fb_driver = &ffb_fbdriver; 364 sc->sc_fb.fb_type.fb_cmsize = 0; 365 sc->sc_fb.fb_type.fb_size = maxrow * sc->sc_linebytes; 366 sc->sc_fb.fb_type.fb_type = FBTYPE_CREATOR; 367 sc->sc_fb.fb_type.fb_width = sc->sc_width; 368 sc->sc_fb.fb_type.fb_depth = sc->sc_depth; 369 sc->sc_fb.fb_type.fb_height = sc->sc_height; 370 sc->sc_fb.fb_device = sc->sc_dev; 371 fb_attach(&sc->sc_fb, sc->sc_console); 372 373 ffb_clearscreen(sc); 374 375 if (sc->sc_console) { 376 wsdisplay_cnattach(&ffb_stdscreen, ri, 0, 0, defattr); 377 vcons_replay_msgbuf(&ffb_console_screen); 378 } 379 380 waa.console = sc->sc_console; 381 waa.scrdata = &ffb_screenlist; 382 waa.accessops = &ffb_accessops; 383 waa.accesscookie = &sc->vd; 384 config_found(sc->sc_dev, &waa, wsemuldisplaydevprint); 385 } 386 387 void 388 ffb_attach_i2c(struct ffb_softc *sc) 389 { 390 391 /* Fill in the i2c tag */ 392 sc->sc_i2c.ic_cookie = sc; 393 sc->sc_i2c.ic_acquire_bus = ffb_i2c_acquire_bus; 394 sc->sc_i2c.ic_release_bus = ffb_i2c_release_bus; 395 sc->sc_i2c.ic_send_start = ffb_i2c_send_start; 396 sc->sc_i2c.ic_send_stop = ffb_i2c_send_stop; 397 sc->sc_i2c.ic_initiate_xfer = ffb_i2c_initiate_xfer; 398 sc->sc_i2c.ic_read_byte = ffb_i2c_read_byte; 399 sc->sc_i2c.ic_write_byte = ffb_i2c_write_byte; 400 sc->sc_i2c.ic_exec = NULL; 401 } 402 403 int 404 ffb_ioctl(void *v, void *vs, u_long cmd, void *data, int flags, struct lwp *l) 405 { 406 struct vcons_data *vd = v; 407 struct ffb_softc *sc = vd->cookie; 408 struct wsdisplay_fbinfo *wdf; 409 struct vcons_screen *ms = vd->active; 410 411 DPRINTF(("ffb_ioctl: %s cmd _IO%s%s('%c', %lu)\n", 412 device_xname(sc->sc_dev), 413 (cmd & IOC_IN) ? "W" : "", (cmd & IOC_OUT) ? "R" : "", 414 (char)IOCGROUP(cmd), cmd & 0xff)); 415 416 switch (cmd) { 417 case FBIOGTYPE: 418 *(struct fbtype *)data = sc->sc_fb.fb_type; 419 break; 420 case FBIOGATTR: 421 #define fba ((struct fbgattr *)data) 422 fba->real_type = sc->sc_fb.fb_type.fb_type; 423 fba->owner = 0; /* XXX ??? */ 424 fba->fbtype = sc->sc_fb.fb_type; 425 fba->sattr.flags = 0; 426 fba->sattr.emu_type = sc->sc_fb.fb_type.fb_type; 427 fba->sattr.dev_specific[0] = -1; 428 fba->emu_types[0] = sc->sc_fb.fb_type.fb_type; 429 fba->emu_types[1] = -1; 430 #undef fba 431 break; 432 433 case FBIOGETCMAP: 434 case FBIOPUTCMAP: 435 return EIO; 436 437 case FBIOGVIDEO: 438 case FBIOSVIDEO: 439 return ffb_blank(sc, cmd == FBIOGVIDEO? 440 WSDISPLAYIO_GVIDEO : WSDISPLAYIO_SVIDEO, 441 (u_int *)data); 442 break; 443 case FBIOGCURSOR: 444 case FBIOSCURSOR: 445 /* the console driver is not using the hardware cursor */ 446 break; 447 case FBIOGCURPOS: 448 printf("%s: FBIOGCURPOS not implemented\n", 449 device_xname(sc->sc_dev)); 450 return EIO; 451 case FBIOSCURPOS: 452 printf("%s: FBIOSCURPOS not implemented\n", 453 device_xname(sc->sc_dev)); 454 return EIO; 455 case FBIOGCURMAX: 456 printf("%s: FBIOGCURMAX not implemented\n", 457 device_xname(sc->sc_dev)); 458 return EIO; 459 460 case WSDISPLAYIO_GTYPE: 461 *(u_int *)data = WSDISPLAY_TYPE_SUNFFB; 462 break; 463 case WSDISPLAYIO_SMODE: 464 { 465 if (sc->sc_mode != *(u_int *)data) { 466 sc->sc_mode = *(u_int *)data; 467 if ((sc->sc_mode == WSDISPLAYIO_MODE_EMUL) && 468 (sc->sc_locked == 0)) { 469 ffb_ras_init(sc); 470 vcons_redraw_screen(ms); 471 } 472 } 473 } 474 break; 475 case WSDISPLAYIO_GINFO: 476 wdf = (void *)data; 477 wdf->height = sc->sc_height; 478 wdf->width = sc->sc_width; 479 wdf->depth = 32; 480 wdf->cmsize = 256; /* XXX */ 481 break; 482 #ifdef WSDISPLAYIO_LINEBYTES 483 case WSDISPLAYIO_LINEBYTES: 484 *(u_int *)data = sc->sc_linebytes; 485 break; 486 #endif 487 case WSDISPLAYIO_GETCMAP: 488 break;/* XXX */ 489 490 case WSDISPLAYIO_PUTCMAP: 491 break;/* XXX */ 492 493 case WSDISPLAYIO_SVIDEO: 494 case WSDISPLAYIO_GVIDEO: 495 return(ffb_blank(sc, cmd, (u_int *)data)); 496 break; 497 case WSDISPLAYIO_GCURPOS: 498 case WSDISPLAYIO_SCURPOS: 499 case WSDISPLAYIO_GCURMAX: 500 case WSDISPLAYIO_GCURSOR: 501 case WSDISPLAYIO_SCURSOR: 502 return EIO; /* not supported yet */ 503 break; 504 case WSDISPLAYIO_GET_EDID: { 505 struct wsdisplayio_edid_info *d = data; 506 return wsdisplayio_get_edid(sc->sc_dev, d); 507 } 508 default: 509 return EPASSTHROUGH; 510 } 511 512 return (0); 513 } 514 515 /* blank/unblank the screen */ 516 static int 517 ffb_blank(struct ffb_softc *sc, u_long cmd, u_int *data) 518 { 519 struct vcons_screen *ms = sc->vd.active; 520 u_int val; 521 522 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_TGC); 523 val = DAC_READ(sc, FFB_DAC_VALUE); 524 525 switch (cmd) { 526 case WSDISPLAYIO_GVIDEO: 527 *data = val & 1; 528 return(0); 529 break; 530 case WSDISPLAYIO_SVIDEO: 531 if (*data == WSDISPLAYIO_VIDEO_OFF) 532 val &= ~1; 533 else if (*data == WSDISPLAYIO_VIDEO_ON) 534 val |= 1; 535 else 536 return(EINVAL); 537 break; 538 default: 539 return(EINVAL); 540 } 541 542 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_TGC); 543 DAC_WRITE(sc, FFB_DAC_VALUE, val); 544 545 if ((val & 1) && sc->sc_needredraw) { 546 if (ms != NULL) { 547 if ((sc->sc_mode == WSDISPLAYIO_MODE_EMUL) && 548 (sc->sc_locked == 0)) { 549 ffb_ras_init(sc); 550 vcons_redraw_screen(ms); 551 } 552 } 553 } 554 555 return(0); 556 } 557 558 paddr_t 559 ffb_mmap(void *vsc, void *vs, off_t off, int prot) 560 { 561 struct vcons_data *vd = vsc; 562 struct ffb_softc *sc = vd->cookie; 563 int i; 564 565 switch (sc->sc_mode) { 566 case WSDISPLAYIO_MODE_MAPPED: 567 for (i = 0; i < sc->sc_nreg; i++) { 568 /* Before this set? */ 569 if (off < sc->sc_addrs[i]) 570 continue; 571 /* After this set? */ 572 if (off >= (sc->sc_addrs[i] + sc->sc_sizes[i])) 573 continue; 574 575 return (bus_space_mmap(sc->sc_bt, sc->sc_addrs[i], 576 off - sc->sc_addrs[i], prot, BUS_SPACE_MAP_LINEAR)); 577 } 578 break; 579 #ifdef WSDISPLAYIO_MODE_DUMBFB 580 case WSDISPLAYIO_MODE_DUMBFB: 581 if (sc->sc_nreg < FFB_REG_DFB24) 582 break; 583 if (off >= 0 && off < sc->sc_sizes[FFB_REG_DFB24]) 584 return (bus_space_mmap(sc->sc_bt, 585 sc->sc_addrs[FFB_REG_DFB24], off, prot, 586 BUS_SPACE_MAP_LINEAR)); 587 break; 588 #endif 589 } 590 return (-1); 591 } 592 593 void 594 ffb_ras_fifo_wait(struct ffb_softc *sc, int n) 595 { 596 int32_t cache = sc->sc_fifo_cache; 597 598 if (cache < n) { 599 do { 600 cache = FBC_READ(sc, FFB_FBC_UCSR); 601 cache = (cache & FBC_UCSR_FIFO_MASK) - 8; 602 } while (cache < n); 603 } 604 sc->sc_fifo_cache = cache - n; 605 } 606 607 void 608 ffb_ras_wait(struct ffb_softc *sc) 609 { 610 uint32_t ucsr, r; 611 612 while (1) { 613 ucsr = FBC_READ(sc, FFB_FBC_UCSR); 614 if ((ucsr & (FBC_UCSR_FB_BUSY|FBC_UCSR_RP_BUSY)) == 0) 615 break; 616 r = ucsr & (FBC_UCSR_READ_ERR | FBC_UCSR_FIFO_OVFL); 617 if (r != 0) 618 FBC_WRITE(sc, FFB_FBC_UCSR, r); 619 } 620 } 621 622 void 623 ffb_ras_init(struct ffb_softc *sc) 624 { 625 uint32_t fbc; 626 627 if (sc->sc_width > 1280) { 628 DPRINTF(("ffb_ras_init: high resolution.\n")); 629 fbc = FFB_FBC_WM_COMBINED | FFB_FBC_WE_FORCEON | 630 FFB_FBC_ZE_OFF | FFB_FBC_YE_OFF | FFB_FBC_XE_ON; 631 } else { 632 DPRINTF(("ffb_ras_init: standard resolution.\n")); 633 fbc = FFB_FBC_XE_OFF; 634 } 635 ffb_ras_fifo_wait(sc, 11); 636 DPRINTF(("WID: %08x\n", FBC_READ(sc, FFB_FBC_WID))); 637 FBC_WRITE(sc, FFB_FBC_WID, 0x0); 638 FBC_WRITE(sc, FFB_FBC_PPC, 639 FBC_PPC_VCE_DIS | FBC_PPC_TBE_OPAQUE | FBC_PPC_ACE_DIS | 640 FBC_PPC_APE_DIS | FBC_PPC_DCE_DIS | FBC_PPC_CS_CONST | 641 FBC_PPC_ABE_DIS | FBC_PPC_XS_WID); 642 643 fbc |= FFB_FBC_WB_A | FFB_FBC_RB_A | FFB_FBC_SB_BOTH | 644 FFB_FBC_RGBE_MASK; 645 DPRINTF(("%s: fbc is %08x\n", __func__, fbc)); 646 FBC_WRITE(sc, FFB_FBC_FBC, fbc); 647 FBC_WRITE(sc, FFB_FBC_ROP, FBC_ROP_NEW); 648 FBC_WRITE(sc, FFB_FBC_DRAWOP, FBC_DRAWOP_RECTANGLE); 649 FBC_WRITE(sc, FFB_FBC_PMASK, 0xffffffff); 650 FBC_WRITE(sc, FFB_FBC_FONTINC, 0x10000); 651 sc->sc_fg_cache = 0; 652 FBC_WRITE(sc, FFB_FBC_FG, sc->sc_fg_cache); 653 FBC_WRITE(sc, FFB_FBC_BLENDC, FFB_BLENDC_FORCE_ONE | 654 FFB_BLENDC_DF_ONE_M_A | 655 FFB_BLENDC_SF_A); 656 FBC_WRITE(sc, FFB_FBC_BLENDC1, 0); 657 FBC_WRITE(sc, FFB_FBC_BLENDC2, 0); 658 ffb_ras_wait(sc); 659 } 660 661 void 662 ffb_ras_eraserows(void *cookie, int row, int n, long attr) 663 { 664 struct rasops_info *ri = cookie; 665 struct vcons_screen *scr = ri->ri_hw; 666 struct ffb_softc *sc = scr->scr_cookie; 667 668 if (row < 0) { 669 n += row; 670 row = 0; 671 } 672 if (row + n > ri->ri_rows) 673 n = ri->ri_rows - row; 674 if (n <= 0) 675 return; 676 677 ffb_ras_fill(sc); 678 ffb_ras_setfg(sc, ri->ri_devcmap[(attr >> 16) & 0xf]); 679 ffb_ras_fifo_wait(sc, 4); 680 if ((n == ri->ri_rows) && (ri->ri_flg & RI_FULLCLEAR)) { 681 FBC_WRITE(sc, FFB_FBC_BY, 0); 682 FBC_WRITE(sc, FFB_FBC_BX, 0); 683 FBC_WRITE(sc, FFB_FBC_BH, ri->ri_height); 684 FBC_WRITE(sc, FFB_FBC_BW, ri->ri_width); 685 } else { 686 row *= ri->ri_font->fontheight; 687 FBC_WRITE(sc, FFB_FBC_BY, ri->ri_yorigin + row); 688 FBC_WRITE(sc, FFB_FBC_BX, ri->ri_xorigin); 689 FBC_WRITE(sc, FFB_FBC_BH, n * ri->ri_font->fontheight); 690 FBC_WRITE(sc, FFB_FBC_BW, ri->ri_emuwidth); 691 } 692 SYNC; 693 } 694 695 void 696 ffb_ras_erasecols(void *cookie, int row, int col, int n, long attr) 697 { 698 struct rasops_info *ri = cookie; 699 struct vcons_screen *scr = ri->ri_hw; 700 struct ffb_softc *sc = scr->scr_cookie; 701 702 if ((row < 0) || (row >= ri->ri_rows)) 703 return; 704 if (col < 0) { 705 n += col; 706 col = 0; 707 } 708 if (col + n > ri->ri_cols) 709 n = ri->ri_cols - col; 710 if (n <= 0) 711 return; 712 n *= ri->ri_font->fontwidth; 713 col *= ri->ri_font->fontwidth; 714 row *= ri->ri_font->fontheight; 715 716 ffb_ras_fill(sc); 717 ffb_ras_setfg(sc, ri->ri_devcmap[(attr >> 16) & 0xf]); 718 ffb_ras_fifo_wait(sc, 4); 719 FBC_WRITE(sc, FFB_FBC_BY, ri->ri_yorigin + row); 720 FBC_WRITE(sc, FFB_FBC_BX, ri->ri_xorigin + col); 721 FBC_WRITE(sc, FFB_FBC_BH, ri->ri_font->fontheight); 722 FBC_WRITE(sc, FFB_FBC_BW, n - 1); 723 SYNC; 724 } 725 726 void 727 ffb_ras_fill(struct ffb_softc *sc) 728 { 729 ffb_ras_fifo_wait(sc, 3); 730 FBC_WRITE(sc, FFB_FBC_PPC, 731 FBC_PPC_VCE_DIS | FBC_PPC_TBE_OPAQUE | FBC_PPC_ACE_DIS | 732 FBC_PPC_APE_DIS | FBC_PPC_DCE_DIS | FBC_PPC_CS_CONST | 733 FBC_PPC_ABE_DIS | FBC_PPC_XS_WID); 734 FBC_WRITE(sc, FFB_FBC_ROP, FBC_ROP_NEW); 735 FBC_WRITE(sc, FFB_FBC_DRAWOP, FBC_DRAWOP_RECTANGLE); 736 SYNC; 737 } 738 739 void 740 ffb_ras_invert(struct ffb_softc *sc) 741 { 742 ffb_ras_fifo_wait(sc, 3); 743 FBC_WRITE(sc, FFB_FBC_PPC, 744 FBC_PPC_VCE_DIS | FBC_PPC_TBE_OPAQUE | FBC_PPC_ACE_DIS | 745 FBC_PPC_APE_DIS | FBC_PPC_DCE_DIS | FBC_PPC_CS_CONST | 746 FBC_PPC_ABE_DIS | FBC_PPC_XS_WID); 747 FBC_WRITE(sc, FFB_FBC_ROP, FBC_ROP_INVERT); 748 FBC_WRITE(sc, FFB_FBC_DRAWOP, FBC_DRAWOP_RECTANGLE); 749 SYNC; 750 } 751 752 void 753 ffb_ras_copyrows(void *cookie, int src, int dst, int n) 754 { 755 struct rasops_info *ri = cookie; 756 struct vcons_screen *scr = ri->ri_hw; 757 struct ffb_softc *sc = scr->scr_cookie; 758 759 if (dst == src) 760 return; 761 if (src < 0) { 762 n += src; 763 src = 0; 764 } 765 if ((src + n) > ri->ri_rows) 766 n = ri->ri_rows - src; 767 if (dst < 0) { 768 n += dst; 769 dst = 0; 770 } 771 if ((dst + n) > ri->ri_rows) 772 n = ri->ri_rows - dst; 773 if (n <= 0) 774 return; 775 n *= ri->ri_font->fontheight; 776 src *= ri->ri_font->fontheight; 777 dst *= ri->ri_font->fontheight; 778 779 ffb_ras_fifo_wait(sc, 9); 780 FBC_WRITE(sc, FFB_FBC_PPC, 781 FBC_PPC_VCE_DIS | FBC_PPC_TBE_OPAQUE | FBC_PPC_ACE_DIS | 782 FBC_PPC_APE_DIS | FBC_PPC_DCE_DIS | FBC_PPC_CS_CONST | 783 FBC_PPC_ABE_DIS | FBC_PPC_XS_WID); 784 FBC_WRITE(sc, FFB_FBC_ROP, FBC_ROP_OLD | (FBC_ROP_OLD << 8)); 785 FBC_WRITE(sc, FFB_FBC_DRAWOP, FBC_DRAWOP_VSCROLL); 786 FBC_WRITE(sc, FFB_FBC_BY, ri->ri_yorigin + src); 787 FBC_WRITE(sc, FFB_FBC_BX, ri->ri_xorigin); 788 FBC_WRITE(sc, FFB_FBC_DY, ri->ri_yorigin + dst); 789 FBC_WRITE(sc, FFB_FBC_DX, ri->ri_xorigin); 790 FBC_WRITE(sc, FFB_FBC_BH, n); 791 FBC_WRITE(sc, FFB_FBC_BW, ri->ri_emuwidth); 792 SYNC; 793 } 794 795 static void 796 ffb_ras_setfg(struct ffb_softc *sc, int32_t fg) 797 { 798 ffb_ras_fifo_wait(sc, 1); 799 if (fg == sc->sc_fg_cache) 800 return; 801 sc->sc_fg_cache = fg; 802 FBC_WRITE(sc, FFB_FBC_FG, fg); 803 SYNC; 804 } 805 806 static void 807 ffb_ras_setbg(struct ffb_softc *sc, int32_t bg) 808 { 809 ffb_ras_fifo_wait(sc, 1); 810 if (bg == sc->sc_bg_cache) 811 return; 812 sc->sc_bg_cache = bg; 813 FBC_WRITE(sc, FFB_FBC_BG, bg); 814 SYNC; 815 } 816 817 /* frame buffer generic driver support functions */ 818 static void 819 ffbfb_unblank(device_t dev) 820 { 821 struct ffb_softc *sc = device_private(dev); 822 struct vcons_screen *ms = sc->vd.active; 823 u_int on = 1; 824 int redraw = 0; 825 826 ffb_ras_init(sc); 827 if (sc->sc_locked) { 828 sc->sc_locked = 0; 829 redraw = 1; 830 } 831 832 ffb_blank(sc, WSDISPLAYIO_SVIDEO, &on); 833 #if 0 834 if ((sc->vd.active != &ffb_console_screen) && 835 (ffb_console_screen.scr_flags & VCONS_SCREEN_IS_STATIC)) { 836 /* 837 * force-switch to the console screen. 838 * Caveat: the higher layer will think we're still on the 839 * other screen 840 */ 841 842 SCREEN_INVISIBLE(sc->vd.active); 843 sc->vd.active = &ffb_console_screen; 844 SCREEN_VISIBLE(sc->vd.active); 845 ms = sc->vd.active; 846 redraw = 1; 847 } 848 #endif 849 if (redraw) { 850 vcons_redraw_screen(ms); 851 } 852 } 853 854 int 855 ffbfb_open(dev_t dev, int flags, int mode, struct lwp *l) 856 { 857 struct ffb_softc *sc; 858 859 sc = device_lookup_private(&ffb_cd, minor(dev)); 860 if (sc == NULL) 861 return ENXIO; 862 863 sc->sc_locked = 1; 864 return 0; 865 } 866 867 int 868 ffbfb_close(dev_t dev, int flags, int mode, struct lwp *l) 869 { 870 struct ffb_softc *sc = device_lookup_private(&ffb_cd, minor(dev)); 871 struct vcons_screen *ms = sc->vd.active; 872 873 sc->sc_locked = 0; 874 if (ms != NULL) { 875 if ((sc->sc_mode == WSDISPLAYIO_MODE_EMUL) && 876 (sc->sc_locked == 0)) { 877 ffb_ras_init(sc); 878 vcons_redraw_screen(ms); 879 } 880 } 881 return 0; 882 } 883 884 int 885 ffbfb_ioctl(dev_t dev, u_long cmd, void *data, int flags, struct lwp *l) 886 { 887 struct ffb_softc *sc = device_lookup_private(&ffb_cd, minor(dev)); 888 889 return ffb_ioctl(&sc->vd, NULL, cmd, data, flags, l); 890 } 891 892 paddr_t 893 ffbfb_mmap(dev_t dev, off_t off, int prot) 894 { 895 struct ffb_softc *sc = device_lookup_private(&ffb_cd, minor(dev)); 896 uint64_t size; 897 int i, reg; 898 off_t o; 899 900 /* 901 * off is a magic cookie (see xfree86/drivers/sunffb/ffb.h), 902 * which we map to an index into the "reg" property, and use 903 * our copy of the firmware data as arguments for the real 904 * mapping. 905 */ 906 static struct { unsigned long voff; int reg; } map[] = { 907 { 0x00000000, FFB_REG_SFB8R }, 908 { 0x00400000, FFB_REG_SFB8G }, 909 { 0x00800000, FFB_REG_SFB8B }, 910 { 0x00c00000, FFB_REG_SFB8X }, 911 { 0x01000000, FFB_REG_SFB32 }, 912 { 0x02000000, FFB_REG_SFB64 }, 913 { 0x04000000, FFB_REG_FBC }, 914 { 0x04004000, FFB_REG_DFB8R }, 915 { 0x04404000, FFB_REG_DFB8G }, 916 { 0x04804000, FFB_REG_DFB8B }, 917 { 0x04c04000, FFB_REG_DFB8X }, 918 { 0x05004000, FFB_REG_DFB24 }, 919 { 0x06004000, FFB_REG_DFB32 }, 920 { 0x07004000, FFB_REG_DFB422A }, 921 { 0x0bc06000, FFB_REG_DAC }, 922 { 0x0bc08000, FFB_REG_PROM }, 923 { 0x0bc18000, 0 } 924 }; 925 926 /* special value "FFB_EXP_VOFF" - not backed by any "reg" entry */ 927 if (off == 0x0bc18000) 928 return bus_space_mmap(sc->sc_bt, sc->sc_addrs[FFB_REG_PROM], 929 0x00200000, prot, BUS_SPACE_MAP_LINEAR); 930 931 /* 932 * FFB_VOFF_FBC_KREGS - used by afbinit to upload firmware. We should 933 * probably mmap them only on afb boards 934 */ 935 if ((off >= 0x0bc04000) && (off < 0x0bc06000)) 936 return bus_space_mmap(sc->sc_bt, sc->sc_addrs[FFB_REG_PROM], 937 0x00610000 + (off - 0x0bc04000), prot, 938 BUS_SPACE_MAP_LINEAR); 939 940 #define NELEMS(arr) (sizeof(arr)/sizeof((arr)[0])) 941 942 /* the map is ordered by voff */ 943 for (i = 0; i < NELEMS(map)-1; i++) { 944 reg = map[i].reg; 945 /* the number of entries in reg seems to vary */ 946 if (reg < sc->sc_nreg) { 947 size = min((map[i + 1].voff - map[i].voff), 948 sc->sc_sizes[reg]); 949 if ((off >= map[i].voff) && 950 (off < (map[i].voff + size))) { 951 o = off - map[i].voff; 952 return bus_space_mmap(sc->sc_bt, 953 sc->sc_addrs[reg], o, prot, 954 BUS_SPACE_MAP_LINEAR); 955 } 956 } 957 } 958 959 return -1; 960 } 961 962 void 963 ffb_clearscreen(struct ffb_softc *sc) 964 { 965 struct rasops_info *ri = &ffb_console_screen.scr_ri; 966 ffb_ras_fill(sc); 967 ffb_ras_setfg(sc, ri->ri_devcmap[WS_DEFAULT_BG]); 968 ffb_ras_fifo_wait(sc, 4); 969 FBC_WRITE(sc, FFB_FBC_BY, 0); 970 FBC_WRITE(sc, FFB_FBC_BX, 0); 971 FBC_WRITE(sc, FFB_FBC_BH, sc->sc_height); 972 FBC_WRITE(sc, FFB_FBC_BW, sc->sc_width); 973 } 974 975 void 976 ffb_cursor(void *cookie, int on, int row, int col) 977 { 978 struct rasops_info *ri = cookie; 979 struct vcons_screen *scr; 980 struct ffb_softc *sc; 981 int x, y, wi, he; 982 983 if (cookie != NULL) { 984 scr = ri->ri_hw; 985 sc = scr->scr_cookie; 986 987 wi = ri->ri_font->fontwidth; 988 he = ri->ri_font->fontheight; 989 990 if (sc->sc_mode == WSDISPLAYIO_MODE_EMUL) { 991 992 if (ri->ri_flg & RI_CURSOR) { 993 994 /* remove cursor */ 995 x = ri->ri_ccol * wi + ri->ri_xorigin; 996 y = ri->ri_crow * he + ri->ri_yorigin; 997 998 ffb_ras_invert(sc); 999 ffb_ras_fifo_wait(sc, 4); 1000 FBC_WRITE(sc, FFB_FBC_BY, y); 1001 FBC_WRITE(sc, FFB_FBC_BX, x); 1002 FBC_WRITE(sc, FFB_FBC_BH, he); 1003 FBC_WRITE(sc, FFB_FBC_BW, wi); 1004 1005 ri->ri_flg &= ~RI_CURSOR; 1006 } 1007 ri->ri_crow = row; 1008 ri->ri_ccol = col; 1009 if (on) 1010 { 1011 x = ri->ri_ccol * wi + ri->ri_xorigin; 1012 y = ri->ri_crow * he + ri->ri_yorigin; 1013 1014 ffb_ras_invert(sc); 1015 ffb_ras_fifo_wait(sc, 4); 1016 FBC_WRITE(sc, FFB_FBC_BY, y); 1017 FBC_WRITE(sc, FFB_FBC_BX, x); 1018 FBC_WRITE(sc, FFB_FBC_BH, he); 1019 FBC_WRITE(sc, FFB_FBC_BW, wi); 1020 1021 ri->ri_flg |= RI_CURSOR; 1022 } 1023 } else { 1024 ri->ri_crow = row; 1025 ri->ri_ccol = col; 1026 ri->ri_flg &= ~RI_CURSOR; 1027 } 1028 } 1029 } 1030 1031 /* mono bitmap font */ 1032 void 1033 ffb_putchar_mono(void *cookie, int row, int col, u_int c, long attr) 1034 { 1035 struct rasops_info *ri = cookie; 1036 struct vcons_screen *scr = ri->ri_hw; 1037 struct wsdisplay_font *font = PICK_FONT(ri, c); 1038 struct ffb_softc *sc = scr->scr_cookie; 1039 void *data; 1040 uint32_t fg, bg; 1041 int i; 1042 int x, y, wi, he; 1043 1044 if (sc->sc_mode != WSDISPLAYIO_MODE_EMUL) 1045 return; 1046 1047 wi = font->fontwidth; 1048 he = font->fontheight; 1049 1050 if (!CHAR_IN_FONT(c, font)) 1051 return; 1052 1053 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 1054 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 1055 x = ri->ri_xorigin + col * wi; 1056 y = ri->ri_yorigin + row * he; 1057 1058 data = WSFONT_GLYPH(c, font); 1059 1060 ffb_ras_setbg(sc, bg); 1061 ffb_ras_setfg(sc, fg); 1062 ffb_ras_fifo_wait(sc, 4); 1063 FBC_WRITE(sc, FFB_FBC_ROP, FBC_ROP_NEW); 1064 FBC_WRITE(sc, FFB_FBC_FONTXY, (y << 16) | x); 1065 FBC_WRITE(sc, FFB_FBC_FONTW, wi); 1066 FBC_WRITE(sc, FFB_FBC_PPC, 1067 FBC_PPC_VCE_DIS | FBC_PPC_TBE_OPAQUE | FBC_PPC_ACE_DIS | 1068 FBC_PPC_APE_DIS | FBC_PPC_DCE_DIS | FBC_PPC_CS_CONST | 1069 FBC_PPC_ABE_DIS | FBC_PPC_XS_WID); 1070 1071 switch (font->stride) { 1072 case 1: { 1073 uint8_t *data8 = data; 1074 uint32_t reg; 1075 for (i = 0; i < he; i++) { 1076 reg = *data8; 1077 FBC_WRITE(sc, FFB_FBC_FONT, reg << 24); 1078 data8++; 1079 } 1080 break; 1081 } 1082 case 2: { 1083 uint16_t *data16 = data; 1084 uint32_t reg; 1085 for (i = 0; i < he; i++) { 1086 reg = *data16; 1087 FBC_WRITE(sc, FFB_FBC_FONT, reg << 16); 1088 data16++; 1089 } 1090 break; 1091 } 1092 } 1093 } 1094 1095 /* alpha font */ 1096 void 1097 ffb_putchar_aa(void *cookie, int row, int col, u_int c, long attr) 1098 { 1099 struct rasops_info *ri = cookie; 1100 struct vcons_screen *scr = ri->ri_hw; 1101 struct wsdisplay_font *font = PICK_FONT(ri, c); 1102 struct ffb_softc *sc = scr->scr_cookie; 1103 volatile uint32_t *dest, *ddest; 1104 uint8_t *data8; 1105 uint32_t fg, bg; 1106 int i; 1107 int x, y, wi, he; 1108 uint32_t alpha = 0x80; 1109 int j; 1110 1111 if (sc->sc_mode != WSDISPLAYIO_MODE_EMUL) 1112 return; 1113 1114 wi = font->fontwidth; 1115 he = font->fontheight; 1116 1117 if (!CHAR_IN_FONT(c, font)) 1118 return; 1119 1120 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 1121 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 1122 x = ri->ri_xorigin + col * wi; 1123 y = ri->ri_yorigin + row * he; 1124 1125 data8 = WSFONT_GLYPH(c, font); 1126 1127 /* first we erase the background */ 1128 ffb_ras_fill(sc); 1129 ffb_ras_setfg(sc, bg); 1130 ffb_ras_fifo_wait(sc, 4); 1131 FBC_WRITE(sc, FFB_FBC_BY, y); 1132 FBC_WRITE(sc, FFB_FBC_BX, x); 1133 FBC_WRITE(sc, FFB_FBC_BH, he); 1134 FBC_WRITE(sc, FFB_FBC_BW, wi); 1135 1136 /* if we draw a space we're done */ 1137 if (c == ' ') return; 1138 1139 /* now enable alpha blending */ 1140 ffb_ras_setfg(sc, fg); 1141 ffb_ras_fifo_wait(sc, 2); 1142 FBC_WRITE(sc, FFB_FBC_ROP, FBC_ROP_NEW); 1143 1144 FBC_WRITE(sc, FFB_FBC_PPC, 1145 FBC_PPC_VCE_DIS | FBC_PPC_TBE_OPAQUE | FBC_PPC_ACE_DIS | 1146 FBC_PPC_APE_DIS | FBC_PPC_DCE_DIS | FBC_PPC_CS_CONST | 1147 FBC_PPC_ABE_ENA | FBC_PPC_XS_VAR); 1148 /* 1149 * we have to wait for both the rectangle drawing op above and the 1150 * FFB_FBC_PPC write to finish before mucking around in the SFB aperture 1151 */ 1152 ffb_ras_wait(sc); 1153 1154 /* ... and draw the character */ 1155 dest = sc->sc_sfb32 + (y << 11) + x; 1156 for (i = 0; i < he; i++) { 1157 ddest = dest; 1158 for (j = 0; j < wi; j++) { 1159 alpha = *data8; 1160 /* 1161 * We set the colour source to constant above so we only 1162 * have to write the alpha channel here and the colour 1163 * comes from the FG register. It would be nice if we 1164 * could just use the SFB8X aperture and memcpy() the 1165 * alpha map line by line but for some strange reason 1166 * that will take colour info from the framebuffer even 1167 * if we set the FBC_PPC_CS_CONST bit above. 1168 */ 1169 *ddest = alpha << 24; 1170 data8++; 1171 ddest++; 1172 } 1173 dest += 2048; 1174 } 1175 } 1176 1177 int 1178 ffb_allocattr(void *cookie, int fg, int bg, int flags, long *attrp) 1179 { 1180 if ((fg == 0) && (bg == 0)) 1181 { 1182 fg = WS_DEFAULT_FG; 1183 bg = WS_DEFAULT_BG; 1184 } 1185 if (flags & WSATTR_REVERSE) { 1186 *attrp = (bg & 0xff) << 24 | (fg & 0xff) << 16 | 1187 (flags & 0xff); 1188 } else 1189 *attrp = (fg & 0xff) << 24 | (bg & 0xff) << 16 | 1190 (flags & 0xff); 1191 return 0; 1192 } 1193 1194 void 1195 ffb_init_screen(void *cookie, struct vcons_screen *scr, 1196 int existing, long *defattr) 1197 { 1198 struct ffb_softc *sc = cookie; 1199 struct rasops_info *ri = &scr->scr_ri; 1200 1201 ri->ri_depth = 32; 1202 ri->ri_width = sc->sc_width; 1203 ri->ri_height = sc->sc_height; 1204 ri->ri_stride = sc->sc_linebytes; 1205 ri->ri_flg = RI_CENTER | RI_ENABLE_ALPHA; 1206 1207 /* 1208 * we can't accelerate copycols() so instead of falling back to 1209 * software use vcons' putchar() based implementation 1210 */ 1211 scr->scr_flags |= VCONS_NO_COPYCOLS; 1212 #ifdef VCONS_DRAW_INTR 1213 scr->scr_flags |= VCONS_DONT_READ; 1214 #endif 1215 DPRINTF(("ffb_init_screen: addr: %08lx\n",(ulong)ri->ri_bits)); 1216 1217 /* explicitly request BGR in case the default changes */ 1218 ri->ri_rnum = 8; 1219 ri->ri_gnum = 8; 1220 ri->ri_bnum = 8; 1221 ri->ri_rpos = 0; 1222 ri->ri_gpos = 8; 1223 ri->ri_bpos = 16; 1224 1225 rasops_init(ri, 0, 0); 1226 ri->ri_caps = WSSCREEN_WSCOLORS; 1227 rasops_reconfig(ri, sc->sc_height / ri->ri_font->fontheight, 1228 sc->sc_width / ri->ri_font->fontwidth); 1229 1230 /* enable acceleration */ 1231 ri->ri_ops.copyrows = ffb_ras_copyrows; 1232 ri->ri_ops.eraserows = ffb_ras_eraserows; 1233 ri->ri_ops.erasecols = ffb_ras_erasecols; 1234 ri->ri_ops.cursor = ffb_cursor; 1235 ri->ri_ops.allocattr = ffb_allocattr; 1236 if (FONT_IS_ALPHA(ri->ri_font)) { 1237 ri->ri_ops.putchar = ffb_putchar_aa; 1238 } else 1239 ri->ri_ops.putchar = ffb_putchar_mono; 1240 } 1241 1242 /* I2C bitbanging */ 1243 static void ffb_i2cbb_set_bits(void *cookie, uint32_t bits) 1244 { 1245 struct ffb_softc *sc = cookie; 1246 1247 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_CFG_MPDATA); 1248 DAC_WRITE(sc, FFB_DAC_VALUE, bits); 1249 } 1250 1251 static void ffb_i2cbb_set_dir(void *cookie, uint32_t dir) 1252 { 1253 /* Nothing to do */ 1254 } 1255 1256 static uint32_t ffb_i2cbb_read(void *cookie) 1257 { 1258 struct ffb_softc *sc = cookie; 1259 uint32_t bits; 1260 1261 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_CFG_MPSENSE); 1262 bits = DAC_READ(sc, FFB_DAC_VALUE); 1263 1264 return bits; 1265 } 1266 1267 /* higher level I2C stuff */ 1268 static int 1269 ffb_i2c_acquire_bus(void *cookie, int flags) 1270 { 1271 /* private bus */ 1272 return (0); 1273 } 1274 1275 static void 1276 ffb_i2c_release_bus(void *cookie, int flags) 1277 { 1278 /* private bus */ 1279 } 1280 1281 static int 1282 ffb_i2c_send_start(void *cookie, int flags) 1283 { 1284 return (i2c_bitbang_send_start(cookie, flags, &ffb_i2cbb_ops)); 1285 } 1286 1287 static int 1288 ffb_i2c_send_stop(void *cookie, int flags) 1289 { 1290 1291 return (i2c_bitbang_send_stop(cookie, flags, &ffb_i2cbb_ops)); 1292 } 1293 1294 static int 1295 ffb_i2c_initiate_xfer(void *cookie, i2c_addr_t addr, int flags) 1296 { 1297 /* 1298 * for some reason i2c_bitbang_initiate_xfer left-shifts 1299 * the I2C-address and then sets the direction bit 1300 */ 1301 return (i2c_bitbang_initiate_xfer(cookie, addr, flags, 1302 &ffb_i2cbb_ops)); 1303 } 1304 1305 static int 1306 ffb_i2c_read_byte(void *cookie, uint8_t *valp, int flags) 1307 { 1308 return (i2c_bitbang_read_byte(cookie, valp, flags, &ffb_i2cbb_ops)); 1309 } 1310 1311 static int 1312 ffb_i2c_write_byte(void *cookie, uint8_t val, int flags) 1313 { 1314 return (i2c_bitbang_write_byte(cookie, val, flags, &ffb_i2cbb_ops)); 1315 } 1316 1317 1318 #define TVC_READ_LIMIT 100000 1319 int 1320 ffb_tgc_disable(struct ffb_softc *sc) 1321 { 1322 int i; 1323 1324 /* Is the timing generator disabled? */ 1325 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_TGC); 1326 if (!(DAC_READ(sc, FFB_DAC_VALUE) & FFB_DAC_TGC_TIMING_ENABLE)) 1327 return 1; 1328 1329 /* If not, disable it when the vertical counter reaches 0 */ 1330 for (i = 0; i < TVC_READ_LIMIT; i++) { 1331 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_TVC); 1332 if (!DAC_READ(sc, FFB_DAC_VALUE)) { 1333 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_TGC); 1334 DAC_WRITE(sc, FFB_DAC_VALUE, 0); 1335 return 1; 1336 } 1337 } 1338 return 0; 1339 } 1340 1341 /* 1342 * PLL Control Register values: 1343 * M)ultiplier = bits 0:6 + 1 1344 * D)ivisor = bits 7:10 + 1 1345 * P)ost divisor = bits 11:13 (000 = 1, 001 = 2, 010 = 4, 011 = 8) 1346 * Frequency = 13.5 * M / D / P 1347 */ 1348 #define FFB_PLL_FREQ 13500000 1349 void 1350 ffb_get_pclk(int request, uint32_t *pll, int *diff) 1351 { 1352 int m, d, p, f, hex = 0, curdiff; 1353 1354 *diff = 100000000; 1355 1356 for (m = 32; m <= 80; m++) { 1357 for (d = 4; d <= 11; d++) { 1358 for (p = 1; p <= 8; p = p << 1) { 1359 switch (p) { 1360 case 1: 1361 hex = 0x4000 + (d << 7) + m; 1362 break; 1363 case 2: 1364 hex = 0x4800 + (d << 7) + m; 1365 break; 1366 case 4: 1367 hex = 0x5000 + (d << 7) + m; 1368 break; 1369 case 8: 1370 hex = 0x6000 + (d << 7) + m; 1371 break; 1372 } 1373 f = 13500000 * m / d / p; 1374 if (f == request) { 1375 *diff = 0; 1376 *pll = hex; 1377 return; 1378 } else { 1379 curdiff = abs(request - f); 1380 if (curdiff < *diff) { 1381 *diff = curdiff; 1382 *pll = hex; 1383 } 1384 } 1385 } 1386 } 1387 } 1388 } 1389 1390 /* 1391 * Details of the FFB RAMDAC are contained in the Brooktree BT497/498 1392 * and in the Connexant BT497A/498A documentation. 1393 * 1394 * VESA timings to FFB register conversion: 1395 * If interleave = 4/2:1 then x = 2, if interleave = 8/2:1 then x = 4 1396 * VBE = VBS - vres = (sync pulse - 1) + back porch 1397 * VBS = VSS - front porch = (sync pulse - 1) + back porch + vres 1398 * VSE = sync pulse - 1 1399 * VSS = (sync pulse - 1) + back porch + vres + front porch 1400 * HRE = HSS - HSE - 1 1401 * HBE = (sync pulse + back porch) / x - 1 1402 * HBS = (sync pulse + back porch + hres) / x - 1 1403 * HSE = sync pulse / x - 1 1404 * HSS = (sync pulse + back porch + hres + front porch) / x - 1 1405 * HCE = HBS - 4 1406 * HCS = HBE - 4 1407 * EPE = EIE = EIS = 0 (for all non-interlaced modes) 1408 * 1409 * Note, that 8/2:1 Single Buffered Interleaving is only supported by the 1410 * double-buffered FFB (Creator3D), and at higher resolutions than 1280x1024 1411 * 1412 * Note, that the timing generator should be disabled and re-enabled when the 1413 * the timing parameter registers are being programmed. Stopping the timing 1414 * generator should only be done when the vertical counter is zero. 1415 */ 1416 #define DIVIDE(x,y) (((x) + ((y) / 2)) / (y)) 1417 int 1418 ffb_set_vmode(struct ffb_softc *sc, struct videomode *mode, int btype, 1419 int *hres, int *vres) 1420 { 1421 int diff; 1422 uint32_t fp, sp, bp, x; 1423 uint32_t pll, pfc, ucl, dcl, tgc; 1424 uint32_t vbe, vbs, vse, vss, hre, hbe, hbs, hse, hss, hce, hcs; 1425 uint32_t epe, eie, eis; 1426 uint32_t fbcfg0; 1427 1428 DPRINTF(("ffb_set_vmode: %dx%d@%d", mode->hdisplay, mode->vdisplay, 1429 DIVIDE(DIVIDE(mode->dot_clock * 1000, 1430 mode->htotal), mode->vtotal))); 1431 DPRINTF((" (%d %d %d %d %d %d %d", 1432 mode->dot_clock, mode->hsync_start, mode->hsync_end, mode->htotal, 1433 mode->vsync_start, mode->vsync_end, mode->vtotal)); 1434 DPRINTF((" %s%sH %s%sV)\n", 1435 mode->flags & VID_PHSYNC ? "+" : "", 1436 mode->flags & VID_NHSYNC ? "-" : "", 1437 mode->flags & VID_PVSYNC ? "+" : "", 1438 mode->flags & VID_NVSYNC ? "-" : "")); 1439 1440 /* We don't handle interlaced or doublescan (yet) */ 1441 if ((mode->flags & VID_INTERLACE) || (mode->flags & VID_DBLSCAN)) 1442 return 0; 1443 1444 /* Only Creator3D can be set to > 1280x1024 */ 1445 if(((sc->sc_type == FFB_CREATOR && !((btype & 7) == 3)) || 1446 sc->sc_type == FFB_AFB) 1447 && (mode->hdisplay > 1280 || mode->vdisplay > 1024)) 1448 return 0; 1449 /* Creator3D can be set to <= 1920x1360 */ 1450 if (mode->hdisplay > 1920 || mode->vdisplay > 1360) 1451 return 0; 1452 1453 /* 1454 * Look for a matching pixel clock and set PLL Control. 1455 * XXX: 640x480@60 is 25175000 in modelines but 25125000 in the 1456 * FFB PROM, and the closest match to 25175000 (0x4da9/25159090) 1457 * does not work. So, use the PROM value instead. 1458 */ 1459 if (mode->hdisplay == 640 && mode->vdisplay == 480 && 1460 mode->dot_clock == 25175) { 1461 DPRINTF(("ffb_set_vmode: 640x480@60: adjusted dot clock\n")); 1462 mode->dot_clock = 25125; 1463 } 1464 ffb_get_pclk(mode->dot_clock * 1000, &pll, &diff); 1465 if (diff > 250000) 1466 return 0; 1467 1468 /* Pixel Format Control, User Control and FBC Configuration. */ 1469 if (mode->hdisplay > 1280) { 1470 pfc = FFB_DAC_PIX_FMT_821; 1471 ucl = FFB_DAC_USR_CTRL_OVERLAY | FFB_DAC_USR_CTRL_WMODE_C; 1472 x = 4; 1473 fbcfg0 = FBC_READ(sc, FFB_FBC_FBCFG0) | FBC_CFG0_DOUBLE_BUF; 1474 } else { 1475 pfc = FFB_DAC_PIX_FMT_421; 1476 /* Only Creator3D and Elite3D can have double-buffer */ 1477 if ((sc->sc_type == FFB_CREATOR && !((btype & 7) == 3))) 1478 ucl = 0; 1479 else 1480 ucl = FFB_DAC_USR_CTRL_DOUBLE; 1481 ucl |= (FFB_DAC_USR_CTRL_OVERLAY | FFB_DAC_USR_CTRL_WMODE_S8); 1482 x = 2; 1483 fbcfg0 = FBC_READ(sc, FFB_FBC_FBCFG0) | FBC_CFG0_SINGLE_BUF; 1484 } 1485 1486 /* DAC Control and Timing Generator Control */ 1487 if (mode->flags & VID_PVSYNC) 1488 dcl = FFB_DAC_DAC_CTRL_POS_VSYNC; 1489 else 1490 dcl = 0; 1491 tgc = 0; 1492 #define EDID_VID_INP sc->sc_edid_info.edid_video_input 1493 if ((EDID_VID_INP & EDID_VIDEO_INPUT_COMPOSITE_SYNC)) { 1494 dcl |= FFB_DAC_DAC_CTRL_VSYNC_DIS; 1495 tgc = FFB_DAC_TGC_EQUAL_DISABLE; 1496 } else { 1497 dcl |= FFB_DAC_DAC_CTRL_SYNC_G; 1498 if (EDID_VID_INP & EDID_VIDEO_INPUT_SEPARATE_SYNCS) 1499 tgc |= FFB_DAC_TGC_VSYNC_DISABLE; 1500 else 1501 tgc = FFB_DAC_TGC_EQUAL_DISABLE; 1502 } 1503 if (EDID_VID_INP & EDID_VIDEO_INPUT_BLANK_TO_BLACK) 1504 dcl |= FFB_DAC_DAC_CTRL_PED_ENABLE; 1505 tgc |= (FFB_DAC_TGC_VIDEO_ENABLE | FFB_DAC_TGC_TIMING_ENABLE | 1506 FFB_DAC_TGC_MASTER_ENABLE); 1507 1508 /* Vertical timing */ 1509 fp = mode->vsync_start - mode->vdisplay; 1510 sp = mode->vsync_end - mode->vsync_start; 1511 bp = mode->vtotal - mode->vsync_end; 1512 1513 vbe = sp - 1 + bp; 1514 vbs = sp - 1 + bp + mode->vdisplay; 1515 vse = sp - 1; 1516 vss = sp - 1 + bp + mode->vdisplay + fp; 1517 1518 /* Horizontal timing */ 1519 fp = mode->hsync_start - mode->hdisplay; 1520 sp = mode->hsync_end - mode->hsync_start; 1521 bp = mode->htotal - mode->hsync_end; 1522 1523 hbe = (sp + bp) / x - 1; 1524 hbs = (sp + bp + mode->hdisplay) / x - 1; 1525 hse = sp / x - 1; 1526 hss = (sp + bp + mode->hdisplay + fp) / x -1; 1527 hre = hss - hse - 1; 1528 hce = hbs - 4; 1529 hcs = hbe - 4; 1530 1531 /* Equalisation (interlaced modes) */ 1532 epe = 0; 1533 eie = 0; 1534 eis = 0; 1535 1536 DPRINTF(("ffb_set_vmode: 0x%04x 0x%04x 0x%04x 0x%04x 0x%04x\n", 1537 pll, pfc, ucl, dcl, tgc)); 1538 DPRINTF(("\t0x%04x 0x%04x 0x%04x 0x%04x\n", vbe, vbs, vse, vss)); 1539 DPRINTF(("\t0x%04x 0x%04x 0x%04x 0x%04x 0x%04x 0x%04x 0x%04x\n", 1540 hre, hbe, hbs, hse, hss, hce, hcs)); 1541 DPRINTF(("\t0x%04x 0x%04x 0x%04x\n", epe, eie, eis)); 1542 1543 if (!ffb_tgc_disable(sc)) { 1544 DPRINTF(("ffb_set_vmode: failed to disable TGC register\n")); 1545 return 0; 1546 } 1547 1548 /* 1549 * Program the mode registers. 1550 * Program the timing generator last, as that re-enables output. 1551 * Note, that a read to/write from a register increments the 1552 * register address to the next register automatically. 1553 */ 1554 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_PLL_CTRL); 1555 DAC_WRITE(sc, FFB_DAC_VALUE, pll); 1556 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_PIX_FMT); 1557 DAC_WRITE(sc, FFB_DAC_VALUE, pfc); 1558 DAC_WRITE(sc, FFB_DAC_VALUE, ucl); 1559 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_DAC_CTRL); 1560 DAC_WRITE(sc, FFB_DAC_VALUE, dcl); 1561 1562 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_VBE); 1563 DAC_WRITE(sc, FFB_DAC_VALUE, vbe); 1564 DAC_WRITE(sc, FFB_DAC_VALUE, vbs); 1565 DAC_WRITE(sc, FFB_DAC_VALUE, vse); 1566 DAC_WRITE(sc, FFB_DAC_VALUE, vss); 1567 1568 DAC_WRITE(sc, FFB_DAC_VALUE, hre); 1569 DAC_WRITE(sc, FFB_DAC_VALUE, hbe); 1570 DAC_WRITE(sc, FFB_DAC_VALUE, hbs); 1571 DAC_WRITE(sc, FFB_DAC_VALUE, hse); 1572 DAC_WRITE(sc, FFB_DAC_VALUE, hss); 1573 DAC_WRITE(sc, FFB_DAC_VALUE, hce); 1574 DAC_WRITE(sc, FFB_DAC_VALUE, hcs); 1575 1576 DAC_WRITE(sc, FFB_DAC_VALUE, epe); 1577 DAC_WRITE(sc, FFB_DAC_VALUE, eie); 1578 DAC_WRITE(sc, FFB_DAC_VALUE, eis); 1579 1580 FBC_WRITE(sc, FFB_FBC_FBCFG0, fbcfg0); 1581 1582 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_TGC); 1583 DAC_WRITE(sc, FFB_DAC_VALUE, tgc); 1584 DPRINTF(("new tgc: %08x\n", tgc)); 1585 1586 *hres = mode->hdisplay; 1587 *vres = mode->vdisplay; 1588 1589 printf("%s: video mode set to %d x %d @ %dHz\n", 1590 device_xname(sc->sc_dev), 1591 mode->hdisplay, mode->vdisplay, 1592 DIVIDE(DIVIDE(mode->dot_clock * 1000, 1593 mode->htotal), mode->vtotal)); 1594 1595 return 1; 1596 } 1597
Indexes created Fri Sep 26 20:09:58 GMT 2025