ffb.c revision 1.55
1 /* $NetBSD: ffb.c,v 1.55 2013/10/09 17:21:39 macallan Exp $ */ 2 /* $OpenBSD: creator.c,v 1.20 2002/07/30 19:48:15 jason Exp $ */ 3 4 /* 5 * Copyright (c) 2002 Jason L. Wright (jason (at) thought.net) 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Jason L. Wright 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 25 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 26 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 27 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 30 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 31 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32 * POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: ffb.c,v 1.55 2013/10/09 17:21:39 macallan Exp $"); 37 38 #include <sys/types.h> 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/kernel.h> 42 #include <sys/device.h> 43 #include <sys/conf.h> 44 #include <sys/ioctl.h> 45 #include <sys/malloc.h> 46 #include <sys/mman.h> 47 48 #include <sys/bus.h> 49 #include <machine/autoconf.h> 50 #include <machine/openfirm.h> 51 #include <machine/vmparam.h> 52 53 #include <dev/wscons/wsconsio.h> 54 #include <dev/sun/fbio.h> 55 #include <dev/sun/fbvar.h> 56 57 #include <dev/wsfont/wsfont.h> 58 #include <dev/wscons/wsdisplay_vconsvar.h> 59 60 #include <prop/proplib.h> 61 62 #include <dev/i2c/i2cvar.h> 63 #include <dev/i2c/i2c_bitbang.h> 64 #include <dev/i2c/ddcvar.h> 65 66 #include <sparc64/dev/ffbreg.h> 67 #include <sparc64/dev/ffbvar.h> 68 69 #include "opt_wsdisplay_compat.h" 70 #include "opt_ffb.h" 71 72 #ifndef WS_DEFAULT_BG 73 /* Sun -> background should be white */ 74 #define WS_DEFAULT_BG 0xf 75 #endif 76 77 #ifdef FFB_SYNC 78 #define SYNC ffb_ras_wait(sc) 79 #else 80 #define SYNC 81 #endif 82 83 /* Debugging */ 84 #if !defined FFB_DEBUG 85 #define FFB_DEBUG 0 86 #endif 87 #define DPRINTF(x) if (ffb_debug) printf x 88 /* Patchable */ 89 extern int ffb_debug; 90 #if FFB_DEBUG > 0 91 int ffb_debug = 1; 92 #else 93 int ffb_debug = 0; 94 #endif 95 96 extern struct cfdriver ffb_cd; 97 98 struct wsscreen_descr ffb_stdscreen = { 99 "sunffb", 100 0, 0, /* will be filled in -- XXX shouldn't, it's global. */ 101 0, 102 0, 0, 103 WSSCREEN_REVERSE | WSSCREEN_WSCOLORS, 104 NULL /* modecookie */ 105 }; 106 107 const struct wsscreen_descr *ffb_scrlist[] = { 108 &ffb_stdscreen, 109 /* XXX other formats? */ 110 }; 111 112 struct wsscreen_list ffb_screenlist = { 113 sizeof(ffb_scrlist) / sizeof(struct wsscreen_descr *), 114 ffb_scrlist 115 }; 116 117 static struct vcons_screen ffb_console_screen; 118 119 int ffb_ioctl(void *, void *, u_long, void *, int, struct lwp *); 120 static int ffb_blank(struct ffb_softc *, u_long, u_int *); 121 paddr_t ffb_mmap(void *, void *, off_t, int); 122 void ffb_ras_fifo_wait(struct ffb_softc *, int); 123 void ffb_ras_wait(struct ffb_softc *); 124 void ffb_ras_init(struct ffb_softc *); 125 void ffb_ras_copyrows(void *, int, int, int); 126 void ffb_ras_erasecols(void *, int, int, int, long int); 127 void ffb_ras_eraserows(void *, int, int, long int); 128 void ffb_ras_do_cursor(struct rasops_info *); 129 void ffb_ras_fill(struct ffb_softc *); 130 void ffb_ras_invert(struct ffb_softc *); 131 static void ffb_ras_setfg(struct ffb_softc *, int32_t); 132 static void ffb_ras_setbg(struct ffb_softc *, int32_t); 133 134 void ffb_clearscreen(struct ffb_softc *); 135 int ffb_load_font(void *, void *, struct wsdisplay_font *); 136 void ffb_init_screen(void *, struct vcons_screen *, int, 137 long *); 138 int ffb_allocattr(void *, int, int, int, long *); 139 void ffb_putchar_mono(void *, int, int, u_int, long); 140 void ffb_putchar_aa(void *, int, int, u_int, long); 141 void ffb_cursor(void *, int, int, int); 142 143 /* frame buffer generic driver */ 144 static void ffbfb_unblank(device_t); 145 dev_type_open(ffbfb_open); 146 dev_type_close(ffbfb_close); 147 dev_type_ioctl(ffbfb_ioctl); 148 dev_type_mmap(ffbfb_mmap); 149 150 static struct fbdriver ffb_fbdriver = { 151 ffbfb_unblank, ffbfb_open, ffbfb_close, ffbfb_ioctl, nopoll, 152 ffbfb_mmap, nokqfilter 153 }; 154 155 struct wsdisplay_accessops ffb_accessops = { 156 .ioctl = ffb_ioctl, 157 .mmap = ffb_mmap, 158 }; 159 160 /* I2C glue */ 161 static int ffb_i2c_acquire_bus(void *, int); 162 static void ffb_i2c_release_bus(void *, int); 163 static int ffb_i2c_send_start(void *, int); 164 static int ffb_i2c_send_stop(void *, int); 165 static int ffb_i2c_initiate_xfer(void *, i2c_addr_t, int); 166 static int ffb_i2c_read_byte(void *, uint8_t *, int); 167 static int ffb_i2c_write_byte(void *, uint8_t, int); 168 169 /* I2C bitbang glue */ 170 static void ffb_i2cbb_set_bits(void *, uint32_t); 171 static void ffb_i2cbb_set_dir(void *, uint32_t); 172 static uint32_t ffb_i2cbb_read(void *); 173 174 static const struct i2c_bitbang_ops ffb_i2cbb_ops = { 175 ffb_i2cbb_set_bits, 176 ffb_i2cbb_set_dir, 177 ffb_i2cbb_read, 178 { 179 FFB_DAC_CFG_MPDATA_SDA, 180 FFB_DAC_CFG_MPDATA_SCL, 181 0, 182 0 183 } 184 }; 185 186 void ffb_attach_i2c(struct ffb_softc *); 187 188 /* Video mode setting */ 189 int ffb_tgc_disable(struct ffb_softc *); 190 void ffb_get_pclk(int, uint32_t *, int *); 191 int ffb_set_vmode(struct ffb_softc *, struct videomode *, int, int *, int *); 192 193 194 void 195 ffb_attach(device_t self) 196 { 197 struct ffb_softc *sc = device_private(self); 198 struct wsemuldisplaydev_attach_args waa; 199 struct rasops_info *ri; 200 long defattr; 201 const char *model, *out_dev; 202 int btype; 203 uint32_t dac; 204 int maxrow; 205 u_int blank = WSDISPLAYIO_VIDEO_ON; 206 char buf[6+1]; 207 int i, try_edid; 208 prop_data_t data; 209 210 printf(":"); 211 212 if (sc->sc_type == FFB_CREATOR) { 213 btype = prom_getpropint(sc->sc_node, "board_type", 0); 214 if ((btype & 7) == 3) 215 printf(" Creator3D"); 216 else 217 printf(" Creator"); 218 } else { 219 printf(" Elite3D"); 220 btype = 0; 221 } 222 223 model = prom_getpropstring(sc->sc_node, "model"); 224 if (model == NULL || strlen(model) == 0) 225 model = "unknown"; 226 227 sc->sc_depth = 24; 228 sc->sc_linebytes = 8192; 229 /* We might alter these during EDID mode setting */ 230 sc->sc_height = prom_getpropint(sc->sc_node, "height", 0); 231 sc->sc_width = prom_getpropint(sc->sc_node, "width", 0); 232 233 sc->sc_locked = 0; 234 sc->sc_mode = WSDISPLAYIO_MODE_EMUL; 235 236 maxrow = (prom_getoption("screen-#rows", buf, sizeof buf) != 0) 237 ? strtoul(buf, NULL, 10) 238 : 34; 239 240 /* collect DAC version, as Elite3D cursor enable bit is reversed */ 241 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_DEVID); 242 dac = DAC_READ(sc, FFB_DAC_VALUE); 243 sc->sc_dacrev = (dac >> 28) & 0xf; 244 245 if (sc->sc_type == FFB_AFB) { 246 sc->sc_dacrev = 10; 247 sc->sc_needredraw = 0; 248 } else { 249 /* see what kind of DAC we have */ 250 int pnum = (dac & 0x0ffff000) >> 12; 251 if (pnum == 0x236e) { 252 sc->sc_needredraw = 0; 253 } else { 254 sc->sc_needredraw = 1; 255 } 256 } 257 printf(", model %s, dac %u\n", model, sc->sc_dacrev); 258 if (sc->sc_needredraw) 259 printf("%s: found old DAC, enabling redraw on unblank\n", 260 device_xname(sc->sc_dev)); 261 262 /* Check if a console resolution "<device>:r<res>" is set. */ 263 if (sc->sc_console) { 264 out_dev = prom_getpropstring(sc->sc_node, "output_device"); 265 if (out_dev != NULL && strlen(out_dev) != 0 && 266 strstr(out_dev, ":r") != NULL) 267 try_edid = 0; 268 else 269 try_edid = 1; 270 } else 271 try_edid = 1; 272 273 #if FFB_DEBUG > 0 274 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_TGC); 275 printf("tgc: %08x\n", DAC_READ(sc, FFB_DAC_VALUE)); 276 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_DAC_CTRL); 277 printf("dcl: %08x\n", DAC_READ(sc, FFB_DAC_VALUE)); 278 #endif 279 ffb_attach_i2c(sc); 280 281 /* Need to set asynchronous blank during DDC write/read */ 282 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_USR_CTRL); 283 dac = DAC_READ(sc, FFB_DAC_VALUE); 284 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_USR_CTRL); 285 DAC_WRITE(sc, FFB_DAC_VALUE, dac | FFB_DAC_USR_CTRL_BLANK); 286 287 /* Some monitors don't respond first time */ 288 i = 0; 289 while (sc->sc_edid_data[1] == 0 && i++ < 3) 290 ddc_read_edid(&sc->sc_i2c, sc->sc_edid_data, EDID_DATA_LEN); 291 292 /* Remove asynchronous blank */ 293 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_USR_CTRL); 294 DAC_WRITE(sc, FFB_DAC_VALUE, dac); 295 296 if (edid_parse(&sc->sc_edid_data[0], &sc->sc_edid_info) != -1) { 297 sort_modes(sc->sc_edid_info.edid_modes, 298 &sc->sc_edid_info.edid_preferred_mode, 299 sc->sc_edid_info.edid_nmodes); 300 DPRINTF(("%s: EDID data:\n ", device_xname(sc->sc_dev))); 301 for (i = 0; i < EDID_DATA_LEN; i++) { 302 if (i && !(i % 32)) 303 DPRINTF(("\n ")); 304 if (i && !(i % 4)) 305 DPRINTF((" ")); 306 DPRINTF(("%02x", sc->sc_edid_data[i])); 307 } 308 DPRINTF(("\n")); 309 if (ffb_debug) 310 edid_print(&sc->sc_edid_info); 311 312 data = prop_data_create_data(sc->sc_edid_data, EDID_DATA_LEN); 313 prop_dictionary_set(device_properties(self), "EDID", data); 314 prop_object_release(data); 315 316 if (try_edid) 317 for (i = 0; i < sc->sc_edid_info.edid_nmodes; i++) { 318 if (ffb_set_vmode(sc, 319 &(sc->sc_edid_info.edid_modes[i]), btype, 320 &(sc->sc_width), &(sc->sc_height))) 321 break; 322 } 323 } else { 324 DPRINTF(("%s: No EDID data.\n", device_xname(sc->sc_dev))); 325 } 326 327 ffb_ras_init(sc); 328 329 ffb_blank(sc, WSDISPLAYIO_SVIDEO, &blank); 330 331 sc->sc_accel = ((device_cfdata(sc->sc_dev)->cf_flags & 332 FFB_CFFLAG_NOACCEL) == 0); 333 334 wsfont_init(); 335 336 vcons_init(&sc->vd, sc, &ffb_stdscreen, &ffb_accessops); 337 sc->vd.init_screen = ffb_init_screen; 338 ri = &ffb_console_screen.scr_ri; 339 340 /* we mess with ffb_console_screen only once */ 341 if (sc->sc_console) { 342 vcons_init_screen(&sc->vd, &ffb_console_screen, 1, &defattr); 343 SCREEN_VISIBLE((&ffb_console_screen)); 344 /* 345 * XXX we shouldn't use a global variable for the console 346 * screen 347 */ 348 sc->vd.active = &ffb_console_screen; 349 ffb_console_screen.scr_flags = VCONS_SCREEN_IS_STATIC; 350 } else { 351 if (ffb_console_screen.scr_ri.ri_rows == 0) { 352 /* do some minimal setup to avoid weirdnesses later */ 353 vcons_init_screen(&sc->vd, &ffb_console_screen, 1, &defattr); 354 } else 355 (*ri->ri_ops.allocattr)(ri, 0, 0, 0, &defattr); 356 } 357 358 ffb_stdscreen.nrows = ri->ri_rows; 359 ffb_stdscreen.ncols = ri->ri_cols; 360 ffb_stdscreen.textops = &ri->ri_ops; 361 ffb_stdscreen.capabilities = ri->ri_caps; 362 363 sc->sc_fb.fb_driver = &ffb_fbdriver; 364 sc->sc_fb.fb_type.fb_cmsize = 0; 365 sc->sc_fb.fb_type.fb_size = maxrow * sc->sc_linebytes; 366 sc->sc_fb.fb_type.fb_type = FBTYPE_CREATOR; 367 sc->sc_fb.fb_type.fb_width = sc->sc_width; 368 sc->sc_fb.fb_type.fb_depth = sc->sc_depth; 369 sc->sc_fb.fb_type.fb_height = sc->sc_height; 370 sc->sc_fb.fb_device = sc->sc_dev; 371 fb_attach(&sc->sc_fb, sc->sc_console); 372 373 ffb_clearscreen(sc); 374 375 if (sc->sc_console) { 376 wsdisplay_cnattach(&ffb_stdscreen, ri, 0, 0, defattr); 377 vcons_replay_msgbuf(&ffb_console_screen); 378 } 379 380 waa.console = sc->sc_console; 381 waa.scrdata = &ffb_screenlist; 382 waa.accessops = &ffb_accessops; 383 waa.accesscookie = &sc->vd; 384 config_found(sc->sc_dev, &waa, wsemuldisplaydevprint); 385 } 386 387 void 388 ffb_attach_i2c(struct ffb_softc *sc) 389 { 390 391 /* Fill in the i2c tag */ 392 sc->sc_i2c.ic_cookie = sc; 393 sc->sc_i2c.ic_acquire_bus = ffb_i2c_acquire_bus; 394 sc->sc_i2c.ic_release_bus = ffb_i2c_release_bus; 395 sc->sc_i2c.ic_send_start = ffb_i2c_send_start; 396 sc->sc_i2c.ic_send_stop = ffb_i2c_send_stop; 397 sc->sc_i2c.ic_initiate_xfer = ffb_i2c_initiate_xfer; 398 sc->sc_i2c.ic_read_byte = ffb_i2c_read_byte; 399 sc->sc_i2c.ic_write_byte = ffb_i2c_write_byte; 400 sc->sc_i2c.ic_exec = NULL; 401 } 402 403 int 404 ffb_ioctl(void *v, void *vs, u_long cmd, void *data, int flags, struct lwp *l) 405 { 406 struct vcons_data *vd = v; 407 struct ffb_softc *sc = vd->cookie; 408 struct wsdisplay_fbinfo *wdf; 409 struct vcons_screen *ms = vd->active; 410 411 DPRINTF(("ffb_ioctl: %s cmd _IO%s%s('%c', %lu)\n", 412 device_xname(sc->sc_dev), 413 (cmd & IOC_IN) ? "W" : "", (cmd & IOC_OUT) ? "R" : "", 414 (char)IOCGROUP(cmd), cmd & 0xff)); 415 416 switch (cmd) { 417 case FBIOGTYPE: 418 *(struct fbtype *)data = sc->sc_fb.fb_type; 419 break; 420 case FBIOGATTR: 421 #define fba ((struct fbgattr *)data) 422 fba->real_type = sc->sc_fb.fb_type.fb_type; 423 fba->owner = 0; /* XXX ??? */ 424 fba->fbtype = sc->sc_fb.fb_type; 425 fba->sattr.flags = 0; 426 fba->sattr.emu_type = sc->sc_fb.fb_type.fb_type; 427 fba->sattr.dev_specific[0] = -1; 428 fba->emu_types[0] = sc->sc_fb.fb_type.fb_type; 429 fba->emu_types[1] = -1; 430 #undef fba 431 break; 432 433 case FBIOGETCMAP: 434 case FBIOPUTCMAP: 435 return EIO; 436 437 case FBIOGVIDEO: 438 case FBIOSVIDEO: 439 return ffb_blank(sc, cmd == FBIOGVIDEO? 440 WSDISPLAYIO_GVIDEO : WSDISPLAYIO_SVIDEO, 441 (u_int *)data); 442 break; 443 case FBIOGCURSOR: 444 case FBIOSCURSOR: 445 /* the console driver is not using the hardware cursor */ 446 break; 447 case FBIOGCURPOS: 448 printf("%s: FBIOGCURPOS not implemented\n", 449 device_xname(sc->sc_dev)); 450 return EIO; 451 case FBIOSCURPOS: 452 printf("%s: FBIOSCURPOS not implemented\n", 453 device_xname(sc->sc_dev)); 454 return EIO; 455 case FBIOGCURMAX: 456 printf("%s: FBIOGCURMAX not implemented\n", 457 device_xname(sc->sc_dev)); 458 return EIO; 459 460 case WSDISPLAYIO_GTYPE: 461 *(u_int *)data = WSDISPLAY_TYPE_SUNFFB; 462 break; 463 case WSDISPLAYIO_SMODE: 464 { 465 if (sc->sc_mode != *(u_int *)data) { 466 sc->sc_mode = *(u_int *)data; 467 if ((sc->sc_mode == WSDISPLAYIO_MODE_EMUL) && 468 (sc->sc_locked == 0)) { 469 ffb_ras_init(sc); 470 vcons_redraw_screen(ms); 471 } 472 } 473 } 474 break; 475 case WSDISPLAYIO_GINFO: 476 wdf = (void *)data; 477 wdf->height = sc->sc_height; 478 wdf->width = sc->sc_width; 479 wdf->depth = 32; 480 wdf->cmsize = 256; /* XXX */ 481 break; 482 #ifdef WSDISPLAYIO_LINEBYTES 483 case WSDISPLAYIO_LINEBYTES: 484 *(u_int *)data = sc->sc_linebytes; 485 break; 486 #endif 487 case WSDISPLAYIO_GETCMAP: 488 break;/* XXX */ 489 490 case WSDISPLAYIO_PUTCMAP: 491 break;/* XXX */ 492 493 case WSDISPLAYIO_SVIDEO: 494 case WSDISPLAYIO_GVIDEO: 495 return(ffb_blank(sc, cmd, (u_int *)data)); 496 break; 497 498 case WSDISPLAYIO_GCURPOS: 499 case WSDISPLAYIO_SCURPOS: 500 case WSDISPLAYIO_GCURMAX: 501 case WSDISPLAYIO_GCURSOR: 502 case WSDISPLAYIO_SCURSOR: 503 return EIO; /* not supported yet */ 504 break; 505 506 case WSDISPLAYIO_GET_EDID: { 507 struct wsdisplayio_edid_info *d = data; 508 return wsdisplayio_get_edid(sc->sc_dev, d); 509 } 510 511 case WSDISPLAYIO_GET_FBINFO: { 512 struct wsdisplayio_fbinfo *fbi = data; 513 return wsdisplayio_get_fbinfo(&ms->scr_ri, fbi); 514 } 515 516 default: 517 return EPASSTHROUGH; 518 } 519 520 return (0); 521 } 522 523 /* blank/unblank the screen */ 524 static int 525 ffb_blank(struct ffb_softc *sc, u_long cmd, u_int *data) 526 { 527 struct vcons_screen *ms = sc->vd.active; 528 u_int val; 529 530 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_TGC); 531 val = DAC_READ(sc, FFB_DAC_VALUE); 532 533 switch (cmd) { 534 case WSDISPLAYIO_GVIDEO: 535 *data = val & 1; 536 return(0); 537 break; 538 case WSDISPLAYIO_SVIDEO: 539 if (*data == WSDISPLAYIO_VIDEO_OFF) 540 val &= ~1; 541 else if (*data == WSDISPLAYIO_VIDEO_ON) 542 val |= 1; 543 else 544 return(EINVAL); 545 break; 546 default: 547 return(EINVAL); 548 } 549 550 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_TGC); 551 DAC_WRITE(sc, FFB_DAC_VALUE, val); 552 553 if ((val & 1) && sc->sc_needredraw) { 554 if (ms != NULL) { 555 if ((sc->sc_mode == WSDISPLAYIO_MODE_EMUL) && 556 (sc->sc_locked == 0)) { 557 ffb_ras_init(sc); 558 vcons_redraw_screen(ms); 559 } 560 } 561 } 562 563 return(0); 564 } 565 566 paddr_t 567 ffb_mmap(void *vsc, void *vs, off_t off, int prot) 568 { 569 struct vcons_data *vd = vsc; 570 struct ffb_softc *sc = vd->cookie; 571 int i; 572 573 switch (sc->sc_mode) { 574 case WSDISPLAYIO_MODE_MAPPED: 575 for (i = 0; i < sc->sc_nreg; i++) { 576 /* Before this set? */ 577 if (off < sc->sc_addrs[i]) 578 continue; 579 /* After this set? */ 580 if (off >= (sc->sc_addrs[i] + sc->sc_sizes[i])) 581 continue; 582 583 return (bus_space_mmap(sc->sc_bt, sc->sc_addrs[i], 584 off - sc->sc_addrs[i], prot, BUS_SPACE_MAP_LINEAR)); 585 } 586 break; 587 #ifdef WSDISPLAYIO_MODE_DUMBFB 588 case WSDISPLAYIO_MODE_DUMBFB: 589 if (sc->sc_nreg < FFB_REG_DFB24) 590 break; 591 if (off >= 0 && off < sc->sc_sizes[FFB_REG_DFB24]) 592 return (bus_space_mmap(sc->sc_bt, 593 sc->sc_addrs[FFB_REG_DFB24], off, prot, 594 BUS_SPACE_MAP_LINEAR)); 595 break; 596 #endif 597 } 598 return (-1); 599 } 600 601 void 602 ffb_ras_fifo_wait(struct ffb_softc *sc, int n) 603 { 604 int32_t cache = sc->sc_fifo_cache; 605 606 if (cache < n) { 607 do { 608 cache = FBC_READ(sc, FFB_FBC_UCSR); 609 cache = (cache & FBC_UCSR_FIFO_MASK) - 8; 610 } while (cache < n); 611 } 612 sc->sc_fifo_cache = cache - n; 613 } 614 615 void 616 ffb_ras_wait(struct ffb_softc *sc) 617 { 618 uint32_t ucsr, r; 619 620 while (1) { 621 ucsr = FBC_READ(sc, FFB_FBC_UCSR); 622 if ((ucsr & (FBC_UCSR_FB_BUSY|FBC_UCSR_RP_BUSY)) == 0) 623 break; 624 r = ucsr & (FBC_UCSR_READ_ERR | FBC_UCSR_FIFO_OVFL); 625 if (r != 0) 626 FBC_WRITE(sc, FFB_FBC_UCSR, r); 627 } 628 } 629 630 void 631 ffb_ras_init(struct ffb_softc *sc) 632 { 633 uint32_t fbc; 634 635 if (sc->sc_width > 1280) { 636 DPRINTF(("ffb_ras_init: high resolution.\n")); 637 fbc = FFB_FBC_WM_COMBINED | FFB_FBC_WE_FORCEON | 638 FFB_FBC_ZE_OFF | FFB_FBC_YE_OFF | FFB_FBC_XE_ON; 639 } else { 640 DPRINTF(("ffb_ras_init: standard resolution.\n")); 641 fbc = FFB_FBC_XE_OFF; 642 } 643 ffb_ras_fifo_wait(sc, 11); 644 DPRINTF(("WID: %08x\n", FBC_READ(sc, FFB_FBC_WID))); 645 FBC_WRITE(sc, FFB_FBC_WID, 0x0); 646 FBC_WRITE(sc, FFB_FBC_PPC, 647 FBC_PPC_VCE_DIS | FBC_PPC_TBE_OPAQUE | FBC_PPC_ACE_DIS | 648 FBC_PPC_APE_DIS | FBC_PPC_DCE_DIS | FBC_PPC_CS_CONST | 649 FBC_PPC_ABE_DIS | FBC_PPC_XS_WID); 650 651 fbc |= FFB_FBC_WB_A | FFB_FBC_RB_A | FFB_FBC_SB_BOTH | 652 FFB_FBC_RGBE_MASK; 653 DPRINTF(("%s: fbc is %08x\n", __func__, fbc)); 654 FBC_WRITE(sc, FFB_FBC_FBC, fbc); 655 FBC_WRITE(sc, FFB_FBC_ROP, FBC_ROP_NEW); 656 FBC_WRITE(sc, FFB_FBC_DRAWOP, FBC_DRAWOP_RECTANGLE); 657 FBC_WRITE(sc, FFB_FBC_PMASK, 0xffffffff); 658 FBC_WRITE(sc, FFB_FBC_FONTINC, 0x10000); 659 sc->sc_fg_cache = 0; 660 FBC_WRITE(sc, FFB_FBC_FG, sc->sc_fg_cache); 661 FBC_WRITE(sc, FFB_FBC_BLENDC, FFB_BLENDC_FORCE_ONE | 662 FFB_BLENDC_DF_ONE_M_A | 663 FFB_BLENDC_SF_A); 664 FBC_WRITE(sc, FFB_FBC_BLENDC1, 0); 665 FBC_WRITE(sc, FFB_FBC_BLENDC2, 0); 666 ffb_ras_wait(sc); 667 } 668 669 void 670 ffb_ras_eraserows(void *cookie, int row, int n, long attr) 671 { 672 struct rasops_info *ri = cookie; 673 struct vcons_screen *scr = ri->ri_hw; 674 struct ffb_softc *sc = scr->scr_cookie; 675 676 if (row < 0) { 677 n += row; 678 row = 0; 679 } 680 if (row + n > ri->ri_rows) 681 n = ri->ri_rows - row; 682 if (n <= 0) 683 return; 684 685 ffb_ras_fill(sc); 686 ffb_ras_setfg(sc, ri->ri_devcmap[(attr >> 16) & 0xf]); 687 ffb_ras_fifo_wait(sc, 4); 688 if ((n == ri->ri_rows) && (ri->ri_flg & RI_FULLCLEAR)) { 689 FBC_WRITE(sc, FFB_FBC_BY, 0); 690 FBC_WRITE(sc, FFB_FBC_BX, 0); 691 FBC_WRITE(sc, FFB_FBC_BH, ri->ri_height); 692 FBC_WRITE(sc, FFB_FBC_BW, ri->ri_width); 693 } else { 694 row *= ri->ri_font->fontheight; 695 FBC_WRITE(sc, FFB_FBC_BY, ri->ri_yorigin + row); 696 FBC_WRITE(sc, FFB_FBC_BX, ri->ri_xorigin); 697 FBC_WRITE(sc, FFB_FBC_BH, n * ri->ri_font->fontheight); 698 FBC_WRITE(sc, FFB_FBC_BW, ri->ri_emuwidth); 699 } 700 SYNC; 701 } 702 703 void 704 ffb_ras_erasecols(void *cookie, int row, int col, int n, long attr) 705 { 706 struct rasops_info *ri = cookie; 707 struct vcons_screen *scr = ri->ri_hw; 708 struct ffb_softc *sc = scr->scr_cookie; 709 710 if ((row < 0) || (row >= ri->ri_rows)) 711 return; 712 if (col < 0) { 713 n += col; 714 col = 0; 715 } 716 if (col + n > ri->ri_cols) 717 n = ri->ri_cols - col; 718 if (n <= 0) 719 return; 720 n *= ri->ri_font->fontwidth; 721 col *= ri->ri_font->fontwidth; 722 row *= ri->ri_font->fontheight; 723 724 ffb_ras_fill(sc); 725 ffb_ras_setfg(sc, ri->ri_devcmap[(attr >> 16) & 0xf]); 726 ffb_ras_fifo_wait(sc, 4); 727 FBC_WRITE(sc, FFB_FBC_BY, ri->ri_yorigin + row); 728 FBC_WRITE(sc, FFB_FBC_BX, ri->ri_xorigin + col); 729 FBC_WRITE(sc, FFB_FBC_BH, ri->ri_font->fontheight); 730 FBC_WRITE(sc, FFB_FBC_BW, n - 1); 731 SYNC; 732 } 733 734 void 735 ffb_ras_fill(struct ffb_softc *sc) 736 { 737 ffb_ras_fifo_wait(sc, 3); 738 FBC_WRITE(sc, FFB_FBC_PPC, 739 FBC_PPC_VCE_DIS | FBC_PPC_TBE_OPAQUE | FBC_PPC_ACE_DIS | 740 FBC_PPC_APE_DIS | FBC_PPC_DCE_DIS | FBC_PPC_CS_CONST | 741 FBC_PPC_ABE_DIS | FBC_PPC_XS_WID); 742 FBC_WRITE(sc, FFB_FBC_ROP, FBC_ROP_NEW); 743 FBC_WRITE(sc, FFB_FBC_DRAWOP, FBC_DRAWOP_RECTANGLE); 744 SYNC; 745 } 746 747 void 748 ffb_ras_invert(struct ffb_softc *sc) 749 { 750 ffb_ras_fifo_wait(sc, 3); 751 FBC_WRITE(sc, FFB_FBC_PPC, 752 FBC_PPC_VCE_DIS | FBC_PPC_TBE_OPAQUE | FBC_PPC_ACE_DIS | 753 FBC_PPC_APE_DIS | FBC_PPC_DCE_DIS | FBC_PPC_CS_CONST | 754 FBC_PPC_ABE_DIS | FBC_PPC_XS_WID); 755 FBC_WRITE(sc, FFB_FBC_ROP, FBC_ROP_INVERT); 756 FBC_WRITE(sc, FFB_FBC_DRAWOP, FBC_DRAWOP_RECTANGLE); 757 SYNC; 758 } 759 760 void 761 ffb_ras_copyrows(void *cookie, int src, int dst, int n) 762 { 763 struct rasops_info *ri = cookie; 764 struct vcons_screen *scr = ri->ri_hw; 765 struct ffb_softc *sc = scr->scr_cookie; 766 767 if (dst == src) 768 return; 769 if (src < 0) { 770 n += src; 771 src = 0; 772 } 773 if ((src + n) > ri->ri_rows) 774 n = ri->ri_rows - src; 775 if (dst < 0) { 776 n += dst; 777 dst = 0; 778 } 779 if ((dst + n) > ri->ri_rows) 780 n = ri->ri_rows - dst; 781 if (n <= 0) 782 return; 783 n *= ri->ri_font->fontheight; 784 src *= ri->ri_font->fontheight; 785 dst *= ri->ri_font->fontheight; 786 787 ffb_ras_fifo_wait(sc, 9); 788 FBC_WRITE(sc, FFB_FBC_PPC, 789 FBC_PPC_VCE_DIS | FBC_PPC_TBE_OPAQUE | FBC_PPC_ACE_DIS | 790 FBC_PPC_APE_DIS | FBC_PPC_DCE_DIS | FBC_PPC_CS_CONST | 791 FBC_PPC_ABE_DIS | FBC_PPC_XS_WID); 792 FBC_WRITE(sc, FFB_FBC_ROP, FBC_ROP_OLD | (FBC_ROP_OLD << 8)); 793 FBC_WRITE(sc, FFB_FBC_DRAWOP, FBC_DRAWOP_VSCROLL); 794 FBC_WRITE(sc, FFB_FBC_BY, ri->ri_yorigin + src); 795 FBC_WRITE(sc, FFB_FBC_BX, ri->ri_xorigin); 796 FBC_WRITE(sc, FFB_FBC_DY, ri->ri_yorigin + dst); 797 FBC_WRITE(sc, FFB_FBC_DX, ri->ri_xorigin); 798 FBC_WRITE(sc, FFB_FBC_BH, n); 799 FBC_WRITE(sc, FFB_FBC_BW, ri->ri_emuwidth); 800 SYNC; 801 } 802 803 static void 804 ffb_ras_setfg(struct ffb_softc *sc, int32_t fg) 805 { 806 ffb_ras_fifo_wait(sc, 1); 807 if (fg == sc->sc_fg_cache) 808 return; 809 sc->sc_fg_cache = fg; 810 FBC_WRITE(sc, FFB_FBC_FG, fg); 811 SYNC; 812 } 813 814 static void 815 ffb_ras_setbg(struct ffb_softc *sc, int32_t bg) 816 { 817 ffb_ras_fifo_wait(sc, 1); 818 if (bg == sc->sc_bg_cache) 819 return; 820 sc->sc_bg_cache = bg; 821 FBC_WRITE(sc, FFB_FBC_BG, bg); 822 SYNC; 823 } 824 825 /* frame buffer generic driver support functions */ 826 static void 827 ffbfb_unblank(device_t dev) 828 { 829 struct ffb_softc *sc = device_private(dev); 830 struct vcons_screen *ms = sc->vd.active; 831 u_int on = 1; 832 int redraw = 0; 833 834 ffb_ras_init(sc); 835 if (sc->sc_locked) { 836 sc->sc_locked = 0; 837 redraw = 1; 838 } 839 840 ffb_blank(sc, WSDISPLAYIO_SVIDEO, &on); 841 #if 0 842 if ((sc->vd.active != &ffb_console_screen) && 843 (ffb_console_screen.scr_flags & VCONS_SCREEN_IS_STATIC)) { 844 /* 845 * force-switch to the console screen. 846 * Caveat: the higher layer will think we're still on the 847 * other screen 848 */ 849 850 SCREEN_INVISIBLE(sc->vd.active); 851 sc->vd.active = &ffb_console_screen; 852 SCREEN_VISIBLE(sc->vd.active); 853 ms = sc->vd.active; 854 redraw = 1; 855 } 856 #endif 857 if (redraw) { 858 vcons_redraw_screen(ms); 859 } 860 } 861 862 int 863 ffbfb_open(dev_t dev, int flags, int mode, struct lwp *l) 864 { 865 struct ffb_softc *sc; 866 867 sc = device_lookup_private(&ffb_cd, minor(dev)); 868 if (sc == NULL) 869 return ENXIO; 870 871 sc->sc_locked = 1; 872 return 0; 873 } 874 875 int 876 ffbfb_close(dev_t dev, int flags, int mode, struct lwp *l) 877 { 878 struct ffb_softc *sc = device_lookup_private(&ffb_cd, minor(dev)); 879 struct vcons_screen *ms = sc->vd.active; 880 881 sc->sc_locked = 0; 882 if (ms != NULL) { 883 if ((sc->sc_mode == WSDISPLAYIO_MODE_EMUL) && 884 (sc->sc_locked == 0)) { 885 ffb_ras_init(sc); 886 vcons_redraw_screen(ms); 887 } 888 } 889 return 0; 890 } 891 892 int 893 ffbfb_ioctl(dev_t dev, u_long cmd, void *data, int flags, struct lwp *l) 894 { 895 struct ffb_softc *sc = device_lookup_private(&ffb_cd, minor(dev)); 896 897 return ffb_ioctl(&sc->vd, NULL, cmd, data, flags, l); 898 } 899 900 paddr_t 901 ffbfb_mmap(dev_t dev, off_t off, int prot) 902 { 903 struct ffb_softc *sc = device_lookup_private(&ffb_cd, minor(dev)); 904 uint64_t size; 905 int i, reg; 906 off_t o; 907 908 /* 909 * off is a magic cookie (see xfree86/drivers/sunffb/ffb.h), 910 * which we map to an index into the "reg" property, and use 911 * our copy of the firmware data as arguments for the real 912 * mapping. 913 */ 914 static struct { unsigned long voff; int reg; } map[] = { 915 { 0x00000000, FFB_REG_SFB8R }, 916 { 0x00400000, FFB_REG_SFB8G }, 917 { 0x00800000, FFB_REG_SFB8B }, 918 { 0x00c00000, FFB_REG_SFB8X }, 919 { 0x01000000, FFB_REG_SFB32 }, 920 { 0x02000000, FFB_REG_SFB64 }, 921 { 0x04000000, FFB_REG_FBC }, 922 { 0x04004000, FFB_REG_DFB8R }, 923 { 0x04404000, FFB_REG_DFB8G }, 924 { 0x04804000, FFB_REG_DFB8B }, 925 { 0x04c04000, FFB_REG_DFB8X }, 926 { 0x05004000, FFB_REG_DFB24 }, 927 { 0x06004000, FFB_REG_DFB32 }, 928 { 0x07004000, FFB_REG_DFB422A }, 929 { 0x0bc06000, FFB_REG_DAC }, 930 { 0x0bc08000, FFB_REG_PROM }, 931 { 0x0bc18000, 0 } 932 }; 933 934 /* special value "FFB_EXP_VOFF" - not backed by any "reg" entry */ 935 if (off == 0x0bc18000) 936 return bus_space_mmap(sc->sc_bt, sc->sc_addrs[FFB_REG_PROM], 937 0x00200000, prot, BUS_SPACE_MAP_LINEAR); 938 939 /* 940 * FFB_VOFF_FBC_KREGS - used by afbinit to upload firmware. We should 941 * probably mmap them only on afb boards 942 */ 943 if ((off >= 0x0bc04000) && (off < 0x0bc06000)) 944 return bus_space_mmap(sc->sc_bt, sc->sc_addrs[FFB_REG_PROM], 945 0x00610000 + (off - 0x0bc04000), prot, 946 BUS_SPACE_MAP_LINEAR); 947 948 #define NELEMS(arr) (sizeof(arr)/sizeof((arr)[0])) 949 950 /* the map is ordered by voff */ 951 for (i = 0; i < NELEMS(map)-1; i++) { 952 reg = map[i].reg; 953 /* the number of entries in reg seems to vary */ 954 if (reg < sc->sc_nreg) { 955 size = min((map[i + 1].voff - map[i].voff), 956 sc->sc_sizes[reg]); 957 if ((off >= map[i].voff) && 958 (off < (map[i].voff + size))) { 959 o = off - map[i].voff; 960 return bus_space_mmap(sc->sc_bt, 961 sc->sc_addrs[reg], o, prot, 962 BUS_SPACE_MAP_LINEAR); 963 } 964 } 965 } 966 967 return -1; 968 } 969 970 void 971 ffb_clearscreen(struct ffb_softc *sc) 972 { 973 struct rasops_info *ri = &ffb_console_screen.scr_ri; 974 ffb_ras_fill(sc); 975 ffb_ras_setfg(sc, ri->ri_devcmap[WS_DEFAULT_BG]); 976 ffb_ras_fifo_wait(sc, 4); 977 FBC_WRITE(sc, FFB_FBC_BY, 0); 978 FBC_WRITE(sc, FFB_FBC_BX, 0); 979 FBC_WRITE(sc, FFB_FBC_BH, sc->sc_height); 980 FBC_WRITE(sc, FFB_FBC_BW, sc->sc_width); 981 } 982 983 void 984 ffb_cursor(void *cookie, int on, int row, int col) 985 { 986 struct rasops_info *ri = cookie; 987 struct vcons_screen *scr; 988 struct ffb_softc *sc; 989 int x, y, wi, he; 990 991 if (cookie != NULL) { 992 scr = ri->ri_hw; 993 sc = scr->scr_cookie; 994 995 wi = ri->ri_font->fontwidth; 996 he = ri->ri_font->fontheight; 997 998 if (sc->sc_mode == WSDISPLAYIO_MODE_EMUL) { 999 1000 if (ri->ri_flg & RI_CURSOR) { 1001 1002 /* remove cursor */ 1003 x = ri->ri_ccol * wi + ri->ri_xorigin; 1004 y = ri->ri_crow * he + ri->ri_yorigin; 1005 1006 ffb_ras_invert(sc); 1007 ffb_ras_fifo_wait(sc, 4); 1008 FBC_WRITE(sc, FFB_FBC_BY, y); 1009 FBC_WRITE(sc, FFB_FBC_BX, x); 1010 FBC_WRITE(sc, FFB_FBC_BH, he); 1011 FBC_WRITE(sc, FFB_FBC_BW, wi); 1012 1013 ri->ri_flg &= ~RI_CURSOR; 1014 } 1015 ri->ri_crow = row; 1016 ri->ri_ccol = col; 1017 if (on) 1018 { 1019 x = ri->ri_ccol * wi + ri->ri_xorigin; 1020 y = ri->ri_crow * he + ri->ri_yorigin; 1021 1022 ffb_ras_invert(sc); 1023 ffb_ras_fifo_wait(sc, 4); 1024 FBC_WRITE(sc, FFB_FBC_BY, y); 1025 FBC_WRITE(sc, FFB_FBC_BX, x); 1026 FBC_WRITE(sc, FFB_FBC_BH, he); 1027 FBC_WRITE(sc, FFB_FBC_BW, wi); 1028 1029 ri->ri_flg |= RI_CURSOR; 1030 } 1031 } else { 1032 ri->ri_crow = row; 1033 ri->ri_ccol = col; 1034 ri->ri_flg &= ~RI_CURSOR; 1035 } 1036 } 1037 } 1038 1039 /* mono bitmap font */ 1040 void 1041 ffb_putchar_mono(void *cookie, int row, int col, u_int c, long attr) 1042 { 1043 struct rasops_info *ri = cookie; 1044 struct vcons_screen *scr = ri->ri_hw; 1045 struct wsdisplay_font *font = PICK_FONT(ri, c); 1046 struct ffb_softc *sc = scr->scr_cookie; 1047 void *data; 1048 uint32_t fg, bg; 1049 int i; 1050 int x, y, wi, he; 1051 1052 if (sc->sc_mode != WSDISPLAYIO_MODE_EMUL) 1053 return; 1054 1055 wi = font->fontwidth; 1056 he = font->fontheight; 1057 1058 if (!CHAR_IN_FONT(c, font)) 1059 return; 1060 1061 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 1062 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 1063 x = ri->ri_xorigin + col * wi; 1064 y = ri->ri_yorigin + row * he; 1065 1066 data = WSFONT_GLYPH(c, font); 1067 1068 ffb_ras_setbg(sc, bg); 1069 ffb_ras_setfg(sc, fg); 1070 ffb_ras_fifo_wait(sc, 4); 1071 FBC_WRITE(sc, FFB_FBC_ROP, FBC_ROP_NEW); 1072 FBC_WRITE(sc, FFB_FBC_FONTXY, (y << 16) | x); 1073 FBC_WRITE(sc, FFB_FBC_FONTW, wi); 1074 FBC_WRITE(sc, FFB_FBC_PPC, 1075 FBC_PPC_VCE_DIS | FBC_PPC_TBE_OPAQUE | FBC_PPC_ACE_DIS | 1076 FBC_PPC_APE_DIS | FBC_PPC_DCE_DIS | FBC_PPC_CS_CONST | 1077 FBC_PPC_ABE_DIS | FBC_PPC_XS_WID); 1078 1079 switch (font->stride) { 1080 case 1: { 1081 uint8_t *data8 = data; 1082 uint32_t reg; 1083 for (i = 0; i < he; i++) { 1084 reg = *data8; 1085 FBC_WRITE(sc, FFB_FBC_FONT, reg << 24); 1086 data8++; 1087 } 1088 break; 1089 } 1090 case 2: { 1091 uint16_t *data16 = data; 1092 uint32_t reg; 1093 for (i = 0; i < he; i++) { 1094 reg = *data16; 1095 FBC_WRITE(sc, FFB_FBC_FONT, reg << 16); 1096 data16++; 1097 } 1098 break; 1099 } 1100 } 1101 } 1102 1103 /* alpha font */ 1104 void 1105 ffb_putchar_aa(void *cookie, int row, int col, u_int c, long attr) 1106 { 1107 struct rasops_info *ri = cookie; 1108 struct vcons_screen *scr = ri->ri_hw; 1109 struct wsdisplay_font *font = PICK_FONT(ri, c); 1110 struct ffb_softc *sc = scr->scr_cookie; 1111 volatile uint32_t *dest, *ddest; 1112 uint8_t *data8; 1113 uint32_t fg, bg; 1114 int i; 1115 int x, y, wi, he; 1116 uint32_t alpha = 0x80; 1117 int j; 1118 1119 if (sc->sc_mode != WSDISPLAYIO_MODE_EMUL) 1120 return; 1121 1122 wi = font->fontwidth; 1123 he = font->fontheight; 1124 1125 if (!CHAR_IN_FONT(c, font)) 1126 return; 1127 1128 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 1129 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 1130 x = ri->ri_xorigin + col * wi; 1131 y = ri->ri_yorigin + row * he; 1132 1133 data8 = WSFONT_GLYPH(c, font); 1134 1135 /* first we erase the background */ 1136 ffb_ras_fill(sc); 1137 ffb_ras_setfg(sc, bg); 1138 ffb_ras_fifo_wait(sc, 4); 1139 FBC_WRITE(sc, FFB_FBC_BY, y); 1140 FBC_WRITE(sc, FFB_FBC_BX, x); 1141 FBC_WRITE(sc, FFB_FBC_BH, he); 1142 FBC_WRITE(sc, FFB_FBC_BW, wi); 1143 1144 /* if we draw a space we're done */ 1145 if (c == ' ') return; 1146 1147 /* now enable alpha blending */ 1148 ffb_ras_setfg(sc, fg); 1149 ffb_ras_fifo_wait(sc, 2); 1150 FBC_WRITE(sc, FFB_FBC_ROP, FBC_ROP_NEW); 1151 1152 FBC_WRITE(sc, FFB_FBC_PPC, 1153 FBC_PPC_VCE_DIS | FBC_PPC_TBE_OPAQUE | FBC_PPC_ACE_DIS | 1154 FBC_PPC_APE_DIS | FBC_PPC_DCE_DIS | FBC_PPC_CS_CONST | 1155 FBC_PPC_ABE_ENA | FBC_PPC_XS_VAR); 1156 /* 1157 * we have to wait for both the rectangle drawing op above and the 1158 * FFB_FBC_PPC write to finish before mucking around in the SFB aperture 1159 */ 1160 ffb_ras_wait(sc); 1161 1162 /* ... and draw the character */ 1163 dest = sc->sc_sfb32 + (y << 11) + x; 1164 for (i = 0; i < he; i++) { 1165 ddest = dest; 1166 for (j = 0; j < wi; j++) { 1167 alpha = *data8; 1168 /* 1169 * We set the colour source to constant above so we only 1170 * have to write the alpha channel here and the colour 1171 * comes from the FG register. It would be nice if we 1172 * could just use the SFB8X aperture and memcpy() the 1173 * alpha map line by line but for some strange reason 1174 * that will take colour info from the framebuffer even 1175 * if we set the FBC_PPC_CS_CONST bit above. 1176 */ 1177 *ddest = alpha << 24; 1178 data8++; 1179 ddest++; 1180 } 1181 dest += 2048; 1182 } 1183 } 1184 1185 int 1186 ffb_allocattr(void *cookie, int fg, int bg, int flags, long *attrp) 1187 { 1188 if ((fg == 0) && (bg == 0)) 1189 { 1190 fg = WS_DEFAULT_FG; 1191 bg = WS_DEFAULT_BG; 1192 } 1193 if (flags & WSATTR_REVERSE) { 1194 *attrp = (bg & 0xff) << 24 | (fg & 0xff) << 16 | 1195 (flags & 0xff); 1196 } else 1197 *attrp = (fg & 0xff) << 24 | (bg & 0xff) << 16 | 1198 (flags & 0xff); 1199 return 0; 1200 } 1201 1202 void 1203 ffb_init_screen(void *cookie, struct vcons_screen *scr, 1204 int existing, long *defattr) 1205 { 1206 struct ffb_softc *sc = cookie; 1207 struct rasops_info *ri = &scr->scr_ri; 1208 1209 ri->ri_depth = 32; 1210 ri->ri_width = sc->sc_width; 1211 ri->ri_height = sc->sc_height; 1212 ri->ri_stride = sc->sc_linebytes; 1213 ri->ri_flg = RI_CENTER | RI_ENABLE_ALPHA; 1214 1215 /* 1216 * we can't accelerate copycols() so instead of falling back to 1217 * software use vcons' putchar() based implementation 1218 */ 1219 scr->scr_flags |= VCONS_NO_COPYCOLS; 1220 #ifdef VCONS_DRAW_INTR 1221 scr->scr_flags |= VCONS_DONT_READ; 1222 #endif 1223 DPRINTF(("ffb_init_screen: addr: %08lx\n",(ulong)ri->ri_bits)); 1224 1225 /* explicitly request BGR in case the default changes */ 1226 ri->ri_rnum = 8; 1227 ri->ri_gnum = 8; 1228 ri->ri_bnum = 8; 1229 ri->ri_rpos = 0; 1230 ri->ri_gpos = 8; 1231 ri->ri_bpos = 16; 1232 1233 rasops_init(ri, 0, 0); 1234 ri->ri_caps = WSSCREEN_WSCOLORS; 1235 rasops_reconfig(ri, sc->sc_height / ri->ri_font->fontheight, 1236 sc->sc_width / ri->ri_font->fontwidth); 1237 1238 /* enable acceleration */ 1239 ri->ri_ops.copyrows = ffb_ras_copyrows; 1240 ri->ri_ops.eraserows = ffb_ras_eraserows; 1241 ri->ri_ops.erasecols = ffb_ras_erasecols; 1242 ri->ri_ops.cursor = ffb_cursor; 1243 ri->ri_ops.allocattr = ffb_allocattr; 1244 if (FONT_IS_ALPHA(ri->ri_font)) { 1245 ri->ri_ops.putchar = ffb_putchar_aa; 1246 } else 1247 ri->ri_ops.putchar = ffb_putchar_mono; 1248 } 1249 1250 /* I2C bitbanging */ 1251 static void ffb_i2cbb_set_bits(void *cookie, uint32_t bits) 1252 { 1253 struct ffb_softc *sc = cookie; 1254 1255 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_CFG_MPDATA); 1256 DAC_WRITE(sc, FFB_DAC_VALUE, bits); 1257 } 1258 1259 static void ffb_i2cbb_set_dir(void *cookie, uint32_t dir) 1260 { 1261 /* Nothing to do */ 1262 } 1263 1264 static uint32_t ffb_i2cbb_read(void *cookie) 1265 { 1266 struct ffb_softc *sc = cookie; 1267 uint32_t bits; 1268 1269 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_CFG_MPSENSE); 1270 bits = DAC_READ(sc, FFB_DAC_VALUE); 1271 1272 return bits; 1273 } 1274 1275 /* higher level I2C stuff */ 1276 static int 1277 ffb_i2c_acquire_bus(void *cookie, int flags) 1278 { 1279 /* private bus */ 1280 return (0); 1281 } 1282 1283 static void 1284 ffb_i2c_release_bus(void *cookie, int flags) 1285 { 1286 /* private bus */ 1287 } 1288 1289 static int 1290 ffb_i2c_send_start(void *cookie, int flags) 1291 { 1292 return (i2c_bitbang_send_start(cookie, flags, &ffb_i2cbb_ops)); 1293 } 1294 1295 static int 1296 ffb_i2c_send_stop(void *cookie, int flags) 1297 { 1298 1299 return (i2c_bitbang_send_stop(cookie, flags, &ffb_i2cbb_ops)); 1300 } 1301 1302 static int 1303 ffb_i2c_initiate_xfer(void *cookie, i2c_addr_t addr, int flags) 1304 { 1305 /* 1306 * for some reason i2c_bitbang_initiate_xfer left-shifts 1307 * the I2C-address and then sets the direction bit 1308 */ 1309 return (i2c_bitbang_initiate_xfer(cookie, addr, flags, 1310 &ffb_i2cbb_ops)); 1311 } 1312 1313 static int 1314 ffb_i2c_read_byte(void *cookie, uint8_t *valp, int flags) 1315 { 1316 return (i2c_bitbang_read_byte(cookie, valp, flags, &ffb_i2cbb_ops)); 1317 } 1318 1319 static int 1320 ffb_i2c_write_byte(void *cookie, uint8_t val, int flags) 1321 { 1322 return (i2c_bitbang_write_byte(cookie, val, flags, &ffb_i2cbb_ops)); 1323 } 1324 1325 1326 #define TVC_READ_LIMIT 100000 1327 int 1328 ffb_tgc_disable(struct ffb_softc *sc) 1329 { 1330 int i; 1331 1332 /* Is the timing generator disabled? */ 1333 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_TGC); 1334 if (!(DAC_READ(sc, FFB_DAC_VALUE) & FFB_DAC_TGC_TIMING_ENABLE)) 1335 return 1; 1336 1337 /* If not, disable it when the vertical counter reaches 0 */ 1338 for (i = 0; i < TVC_READ_LIMIT; i++) { 1339 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_TVC); 1340 if (!DAC_READ(sc, FFB_DAC_VALUE)) { 1341 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_TGC); 1342 DAC_WRITE(sc, FFB_DAC_VALUE, 0); 1343 return 1; 1344 } 1345 } 1346 return 0; 1347 } 1348 1349 /* 1350 * PLL Control Register values: 1351 * M)ultiplier = bits 0:6 + 1 1352 * D)ivisor = bits 7:10 + 1 1353 * P)ost divisor = bits 11:13 (000 = 1, 001 = 2, 010 = 4, 011 = 8) 1354 * Frequency = 13.5 * M / D / P 1355 */ 1356 #define FFB_PLL_FREQ 13500000 1357 void 1358 ffb_get_pclk(int request, uint32_t *pll, int *diff) 1359 { 1360 int m, d, p, f, hex = 0, curdiff; 1361 1362 *diff = 100000000; 1363 1364 for (m = 32; m <= 80; m++) { 1365 for (d = 4; d <= 11; d++) { 1366 for (p = 1; p <= 8; p = p << 1) { 1367 switch (p) { 1368 case 1: 1369 hex = 0x4000 + (d << 7) + m; 1370 break; 1371 case 2: 1372 hex = 0x4800 + (d << 7) + m; 1373 break; 1374 case 4: 1375 hex = 0x5000 + (d << 7) + m; 1376 break; 1377 case 8: 1378 hex = 0x6000 + (d << 7) + m; 1379 break; 1380 } 1381 f = 13500000 * m / d / p; 1382 if (f == request) { 1383 *diff = 0; 1384 *pll = hex; 1385 return; 1386 } else { 1387 curdiff = abs(request - f); 1388 if (curdiff < *diff) { 1389 *diff = curdiff; 1390 *pll = hex; 1391 } 1392 } 1393 } 1394 } 1395 } 1396 } 1397 1398 /* 1399 * Details of the FFB RAMDAC are contained in the Brooktree BT497/498 1400 * and in the Connexant BT497A/498A documentation. 1401 * 1402 * VESA timings to FFB register conversion: 1403 * If interleave = 4/2:1 then x = 2, if interleave = 8/2:1 then x = 4 1404 * VBE = VBS - vres = (sync pulse - 1) + back porch 1405 * VBS = VSS - front porch = (sync pulse - 1) + back porch + vres 1406 * VSE = sync pulse - 1 1407 * VSS = (sync pulse - 1) + back porch + vres + front porch 1408 * HRE = HSS - HSE - 1 1409 * HBE = (sync pulse + back porch) / x - 1 1410 * HBS = (sync pulse + back porch + hres) / x - 1 1411 * HSE = sync pulse / x - 1 1412 * HSS = (sync pulse + back porch + hres + front porch) / x - 1 1413 * HCE = HBS - 4 1414 * HCS = HBE - 4 1415 * EPE = EIE = EIS = 0 (for all non-interlaced modes) 1416 * 1417 * Note, that 8/2:1 Single Buffered Interleaving is only supported by the 1418 * double-buffered FFB (Creator3D), and at higher resolutions than 1280x1024 1419 * 1420 * Note, that the timing generator should be disabled and re-enabled when the 1421 * the timing parameter registers are being programmed. Stopping the timing 1422 * generator should only be done when the vertical counter is zero. 1423 */ 1424 #define DIVIDE(x,y) (((x) + ((y) / 2)) / (y)) 1425 int 1426 ffb_set_vmode(struct ffb_softc *sc, struct videomode *mode, int btype, 1427 int *hres, int *vres) 1428 { 1429 int diff; 1430 uint32_t fp, sp, bp, x; 1431 uint32_t pll, pfc, ucl, dcl, tgc; 1432 uint32_t vbe, vbs, vse, vss, hre, hbe, hbs, hse, hss, hce, hcs; 1433 uint32_t epe, eie, eis; 1434 uint32_t fbcfg0; 1435 1436 DPRINTF(("ffb_set_vmode: %dx%d@%d", mode->hdisplay, mode->vdisplay, 1437 DIVIDE(DIVIDE(mode->dot_clock * 1000, 1438 mode->htotal), mode->vtotal))); 1439 DPRINTF((" (%d %d %d %d %d %d %d", 1440 mode->dot_clock, mode->hsync_start, mode->hsync_end, mode->htotal, 1441 mode->vsync_start, mode->vsync_end, mode->vtotal)); 1442 DPRINTF((" %s%sH %s%sV)\n", 1443 mode->flags & VID_PHSYNC ? "+" : "", 1444 mode->flags & VID_NHSYNC ? "-" : "", 1445 mode->flags & VID_PVSYNC ? "+" : "", 1446 mode->flags & VID_NVSYNC ? "-" : "")); 1447 1448 /* We don't handle interlaced or doublescan (yet) */ 1449 if ((mode->flags & VID_INTERLACE) || (mode->flags & VID_DBLSCAN)) 1450 return 0; 1451 1452 /* Only Creator3D can be set to > 1280x1024 */ 1453 if(((sc->sc_type == FFB_CREATOR && !((btype & 7) == 3)) || 1454 sc->sc_type == FFB_AFB) 1455 && (mode->hdisplay > 1280 || mode->vdisplay > 1024)) 1456 return 0; 1457 /* Creator3D can be set to <= 1920x1360 */ 1458 if (mode->hdisplay > 1920 || mode->vdisplay > 1360) 1459 return 0; 1460 1461 /* 1462 * Look for a matching pixel clock and set PLL Control. 1463 * XXX: 640x480@60 is 25175000 in modelines but 25125000 in the 1464 * FFB PROM, and the closest match to 25175000 (0x4da9/25159090) 1465 * does not work. So, use the PROM value instead. 1466 */ 1467 if (mode->hdisplay == 640 && mode->vdisplay == 480 && 1468 mode->dot_clock == 25175) { 1469 DPRINTF(("ffb_set_vmode: 640x480@60: adjusted dot clock\n")); 1470 mode->dot_clock = 25125; 1471 } 1472 ffb_get_pclk(mode->dot_clock * 1000, &pll, &diff); 1473 if (diff > 250000) 1474 return 0; 1475 1476 /* Pixel Format Control, User Control and FBC Configuration. */ 1477 if (mode->hdisplay > 1280) { 1478 pfc = FFB_DAC_PIX_FMT_821; 1479 ucl = FFB_DAC_USR_CTRL_OVERLAY | FFB_DAC_USR_CTRL_WMODE_C; 1480 x = 4; 1481 fbcfg0 = FBC_READ(sc, FFB_FBC_FBCFG0) | FBC_CFG0_DOUBLE_BUF; 1482 } else { 1483 pfc = FFB_DAC_PIX_FMT_421; 1484 /* Only Creator3D and Elite3D can have double-buffer */ 1485 if ((sc->sc_type == FFB_CREATOR && !((btype & 7) == 3))) 1486 ucl = 0; 1487 else 1488 ucl = FFB_DAC_USR_CTRL_DOUBLE; 1489 ucl |= (FFB_DAC_USR_CTRL_OVERLAY | FFB_DAC_USR_CTRL_WMODE_S8); 1490 x = 2; 1491 fbcfg0 = FBC_READ(sc, FFB_FBC_FBCFG0) | FBC_CFG0_SINGLE_BUF; 1492 } 1493 1494 /* DAC Control and Timing Generator Control */ 1495 if (mode->flags & VID_PVSYNC) 1496 dcl = FFB_DAC_DAC_CTRL_POS_VSYNC; 1497 else 1498 dcl = 0; 1499 tgc = 0; 1500 #define EDID_VID_INP sc->sc_edid_info.edid_video_input 1501 if ((EDID_VID_INP & EDID_VIDEO_INPUT_COMPOSITE_SYNC)) { 1502 dcl |= FFB_DAC_DAC_CTRL_VSYNC_DIS; 1503 tgc = FFB_DAC_TGC_EQUAL_DISABLE; 1504 } else { 1505 dcl |= FFB_DAC_DAC_CTRL_SYNC_G; 1506 if (EDID_VID_INP & EDID_VIDEO_INPUT_SEPARATE_SYNCS) 1507 tgc |= FFB_DAC_TGC_VSYNC_DISABLE; 1508 else 1509 tgc = FFB_DAC_TGC_EQUAL_DISABLE; 1510 } 1511 if (EDID_VID_INP & EDID_VIDEO_INPUT_BLANK_TO_BLACK) 1512 dcl |= FFB_DAC_DAC_CTRL_PED_ENABLE; 1513 tgc |= (FFB_DAC_TGC_VIDEO_ENABLE | FFB_DAC_TGC_TIMING_ENABLE | 1514 FFB_DAC_TGC_MASTER_ENABLE); 1515 1516 /* Vertical timing */ 1517 fp = mode->vsync_start - mode->vdisplay; 1518 sp = mode->vsync_end - mode->vsync_start; 1519 bp = mode->vtotal - mode->vsync_end; 1520 1521 vbe = sp - 1 + bp; 1522 vbs = sp - 1 + bp + mode->vdisplay; 1523 vse = sp - 1; 1524 vss = sp - 1 + bp + mode->vdisplay + fp; 1525 1526 /* Horizontal timing */ 1527 fp = mode->hsync_start - mode->hdisplay; 1528 sp = mode->hsync_end - mode->hsync_start; 1529 bp = mode->htotal - mode->hsync_end; 1530 1531 hbe = (sp + bp) / x - 1; 1532 hbs = (sp + bp + mode->hdisplay) / x - 1; 1533 hse = sp / x - 1; 1534 hss = (sp + bp + mode->hdisplay + fp) / x -1; 1535 hre = hss - hse - 1; 1536 hce = hbs - 4; 1537 hcs = hbe - 4; 1538 1539 /* Equalisation (interlaced modes) */ 1540 epe = 0; 1541 eie = 0; 1542 eis = 0; 1543 1544 DPRINTF(("ffb_set_vmode: 0x%04x 0x%04x 0x%04x 0x%04x 0x%04x\n", 1545 pll, pfc, ucl, dcl, tgc)); 1546 DPRINTF(("\t0x%04x 0x%04x 0x%04x 0x%04x\n", vbe, vbs, vse, vss)); 1547 DPRINTF(("\t0x%04x 0x%04x 0x%04x 0x%04x 0x%04x 0x%04x 0x%04x\n", 1548 hre, hbe, hbs, hse, hss, hce, hcs)); 1549 DPRINTF(("\t0x%04x 0x%04x 0x%04x\n", epe, eie, eis)); 1550 1551 if (!ffb_tgc_disable(sc)) { 1552 DPRINTF(("ffb_set_vmode: failed to disable TGC register\n")); 1553 return 0; 1554 } 1555 1556 /* 1557 * Program the mode registers. 1558 * Program the timing generator last, as that re-enables output. 1559 * Note, that a read to/write from a register increments the 1560 * register address to the next register automatically. 1561 */ 1562 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_PLL_CTRL); 1563 DAC_WRITE(sc, FFB_DAC_VALUE, pll); 1564 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_PIX_FMT); 1565 DAC_WRITE(sc, FFB_DAC_VALUE, pfc); 1566 DAC_WRITE(sc, FFB_DAC_VALUE, ucl); 1567 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_DAC_CTRL); 1568 DAC_WRITE(sc, FFB_DAC_VALUE, dcl); 1569 1570 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_VBE); 1571 DAC_WRITE(sc, FFB_DAC_VALUE, vbe); 1572 DAC_WRITE(sc, FFB_DAC_VALUE, vbs); 1573 DAC_WRITE(sc, FFB_DAC_VALUE, vse); 1574 DAC_WRITE(sc, FFB_DAC_VALUE, vss); 1575 1576 DAC_WRITE(sc, FFB_DAC_VALUE, hre); 1577 DAC_WRITE(sc, FFB_DAC_VALUE, hbe); 1578 DAC_WRITE(sc, FFB_DAC_VALUE, hbs); 1579 DAC_WRITE(sc, FFB_DAC_VALUE, hse); 1580 DAC_WRITE(sc, FFB_DAC_VALUE, hss); 1581 DAC_WRITE(sc, FFB_DAC_VALUE, hce); 1582 DAC_WRITE(sc, FFB_DAC_VALUE, hcs); 1583 1584 DAC_WRITE(sc, FFB_DAC_VALUE, epe); 1585 DAC_WRITE(sc, FFB_DAC_VALUE, eie); 1586 DAC_WRITE(sc, FFB_DAC_VALUE, eis); 1587 1588 FBC_WRITE(sc, FFB_FBC_FBCFG0, fbcfg0); 1589 1590 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_TGC); 1591 DAC_WRITE(sc, FFB_DAC_VALUE, tgc); 1592 DPRINTF(("new tgc: %08x\n", tgc)); 1593 1594 *hres = mode->hdisplay; 1595 *vres = mode->vdisplay; 1596 1597 printf("%s: video mode set to %d x %d @ %dHz\n", 1598 device_xname(sc->sc_dev), 1599 mode->hdisplay, mode->vdisplay, 1600 DIVIDE(DIVIDE(mode->dot_clock * 1000, 1601 mode->htotal), mode->vtotal)); 1602 1603 return 1; 1604 } 1605
Indexes created Thu Sep 25 16:09:42 GMT 2025