ffb.c revision 1.57.2.2
1 /* $NetBSD: ffb.c,v 1.57.2.2 2017/04/26 02:53:07 pgoyette Exp $ */ 2 /* $OpenBSD: creator.c,v 1.20 2002/07/30 19:48:15 jason Exp $ */ 3 4 /* 5 * Copyright (c) 2002 Jason L. Wright (jason (at) thought.net) 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Jason L. Wright 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 25 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 26 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 27 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 30 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 31 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32 * POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: ffb.c,v 1.57.2.2 2017/04/26 02:53:07 pgoyette Exp $"); 37 38 #include <sys/types.h> 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/kernel.h> 42 #include <sys/device.h> 43 #include <sys/conf.h> 44 #include <sys/ioctl.h> 45 #include <sys/malloc.h> 46 #include <sys/mman.h> 47 48 #include <sys/bus.h> 49 #include <machine/autoconf.h> 50 #include <machine/openfirm.h> 51 #include <machine/vmparam.h> 52 53 #include <dev/wscons/wsconsio.h> 54 #include <dev/sun/fbio.h> 55 #include <dev/sun/fbvar.h> 56 57 #include <dev/wsfont/wsfont.h> 58 #include <dev/wscons/wsdisplay_vconsvar.h> 59 60 #include <prop/proplib.h> 61 62 #include <dev/i2c/i2cvar.h> 63 #include <dev/i2c/i2c_bitbang.h> 64 #include <dev/i2c/ddcvar.h> 65 66 #include <sparc64/dev/ffbreg.h> 67 #include <sparc64/dev/ffbvar.h> 68 69 #include "opt_wsdisplay_compat.h" 70 #include "opt_ffb.h" 71 72 #ifndef WS_DEFAULT_BG 73 /* Sun -> background should be white */ 74 #define WS_DEFAULT_BG 0xf 75 #endif 76 77 #ifdef FFB_SYNC 78 #define SYNC ffb_ras_wait(sc) 79 #else 80 #define SYNC 81 #endif 82 83 /* Debugging */ 84 #if !defined FFB_DEBUG 85 #define FFB_DEBUG 0 86 #endif 87 #define DPRINTF(x) if (ffb_debug) printf x 88 /* Patchable */ 89 extern int ffb_debug; 90 #if FFB_DEBUG > 0 91 int ffb_debug = 1; 92 #else 93 int ffb_debug = 0; 94 #endif 95 96 extern struct cfdriver ffb_cd; 97 98 struct wsscreen_descr ffb_stdscreen = { 99 "sunffb", 100 0, 0, /* will be filled in -- XXX shouldn't, it's global. */ 101 0, 102 0, 0, 103 WSSCREEN_REVERSE | WSSCREEN_WSCOLORS, 104 NULL /* modecookie */ 105 }; 106 107 const struct wsscreen_descr *ffb_scrlist[] = { 108 &ffb_stdscreen, 109 /* XXX other formats? */ 110 }; 111 112 struct wsscreen_list ffb_screenlist = { 113 sizeof(ffb_scrlist) / sizeof(struct wsscreen_descr *), 114 ffb_scrlist 115 }; 116 117 static struct vcons_screen ffb_console_screen; 118 119 int ffb_ioctl(void *, void *, u_long, void *, int, struct lwp *); 120 static int ffb_blank(struct ffb_softc *, u_long, u_int *); 121 paddr_t ffb_mmap(void *, void *, off_t, int); 122 void ffb_ras_fifo_wait(struct ffb_softc *, int); 123 void ffb_ras_wait(struct ffb_softc *); 124 void ffb_ras_init(struct ffb_softc *); 125 void ffb_ras_copyrows(void *, int, int, int); 126 void ffb_ras_erasecols(void *, int, int, int, long int); 127 void ffb_ras_eraserows(void *, int, int, long int); 128 void ffb_ras_do_cursor(struct rasops_info *); 129 void ffb_ras_fill(struct ffb_softc *); 130 void ffb_ras_invert(struct ffb_softc *); 131 static void ffb_ras_setfg(struct ffb_softc *, int32_t); 132 static void ffb_ras_setbg(struct ffb_softc *, int32_t); 133 134 void ffb_clearscreen(struct ffb_softc *); 135 int ffb_load_font(void *, void *, struct wsdisplay_font *); 136 void ffb_init_screen(void *, struct vcons_screen *, int, 137 long *); 138 int ffb_allocattr(void *, int, int, int, long *); 139 void ffb_putchar_mono(void *, int, int, u_int, long); 140 void ffb_putchar_aa(void *, int, int, u_int, long); 141 void ffb_cursor(void *, int, int, int); 142 143 /* frame buffer generic driver */ 144 static void ffbfb_unblank(device_t); 145 dev_type_open(ffbfb_open); 146 dev_type_close(ffbfb_close); 147 dev_type_ioctl(ffbfb_ioctl); 148 dev_type_mmap(ffbfb_mmap); 149 150 static struct fbdriver ffb_fbdriver = { 151 ffbfb_unblank, ffbfb_open, ffbfb_close, ffbfb_ioctl, nopoll, 152 ffbfb_mmap, nokqfilter 153 }; 154 155 struct wsdisplay_accessops ffb_accessops = { 156 .ioctl = ffb_ioctl, 157 .mmap = ffb_mmap, 158 }; 159 160 /* I2C glue */ 161 static int ffb_i2c_acquire_bus(void *, int); 162 static void ffb_i2c_release_bus(void *, int); 163 static int ffb_i2c_send_start(void *, int); 164 static int ffb_i2c_send_stop(void *, int); 165 static int ffb_i2c_initiate_xfer(void *, i2c_addr_t, int); 166 static int ffb_i2c_read_byte(void *, uint8_t *, int); 167 static int ffb_i2c_write_byte(void *, uint8_t, int); 168 169 /* I2C bitbang glue */ 170 static void ffb_i2cbb_set_bits(void *, uint32_t); 171 static void ffb_i2cbb_set_dir(void *, uint32_t); 172 static uint32_t ffb_i2cbb_read(void *); 173 174 static const struct i2c_bitbang_ops ffb_i2cbb_ops = { 175 ffb_i2cbb_set_bits, 176 ffb_i2cbb_set_dir, 177 ffb_i2cbb_read, 178 { 179 FFB_DAC_CFG_MPDATA_SDA, 180 FFB_DAC_CFG_MPDATA_SCL, 181 0, 182 0 183 } 184 }; 185 186 void ffb_attach_i2c(struct ffb_softc *); 187 188 /* Video mode setting */ 189 int ffb_tgc_disable(struct ffb_softc *); 190 void ffb_get_pclk(int, uint32_t *, int *); 191 int ffb_set_vmode(struct ffb_softc *, struct videomode *, int, int *, int *); 192 193 194 void 195 ffb_attach(device_t self) 196 { 197 struct ffb_softc *sc = device_private(self); 198 struct wsemuldisplaydev_attach_args waa; 199 struct rasops_info *ri; 200 long defattr; 201 const char *model, *out_dev; 202 int btype; 203 uint32_t dac; 204 int maxrow; 205 u_int blank = WSDISPLAYIO_VIDEO_ON; 206 char buf[6+1]; 207 int i, try_edid; 208 prop_data_t data; 209 210 printf(":"); 211 212 if (sc->sc_type == FFB_CREATOR) { 213 btype = prom_getpropint(sc->sc_node, "board_type", 0); 214 if ((btype & 7) == 3) 215 printf(" Creator3D"); 216 else 217 printf(" Creator"); 218 } else { 219 printf(" Elite3D"); 220 btype = 0; 221 } 222 223 model = prom_getpropstring(sc->sc_node, "model"); 224 if (model == NULL || strlen(model) == 0) 225 model = "unknown"; 226 227 sc->sc_depth = 24; 228 sc->sc_linebytes = 8192; 229 /* We might alter these during EDID mode setting */ 230 sc->sc_height = prom_getpropint(sc->sc_node, "height", 0); 231 sc->sc_width = prom_getpropint(sc->sc_node, "width", 0); 232 233 sc->sc_locked = 0; 234 sc->sc_mode = WSDISPLAYIO_MODE_EMUL; 235 236 maxrow = (prom_getoption("screen-#rows", buf, sizeof buf) != 0) 237 ? strtoul(buf, NULL, 10) 238 : 34; 239 240 /* collect DAC version, as Elite3D cursor enable bit is reversed */ 241 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_DEVID); 242 dac = DAC_READ(sc, FFB_DAC_VALUE); 243 sc->sc_dacrev = (dac >> 28) & 0xf; 244 245 if (sc->sc_type == FFB_AFB) { 246 sc->sc_dacrev = 10; 247 sc->sc_needredraw = 0; 248 } else { 249 /* see what kind of DAC we have */ 250 int pnum = (dac & 0x0ffff000) >> 12; 251 if (pnum == 0x236e) { 252 sc->sc_needredraw = 0; 253 } else { 254 sc->sc_needredraw = 1; 255 } 256 } 257 printf(", model %s, dac %u\n", model, sc->sc_dacrev); 258 if (sc->sc_needredraw) 259 printf("%s: found old DAC, enabling redraw on unblank\n", 260 device_xname(sc->sc_dev)); 261 262 /* Check if a console resolution "<device>:r<res>" is set. */ 263 if (sc->sc_console) { 264 out_dev = prom_getpropstring(sc->sc_node, "output_device"); 265 if (out_dev != NULL && strlen(out_dev) != 0 && 266 strstr(out_dev, ":r") != NULL) 267 try_edid = 0; 268 else 269 try_edid = 1; 270 } else 271 try_edid = 1; 272 273 #if FFB_DEBUG > 0 274 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_TGC); 275 printf("tgc: %08x\n", DAC_READ(sc, FFB_DAC_VALUE)); 276 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_DAC_CTRL); 277 printf("dcl: %08x\n", DAC_READ(sc, FFB_DAC_VALUE)); 278 #endif 279 ffb_attach_i2c(sc); 280 281 /* Need to set asynchronous blank during DDC write/read */ 282 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_USR_CTRL); 283 dac = DAC_READ(sc, FFB_DAC_VALUE); 284 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_USR_CTRL); 285 DAC_WRITE(sc, FFB_DAC_VALUE, dac | FFB_DAC_USR_CTRL_BLANK); 286 287 /* Some monitors don't respond first time */ 288 i = 0; 289 while (sc->sc_edid_data[1] == 0 && i++ < 3) 290 ddc_read_edid(&sc->sc_i2c, sc->sc_edid_data, EDID_DATA_LEN); 291 292 /* Remove asynchronous blank */ 293 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_USR_CTRL); 294 DAC_WRITE(sc, FFB_DAC_VALUE, dac); 295 296 if (edid_parse(&sc->sc_edid_data[0], &sc->sc_edid_info) != -1) { 297 sort_modes(sc->sc_edid_info.edid_modes, 298 &sc->sc_edid_info.edid_preferred_mode, 299 sc->sc_edid_info.edid_nmodes); 300 DPRINTF(("%s: EDID data:\n ", device_xname(sc->sc_dev))); 301 for (i = 0; i < EDID_DATA_LEN; i++) { 302 if (i && !(i % 32)) 303 DPRINTF(("\n ")); 304 if (i && !(i % 4)) 305 DPRINTF((" ")); 306 DPRINTF(("%02x", sc->sc_edid_data[i])); 307 } 308 DPRINTF(("\n")); 309 if (ffb_debug) 310 edid_print(&sc->sc_edid_info); 311 312 data = prop_data_create_data(sc->sc_edid_data, EDID_DATA_LEN); 313 prop_dictionary_set(device_properties(self), "EDID", data); 314 prop_object_release(data); 315 316 if (try_edid) 317 for (i = 0; i < sc->sc_edid_info.edid_nmodes; i++) { 318 if (ffb_set_vmode(sc, 319 &(sc->sc_edid_info.edid_modes[i]), btype, 320 &(sc->sc_width), &(sc->sc_height))) 321 break; 322 } 323 } else { 324 DPRINTF(("%s: No EDID data.\n", device_xname(sc->sc_dev))); 325 } 326 327 ffb_ras_init(sc); 328 329 ffb_blank(sc, WSDISPLAYIO_SVIDEO, &blank); 330 331 sc->sc_accel = ((device_cfdata(sc->sc_dev)->cf_flags & 332 FFB_CFFLAG_NOACCEL) == 0); 333 334 wsfont_init(); 335 336 vcons_init(&sc->vd, sc, &ffb_stdscreen, &ffb_accessops); 337 sc->vd.init_screen = ffb_init_screen; 338 ri = &ffb_console_screen.scr_ri; 339 340 /* we mess with ffb_console_screen only once */ 341 if (sc->sc_console) { 342 vcons_init_screen(&sc->vd, &ffb_console_screen, 1, &defattr); 343 SCREEN_VISIBLE((&ffb_console_screen)); 344 /* 345 * XXX we shouldn't use a global variable for the console 346 * screen 347 */ 348 sc->vd.active = &ffb_console_screen; 349 ffb_console_screen.scr_flags = VCONS_SCREEN_IS_STATIC; 350 } else { 351 if (ffb_console_screen.scr_ri.ri_rows == 0) { 352 /* do some minimal setup to avoid weirdnesses later */ 353 vcons_init_screen(&sc->vd, &ffb_console_screen, 1, &defattr); 354 } else 355 (*ri->ri_ops.allocattr)(ri, 0, 0, 0, &defattr); 356 } 357 358 ffb_stdscreen.nrows = ri->ri_rows; 359 ffb_stdscreen.ncols = ri->ri_cols; 360 ffb_stdscreen.textops = &ri->ri_ops; 361 ffb_stdscreen.capabilities = ri->ri_caps; 362 363 sc->sc_fb.fb_driver = &ffb_fbdriver; 364 sc->sc_fb.fb_type.fb_cmsize = 0; 365 sc->sc_fb.fb_type.fb_size = maxrow * sc->sc_linebytes; 366 sc->sc_fb.fb_type.fb_type = FBTYPE_CREATOR; 367 sc->sc_fb.fb_type.fb_width = sc->sc_width; 368 sc->sc_fb.fb_type.fb_depth = sc->sc_depth; 369 sc->sc_fb.fb_type.fb_height = sc->sc_height; 370 sc->sc_fb.fb_device = sc->sc_dev; 371 fb_attach(&sc->sc_fb, sc->sc_console); 372 373 ffb_clearscreen(sc); 374 375 if (sc->sc_console) { 376 wsdisplay_cnattach(&ffb_stdscreen, ri, 0, 0, defattr); 377 vcons_replay_msgbuf(&ffb_console_screen); 378 } 379 380 waa.console = sc->sc_console; 381 waa.scrdata = &ffb_screenlist; 382 waa.accessops = &ffb_accessops; 383 waa.accesscookie = &sc->vd; 384 config_found(sc->sc_dev, &waa, wsemuldisplaydevprint); 385 } 386 387 void 388 ffb_attach_i2c(struct ffb_softc *sc) 389 { 390 391 /* Fill in the i2c tag */ 392 sc->sc_i2c.ic_cookie = sc; 393 sc->sc_i2c.ic_acquire_bus = ffb_i2c_acquire_bus; 394 sc->sc_i2c.ic_release_bus = ffb_i2c_release_bus; 395 sc->sc_i2c.ic_send_start = ffb_i2c_send_start; 396 sc->sc_i2c.ic_send_stop = ffb_i2c_send_stop; 397 sc->sc_i2c.ic_initiate_xfer = ffb_i2c_initiate_xfer; 398 sc->sc_i2c.ic_read_byte = ffb_i2c_read_byte; 399 sc->sc_i2c.ic_write_byte = ffb_i2c_write_byte; 400 sc->sc_i2c.ic_exec = NULL; 401 } 402 403 int 404 ffb_ioctl(void *v, void *vs, u_long cmd, void *data, int flags, struct lwp *l) 405 { 406 struct vcons_data *vd = v; 407 struct ffb_softc *sc = vd->cookie; 408 struct wsdisplay_fbinfo *wdf; 409 struct vcons_screen *ms = vd->active; 410 411 DPRINTF(("ffb_ioctl: %s cmd _IO%s%s('%c', %lu)\n", 412 device_xname(sc->sc_dev), 413 (cmd & IOC_IN) ? "W" : "", (cmd & IOC_OUT) ? "R" : "", 414 (char)IOCGROUP(cmd), cmd & 0xff)); 415 416 switch (cmd) { 417 case FBIOGTYPE: 418 *(struct fbtype *)data = sc->sc_fb.fb_type; 419 break; 420 case FBIOGATTR: 421 #define fba ((struct fbgattr *)data) 422 fba->real_type = sc->sc_fb.fb_type.fb_type; 423 fba->owner = 0; /* XXX ??? */ 424 fba->fbtype = sc->sc_fb.fb_type; 425 fba->sattr.flags = 0; 426 fba->sattr.emu_type = sc->sc_fb.fb_type.fb_type; 427 fba->sattr.dev_specific[0] = -1; 428 fba->emu_types[0] = sc->sc_fb.fb_type.fb_type; 429 fba->emu_types[1] = -1; 430 #undef fba 431 break; 432 433 case FBIOGETCMAP: 434 case FBIOPUTCMAP: 435 return EIO; 436 437 case FBIOGVIDEO: 438 case FBIOSVIDEO: 439 return ffb_blank(sc, cmd == FBIOGVIDEO? 440 WSDISPLAYIO_GVIDEO : WSDISPLAYIO_SVIDEO, 441 (u_int *)data); 442 break; 443 case FBIOGCURSOR: 444 case FBIOSCURSOR: 445 /* the console driver is not using the hardware cursor */ 446 break; 447 case FBIOGCURPOS: 448 printf("%s: FBIOGCURPOS not implemented\n", 449 device_xname(sc->sc_dev)); 450 return EIO; 451 case FBIOSCURPOS: 452 printf("%s: FBIOSCURPOS not implemented\n", 453 device_xname(sc->sc_dev)); 454 return EIO; 455 case FBIOGCURMAX: 456 printf("%s: FBIOGCURMAX not implemented\n", 457 device_xname(sc->sc_dev)); 458 return EIO; 459 460 case WSDISPLAYIO_GTYPE: 461 *(u_int *)data = WSDISPLAY_TYPE_SUNFFB; 462 break; 463 case WSDISPLAYIO_SMODE: 464 { 465 if (sc->sc_mode != *(u_int *)data) { 466 sc->sc_mode = *(u_int *)data; 467 if ((sc->sc_mode == WSDISPLAYIO_MODE_EMUL) && 468 (sc->sc_locked == 0)) { 469 ffb_ras_init(sc); 470 vcons_redraw_screen(ms); 471 } else { 472 ffb_ras_wait(sc); 473 } 474 } 475 } 476 break; 477 case WSDISPLAYIO_GINFO: 478 wdf = (void *)data; 479 wdf->height = sc->sc_height; 480 wdf->width = sc->sc_width; 481 wdf->depth = 32; 482 wdf->cmsize = 256; /* XXX */ 483 break; 484 #ifdef WSDISPLAYIO_LINEBYTES 485 case WSDISPLAYIO_LINEBYTES: 486 *(u_int *)data = sc->sc_linebytes; 487 break; 488 #endif 489 case WSDISPLAYIO_GETCMAP: 490 break;/* XXX */ 491 492 case WSDISPLAYIO_PUTCMAP: 493 break;/* XXX */ 494 495 case WSDISPLAYIO_SVIDEO: 496 case WSDISPLAYIO_GVIDEO: 497 return(ffb_blank(sc, cmd, (u_int *)data)); 498 break; 499 500 case WSDISPLAYIO_GCURPOS: 501 case WSDISPLAYIO_SCURPOS: 502 case WSDISPLAYIO_GCURMAX: 503 case WSDISPLAYIO_GCURSOR: 504 case WSDISPLAYIO_SCURSOR: 505 return EIO; /* not supported yet */ 506 break; 507 508 case WSDISPLAYIO_GET_EDID: { 509 struct wsdisplayio_edid_info *d = data; 510 return wsdisplayio_get_edid(sc->sc_dev, d); 511 } 512 513 case WSDISPLAYIO_GET_FBINFO: { 514 struct wsdisplayio_fbinfo *fbi = data; 515 return wsdisplayio_get_fbinfo(&ms->scr_ri, fbi); 516 } 517 518 default: 519 return EPASSTHROUGH; 520 } 521 522 return (0); 523 } 524 525 /* blank/unblank the screen */ 526 static int 527 ffb_blank(struct ffb_softc *sc, u_long cmd, u_int *data) 528 { 529 struct vcons_screen *ms = sc->vd.active; 530 u_int val; 531 532 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_TGC); 533 val = DAC_READ(sc, FFB_DAC_VALUE); 534 535 switch (cmd) { 536 case WSDISPLAYIO_GVIDEO: 537 *data = val & 1; 538 return(0); 539 break; 540 case WSDISPLAYIO_SVIDEO: 541 if (*data == WSDISPLAYIO_VIDEO_OFF) 542 val &= ~1; 543 else if (*data == WSDISPLAYIO_VIDEO_ON) 544 val |= 1; 545 else 546 return(EINVAL); 547 break; 548 default: 549 return(EINVAL); 550 } 551 552 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_TGC); 553 DAC_WRITE(sc, FFB_DAC_VALUE, val); 554 555 if ((val & 1) && sc->sc_needredraw) { 556 if (ms != NULL) { 557 if ((sc->sc_mode == WSDISPLAYIO_MODE_EMUL) && 558 (sc->sc_locked == 0)) { 559 ffb_ras_init(sc); 560 vcons_redraw_screen(ms); 561 } 562 } 563 } 564 565 return(0); 566 } 567 568 paddr_t 569 ffb_mmap(void *vsc, void *vs, off_t off, int prot) 570 { 571 struct vcons_data *vd = vsc; 572 struct ffb_softc *sc = vd->cookie; 573 int i; 574 575 switch (sc->sc_mode) { 576 case WSDISPLAYIO_MODE_MAPPED: 577 for (i = 0; i < sc->sc_nreg; i++) { 578 /* Before this set? */ 579 if (off < sc->sc_addrs[i]) 580 continue; 581 /* After this set? */ 582 if (off >= (sc->sc_addrs[i] + sc->sc_sizes[i])) 583 continue; 584 585 return (bus_space_mmap(sc->sc_bt, sc->sc_addrs[i], 586 off - sc->sc_addrs[i], prot, BUS_SPACE_MAP_LINEAR)); 587 } 588 break; 589 #ifdef WSDISPLAYIO_MODE_DUMBFB 590 case WSDISPLAYIO_MODE_DUMBFB: 591 if (sc->sc_nreg < FFB_REG_DFB24) 592 break; 593 if (off >= 0 && off < sc->sc_sizes[FFB_REG_DFB24]) 594 return (bus_space_mmap(sc->sc_bt, 595 sc->sc_addrs[FFB_REG_DFB24], off, prot, 596 BUS_SPACE_MAP_LINEAR | BUS_SPACE_MAP_PREFETCHABLE)); 597 break; 598 #endif 599 } 600 return (-1); 601 } 602 603 void 604 ffb_ras_fifo_wait(struct ffb_softc *sc, int n) 605 { 606 int32_t cache = sc->sc_fifo_cache; 607 608 if (cache < n) { 609 do { 610 cache = FBC_READ(sc, FFB_FBC_UCSR); 611 cache = (cache & FBC_UCSR_FIFO_MASK) - 8; 612 } while (cache < n); 613 } 614 sc->sc_fifo_cache = cache - n; 615 } 616 617 void 618 ffb_ras_wait(struct ffb_softc *sc) 619 { 620 uint32_t ucsr, r; 621 622 while (1) { 623 ucsr = FBC_READ(sc, FFB_FBC_UCSR); 624 if ((ucsr & (FBC_UCSR_FB_BUSY|FBC_UCSR_RP_BUSY)) == 0) 625 break; 626 r = ucsr & (FBC_UCSR_READ_ERR | FBC_UCSR_FIFO_OVFL); 627 if (r != 0) 628 FBC_WRITE(sc, FFB_FBC_UCSR, r); 629 } 630 } 631 632 void 633 ffb_ras_init(struct ffb_softc *sc) 634 { 635 uint32_t fbc; 636 637 if (sc->sc_width > 1280) { 638 DPRINTF(("ffb_ras_init: high resolution.\n")); 639 fbc = FFB_FBC_WM_COMBINED | FFB_FBC_WE_FORCEON | 640 FFB_FBC_ZE_OFF | FFB_FBC_YE_OFF | FFB_FBC_XE_ON; 641 } else { 642 DPRINTF(("ffb_ras_init: standard resolution.\n")); 643 fbc = FFB_FBC_XE_OFF; 644 } 645 ffb_ras_fifo_wait(sc, 7); 646 DPRINTF(("WID: %08x\n", FBC_READ(sc, FFB_FBC_WID))); 647 FBC_WRITE(sc, FFB_FBC_WID, 0x0); 648 FBC_WRITE(sc, FFB_FBC_PPC, 649 FBC_PPC_VCE_DIS | FBC_PPC_TBE_OPAQUE | FBC_PPC_ACE_DIS | 650 FBC_PPC_APE_DIS | FBC_PPC_DCE_DIS | FBC_PPC_CS_CONST | 651 FBC_PPC_ABE_DIS | FBC_PPC_XS_WID); 652 653 fbc |= FFB_FBC_WB_A | FFB_FBC_RB_A | FFB_FBC_SB_BOTH | 654 FFB_FBC_RGBE_MASK; 655 DPRINTF(("%s: fbc is %08x\n", __func__, fbc)); 656 FBC_WRITE(sc, FFB_FBC_FBC, fbc); 657 FBC_WRITE(sc, FFB_FBC_ROP, FBC_ROP_NEW); 658 FBC_WRITE(sc, FFB_FBC_DRAWOP, FBC_DRAWOP_RECTANGLE); 659 FBC_WRITE(sc, FFB_FBC_PMASK, 0xffffffff); 660 FBC_WRITE(sc, FFB_FBC_FONTINC, 0x10000); 661 ffb_ras_fifo_wait(sc, 5); 662 sc->sc_fg_cache = 0; 663 FBC_WRITE(sc, FFB_FBC_FG, sc->sc_fg_cache); 664 sc->sc_bg_cache = 0; 665 FBC_WRITE(sc, FFB_FBC_BG, sc->sc_bg_cache); 666 FBC_WRITE(sc, FFB_FBC_BLENDC, FFB_BLENDC_FORCE_ONE | 667 FFB_BLENDC_DF_ONE_M_A | 668 FFB_BLENDC_SF_A); 669 FBC_WRITE(sc, FFB_FBC_BLENDC1, 0); 670 FBC_WRITE(sc, FFB_FBC_BLENDC2, 0); 671 ffb_ras_wait(sc); 672 } 673 674 void 675 ffb_ras_eraserows(void *cookie, int row, int n, long attr) 676 { 677 struct rasops_info *ri = cookie; 678 struct vcons_screen *scr = ri->ri_hw; 679 struct ffb_softc *sc = scr->scr_cookie; 680 681 if (row < 0) { 682 n += row; 683 row = 0; 684 } 685 if (row + n > ri->ri_rows) 686 n = ri->ri_rows - row; 687 if (n <= 0) 688 return; 689 690 ffb_ras_fill(sc); 691 ffb_ras_setfg(sc, ri->ri_devcmap[(attr >> 16) & 0xf]); 692 ffb_ras_fifo_wait(sc, 4); 693 if ((n == ri->ri_rows) && (ri->ri_flg & RI_FULLCLEAR)) { 694 FBC_WRITE(sc, FFB_FBC_BY, 0); 695 FBC_WRITE(sc, FFB_FBC_BX, 0); 696 FBC_WRITE(sc, FFB_FBC_BH, ri->ri_height); 697 FBC_WRITE(sc, FFB_FBC_BW, ri->ri_width); 698 ri->ri_flg &= ~RI_CURSOR; 699 } else { 700 row *= ri->ri_font->fontheight; 701 FBC_WRITE(sc, FFB_FBC_BY, ri->ri_yorigin + row); 702 FBC_WRITE(sc, FFB_FBC_BX, ri->ri_xorigin); 703 FBC_WRITE(sc, FFB_FBC_BH, n * ri->ri_font->fontheight); 704 FBC_WRITE(sc, FFB_FBC_BW, ri->ri_emuwidth); 705 } 706 SYNC; 707 } 708 709 void 710 ffb_ras_erasecols(void *cookie, int row, int col, int n, long attr) 711 { 712 struct rasops_info *ri = cookie; 713 struct vcons_screen *scr = ri->ri_hw; 714 struct ffb_softc *sc = scr->scr_cookie; 715 716 if ((row < 0) || (row >= ri->ri_rows)) 717 return; 718 if (col < 0) { 719 n += col; 720 col = 0; 721 } 722 if (col + n > ri->ri_cols) 723 n = ri->ri_cols - col; 724 if (n <= 0) 725 return; 726 727 n *= ri->ri_font->fontwidth; 728 col *= ri->ri_font->fontwidth; 729 row *= ri->ri_font->fontheight; 730 731 ffb_ras_fill(sc); 732 ffb_ras_setfg(sc, ri->ri_devcmap[(attr >> 16) & 0xf]); 733 ffb_ras_fifo_wait(sc, 4); 734 FBC_WRITE(sc, FFB_FBC_BY, ri->ri_yorigin + row); 735 FBC_WRITE(sc, FFB_FBC_BX, ri->ri_xorigin + col); 736 FBC_WRITE(sc, FFB_FBC_BH, ri->ri_font->fontheight); 737 FBC_WRITE(sc, FFB_FBC_BW, n); 738 SYNC; 739 } 740 741 void 742 ffb_ras_fill(struct ffb_softc *sc) 743 { 744 ffb_ras_fifo_wait(sc, 3); 745 FBC_WRITE(sc, FFB_FBC_PPC, 746 FBC_PPC_VCE_DIS | FBC_PPC_TBE_OPAQUE | FBC_PPC_ACE_DIS | 747 FBC_PPC_APE_DIS | FBC_PPC_DCE_DIS | FBC_PPC_CS_CONST | 748 FBC_PPC_ABE_DIS | FBC_PPC_XS_WID); 749 FBC_WRITE(sc, FFB_FBC_ROP, FBC_ROP_NEW); 750 FBC_WRITE(sc, FFB_FBC_DRAWOP, FBC_DRAWOP_RECTANGLE); 751 SYNC; 752 } 753 754 void 755 ffb_ras_invert(struct ffb_softc *sc) 756 { 757 ffb_ras_fifo_wait(sc, 3); 758 FBC_WRITE(sc, FFB_FBC_PPC, 759 FBC_PPC_VCE_DIS | FBC_PPC_TBE_OPAQUE | FBC_PPC_ACE_DIS | 760 FBC_PPC_APE_DIS | FBC_PPC_DCE_DIS | FBC_PPC_CS_CONST | 761 FBC_PPC_ABE_DIS | FBC_PPC_XS_WID); 762 FBC_WRITE(sc, FFB_FBC_ROP, FBC_ROP_INVERT); 763 FBC_WRITE(sc, FFB_FBC_DRAWOP, FBC_DRAWOP_RECTANGLE); 764 SYNC; 765 } 766 767 void 768 ffb_ras_copyrows(void *cookie, int src, int dst, int n) 769 { 770 struct rasops_info *ri = cookie; 771 struct vcons_screen *scr = ri->ri_hw; 772 struct ffb_softc *sc = scr->scr_cookie; 773 774 if (dst == src) 775 return; 776 if (src < 0) { 777 n += src; 778 src = 0; 779 } 780 if ((src + n) > ri->ri_rows) 781 n = ri->ri_rows - src; 782 if (dst < 0) { 783 n += dst; 784 dst = 0; 785 } 786 if ((dst + n) > ri->ri_rows) 787 n = ri->ri_rows - dst; 788 if (n <= 0) 789 return; 790 n *= ri->ri_font->fontheight; 791 src *= ri->ri_font->fontheight; 792 dst *= ri->ri_font->fontheight; 793 794 ffb_ras_fifo_wait(sc, 9); 795 FBC_WRITE(sc, FFB_FBC_PPC, 796 FBC_PPC_VCE_DIS | FBC_PPC_TBE_OPAQUE | FBC_PPC_ACE_DIS | 797 FBC_PPC_APE_DIS | FBC_PPC_DCE_DIS | FBC_PPC_CS_CONST | 798 FBC_PPC_ABE_DIS | FBC_PPC_XS_WID); 799 FBC_WRITE(sc, FFB_FBC_ROP, FBC_ROP_OLD | (FBC_ROP_OLD << 8)); 800 FBC_WRITE(sc, FFB_FBC_DRAWOP, FBC_DRAWOP_VSCROLL); 801 FBC_WRITE(sc, FFB_FBC_BY, ri->ri_yorigin + src); 802 FBC_WRITE(sc, FFB_FBC_BX, ri->ri_xorigin); 803 FBC_WRITE(sc, FFB_FBC_DY, ri->ri_yorigin + dst); 804 FBC_WRITE(sc, FFB_FBC_DX, ri->ri_xorigin); 805 FBC_WRITE(sc, FFB_FBC_BH, n); 806 FBC_WRITE(sc, FFB_FBC_BW, ri->ri_emuwidth); 807 SYNC; 808 } 809 810 static void 811 ffb_ras_setfg(struct ffb_softc *sc, int32_t fg) 812 { 813 ffb_ras_fifo_wait(sc, 1); 814 if (fg == sc->sc_fg_cache) 815 return; 816 sc->sc_fg_cache = fg; 817 FBC_WRITE(sc, FFB_FBC_FG, fg); 818 SYNC; 819 } 820 821 static void 822 ffb_ras_setbg(struct ffb_softc *sc, int32_t bg) 823 { 824 ffb_ras_fifo_wait(sc, 1); 825 if (bg == sc->sc_bg_cache) 826 return; 827 sc->sc_bg_cache = bg; 828 FBC_WRITE(sc, FFB_FBC_BG, bg); 829 SYNC; 830 } 831 832 /* frame buffer generic driver support functions */ 833 static void 834 ffbfb_unblank(device_t dev) 835 { 836 struct ffb_softc *sc = device_private(dev); 837 struct vcons_screen *ms = sc->vd.active; 838 u_int on = 1; 839 int redraw = 0; 840 841 ffb_ras_init(sc); 842 if (sc->sc_locked) { 843 sc->sc_locked = 0; 844 redraw = 1; 845 } 846 847 ffb_blank(sc, WSDISPLAYIO_SVIDEO, &on); 848 #if 0 849 if ((sc->vd.active != &ffb_console_screen) && 850 (ffb_console_screen.scr_flags & VCONS_SCREEN_IS_STATIC)) { 851 /* 852 * force-switch to the console screen. 853 * Caveat: the higher layer will think we're still on the 854 * other screen 855 */ 856 857 SCREEN_INVISIBLE(sc->vd.active); 858 sc->vd.active = &ffb_console_screen; 859 SCREEN_VISIBLE(sc->vd.active); 860 ms = sc->vd.active; 861 redraw = 1; 862 } 863 #endif 864 if (redraw) { 865 vcons_redraw_screen(ms); 866 } 867 } 868 869 int 870 ffbfb_open(dev_t dev, int flags, int mode, struct lwp *l) 871 { 872 struct ffb_softc *sc; 873 874 sc = device_lookup_private(&ffb_cd, minor(dev)); 875 if (sc == NULL) 876 return ENXIO; 877 878 sc->sc_locked = 1; 879 return 0; 880 } 881 882 int 883 ffbfb_close(dev_t dev, int flags, int mode, struct lwp *l) 884 { 885 struct ffb_softc *sc = device_lookup_private(&ffb_cd, minor(dev)); 886 struct vcons_screen *ms = sc->vd.active; 887 888 sc->sc_locked = 0; 889 if (ms != NULL) { 890 if ((sc->sc_mode == WSDISPLAYIO_MODE_EMUL) && 891 (sc->sc_locked == 0)) { 892 ffb_ras_init(sc); 893 vcons_redraw_screen(ms); 894 } 895 } 896 return 0; 897 } 898 899 int 900 ffbfb_ioctl(dev_t dev, u_long cmd, void *data, int flags, struct lwp *l) 901 { 902 struct ffb_softc *sc = device_lookup_private(&ffb_cd, minor(dev)); 903 904 return ffb_ioctl(&sc->vd, NULL, cmd, data, flags, l); 905 } 906 907 paddr_t 908 ffbfb_mmap(dev_t dev, off_t off, int prot) 909 { 910 struct ffb_softc *sc = device_lookup_private(&ffb_cd, minor(dev)); 911 uint64_t size; 912 int i, reg; 913 off_t o; 914 915 /* 916 * off is a magic cookie (see xfree86/drivers/sunffb/ffb.h), 917 * which we map to an index into the "reg" property, and use 918 * our copy of the firmware data as arguments for the real 919 * mapping. 920 */ 921 static struct { unsigned long voff; int reg; long flags; } map[] = { 922 { 0x00000000, FFB_REG_SFB8R, BUS_SPACE_MAP_PREFETCHABLE }, 923 { 0x00400000, FFB_REG_SFB8G, BUS_SPACE_MAP_PREFETCHABLE }, 924 { 0x00800000, FFB_REG_SFB8B, BUS_SPACE_MAP_PREFETCHABLE }, 925 { 0x00c00000, FFB_REG_SFB8X, BUS_SPACE_MAP_PREFETCHABLE }, 926 { 0x01000000, FFB_REG_SFB32, BUS_SPACE_MAP_PREFETCHABLE }, 927 { 0x02000000, FFB_REG_SFB64, BUS_SPACE_MAP_PREFETCHABLE }, 928 { 0x04000000, FFB_REG_FBC, 0 }, 929 { 0x04004000, FFB_REG_DFB8R, BUS_SPACE_MAP_PREFETCHABLE }, 930 { 0x04404000, FFB_REG_DFB8G, BUS_SPACE_MAP_PREFETCHABLE }, 931 { 0x04804000, FFB_REG_DFB8B, BUS_SPACE_MAP_PREFETCHABLE }, 932 { 0x04c04000, FFB_REG_DFB8X, BUS_SPACE_MAP_PREFETCHABLE }, 933 { 0x05004000, FFB_REG_DFB24, BUS_SPACE_MAP_PREFETCHABLE }, 934 { 0x06004000, FFB_REG_DFB32, BUS_SPACE_MAP_PREFETCHABLE }, 935 { 0x07004000, FFB_REG_DFB422A, BUS_SPACE_MAP_PREFETCHABLE }, 936 { 0x0bc06000, FFB_REG_DAC, 0 }, 937 { 0x0bc08000, FFB_REG_PROM, 0 }, 938 { 0x0bc18000, 0, 0 } 939 }; 940 941 /* special value "FFB_EXP_VOFF" - not backed by any "reg" entry */ 942 if (off == 0x0bc18000) 943 return bus_space_mmap(sc->sc_bt, sc->sc_addrs[FFB_REG_PROM], 944 0x00200000, prot, BUS_SPACE_MAP_LINEAR); 945 946 /* 947 * FFB_VOFF_FBC_KREGS - used by afbinit to upload firmware. We should 948 * probably mmap them only on afb boards 949 */ 950 if ((off >= 0x0bc04000) && (off < 0x0bc06000)) 951 return bus_space_mmap(sc->sc_bt, sc->sc_addrs[FFB_REG_PROM], 952 0x00610000 + (off - 0x0bc04000), prot, 953 BUS_SPACE_MAP_LINEAR); 954 955 #define NELEMS(arr) (sizeof(arr)/sizeof((arr)[0])) 956 957 /* the map is ordered by voff */ 958 for (i = 0; i < NELEMS(map)-1; i++) { 959 reg = map[i].reg; 960 /* the number of entries in reg seems to vary */ 961 if (reg < sc->sc_nreg) { 962 size = min((map[i + 1].voff - map[i].voff), 963 sc->sc_sizes[reg]); 964 if ((off >= map[i].voff) && 965 (off < (map[i].voff + size))) { 966 o = off - map[i].voff; 967 return bus_space_mmap(sc->sc_bt, 968 sc->sc_addrs[reg], o, prot, 969 BUS_SPACE_MAP_LINEAR | map[i].flags); 970 } 971 } 972 } 973 974 return -1; 975 } 976 977 void 978 ffb_clearscreen(struct ffb_softc *sc) 979 { 980 struct rasops_info *ri = &ffb_console_screen.scr_ri; 981 ffb_ras_fill(sc); 982 ffb_ras_setfg(sc, ri->ri_devcmap[WS_DEFAULT_BG]); 983 ffb_ras_fifo_wait(sc, 4); 984 FBC_WRITE(sc, FFB_FBC_BY, 0); 985 FBC_WRITE(sc, FFB_FBC_BX, 0); 986 FBC_WRITE(sc, FFB_FBC_BH, sc->sc_height); 987 FBC_WRITE(sc, FFB_FBC_BW, sc->sc_width); 988 } 989 990 void 991 ffb_cursor(void *cookie, int on, int row, int col) 992 { 993 struct rasops_info *ri = cookie; 994 struct vcons_screen *scr; 995 struct ffb_softc *sc; 996 int x, y, wi, he; 997 998 if (cookie != NULL) { 999 scr = ri->ri_hw; 1000 sc = scr->scr_cookie; 1001 1002 wi = ri->ri_font->fontwidth; 1003 he = ri->ri_font->fontheight; 1004 1005 if (sc->sc_mode == WSDISPLAYIO_MODE_EMUL) { 1006 1007 if (ri->ri_flg & RI_CURSOR) { 1008 1009 /* remove cursor */ 1010 x = ri->ri_ccol * wi + ri->ri_xorigin; 1011 y = ri->ri_crow * he + ri->ri_yorigin; 1012 1013 ffb_ras_invert(sc); 1014 ffb_ras_fifo_wait(sc, 4); 1015 FBC_WRITE(sc, FFB_FBC_BY, y); 1016 FBC_WRITE(sc, FFB_FBC_BX, x); 1017 FBC_WRITE(sc, FFB_FBC_BH, he); 1018 FBC_WRITE(sc, FFB_FBC_BW, wi); 1019 1020 ri->ri_flg &= ~RI_CURSOR; 1021 } 1022 ri->ri_crow = row; 1023 ri->ri_ccol = col; 1024 if (on) 1025 { 1026 x = ri->ri_ccol * wi + ri->ri_xorigin; 1027 y = ri->ri_crow * he + ri->ri_yorigin; 1028 1029 ffb_ras_invert(sc); 1030 ffb_ras_fifo_wait(sc, 4); 1031 FBC_WRITE(sc, FFB_FBC_BY, y); 1032 FBC_WRITE(sc, FFB_FBC_BX, x); 1033 FBC_WRITE(sc, FFB_FBC_BH, he); 1034 FBC_WRITE(sc, FFB_FBC_BW, wi); 1035 1036 ri->ri_flg |= RI_CURSOR; 1037 } 1038 } else { 1039 ri->ri_crow = row; 1040 ri->ri_ccol = col; 1041 ri->ri_flg &= ~RI_CURSOR; 1042 } 1043 } 1044 } 1045 1046 /* mono bitmap font */ 1047 void 1048 ffb_putchar_mono(void *cookie, int row, int col, u_int c, long attr) 1049 { 1050 struct rasops_info *ri = cookie; 1051 struct vcons_screen *scr = ri->ri_hw; 1052 struct wsdisplay_font *font = PICK_FONT(ri, c); 1053 struct ffb_softc *sc = scr->scr_cookie; 1054 void *data; 1055 uint32_t fg, bg; 1056 int i; 1057 int x, y, wi, he; 1058 1059 if (sc->sc_mode != WSDISPLAYIO_MODE_EMUL) 1060 return; 1061 1062 wi = font->fontwidth; 1063 he = font->fontheight; 1064 1065 if (!CHAR_IN_FONT(c, font)) 1066 return; 1067 1068 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 1069 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 1070 x = ri->ri_xorigin + col * wi; 1071 y = ri->ri_yorigin + row * he; 1072 1073 data = WSFONT_GLYPH(c, font); 1074 1075 ffb_ras_setbg(sc, bg); 1076 ffb_ras_setfg(sc, fg); 1077 ffb_ras_fifo_wait(sc, 4); 1078 FBC_WRITE(sc, FFB_FBC_ROP, FBC_ROP_NEW); 1079 FBC_WRITE(sc, FFB_FBC_FONTXY, (y << 16) | x); 1080 FBC_WRITE(sc, FFB_FBC_FONTW, wi); 1081 FBC_WRITE(sc, FFB_FBC_PPC, 1082 FBC_PPC_VCE_DIS | FBC_PPC_TBE_OPAQUE | FBC_PPC_ACE_DIS | 1083 FBC_PPC_APE_DIS | FBC_PPC_DCE_DIS | FBC_PPC_CS_CONST | 1084 FBC_PPC_ABE_DIS | FBC_PPC_XS_WID); 1085 1086 switch (font->stride) { 1087 case 1: { 1088 uint8_t *data8 = data; 1089 uint32_t reg; 1090 for (i = 0; i < he; i++) { 1091 reg = *data8; 1092 FBC_WRITE(sc, FFB_FBC_FONT, reg << 24); 1093 data8++; 1094 } 1095 break; 1096 } 1097 case 2: { 1098 uint16_t *data16 = data; 1099 uint32_t reg; 1100 for (i = 0; i < he; i++) { 1101 reg = *data16; 1102 FBC_WRITE(sc, FFB_FBC_FONT, reg << 16); 1103 data16++; 1104 } 1105 break; 1106 } 1107 } 1108 } 1109 1110 /* alpha font */ 1111 void 1112 ffb_putchar_aa(void *cookie, int row, int col, u_int c, long attr) 1113 { 1114 struct rasops_info *ri = cookie; 1115 struct vcons_screen *scr = ri->ri_hw; 1116 struct wsdisplay_font *font = PICK_FONT(ri, c); 1117 struct ffb_softc *sc = scr->scr_cookie; 1118 volatile uint32_t *dest, *ddest; 1119 uint8_t *data8; 1120 uint32_t fg, bg; 1121 int i; 1122 int x, y, wi, he; 1123 uint32_t alpha = 0x80; 1124 int j; 1125 1126 if (sc->sc_mode != WSDISPLAYIO_MODE_EMUL) 1127 return; 1128 1129 wi = font->fontwidth; 1130 he = font->fontheight; 1131 1132 if (!CHAR_IN_FONT(c, font)) 1133 return; 1134 1135 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 1136 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 1137 x = ri->ri_xorigin + col * wi; 1138 y = ri->ri_yorigin + row * he; 1139 1140 data8 = WSFONT_GLYPH(c, font); 1141 1142 /* first we erase the background */ 1143 ffb_ras_fill(sc); 1144 ffb_ras_setfg(sc, bg); 1145 ffb_ras_fifo_wait(sc, 4); 1146 FBC_WRITE(sc, FFB_FBC_BY, y); 1147 FBC_WRITE(sc, FFB_FBC_BX, x); 1148 FBC_WRITE(sc, FFB_FBC_BH, he); 1149 FBC_WRITE(sc, FFB_FBC_BW, wi); 1150 1151 /* if we draw a space we're done */ 1152 if (c == ' ') return; 1153 1154 /* now enable alpha blending */ 1155 ffb_ras_setfg(sc, fg); 1156 ffb_ras_fifo_wait(sc, 2); 1157 FBC_WRITE(sc, FFB_FBC_ROP, FBC_ROP_NEW); 1158 1159 FBC_WRITE(sc, FFB_FBC_PPC, 1160 FBC_PPC_VCE_DIS | FBC_PPC_TBE_OPAQUE | FBC_PPC_ACE_DIS | 1161 FBC_PPC_APE_DIS | FBC_PPC_DCE_DIS | FBC_PPC_CS_CONST | 1162 FBC_PPC_ABE_ENA | FBC_PPC_XS_VAR); 1163 /* 1164 * we have to wait for both the rectangle drawing op above and the 1165 * FFB_FBC_PPC write to finish before mucking around in the SFB aperture 1166 */ 1167 ffb_ras_wait(sc); 1168 1169 /* ... and draw the character */ 1170 dest = sc->sc_sfb32 + (y << 11) + x; 1171 for (i = 0; i < he; i++) { 1172 ddest = dest; 1173 for (j = 0; j < wi; j++) { 1174 alpha = *data8; 1175 /* 1176 * We set the colour source to constant above so we only 1177 * have to write the alpha channel here and the colour 1178 * comes from the FG register. It would be nice if we 1179 * could just use the SFB8X aperture and memcpy() the 1180 * alpha map line by line but for some strange reason 1181 * that will take colour info from the framebuffer even 1182 * if we set the FBC_PPC_CS_CONST bit above. 1183 */ 1184 *ddest = alpha << 24; 1185 data8++; 1186 ddest++; 1187 } 1188 dest += 2048; 1189 } 1190 } 1191 1192 int 1193 ffb_allocattr(void *cookie, int fg, int bg, int flags, long *attrp) 1194 { 1195 if ((fg == 0) && (bg == 0)) 1196 { 1197 fg = WS_DEFAULT_FG; 1198 bg = WS_DEFAULT_BG; 1199 } 1200 if (flags & WSATTR_REVERSE) { 1201 *attrp = (bg & 0xff) << 24 | (fg & 0xff) << 16 | 1202 (flags & 0xff); 1203 } else 1204 *attrp = (fg & 0xff) << 24 | (bg & 0xff) << 16 | 1205 (flags & 0xff); 1206 return 0; 1207 } 1208 1209 void 1210 ffb_init_screen(void *cookie, struct vcons_screen *scr, 1211 int existing, long *defattr) 1212 { 1213 struct ffb_softc *sc = cookie; 1214 struct rasops_info *ri = &scr->scr_ri; 1215 1216 ri->ri_depth = 32; 1217 ri->ri_width = sc->sc_width; 1218 ri->ri_height = sc->sc_height; 1219 ri->ri_stride = sc->sc_linebytes; 1220 ri->ri_flg = RI_CENTER | RI_ENABLE_ALPHA | RI_PREFER_ALPHA | 1221 RI_FULLCLEAR; 1222 1223 /* 1224 * we can't accelerate copycols() so instead of falling back to 1225 * software use vcons' putchar() based implementation 1226 */ 1227 scr->scr_flags |= VCONS_NO_COPYCOLS; 1228 #ifdef VCONS_DRAW_INTR 1229 scr->scr_flags |= VCONS_DONT_READ; 1230 #endif 1231 DPRINTF(("ffb_init_screen: addr: %08lx\n",(ulong)ri->ri_bits)); 1232 1233 /* explicitly request BGR in case the default changes */ 1234 ri->ri_rnum = 8; 1235 ri->ri_gnum = 8; 1236 ri->ri_bnum = 8; 1237 ri->ri_rpos = 0; 1238 ri->ri_gpos = 8; 1239 ri->ri_bpos = 16; 1240 1241 rasops_init(ri, 0, 0); 1242 ri->ri_caps = WSSCREEN_WSCOLORS; 1243 rasops_reconfig(ri, sc->sc_height / ri->ri_font->fontheight, 1244 sc->sc_width / ri->ri_font->fontwidth); 1245 1246 /* enable acceleration */ 1247 ri->ri_ops.copyrows = ffb_ras_copyrows; 1248 ri->ri_ops.eraserows = ffb_ras_eraserows; 1249 ri->ri_ops.erasecols = ffb_ras_erasecols; 1250 ri->ri_ops.cursor = ffb_cursor; 1251 ri->ri_ops.allocattr = ffb_allocattr; 1252 if (FONT_IS_ALPHA(ri->ri_font)) { 1253 ri->ri_ops.putchar = ffb_putchar_aa; 1254 } else 1255 ri->ri_ops.putchar = ffb_putchar_mono; 1256 } 1257 1258 /* I2C bitbanging */ 1259 static void ffb_i2cbb_set_bits(void *cookie, uint32_t bits) 1260 { 1261 struct ffb_softc *sc = cookie; 1262 1263 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_CFG_MPDATA); 1264 DAC_WRITE(sc, FFB_DAC_VALUE, bits); 1265 } 1266 1267 static void ffb_i2cbb_set_dir(void *cookie, uint32_t dir) 1268 { 1269 /* Nothing to do */ 1270 } 1271 1272 static uint32_t ffb_i2cbb_read(void *cookie) 1273 { 1274 struct ffb_softc *sc = cookie; 1275 uint32_t bits; 1276 1277 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_CFG_MPSENSE); 1278 bits = DAC_READ(sc, FFB_DAC_VALUE); 1279 1280 return bits; 1281 } 1282 1283 /* higher level I2C stuff */ 1284 static int 1285 ffb_i2c_acquire_bus(void *cookie, int flags) 1286 { 1287 /* private bus */ 1288 return (0); 1289 } 1290 1291 static void 1292 ffb_i2c_release_bus(void *cookie, int flags) 1293 { 1294 /* private bus */ 1295 } 1296 1297 static int 1298 ffb_i2c_send_start(void *cookie, int flags) 1299 { 1300 return (i2c_bitbang_send_start(cookie, flags, &ffb_i2cbb_ops)); 1301 } 1302 1303 static int 1304 ffb_i2c_send_stop(void *cookie, int flags) 1305 { 1306 1307 return (i2c_bitbang_send_stop(cookie, flags, &ffb_i2cbb_ops)); 1308 } 1309 1310 static int 1311 ffb_i2c_initiate_xfer(void *cookie, i2c_addr_t addr, int flags) 1312 { 1313 /* 1314 * for some reason i2c_bitbang_initiate_xfer left-shifts 1315 * the I2C-address and then sets the direction bit 1316 */ 1317 return (i2c_bitbang_initiate_xfer(cookie, addr, flags, 1318 &ffb_i2cbb_ops)); 1319 } 1320 1321 static int 1322 ffb_i2c_read_byte(void *cookie, uint8_t *valp, int flags) 1323 { 1324 return (i2c_bitbang_read_byte(cookie, valp, flags, &ffb_i2cbb_ops)); 1325 } 1326 1327 static int 1328 ffb_i2c_write_byte(void *cookie, uint8_t val, int flags) 1329 { 1330 return (i2c_bitbang_write_byte(cookie, val, flags, &ffb_i2cbb_ops)); 1331 } 1332 1333 1334 #define TVC_READ_LIMIT 100000 1335 int 1336 ffb_tgc_disable(struct ffb_softc *sc) 1337 { 1338 int i; 1339 1340 /* Is the timing generator disabled? */ 1341 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_TGC); 1342 if (!(DAC_READ(sc, FFB_DAC_VALUE) & FFB_DAC_TGC_TIMING_ENABLE)) 1343 return 1; 1344 1345 /* If not, disable it when the vertical counter reaches 0 */ 1346 for (i = 0; i < TVC_READ_LIMIT; i++) { 1347 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_TVC); 1348 if (!DAC_READ(sc, FFB_DAC_VALUE)) { 1349 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_TGC); 1350 DAC_WRITE(sc, FFB_DAC_VALUE, 0); 1351 return 1; 1352 } 1353 } 1354 return 0; 1355 } 1356 1357 /* 1358 * PLL Control Register values: 1359 * M)ultiplier = bits 0:6 + 1 1360 * D)ivisor = bits 7:10 + 1 1361 * P)ost divisor = bits 11:13 (000 = 1, 001 = 2, 010 = 4, 011 = 8) 1362 * Frequency = 13.5 * M / D / P 1363 */ 1364 #define FFB_PLL_FREQ 13500000 1365 void 1366 ffb_get_pclk(int request, uint32_t *pll, int *diff) 1367 { 1368 int m, d, p, f, hex = 0, curdiff; 1369 1370 *diff = 100000000; 1371 1372 for (m = 32; m <= 80; m++) { 1373 for (d = 4; d <= 11; d++) { 1374 for (p = 1; p <= 8; p = p << 1) { 1375 switch (p) { 1376 case 1: 1377 hex = 0x4000 + (d << 7) + m; 1378 break; 1379 case 2: 1380 hex = 0x4800 + (d << 7) + m; 1381 break; 1382 case 4: 1383 hex = 0x5000 + (d << 7) + m; 1384 break; 1385 case 8: 1386 hex = 0x6000 + (d << 7) + m; 1387 break; 1388 } 1389 f = 13500000 * m / d / p; 1390 if (f == request) { 1391 *diff = 0; 1392 *pll = hex; 1393 return; 1394 } else { 1395 curdiff = abs(request - f); 1396 if (curdiff < *diff) { 1397 *diff = curdiff; 1398 *pll = hex; 1399 } 1400 } 1401 } 1402 } 1403 } 1404 } 1405 1406 /* 1407 * Details of the FFB RAMDAC are contained in the Brooktree BT497/498 1408 * and in the Connexant BT497A/498A documentation. 1409 * 1410 * VESA timings to FFB register conversion: 1411 * If interleave = 4/2:1 then x = 2, if interleave = 8/2:1 then x = 4 1412 * VBE = VBS - vres = (sync pulse - 1) + back porch 1413 * VBS = VSS - front porch = (sync pulse - 1) + back porch + vres 1414 * VSE = sync pulse - 1 1415 * VSS = (sync pulse - 1) + back porch + vres + front porch 1416 * HRE = HSS - HSE - 1 1417 * HBE = (sync pulse + back porch) / x - 1 1418 * HBS = (sync pulse + back porch + hres) / x - 1 1419 * HSE = sync pulse / x - 1 1420 * HSS = (sync pulse + back porch + hres + front porch) / x - 1 1421 * HCE = HBS - 4 1422 * HCS = HBE - 4 1423 * EPE = EIE = EIS = 0 (for all non-interlaced modes) 1424 * 1425 * Note, that 8/2:1 Single Buffered Interleaving is only supported by the 1426 * double-buffered FFB (Creator3D), and at higher resolutions than 1280x1024 1427 * 1428 * Note, that the timing generator should be disabled and re-enabled when the 1429 * the timing parameter registers are being programmed. Stopping the timing 1430 * generator should only be done when the vertical counter is zero. 1431 */ 1432 #define DIVIDE(x,y) (((x) + ((y) / 2)) / (y)) 1433 int 1434 ffb_set_vmode(struct ffb_softc *sc, struct videomode *mode, int btype, 1435 int *hres, int *vres) 1436 { 1437 int diff; 1438 uint32_t fp, sp, bp, x; 1439 uint32_t pll, pfc, ucl, dcl, tgc; 1440 uint32_t vbe, vbs, vse, vss, hre, hbe, hbs, hse, hss, hce, hcs; 1441 uint32_t epe, eie, eis; 1442 uint32_t fbcfg0; 1443 1444 DPRINTF(("ffb_set_vmode: %dx%d@%d", mode->hdisplay, mode->vdisplay, 1445 DIVIDE(DIVIDE(mode->dot_clock * 1000, 1446 mode->htotal), mode->vtotal))); 1447 DPRINTF((" (%d %d %d %d %d %d %d", 1448 mode->dot_clock, mode->hsync_start, mode->hsync_end, mode->htotal, 1449 mode->vsync_start, mode->vsync_end, mode->vtotal)); 1450 DPRINTF((" %s%sH %s%sV)\n", 1451 mode->flags & VID_PHSYNC ? "+" : "", 1452 mode->flags & VID_NHSYNC ? "-" : "", 1453 mode->flags & VID_PVSYNC ? "+" : "", 1454 mode->flags & VID_NVSYNC ? "-" : "")); 1455 1456 /* We don't handle interlaced or doublescan (yet) */ 1457 if ((mode->flags & VID_INTERLACE) || (mode->flags & VID_DBLSCAN)) 1458 return 0; 1459 1460 /* Only Creator3D can be set to > 1280x1024 */ 1461 if(((sc->sc_type == FFB_CREATOR && !((btype & 7) == 3)) || 1462 sc->sc_type == FFB_AFB) 1463 && (mode->hdisplay > 1280 || mode->vdisplay > 1024)) 1464 return 0; 1465 /* Creator3D can be set to <= 1920x1360 */ 1466 if (mode->hdisplay > 1920 || mode->vdisplay > 1360) 1467 return 0; 1468 1469 /* 1470 * Look for a matching pixel clock and set PLL Control. 1471 * XXX: 640x480@60 is 25175000 in modelines but 25125000 in the 1472 * FFB PROM, and the closest match to 25175000 (0x4da9/25159090) 1473 * does not work. So, use the PROM value instead. 1474 */ 1475 if (mode->hdisplay == 640 && mode->vdisplay == 480 && 1476 mode->dot_clock == 25175) { 1477 DPRINTF(("ffb_set_vmode: 640x480@60: adjusted dot clock\n")); 1478 mode->dot_clock = 25125; 1479 } 1480 ffb_get_pclk(mode->dot_clock * 1000, &pll, &diff); 1481 if (diff > 250000) 1482 return 0; 1483 1484 /* Pixel Format Control, User Control and FBC Configuration. */ 1485 if (mode->hdisplay > 1280) { 1486 pfc = FFB_DAC_PIX_FMT_821; 1487 ucl = FFB_DAC_USR_CTRL_OVERLAY | FFB_DAC_USR_CTRL_WMODE_C; 1488 x = 4; 1489 fbcfg0 = FBC_READ(sc, FFB_FBC_FBCFG0) | FBC_CFG0_DOUBLE_BUF; 1490 } else { 1491 pfc = FFB_DAC_PIX_FMT_421; 1492 /* Only Creator3D and Elite3D can have double-buffer */ 1493 if ((sc->sc_type == FFB_CREATOR && !((btype & 7) == 3))) 1494 ucl = 0; 1495 else 1496 ucl = FFB_DAC_USR_CTRL_DOUBLE; 1497 ucl |= (FFB_DAC_USR_CTRL_OVERLAY | FFB_DAC_USR_CTRL_WMODE_S8); 1498 x = 2; 1499 fbcfg0 = FBC_READ(sc, FFB_FBC_FBCFG0) | FBC_CFG0_SINGLE_BUF; 1500 } 1501 1502 /* DAC Control and Timing Generator Control */ 1503 if (mode->flags & VID_PVSYNC) 1504 dcl = FFB_DAC_DAC_CTRL_POS_VSYNC; 1505 else 1506 dcl = 0; 1507 tgc = 0; 1508 #define EDID_VID_INP sc->sc_edid_info.edid_video_input 1509 if ((EDID_VID_INP & EDID_VIDEO_INPUT_COMPOSITE_SYNC)) { 1510 dcl |= FFB_DAC_DAC_CTRL_VSYNC_DIS; 1511 tgc = FFB_DAC_TGC_EQUAL_DISABLE; 1512 } else { 1513 dcl |= FFB_DAC_DAC_CTRL_SYNC_G; 1514 if (EDID_VID_INP & EDID_VIDEO_INPUT_SEPARATE_SYNCS) 1515 tgc |= FFB_DAC_TGC_VSYNC_DISABLE; 1516 else 1517 tgc = FFB_DAC_TGC_EQUAL_DISABLE; 1518 } 1519 if (EDID_VID_INP & EDID_VIDEO_INPUT_BLANK_TO_BLACK) 1520 dcl |= FFB_DAC_DAC_CTRL_PED_ENABLE; 1521 tgc |= (FFB_DAC_TGC_VIDEO_ENABLE | FFB_DAC_TGC_TIMING_ENABLE | 1522 FFB_DAC_TGC_MASTER_ENABLE); 1523 1524 /* Vertical timing */ 1525 fp = mode->vsync_start - mode->vdisplay; 1526 sp = mode->vsync_end - mode->vsync_start; 1527 bp = mode->vtotal - mode->vsync_end; 1528 1529 vbe = sp - 1 + bp; 1530 vbs = sp - 1 + bp + mode->vdisplay; 1531 vse = sp - 1; 1532 vss = sp - 1 + bp + mode->vdisplay + fp; 1533 1534 /* Horizontal timing */ 1535 fp = mode->hsync_start - mode->hdisplay; 1536 sp = mode->hsync_end - mode->hsync_start; 1537 bp = mode->htotal - mode->hsync_end; 1538 1539 hbe = (sp + bp) / x - 1; 1540 hbs = (sp + bp + mode->hdisplay) / x - 1; 1541 hse = sp / x - 1; 1542 hss = (sp + bp + mode->hdisplay + fp) / x -1; 1543 hre = hss - hse - 1; 1544 hce = hbs - 4; 1545 hcs = hbe - 4; 1546 1547 /* Equalisation (interlaced modes) */ 1548 epe = 0; 1549 eie = 0; 1550 eis = 0; 1551 1552 DPRINTF(("ffb_set_vmode: 0x%04x 0x%04x 0x%04x 0x%04x 0x%04x\n", 1553 pll, pfc, ucl, dcl, tgc)); 1554 DPRINTF(("\t0x%04x 0x%04x 0x%04x 0x%04x\n", vbe, vbs, vse, vss)); 1555 DPRINTF(("\t0x%04x 0x%04x 0x%04x 0x%04x 0x%04x 0x%04x 0x%04x\n", 1556 hre, hbe, hbs, hse, hss, hce, hcs)); 1557 DPRINTF(("\t0x%04x 0x%04x 0x%04x\n", epe, eie, eis)); 1558 1559 if (!ffb_tgc_disable(sc)) { 1560 DPRINTF(("ffb_set_vmode: failed to disable TGC register\n")); 1561 return 0; 1562 } 1563 1564 /* 1565 * Program the mode registers. 1566 * Program the timing generator last, as that re-enables output. 1567 * Note, that a read to/write from a register increments the 1568 * register address to the next register automatically. 1569 */ 1570 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_PLL_CTRL); 1571 DAC_WRITE(sc, FFB_DAC_VALUE, pll); 1572 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_PIX_FMT); 1573 DAC_WRITE(sc, FFB_DAC_VALUE, pfc); 1574 DAC_WRITE(sc, FFB_DAC_VALUE, ucl); 1575 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_DAC_CTRL); 1576 DAC_WRITE(sc, FFB_DAC_VALUE, dcl); 1577 1578 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_VBE); 1579 DAC_WRITE(sc, FFB_DAC_VALUE, vbe); 1580 DAC_WRITE(sc, FFB_DAC_VALUE, vbs); 1581 DAC_WRITE(sc, FFB_DAC_VALUE, vse); 1582 DAC_WRITE(sc, FFB_DAC_VALUE, vss); 1583 1584 DAC_WRITE(sc, FFB_DAC_VALUE, hre); 1585 DAC_WRITE(sc, FFB_DAC_VALUE, hbe); 1586 DAC_WRITE(sc, FFB_DAC_VALUE, hbs); 1587 DAC_WRITE(sc, FFB_DAC_VALUE, hse); 1588 DAC_WRITE(sc, FFB_DAC_VALUE, hss); 1589 DAC_WRITE(sc, FFB_DAC_VALUE, hce); 1590 DAC_WRITE(sc, FFB_DAC_VALUE, hcs); 1591 1592 DAC_WRITE(sc, FFB_DAC_VALUE, epe); 1593 DAC_WRITE(sc, FFB_DAC_VALUE, eie); 1594 DAC_WRITE(sc, FFB_DAC_VALUE, eis); 1595 1596 FBC_WRITE(sc, FFB_FBC_FBCFG0, fbcfg0); 1597 1598 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_TGC); 1599 DAC_WRITE(sc, FFB_DAC_VALUE, tgc); 1600 DPRINTF(("new tgc: %08x\n", tgc)); 1601 1602 *hres = mode->hdisplay; 1603 *vres = mode->vdisplay; 1604 1605 printf("%s: video mode set to %d x %d @ %dHz\n", 1606 device_xname(sc->sc_dev), 1607 mode->hdisplay, mode->vdisplay, 1608 DIVIDE(DIVIDE(mode->dot_clock * 1000, 1609 mode->htotal), mode->vtotal)); 1610 1611 return 1; 1612 } 1613
Indexes created Sun Oct 12 02:09:55 GMT 2025