ffb.c revision 1.60
1 /* $NetBSD: ffb.c,v 1.60 2017/04/27 23:17:21 macallan Exp $ */ 2 /* $OpenBSD: creator.c,v 1.20 2002/07/30 19:48:15 jason Exp $ */ 3 4 /* 5 * Copyright (c) 2002 Jason L. Wright (jason (at) thought.net) 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Jason L. Wright 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 25 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 26 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 27 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 30 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 31 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32 * POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: ffb.c,v 1.60 2017/04/27 23:17:21 macallan Exp $"); 37 38 #include <sys/types.h> 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/kernel.h> 42 #include <sys/device.h> 43 #include <sys/conf.h> 44 #include <sys/ioctl.h> 45 #include <sys/malloc.h> 46 #include <sys/mman.h> 47 48 #include <sys/bus.h> 49 #include <machine/autoconf.h> 50 #include <machine/openfirm.h> 51 #include <machine/vmparam.h> 52 53 #include <dev/wscons/wsconsio.h> 54 #include <dev/sun/fbio.h> 55 #include <dev/sun/fbvar.h> 56 57 #include <dev/wsfont/wsfont.h> 58 #include <dev/wscons/wsdisplay_vconsvar.h> 59 60 #include <prop/proplib.h> 61 62 #include <dev/i2c/i2cvar.h> 63 #include <dev/i2c/i2c_bitbang.h> 64 #include <dev/i2c/ddcvar.h> 65 66 #include <sparc64/dev/ffbreg.h> 67 #include <sparc64/dev/ffbvar.h> 68 69 #include "opt_wsdisplay_compat.h" 70 #include "opt_ffb.h" 71 72 #ifndef WS_DEFAULT_BG 73 /* Sun -> background should be white */ 74 #define WS_DEFAULT_BG 0xf 75 #endif 76 77 #ifdef FFB_SYNC 78 #define SYNC ffb_ras_wait(sc) 79 #else 80 #define SYNC 81 #endif 82 83 /* Debugging */ 84 #if !defined FFB_DEBUG 85 #define FFB_DEBUG 0 86 #endif 87 #define DPRINTF(x) if (ffb_debug) printf x 88 /* Patchable */ 89 extern int ffb_debug; 90 #if FFB_DEBUG > 0 91 int ffb_debug = 1; 92 #else 93 int ffb_debug = 0; 94 #endif 95 96 extern struct cfdriver ffb_cd; 97 98 struct wsscreen_descr ffb_stdscreen = { 99 "sunffb", 100 0, 0, /* will be filled in -- XXX shouldn't, it's global. */ 101 0, 102 0, 0, 103 WSSCREEN_REVERSE | WSSCREEN_WSCOLORS, 104 NULL /* modecookie */ 105 }; 106 107 const struct wsscreen_descr *ffb_scrlist[] = { 108 &ffb_stdscreen, 109 /* XXX other formats? */ 110 }; 111 112 struct wsscreen_list ffb_screenlist = { 113 sizeof(ffb_scrlist) / sizeof(struct wsscreen_descr *), 114 ffb_scrlist 115 }; 116 117 static struct vcons_screen ffb_console_screen; 118 119 int ffb_ioctl(void *, void *, u_long, void *, int, struct lwp *); 120 static int ffb_blank(struct ffb_softc *, u_long, u_int *); 121 paddr_t ffb_mmap(void *, void *, off_t, int); 122 void ffb_ras_fifo_wait(struct ffb_softc *, int); 123 void ffb_ras_wait(struct ffb_softc *); 124 void ffb_ras_init(struct ffb_softc *); 125 void ffb_ras_copyrows(void *, int, int, int); 126 void ffb_ras_erasecols(void *, int, int, int, long int); 127 void ffb_ras_eraserows(void *, int, int, long int); 128 void ffb_ras_fill(struct ffb_softc *); 129 void ffb_ras_invert(struct ffb_softc *); 130 static void ffb_ras_setfg(struct ffb_softc *, int32_t); 131 static void ffb_ras_setbg(struct ffb_softc *, int32_t); 132 133 void ffb_clearscreen(struct ffb_softc *); 134 int ffb_load_font(void *, void *, struct wsdisplay_font *); 135 void ffb_init_screen(void *, struct vcons_screen *, int, 136 long *); 137 int ffb_allocattr(void *, int, int, int, long *); 138 void ffb_putchar_mono(void *, int, int, u_int, long); 139 void ffb_putchar_aa(void *, int, int, u_int, long); 140 void ffb_cursor(void *, int, int, int); 141 142 /* frame buffer generic driver */ 143 static void ffbfb_unblank(device_t); 144 dev_type_open(ffbfb_open); 145 dev_type_close(ffbfb_close); 146 dev_type_ioctl(ffbfb_ioctl); 147 dev_type_mmap(ffbfb_mmap); 148 149 static struct fbdriver ffb_fbdriver = { 150 ffbfb_unblank, ffbfb_open, ffbfb_close, ffbfb_ioctl, nopoll, 151 ffbfb_mmap, nokqfilter 152 }; 153 154 struct wsdisplay_accessops ffb_accessops = { 155 .ioctl = ffb_ioctl, 156 .mmap = ffb_mmap, 157 }; 158 159 /* I2C glue */ 160 static int ffb_i2c_acquire_bus(void *, int); 161 static void ffb_i2c_release_bus(void *, int); 162 static int ffb_i2c_send_start(void *, int); 163 static int ffb_i2c_send_stop(void *, int); 164 static int ffb_i2c_initiate_xfer(void *, i2c_addr_t, int); 165 static int ffb_i2c_read_byte(void *, uint8_t *, int); 166 static int ffb_i2c_write_byte(void *, uint8_t, int); 167 168 /* I2C bitbang glue */ 169 static void ffb_i2cbb_set_bits(void *, uint32_t); 170 static void ffb_i2cbb_set_dir(void *, uint32_t); 171 static uint32_t ffb_i2cbb_read(void *); 172 173 static const struct i2c_bitbang_ops ffb_i2cbb_ops = { 174 ffb_i2cbb_set_bits, 175 ffb_i2cbb_set_dir, 176 ffb_i2cbb_read, 177 { 178 FFB_DAC_CFG_MPDATA_SDA, 179 FFB_DAC_CFG_MPDATA_SCL, 180 0, 181 0 182 } 183 }; 184 185 void ffb_attach_i2c(struct ffb_softc *); 186 187 /* Video mode setting */ 188 int ffb_tgc_disable(struct ffb_softc *); 189 void ffb_get_pclk(int, uint32_t *, int *); 190 int ffb_set_vmode(struct ffb_softc *, struct videomode *, int, int *, int *); 191 192 193 void 194 ffb_attach(device_t self) 195 { 196 struct ffb_softc *sc = device_private(self); 197 struct wsemuldisplaydev_attach_args waa; 198 struct rasops_info *ri; 199 long defattr; 200 const char *model, *out_dev; 201 int btype; 202 uint32_t dac; 203 int maxrow; 204 u_int blank = WSDISPLAYIO_VIDEO_ON; 205 char buf[6+1]; 206 int i, try_edid; 207 prop_data_t data; 208 209 printf(":"); 210 211 if (sc->sc_type == FFB_CREATOR) { 212 btype = prom_getpropint(sc->sc_node, "board_type", 0); 213 if ((btype & 7) == 3) 214 printf(" Creator3D"); 215 else 216 printf(" Creator"); 217 } else { 218 printf(" Elite3D"); 219 btype = 0; 220 } 221 222 model = prom_getpropstring(sc->sc_node, "model"); 223 if (model == NULL || strlen(model) == 0) 224 model = "unknown"; 225 226 sc->sc_depth = 24; 227 sc->sc_linebytes = 8192; 228 /* We might alter these during EDID mode setting */ 229 sc->sc_height = prom_getpropint(sc->sc_node, "height", 0); 230 sc->sc_width = prom_getpropint(sc->sc_node, "width", 0); 231 232 sc->sc_locked = 0; 233 sc->sc_mode = WSDISPLAYIO_MODE_EMUL; 234 235 maxrow = (prom_getoption("screen-#rows", buf, sizeof buf) != 0) 236 ? strtoul(buf, NULL, 10) 237 : 34; 238 239 /* collect DAC version, as Elite3D cursor enable bit is reversed */ 240 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_DEVID); 241 dac = DAC_READ(sc, FFB_DAC_VALUE); 242 sc->sc_dacrev = (dac >> 28) & 0xf; 243 244 if (sc->sc_type == FFB_AFB) { 245 sc->sc_dacrev = 10; 246 sc->sc_needredraw = 0; 247 } else { 248 /* see what kind of DAC we have */ 249 int pnum = (dac & 0x0ffff000) >> 12; 250 if (pnum == 0x236e) { 251 sc->sc_needredraw = 0; 252 } else { 253 sc->sc_needredraw = 1; 254 } 255 } 256 printf(", model %s, dac %u\n", model, sc->sc_dacrev); 257 if (sc->sc_needredraw) 258 printf("%s: found old DAC, enabling redraw on unblank\n", 259 device_xname(sc->sc_dev)); 260 261 /* Check if a console resolution "<device>:r<res>" is set. */ 262 if (sc->sc_console) { 263 out_dev = prom_getpropstring(sc->sc_node, "output_device"); 264 if (out_dev != NULL && strlen(out_dev) != 0 && 265 strstr(out_dev, ":r") != NULL) 266 try_edid = 0; 267 else 268 try_edid = 1; 269 } else 270 try_edid = 1; 271 272 #if FFB_DEBUG > 0 273 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_TGC); 274 printf("tgc: %08x\n", DAC_READ(sc, FFB_DAC_VALUE)); 275 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_DAC_CTRL); 276 printf("dcl: %08x\n", DAC_READ(sc, FFB_DAC_VALUE)); 277 #endif 278 ffb_attach_i2c(sc); 279 280 /* Need to set asynchronous blank during DDC write/read */ 281 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_USR_CTRL); 282 dac = DAC_READ(sc, FFB_DAC_VALUE); 283 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_USR_CTRL); 284 DAC_WRITE(sc, FFB_DAC_VALUE, dac | FFB_DAC_USR_CTRL_BLANK); 285 286 /* Some monitors don't respond first time */ 287 i = 0; 288 while (sc->sc_edid_data[1] == 0 && i++ < 3) 289 ddc_read_edid(&sc->sc_i2c, sc->sc_edid_data, EDID_DATA_LEN); 290 291 /* Remove asynchronous blank */ 292 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_USR_CTRL); 293 DAC_WRITE(sc, FFB_DAC_VALUE, dac); 294 295 if (edid_parse(&sc->sc_edid_data[0], &sc->sc_edid_info) != -1) { 296 sort_modes(sc->sc_edid_info.edid_modes, 297 &sc->sc_edid_info.edid_preferred_mode, 298 sc->sc_edid_info.edid_nmodes); 299 DPRINTF(("%s: EDID data:\n ", device_xname(sc->sc_dev))); 300 for (i = 0; i < EDID_DATA_LEN; i++) { 301 if (i && !(i % 32)) 302 DPRINTF(("\n ")); 303 if (i && !(i % 4)) 304 DPRINTF((" ")); 305 DPRINTF(("%02x", sc->sc_edid_data[i])); 306 } 307 DPRINTF(("\n")); 308 if (ffb_debug) 309 edid_print(&sc->sc_edid_info); 310 311 data = prop_data_create_data(sc->sc_edid_data, EDID_DATA_LEN); 312 prop_dictionary_set(device_properties(self), "EDID", data); 313 prop_object_release(data); 314 315 if (try_edid) 316 for (i = 0; i < sc->sc_edid_info.edid_nmodes; i++) { 317 if (ffb_set_vmode(sc, 318 &(sc->sc_edid_info.edid_modes[i]), btype, 319 &(sc->sc_width), &(sc->sc_height))) 320 break; 321 } 322 } else { 323 DPRINTF(("%s: No EDID data.\n", device_xname(sc->sc_dev))); 324 } 325 326 ffb_ras_init(sc); 327 328 ffb_blank(sc, WSDISPLAYIO_SVIDEO, &blank); 329 330 sc->sc_accel = ((device_cfdata(sc->sc_dev)->cf_flags & 331 FFB_CFFLAG_NOACCEL) == 0); 332 333 wsfont_init(); 334 335 vcons_init(&sc->vd, sc, &ffb_stdscreen, &ffb_accessops); 336 sc->vd.init_screen = ffb_init_screen; 337 ri = &ffb_console_screen.scr_ri; 338 339 /* we mess with ffb_console_screen only once */ 340 if (sc->sc_console) { 341 vcons_init_screen(&sc->vd, &ffb_console_screen, 1, &defattr); 342 SCREEN_VISIBLE((&ffb_console_screen)); 343 /* 344 * XXX we shouldn't use a global variable for the console 345 * screen 346 */ 347 sc->vd.active = &ffb_console_screen; 348 ffb_console_screen.scr_flags = VCONS_SCREEN_IS_STATIC; 349 } else { 350 if (ffb_console_screen.scr_ri.ri_rows == 0) { 351 /* do some minimal setup to avoid weirdnesses later */ 352 vcons_init_screen(&sc->vd, &ffb_console_screen, 1, &defattr); 353 } else 354 (*ri->ri_ops.allocattr)(ri, 0, 0, 0, &defattr); 355 } 356 357 ffb_stdscreen.nrows = ri->ri_rows; 358 ffb_stdscreen.ncols = ri->ri_cols; 359 ffb_stdscreen.textops = &ri->ri_ops; 360 ffb_stdscreen.capabilities = ri->ri_caps; 361 362 sc->sc_fb.fb_driver = &ffb_fbdriver; 363 sc->sc_fb.fb_type.fb_cmsize = 0; 364 sc->sc_fb.fb_type.fb_size = maxrow * sc->sc_linebytes; 365 sc->sc_fb.fb_type.fb_type = FBTYPE_CREATOR; 366 sc->sc_fb.fb_type.fb_width = sc->sc_width; 367 sc->sc_fb.fb_type.fb_depth = sc->sc_depth; 368 sc->sc_fb.fb_type.fb_height = sc->sc_height; 369 sc->sc_fb.fb_device = sc->sc_dev; 370 fb_attach(&sc->sc_fb, sc->sc_console); 371 372 ffb_clearscreen(sc); 373 374 if (sc->sc_console) { 375 wsdisplay_cnattach(&ffb_stdscreen, ri, 0, 0, defattr); 376 vcons_replay_msgbuf(&ffb_console_screen); 377 } 378 379 waa.console = sc->sc_console; 380 waa.scrdata = &ffb_screenlist; 381 waa.accessops = &ffb_accessops; 382 waa.accesscookie = &sc->vd; 383 config_found(sc->sc_dev, &waa, wsemuldisplaydevprint); 384 } 385 386 void 387 ffb_attach_i2c(struct ffb_softc *sc) 388 { 389 390 /* Fill in the i2c tag */ 391 sc->sc_i2c.ic_cookie = sc; 392 sc->sc_i2c.ic_acquire_bus = ffb_i2c_acquire_bus; 393 sc->sc_i2c.ic_release_bus = ffb_i2c_release_bus; 394 sc->sc_i2c.ic_send_start = ffb_i2c_send_start; 395 sc->sc_i2c.ic_send_stop = ffb_i2c_send_stop; 396 sc->sc_i2c.ic_initiate_xfer = ffb_i2c_initiate_xfer; 397 sc->sc_i2c.ic_read_byte = ffb_i2c_read_byte; 398 sc->sc_i2c.ic_write_byte = ffb_i2c_write_byte; 399 sc->sc_i2c.ic_exec = NULL; 400 } 401 402 int 403 ffb_ioctl(void *v, void *vs, u_long cmd, void *data, int flags, struct lwp *l) 404 { 405 struct vcons_data *vd = v; 406 struct ffb_softc *sc = vd->cookie; 407 struct wsdisplay_fbinfo *wdf; 408 struct vcons_screen *ms = vd->active; 409 410 DPRINTF(("ffb_ioctl: %s cmd _IO%s%s('%c', %lu)\n", 411 device_xname(sc->sc_dev), 412 (cmd & IOC_IN) ? "W" : "", (cmd & IOC_OUT) ? "R" : "", 413 (char)IOCGROUP(cmd), cmd & 0xff)); 414 415 switch (cmd) { 416 case FBIOGTYPE: 417 *(struct fbtype *)data = sc->sc_fb.fb_type; 418 break; 419 case FBIOGATTR: 420 #define fba ((struct fbgattr *)data) 421 fba->real_type = sc->sc_fb.fb_type.fb_type; 422 fba->owner = 0; /* XXX ??? */ 423 fba->fbtype = sc->sc_fb.fb_type; 424 fba->sattr.flags = 0; 425 fba->sattr.emu_type = sc->sc_fb.fb_type.fb_type; 426 fba->sattr.dev_specific[0] = -1; 427 fba->emu_types[0] = sc->sc_fb.fb_type.fb_type; 428 fba->emu_types[1] = -1; 429 #undef fba 430 break; 431 432 case FBIOGETCMAP: 433 case FBIOPUTCMAP: 434 return EIO; 435 436 case FBIOGVIDEO: 437 case FBIOSVIDEO: 438 return ffb_blank(sc, cmd == FBIOGVIDEO? 439 WSDISPLAYIO_GVIDEO : WSDISPLAYIO_SVIDEO, 440 (u_int *)data); 441 break; 442 case FBIOGCURSOR: 443 case FBIOSCURSOR: 444 /* the console driver is not using the hardware cursor */ 445 break; 446 case FBIOGCURPOS: 447 printf("%s: FBIOGCURPOS not implemented\n", 448 device_xname(sc->sc_dev)); 449 return EIO; 450 case FBIOSCURPOS: 451 printf("%s: FBIOSCURPOS not implemented\n", 452 device_xname(sc->sc_dev)); 453 return EIO; 454 case FBIOGCURMAX: 455 printf("%s: FBIOGCURMAX not implemented\n", 456 device_xname(sc->sc_dev)); 457 return EIO; 458 459 case WSDISPLAYIO_GTYPE: 460 *(u_int *)data = WSDISPLAY_TYPE_SUNFFB; 461 break; 462 case WSDISPLAYIO_SMODE: 463 { 464 if (sc->sc_mode != *(u_int *)data) { 465 sc->sc_mode = *(u_int *)data; 466 if ((sc->sc_mode == WSDISPLAYIO_MODE_EMUL) && 467 (sc->sc_locked == 0)) { 468 ffb_ras_init(sc); 469 vcons_redraw_screen(ms); 470 } else { 471 ffb_ras_wait(sc); 472 } 473 } 474 } 475 break; 476 case WSDISPLAYIO_GINFO: 477 wdf = (void *)data; 478 wdf->height = sc->sc_height; 479 wdf->width = sc->sc_width; 480 wdf->depth = 32; 481 wdf->cmsize = 256; /* XXX */ 482 break; 483 #ifdef WSDISPLAYIO_LINEBYTES 484 case WSDISPLAYIO_LINEBYTES: 485 *(u_int *)data = sc->sc_linebytes; 486 break; 487 #endif 488 case WSDISPLAYIO_GETCMAP: 489 break;/* XXX */ 490 491 case WSDISPLAYIO_PUTCMAP: 492 break;/* XXX */ 493 494 case WSDISPLAYIO_SVIDEO: 495 case WSDISPLAYIO_GVIDEO: 496 return(ffb_blank(sc, cmd, (u_int *)data)); 497 break; 498 499 case WSDISPLAYIO_GCURPOS: 500 case WSDISPLAYIO_SCURPOS: 501 case WSDISPLAYIO_GCURMAX: 502 case WSDISPLAYIO_GCURSOR: 503 case WSDISPLAYIO_SCURSOR: 504 return EIO; /* not supported yet */ 505 break; 506 507 case WSDISPLAYIO_GET_EDID: { 508 struct wsdisplayio_edid_info *d = data; 509 return wsdisplayio_get_edid(sc->sc_dev, d); 510 } 511 512 case WSDISPLAYIO_GET_FBINFO: { 513 struct wsdisplayio_fbinfo *fbi = data; 514 return wsdisplayio_get_fbinfo(&ms->scr_ri, fbi); 515 } 516 517 default: 518 return EPASSTHROUGH; 519 } 520 521 return (0); 522 } 523 524 /* blank/unblank the screen */ 525 static int 526 ffb_blank(struct ffb_softc *sc, u_long cmd, u_int *data) 527 { 528 struct vcons_screen *ms = sc->vd.active; 529 u_int val; 530 531 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_TGC); 532 val = DAC_READ(sc, FFB_DAC_VALUE); 533 534 switch (cmd) { 535 case WSDISPLAYIO_GVIDEO: 536 *data = val & 1; 537 return(0); 538 break; 539 case WSDISPLAYIO_SVIDEO: 540 if (*data == WSDISPLAYIO_VIDEO_OFF) 541 val &= ~1; 542 else if (*data == WSDISPLAYIO_VIDEO_ON) 543 val |= 1; 544 else 545 return(EINVAL); 546 break; 547 default: 548 return(EINVAL); 549 } 550 551 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_TGC); 552 DAC_WRITE(sc, FFB_DAC_VALUE, val); 553 554 if ((val & 1) && sc->sc_needredraw) { 555 if (ms != NULL) { 556 if ((sc->sc_mode == WSDISPLAYIO_MODE_EMUL) && 557 (sc->sc_locked == 0)) { 558 ffb_ras_init(sc); 559 vcons_redraw_screen(ms); 560 } 561 } 562 } 563 564 return(0); 565 } 566 567 paddr_t 568 ffb_mmap(void *vsc, void *vs, off_t off, int prot) 569 { 570 struct vcons_data *vd = vsc; 571 struct ffb_softc *sc = vd->cookie; 572 int i; 573 574 switch (sc->sc_mode) { 575 case WSDISPLAYIO_MODE_MAPPED: 576 for (i = 0; i < sc->sc_nreg; i++) { 577 /* Before this set? */ 578 if (off < sc->sc_addrs[i]) 579 continue; 580 /* After this set? */ 581 if (off >= (sc->sc_addrs[i] + sc->sc_sizes[i])) 582 continue; 583 584 return (bus_space_mmap(sc->sc_bt, sc->sc_addrs[i], 585 off - sc->sc_addrs[i], prot, BUS_SPACE_MAP_LINEAR)); 586 } 587 break; 588 #ifdef WSDISPLAYIO_MODE_DUMBFB 589 case WSDISPLAYIO_MODE_DUMBFB: 590 if (sc->sc_nreg < FFB_REG_DFB24) 591 break; 592 if (off >= 0 && off < sc->sc_sizes[FFB_REG_DFB24]) 593 return (bus_space_mmap(sc->sc_bt, 594 sc->sc_addrs[FFB_REG_DFB24], off, prot, 595 BUS_SPACE_MAP_LINEAR | BUS_SPACE_MAP_PREFETCHABLE)); 596 break; 597 #endif 598 } 599 return (-1); 600 } 601 602 void 603 ffb_ras_fifo_wait(struct ffb_softc *sc, int n) 604 { 605 int32_t cache = sc->sc_fifo_cache; 606 607 if (cache < n) { 608 do { 609 cache = FBC_READ(sc, FFB_FBC_UCSR); 610 cache = (cache & FBC_UCSR_FIFO_MASK) - 8; 611 } while (cache < n); 612 } 613 sc->sc_fifo_cache = cache - n; 614 } 615 616 void 617 ffb_ras_wait(struct ffb_softc *sc) 618 { 619 uint32_t ucsr, r; 620 621 while (1) { 622 ucsr = FBC_READ(sc, FFB_FBC_UCSR); 623 if ((ucsr & (FBC_UCSR_FB_BUSY|FBC_UCSR_RP_BUSY)) == 0) 624 break; 625 r = ucsr & (FBC_UCSR_READ_ERR | FBC_UCSR_FIFO_OVFL); 626 if (r != 0) 627 FBC_WRITE(sc, FFB_FBC_UCSR, r); 628 } 629 } 630 631 void 632 ffb_ras_init(struct ffb_softc *sc) 633 { 634 uint32_t fbc; 635 636 if (sc->sc_width > 1280) { 637 DPRINTF(("ffb_ras_init: high resolution.\n")); 638 fbc = FFB_FBC_WM_COMBINED | FFB_FBC_WE_FORCEON | 639 FFB_FBC_ZE_OFF | FFB_FBC_YE_OFF | FFB_FBC_XE_ON; 640 } else { 641 DPRINTF(("ffb_ras_init: standard resolution.\n")); 642 fbc = FFB_FBC_XE_OFF; 643 } 644 ffb_ras_fifo_wait(sc, 7); 645 DPRINTF(("WID: %08x\n", FBC_READ(sc, FFB_FBC_WID))); 646 FBC_WRITE(sc, FFB_FBC_WID, 0x0); 647 FBC_WRITE(sc, FFB_FBC_PPC, 648 FBC_PPC_VCE_DIS | FBC_PPC_TBE_OPAQUE | FBC_PPC_ACE_DIS | 649 FBC_PPC_APE_DIS | FBC_PPC_DCE_DIS | FBC_PPC_CS_CONST | 650 FBC_PPC_ABE_DIS | FBC_PPC_XS_WID); 651 652 fbc |= FFB_FBC_WB_A | FFB_FBC_RB_A | FFB_FBC_SB_BOTH | 653 FFB_FBC_RGBE_MASK; 654 DPRINTF(("%s: fbc is %08x\n", __func__, fbc)); 655 FBC_WRITE(sc, FFB_FBC_FBC, fbc); 656 FBC_WRITE(sc, FFB_FBC_ROP, FBC_ROP_NEW); 657 FBC_WRITE(sc, FFB_FBC_DRAWOP, FBC_DRAWOP_RECTANGLE); 658 FBC_WRITE(sc, FFB_FBC_PMASK, 0xffffffff); 659 FBC_WRITE(sc, FFB_FBC_FONTINC, 0x10000); 660 ffb_ras_fifo_wait(sc, 5); 661 sc->sc_fg_cache = 0; 662 FBC_WRITE(sc, FFB_FBC_FG, sc->sc_fg_cache); 663 sc->sc_bg_cache = 0; 664 FBC_WRITE(sc, FFB_FBC_BG, sc->sc_bg_cache); 665 FBC_WRITE(sc, FFB_FBC_BLENDC, FFB_BLENDC_FORCE_ONE | 666 FFB_BLENDC_DF_ONE_M_A | 667 FFB_BLENDC_SF_A); 668 FBC_WRITE(sc, FFB_FBC_BLENDC1, 0); 669 FBC_WRITE(sc, FFB_FBC_BLENDC2, 0); 670 ffb_ras_wait(sc); 671 } 672 673 void 674 ffb_ras_eraserows(void *cookie, int row, int n, long attr) 675 { 676 struct rasops_info *ri = cookie; 677 struct vcons_screen *scr = ri->ri_hw; 678 struct ffb_softc *sc = scr->scr_cookie; 679 680 if (row < 0) { 681 n += row; 682 row = 0; 683 } 684 if (row + n > ri->ri_rows) 685 n = ri->ri_rows - row; 686 if (n <= 0) 687 return; 688 689 ffb_ras_fill(sc); 690 ffb_ras_setfg(sc, ri->ri_devcmap[(attr >> 16) & 0xf]); 691 ffb_ras_fifo_wait(sc, 4); 692 if ((n == ri->ri_rows) && (ri->ri_flg & RI_FULLCLEAR)) { 693 FBC_WRITE(sc, FFB_FBC_BY, 0); 694 FBC_WRITE(sc, FFB_FBC_BX, 0); 695 FBC_WRITE(sc, FFB_FBC_BH, ri->ri_height); 696 FBC_WRITE(sc, FFB_FBC_BW, ri->ri_width); 697 ri->ri_flg &= ~RI_CURSOR; 698 } else { 699 row *= ri->ri_font->fontheight; 700 FBC_WRITE(sc, FFB_FBC_BY, ri->ri_yorigin + row); 701 FBC_WRITE(sc, FFB_FBC_BX, ri->ri_xorigin); 702 FBC_WRITE(sc, FFB_FBC_BH, n * ri->ri_font->fontheight); 703 FBC_WRITE(sc, FFB_FBC_BW, ri->ri_emuwidth); 704 } 705 SYNC; 706 } 707 708 void 709 ffb_ras_erasecols(void *cookie, int row, int col, int n, long attr) 710 { 711 struct rasops_info *ri = cookie; 712 struct vcons_screen *scr = ri->ri_hw; 713 struct ffb_softc *sc = scr->scr_cookie; 714 715 if ((row < 0) || (row >= ri->ri_rows)) 716 return; 717 if (col < 0) { 718 n += col; 719 col = 0; 720 } 721 if (col + n > ri->ri_cols) 722 n = ri->ri_cols - col; 723 if (n <= 0) 724 return; 725 726 n *= ri->ri_font->fontwidth; 727 col *= ri->ri_font->fontwidth; 728 row *= ri->ri_font->fontheight; 729 730 ffb_ras_fill(sc); 731 ffb_ras_setfg(sc, ri->ri_devcmap[(attr >> 16) & 0xf]); 732 ffb_ras_fifo_wait(sc, 4); 733 FBC_WRITE(sc, FFB_FBC_BY, ri->ri_yorigin + row); 734 FBC_WRITE(sc, FFB_FBC_BX, ri->ri_xorigin + col); 735 FBC_WRITE(sc, FFB_FBC_BH, ri->ri_font->fontheight); 736 FBC_WRITE(sc, FFB_FBC_BW, n); 737 SYNC; 738 } 739 740 void 741 ffb_ras_fill(struct ffb_softc *sc) 742 { 743 ffb_ras_fifo_wait(sc, 3); 744 FBC_WRITE(sc, FFB_FBC_PPC, 745 FBC_PPC_VCE_DIS | FBC_PPC_TBE_OPAQUE | FBC_PPC_ACE_DIS | 746 FBC_PPC_APE_DIS | FBC_PPC_DCE_DIS | FBC_PPC_CS_CONST | 747 FBC_PPC_ABE_DIS | FBC_PPC_XS_WID); 748 FBC_WRITE(sc, FFB_FBC_ROP, FBC_ROP_NEW); 749 FBC_WRITE(sc, FFB_FBC_DRAWOP, FBC_DRAWOP_RECTANGLE); 750 SYNC; 751 } 752 753 void 754 ffb_ras_invert(struct ffb_softc *sc) 755 { 756 ffb_ras_fifo_wait(sc, 3); 757 FBC_WRITE(sc, FFB_FBC_PPC, 758 FBC_PPC_VCE_DIS | FBC_PPC_TBE_OPAQUE | FBC_PPC_ACE_DIS | 759 FBC_PPC_APE_DIS | FBC_PPC_DCE_DIS | FBC_PPC_CS_CONST | 760 FBC_PPC_ABE_DIS | FBC_PPC_XS_WID); 761 FBC_WRITE(sc, FFB_FBC_ROP, FBC_ROP_INVERT); 762 FBC_WRITE(sc, FFB_FBC_DRAWOP, FBC_DRAWOP_RECTANGLE); 763 SYNC; 764 } 765 766 void 767 ffb_ras_copyrows(void *cookie, int src, int dst, int n) 768 { 769 struct rasops_info *ri = cookie; 770 struct vcons_screen *scr = ri->ri_hw; 771 struct ffb_softc *sc = scr->scr_cookie; 772 773 if (dst == src) 774 return; 775 if (src < 0) { 776 n += src; 777 src = 0; 778 } 779 if ((src + n) > ri->ri_rows) 780 n = ri->ri_rows - src; 781 if (dst < 0) { 782 n += dst; 783 dst = 0; 784 } 785 if ((dst + n) > ri->ri_rows) 786 n = ri->ri_rows - dst; 787 if (n <= 0) 788 return; 789 n *= ri->ri_font->fontheight; 790 src *= ri->ri_font->fontheight; 791 dst *= ri->ri_font->fontheight; 792 793 ffb_ras_fifo_wait(sc, 9); 794 FBC_WRITE(sc, FFB_FBC_PPC, 795 FBC_PPC_VCE_DIS | FBC_PPC_TBE_OPAQUE | FBC_PPC_ACE_DIS | 796 FBC_PPC_APE_DIS | FBC_PPC_DCE_DIS | FBC_PPC_CS_CONST | 797 FBC_PPC_ABE_DIS | FBC_PPC_XS_WID); 798 FBC_WRITE(sc, FFB_FBC_ROP, FBC_ROP_OLD | (FBC_ROP_OLD << 8)); 799 FBC_WRITE(sc, FFB_FBC_DRAWOP, FBC_DRAWOP_VSCROLL); 800 FBC_WRITE(sc, FFB_FBC_BY, ri->ri_yorigin + src); 801 FBC_WRITE(sc, FFB_FBC_BX, ri->ri_xorigin); 802 FBC_WRITE(sc, FFB_FBC_DY, ri->ri_yorigin + dst); 803 FBC_WRITE(sc, FFB_FBC_DX, ri->ri_xorigin); 804 FBC_WRITE(sc, FFB_FBC_BH, n); 805 FBC_WRITE(sc, FFB_FBC_BW, ri->ri_emuwidth); 806 SYNC; 807 } 808 809 static void 810 ffb_ras_setfg(struct ffb_softc *sc, int32_t fg) 811 { 812 ffb_ras_fifo_wait(sc, 1); 813 if (fg == sc->sc_fg_cache) 814 return; 815 sc->sc_fg_cache = fg; 816 FBC_WRITE(sc, FFB_FBC_FG, fg); 817 SYNC; 818 } 819 820 static void 821 ffb_ras_setbg(struct ffb_softc *sc, int32_t bg) 822 { 823 ffb_ras_fifo_wait(sc, 1); 824 if (bg == sc->sc_bg_cache) 825 return; 826 sc->sc_bg_cache = bg; 827 FBC_WRITE(sc, FFB_FBC_BG, bg); 828 SYNC; 829 } 830 831 /* frame buffer generic driver support functions */ 832 static void 833 ffbfb_unblank(device_t dev) 834 { 835 struct ffb_softc *sc = device_private(dev); 836 struct vcons_screen *ms = sc->vd.active; 837 u_int on = 1; 838 int redraw = 0; 839 840 ffb_ras_init(sc); 841 if (sc->sc_locked) { 842 sc->sc_locked = 0; 843 redraw = 1; 844 } 845 846 ffb_blank(sc, WSDISPLAYIO_SVIDEO, &on); 847 #if 0 848 if ((sc->vd.active != &ffb_console_screen) && 849 (ffb_console_screen.scr_flags & VCONS_SCREEN_IS_STATIC)) { 850 /* 851 * force-switch to the console screen. 852 * Caveat: the higher layer will think we're still on the 853 * other screen 854 */ 855 856 SCREEN_INVISIBLE(sc->vd.active); 857 sc->vd.active = &ffb_console_screen; 858 SCREEN_VISIBLE(sc->vd.active); 859 ms = sc->vd.active; 860 redraw = 1; 861 } 862 #endif 863 if (redraw) { 864 vcons_redraw_screen(ms); 865 } 866 } 867 868 int 869 ffbfb_open(dev_t dev, int flags, int mode, struct lwp *l) 870 { 871 struct ffb_softc *sc; 872 873 sc = device_lookup_private(&ffb_cd, minor(dev)); 874 if (sc == NULL) 875 return ENXIO; 876 877 sc->sc_locked = 1; 878 return 0; 879 } 880 881 int 882 ffbfb_close(dev_t dev, int flags, int mode, struct lwp *l) 883 { 884 struct ffb_softc *sc = device_lookup_private(&ffb_cd, minor(dev)); 885 struct vcons_screen *ms = sc->vd.active; 886 887 sc->sc_locked = 0; 888 if (ms != NULL) { 889 if ((sc->sc_mode == WSDISPLAYIO_MODE_EMUL) && 890 (sc->sc_locked == 0)) { 891 ffb_ras_init(sc); 892 vcons_redraw_screen(ms); 893 } 894 } 895 return 0; 896 } 897 898 int 899 ffbfb_ioctl(dev_t dev, u_long cmd, void *data, int flags, struct lwp *l) 900 { 901 struct ffb_softc *sc = device_lookup_private(&ffb_cd, minor(dev)); 902 903 return ffb_ioctl(&sc->vd, NULL, cmd, data, flags, l); 904 } 905 906 paddr_t 907 ffbfb_mmap(dev_t dev, off_t off, int prot) 908 { 909 struct ffb_softc *sc = device_lookup_private(&ffb_cd, minor(dev)); 910 uint64_t size; 911 int i, reg; 912 off_t o; 913 914 /* 915 * off is a magic cookie (see xfree86/drivers/sunffb/ffb.h), 916 * which we map to an index into the "reg" property, and use 917 * our copy of the firmware data as arguments for the real 918 * mapping. 919 */ 920 static struct { unsigned long voff; int reg; long flags; } map[] = { 921 { 0x00000000, FFB_REG_SFB8R, BUS_SPACE_MAP_PREFETCHABLE }, 922 { 0x00400000, FFB_REG_SFB8G, BUS_SPACE_MAP_PREFETCHABLE }, 923 { 0x00800000, FFB_REG_SFB8B, BUS_SPACE_MAP_PREFETCHABLE }, 924 { 0x00c00000, FFB_REG_SFB8X, BUS_SPACE_MAP_PREFETCHABLE }, 925 { 0x01000000, FFB_REG_SFB32, BUS_SPACE_MAP_PREFETCHABLE }, 926 { 0x02000000, FFB_REG_SFB64, BUS_SPACE_MAP_PREFETCHABLE }, 927 { 0x04000000, FFB_REG_FBC, 0 }, 928 { 0x04004000, FFB_REG_DFB8R, BUS_SPACE_MAP_PREFETCHABLE }, 929 { 0x04404000, FFB_REG_DFB8G, BUS_SPACE_MAP_PREFETCHABLE }, 930 { 0x04804000, FFB_REG_DFB8B, BUS_SPACE_MAP_PREFETCHABLE }, 931 { 0x04c04000, FFB_REG_DFB8X, BUS_SPACE_MAP_PREFETCHABLE }, 932 { 0x05004000, FFB_REG_DFB24, BUS_SPACE_MAP_PREFETCHABLE }, 933 { 0x06004000, FFB_REG_DFB32, BUS_SPACE_MAP_PREFETCHABLE }, 934 { 0x07004000, FFB_REG_DFB422A, BUS_SPACE_MAP_PREFETCHABLE }, 935 { 0x0bc06000, FFB_REG_DAC, 0 }, 936 { 0x0bc08000, FFB_REG_PROM, 0 }, 937 { 0x0bc18000, 0, 0 } 938 }; 939 940 /* special value "FFB_EXP_VOFF" - not backed by any "reg" entry */ 941 if (off == 0x0bc18000) 942 return bus_space_mmap(sc->sc_bt, sc->sc_addrs[FFB_REG_PROM], 943 0x00200000, prot, BUS_SPACE_MAP_LINEAR); 944 945 /* 946 * FFB_VOFF_FBC_KREGS - used by afbinit to upload firmware. We should 947 * probably mmap them only on afb boards 948 */ 949 if ((off >= 0x0bc04000) && (off < 0x0bc06000)) 950 return bus_space_mmap(sc->sc_bt, sc->sc_addrs[FFB_REG_PROM], 951 0x00610000 + (off - 0x0bc04000), prot, 952 BUS_SPACE_MAP_LINEAR); 953 954 #define NELEMS(arr) (sizeof(arr)/sizeof((arr)[0])) 955 956 /* the map is ordered by voff */ 957 for (i = 0; i < NELEMS(map)-1; i++) { 958 reg = map[i].reg; 959 /* the number of entries in reg seems to vary */ 960 if (reg < sc->sc_nreg) { 961 size = min((map[i + 1].voff - map[i].voff), 962 sc->sc_sizes[reg]); 963 if ((off >= map[i].voff) && 964 (off < (map[i].voff + size))) { 965 o = off - map[i].voff; 966 return bus_space_mmap(sc->sc_bt, 967 sc->sc_addrs[reg], o, prot, 968 BUS_SPACE_MAP_LINEAR | map[i].flags); 969 } 970 } 971 } 972 973 return -1; 974 } 975 976 void 977 ffb_clearscreen(struct ffb_softc *sc) 978 { 979 struct rasops_info *ri = &ffb_console_screen.scr_ri; 980 ffb_ras_fill(sc); 981 ffb_ras_setfg(sc, ri->ri_devcmap[WS_DEFAULT_BG]); 982 ffb_ras_fifo_wait(sc, 4); 983 FBC_WRITE(sc, FFB_FBC_BY, 0); 984 FBC_WRITE(sc, FFB_FBC_BX, 0); 985 FBC_WRITE(sc, FFB_FBC_BH, sc->sc_height); 986 FBC_WRITE(sc, FFB_FBC_BW, sc->sc_width); 987 } 988 989 void 990 ffb_cursor(void *cookie, int on, int row, int col) 991 { 992 struct rasops_info *ri = cookie; 993 struct vcons_screen *scr; 994 struct ffb_softc *sc; 995 int x, y, wi, he; 996 997 if (cookie != NULL) { 998 scr = ri->ri_hw; 999 sc = scr->scr_cookie; 1000 1001 wi = ri->ri_font->fontwidth; 1002 he = ri->ri_font->fontheight; 1003 1004 if (sc->sc_mode == WSDISPLAYIO_MODE_EMUL) { 1005 1006 if (ri->ri_flg & RI_CURSOR) { 1007 1008 /* remove cursor */ 1009 x = ri->ri_ccol * wi + ri->ri_xorigin; 1010 y = ri->ri_crow * he + ri->ri_yorigin; 1011 1012 ffb_ras_invert(sc); 1013 ffb_ras_fifo_wait(sc, 4); 1014 FBC_WRITE(sc, FFB_FBC_BY, y); 1015 FBC_WRITE(sc, FFB_FBC_BX, x); 1016 FBC_WRITE(sc, FFB_FBC_BH, he); 1017 FBC_WRITE(sc, FFB_FBC_BW, wi); 1018 1019 ri->ri_flg &= ~RI_CURSOR; 1020 } 1021 ri->ri_crow = row; 1022 ri->ri_ccol = col; 1023 if (on) 1024 { 1025 x = ri->ri_ccol * wi + ri->ri_xorigin; 1026 y = ri->ri_crow * he + ri->ri_yorigin; 1027 1028 ffb_ras_invert(sc); 1029 ffb_ras_fifo_wait(sc, 4); 1030 FBC_WRITE(sc, FFB_FBC_BY, y); 1031 FBC_WRITE(sc, FFB_FBC_BX, x); 1032 FBC_WRITE(sc, FFB_FBC_BH, he); 1033 FBC_WRITE(sc, FFB_FBC_BW, wi); 1034 1035 ri->ri_flg |= RI_CURSOR; 1036 } 1037 } else { 1038 ri->ri_crow = row; 1039 ri->ri_ccol = col; 1040 ri->ri_flg &= ~RI_CURSOR; 1041 } 1042 } 1043 } 1044 1045 /* mono bitmap font */ 1046 void 1047 ffb_putchar_mono(void *cookie, int row, int col, u_int c, long attr) 1048 { 1049 struct rasops_info *ri = cookie; 1050 struct vcons_screen *scr = ri->ri_hw; 1051 struct wsdisplay_font *font = PICK_FONT(ri, c); 1052 struct ffb_softc *sc = scr->scr_cookie; 1053 void *data; 1054 uint32_t fg, bg; 1055 int i; 1056 int x, y, wi, he; 1057 1058 if (sc->sc_mode != WSDISPLAYIO_MODE_EMUL) 1059 return; 1060 1061 wi = font->fontwidth; 1062 he = font->fontheight; 1063 1064 if (!CHAR_IN_FONT(c, font)) 1065 return; 1066 1067 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 1068 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 1069 x = ri->ri_xorigin + col * wi; 1070 y = ri->ri_yorigin + row * he; 1071 1072 data = WSFONT_GLYPH(c, font); 1073 1074 ffb_ras_setbg(sc, bg); 1075 ffb_ras_setfg(sc, fg); 1076 ffb_ras_fifo_wait(sc, 4); 1077 FBC_WRITE(sc, FFB_FBC_ROP, FBC_ROP_NEW); 1078 FBC_WRITE(sc, FFB_FBC_FONTXY, (y << 16) | x); 1079 FBC_WRITE(sc, FFB_FBC_FONTW, wi); 1080 FBC_WRITE(sc, FFB_FBC_PPC, 1081 FBC_PPC_VCE_DIS | FBC_PPC_TBE_OPAQUE | FBC_PPC_ACE_DIS | 1082 FBC_PPC_APE_DIS | FBC_PPC_DCE_DIS | FBC_PPC_CS_CONST | 1083 FBC_PPC_ABE_DIS | FBC_PPC_XS_WID); 1084 1085 switch (font->stride) { 1086 case 1: { 1087 uint8_t *data8 = data; 1088 uint32_t reg; 1089 if (attr & WSATTR_UNDERLINE) { 1090 for (i = 0; i < he - 2; i++) { 1091 reg = *data8; 1092 FBC_WRITE(sc, FFB_FBC_FONT, reg << 24); 1093 data8++; 1094 } 1095 FBC_WRITE(sc, FFB_FBC_FONT, 0xff000000); 1096 data8++; 1097 reg = *data8; 1098 FBC_WRITE(sc, FFB_FBC_FONT, reg << 24); 1099 } else { 1100 for (i = 0; i < he; i++) { 1101 reg = *data8; 1102 FBC_WRITE(sc, FFB_FBC_FONT, reg << 24); 1103 data8++; 1104 } 1105 } 1106 break; 1107 } 1108 case 2: { 1109 uint16_t *data16 = data; 1110 uint32_t reg; 1111 if (attr & WSATTR_UNDERLINE) { 1112 for (i = 0; i < he - 2; i++) { 1113 reg = *data16; 1114 FBC_WRITE(sc, FFB_FBC_FONT, reg << 16); 1115 data16++; 1116 } 1117 FBC_WRITE(sc, FFB_FBC_FONT, 0xffff0000); 1118 data16++; 1119 reg = *data16; 1120 FBC_WRITE(sc, FFB_FBC_FONT, reg << 16); 1121 } else { 1122 for (i = 0; i < he; i++) { 1123 reg = *data16; 1124 FBC_WRITE(sc, FFB_FBC_FONT, reg << 16); 1125 data16++; 1126 } 1127 } 1128 break; 1129 } 1130 } 1131 } 1132 1133 /* alpha font */ 1134 void 1135 ffb_putchar_aa(void *cookie, int row, int col, u_int c, long attr) 1136 { 1137 struct rasops_info *ri = cookie; 1138 struct vcons_screen *scr = ri->ri_hw; 1139 struct wsdisplay_font *font = PICK_FONT(ri, c); 1140 struct ffb_softc *sc = scr->scr_cookie; 1141 volatile uint32_t *dest, *ddest; 1142 uint8_t *data8; 1143 uint32_t fg, bg; 1144 int i; 1145 int x, y, wi, he; 1146 uint32_t alpha = 0x80; 1147 int j; 1148 1149 if (sc->sc_mode != WSDISPLAYIO_MODE_EMUL) 1150 return; 1151 1152 wi = font->fontwidth; 1153 he = font->fontheight; 1154 1155 if (!CHAR_IN_FONT(c, font)) 1156 return; 1157 1158 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 1159 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 1160 x = ri->ri_xorigin + col * wi; 1161 y = ri->ri_yorigin + row * he; 1162 1163 data8 = WSFONT_GLYPH(c, font); 1164 1165 /* first we erase the background */ 1166 ffb_ras_fill(sc); 1167 ffb_ras_setfg(sc, bg); 1168 ffb_ras_fifo_wait(sc, 4); 1169 FBC_WRITE(sc, FFB_FBC_BY, y); 1170 FBC_WRITE(sc, FFB_FBC_BX, x); 1171 FBC_WRITE(sc, FFB_FBC_BH, he); 1172 FBC_WRITE(sc, FFB_FBC_BW, wi); 1173 1174 /* if we draw a space we're done */ 1175 if (c == ' ') goto out; 1176 1177 /* now enable alpha blending */ 1178 ffb_ras_setfg(sc, fg); 1179 ffb_ras_fifo_wait(sc, 2); 1180 FBC_WRITE(sc, FFB_FBC_ROP, FBC_ROP_NEW); 1181 1182 FBC_WRITE(sc, FFB_FBC_PPC, 1183 FBC_PPC_VCE_DIS | FBC_PPC_TBE_OPAQUE | FBC_PPC_ACE_DIS | 1184 FBC_PPC_APE_DIS | FBC_PPC_DCE_DIS | FBC_PPC_CS_CONST | 1185 FBC_PPC_ABE_ENA | FBC_PPC_XS_VAR); 1186 /* 1187 * we have to wait for both the rectangle drawing op above and the 1188 * FFB_FBC_PPC write to finish before mucking around in the SFB aperture 1189 */ 1190 ffb_ras_wait(sc); 1191 1192 /* ... and draw the character */ 1193 dest = sc->sc_sfb32 + (y << 11) + x; 1194 for (i = 0; i < he; i++) { 1195 ddest = dest; 1196 for (j = 0; j < wi; j++) { 1197 alpha = *data8; 1198 /* 1199 * We set the colour source to constant above so we only 1200 * have to write the alpha channel here and the colour 1201 * comes from the FG register. It would be nice if we 1202 * could just use the SFB8X aperture and memcpy() the 1203 * alpha map line by line but for some strange reason 1204 * that will take colour info from the framebuffer even 1205 * if we set the FBC_PPC_CS_CONST bit above. 1206 */ 1207 *ddest = alpha << 24; 1208 data8++; 1209 ddest++; 1210 } 1211 dest += 2048; 1212 } 1213 out: 1214 /* check if we need to draw an underline */ 1215 if (attr & WSATTR_UNDERLINE) { 1216 dest = sc->sc_sfb32 + ((y + he - 2) << 11) + x; 1217 for (i = 0; i < wi; i++) { 1218 *dest = 0xa0000000; 1219 dest++; 1220 } 1221 } 1222 } 1223 1224 int 1225 ffb_allocattr(void *cookie, int fg, int bg, int flags, long *attrp) 1226 { 1227 if ((fg == 0) && (bg == 0)) 1228 { 1229 fg = WS_DEFAULT_FG; 1230 bg = WS_DEFAULT_BG; 1231 } 1232 if (flags & WSATTR_REVERSE) { 1233 *attrp = (bg & 0xff) << 24 | (fg & 0xff) << 16; 1234 } else 1235 *attrp = (fg & 0xff) << 24 | (bg & 0xff) << 16; 1236 if (flags & WSATTR_UNDERLINE) 1237 *attrp |= WSATTR_UNDERLINE; 1238 return 0; 1239 } 1240 1241 void 1242 ffb_init_screen(void *cookie, struct vcons_screen *scr, 1243 int existing, long *defattr) 1244 { 1245 struct ffb_softc *sc = cookie; 1246 struct rasops_info *ri = &scr->scr_ri; 1247 1248 ri->ri_depth = 32; 1249 ri->ri_width = sc->sc_width; 1250 ri->ri_height = sc->sc_height; 1251 ri->ri_stride = sc->sc_linebytes; 1252 ri->ri_flg = RI_CENTER | RI_ENABLE_ALPHA | RI_PREFER_ALPHA; 1253 1254 /* 1255 * we can't accelerate copycols() so instead of falling back to 1256 * software use vcons' putchar() based implementation 1257 */ 1258 scr->scr_flags |= VCONS_NO_COPYCOLS; 1259 #ifdef VCONS_DRAW_INTR 1260 scr->scr_flags |= VCONS_DONT_READ; 1261 #endif 1262 DPRINTF(("ffb_init_screen: addr: %08lx\n",(ulong)ri->ri_bits)); 1263 1264 /* explicitly request BGR in case the default changes */ 1265 ri->ri_rnum = 8; 1266 ri->ri_gnum = 8; 1267 ri->ri_bnum = 8; 1268 ri->ri_rpos = 0; 1269 ri->ri_gpos = 8; 1270 ri->ri_bpos = 16; 1271 1272 rasops_init(ri, 0, 0); 1273 ri->ri_caps = WSSCREEN_WSCOLORS | WSSCREEN_UNDERLINE | WSSCREEN_REVERSE; 1274 rasops_reconfig(ri, sc->sc_height / ri->ri_font->fontheight, 1275 sc->sc_width / ri->ri_font->fontwidth); 1276 1277 /* enable acceleration */ 1278 ri->ri_ops.copyrows = ffb_ras_copyrows; 1279 ri->ri_ops.eraserows = ffb_ras_eraserows; 1280 ri->ri_ops.erasecols = ffb_ras_erasecols; 1281 ri->ri_ops.cursor = ffb_cursor; 1282 ri->ri_ops.allocattr = ffb_allocattr; 1283 if (FONT_IS_ALPHA(ri->ri_font)) { 1284 ri->ri_ops.putchar = ffb_putchar_aa; 1285 } else 1286 ri->ri_ops.putchar = ffb_putchar_mono; 1287 } 1288 1289 /* I2C bitbanging */ 1290 static void ffb_i2cbb_set_bits(void *cookie, uint32_t bits) 1291 { 1292 struct ffb_softc *sc = cookie; 1293 1294 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_CFG_MPDATA); 1295 DAC_WRITE(sc, FFB_DAC_VALUE, bits); 1296 } 1297 1298 static void ffb_i2cbb_set_dir(void *cookie, uint32_t dir) 1299 { 1300 /* Nothing to do */ 1301 } 1302 1303 static uint32_t ffb_i2cbb_read(void *cookie) 1304 { 1305 struct ffb_softc *sc = cookie; 1306 uint32_t bits; 1307 1308 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_CFG_MPSENSE); 1309 bits = DAC_READ(sc, FFB_DAC_VALUE); 1310 1311 return bits; 1312 } 1313 1314 /* higher level I2C stuff */ 1315 static int 1316 ffb_i2c_acquire_bus(void *cookie, int flags) 1317 { 1318 /* private bus */ 1319 return (0); 1320 } 1321 1322 static void 1323 ffb_i2c_release_bus(void *cookie, int flags) 1324 { 1325 /* private bus */ 1326 } 1327 1328 static int 1329 ffb_i2c_send_start(void *cookie, int flags) 1330 { 1331 return (i2c_bitbang_send_start(cookie, flags, &ffb_i2cbb_ops)); 1332 } 1333 1334 static int 1335 ffb_i2c_send_stop(void *cookie, int flags) 1336 { 1337 1338 return (i2c_bitbang_send_stop(cookie, flags, &ffb_i2cbb_ops)); 1339 } 1340 1341 static int 1342 ffb_i2c_initiate_xfer(void *cookie, i2c_addr_t addr, int flags) 1343 { 1344 /* 1345 * for some reason i2c_bitbang_initiate_xfer left-shifts 1346 * the I2C-address and then sets the direction bit 1347 */ 1348 return (i2c_bitbang_initiate_xfer(cookie, addr, flags, 1349 &ffb_i2cbb_ops)); 1350 } 1351 1352 static int 1353 ffb_i2c_read_byte(void *cookie, uint8_t *valp, int flags) 1354 { 1355 return (i2c_bitbang_read_byte(cookie, valp, flags, &ffb_i2cbb_ops)); 1356 } 1357 1358 static int 1359 ffb_i2c_write_byte(void *cookie, uint8_t val, int flags) 1360 { 1361 return (i2c_bitbang_write_byte(cookie, val, flags, &ffb_i2cbb_ops)); 1362 } 1363 1364 1365 #define TVC_READ_LIMIT 100000 1366 int 1367 ffb_tgc_disable(struct ffb_softc *sc) 1368 { 1369 int i; 1370 1371 /* Is the timing generator disabled? */ 1372 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_TGC); 1373 if (!(DAC_READ(sc, FFB_DAC_VALUE) & FFB_DAC_TGC_TIMING_ENABLE)) 1374 return 1; 1375 1376 /* If not, disable it when the vertical counter reaches 0 */ 1377 for (i = 0; i < TVC_READ_LIMIT; i++) { 1378 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_TVC); 1379 if (!DAC_READ(sc, FFB_DAC_VALUE)) { 1380 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_TGC); 1381 DAC_WRITE(sc, FFB_DAC_VALUE, 0); 1382 return 1; 1383 } 1384 } 1385 return 0; 1386 } 1387 1388 /* 1389 * PLL Control Register values: 1390 * M)ultiplier = bits 0:6 + 1 1391 * D)ivisor = bits 7:10 + 1 1392 * P)ost divisor = bits 11:13 (000 = 1, 001 = 2, 010 = 4, 011 = 8) 1393 * Frequency = 13.5 * M / D / P 1394 */ 1395 #define FFB_PLL_FREQ 13500000 1396 void 1397 ffb_get_pclk(int request, uint32_t *pll, int *diff) 1398 { 1399 int m, d, p, f, hex = 0, curdiff; 1400 1401 *diff = 100000000; 1402 1403 for (m = 32; m <= 80; m++) { 1404 for (d = 4; d <= 11; d++) { 1405 for (p = 1; p <= 8; p = p << 1) { 1406 switch (p) { 1407 case 1: 1408 hex = 0x4000 + (d << 7) + m; 1409 break; 1410 case 2: 1411 hex = 0x4800 + (d << 7) + m; 1412 break; 1413 case 4: 1414 hex = 0x5000 + (d << 7) + m; 1415 break; 1416 case 8: 1417 hex = 0x6000 + (d << 7) + m; 1418 break; 1419 } 1420 f = 13500000 * m / d / p; 1421 if (f == request) { 1422 *diff = 0; 1423 *pll = hex; 1424 return; 1425 } else { 1426 curdiff = abs(request - f); 1427 if (curdiff < *diff) { 1428 *diff = curdiff; 1429 *pll = hex; 1430 } 1431 } 1432 } 1433 } 1434 } 1435 } 1436 1437 /* 1438 * Details of the FFB RAMDAC are contained in the Brooktree BT497/498 1439 * and in the Connexant BT497A/498A documentation. 1440 * 1441 * VESA timings to FFB register conversion: 1442 * If interleave = 4/2:1 then x = 2, if interleave = 8/2:1 then x = 4 1443 * VBE = VBS - vres = (sync pulse - 1) + back porch 1444 * VBS = VSS - front porch = (sync pulse - 1) + back porch + vres 1445 * VSE = sync pulse - 1 1446 * VSS = (sync pulse - 1) + back porch + vres + front porch 1447 * HRE = HSS - HSE - 1 1448 * HBE = (sync pulse + back porch) / x - 1 1449 * HBS = (sync pulse + back porch + hres) / x - 1 1450 * HSE = sync pulse / x - 1 1451 * HSS = (sync pulse + back porch + hres + front porch) / x - 1 1452 * HCE = HBS - 4 1453 * HCS = HBE - 4 1454 * EPE = EIE = EIS = 0 (for all non-interlaced modes) 1455 * 1456 * Note, that 8/2:1 Single Buffered Interleaving is only supported by the 1457 * double-buffered FFB (Creator3D), and at higher resolutions than 1280x1024 1458 * 1459 * Note, that the timing generator should be disabled and re-enabled when the 1460 * the timing parameter registers are being programmed. Stopping the timing 1461 * generator should only be done when the vertical counter is zero. 1462 */ 1463 #define DIVIDE(x,y) (((x) + ((y) / 2)) / (y)) 1464 int 1465 ffb_set_vmode(struct ffb_softc *sc, struct videomode *mode, int btype, 1466 int *hres, int *vres) 1467 { 1468 int diff; 1469 uint32_t fp, sp, bp, x; 1470 uint32_t pll, pfc, ucl, dcl, tgc; 1471 uint32_t vbe, vbs, vse, vss, hre, hbe, hbs, hse, hss, hce, hcs; 1472 uint32_t epe, eie, eis; 1473 uint32_t fbcfg0; 1474 1475 DPRINTF(("ffb_set_vmode: %dx%d@%d", mode->hdisplay, mode->vdisplay, 1476 DIVIDE(DIVIDE(mode->dot_clock * 1000, 1477 mode->htotal), mode->vtotal))); 1478 DPRINTF((" (%d %d %d %d %d %d %d", 1479 mode->dot_clock, mode->hsync_start, mode->hsync_end, mode->htotal, 1480 mode->vsync_start, mode->vsync_end, mode->vtotal)); 1481 DPRINTF((" %s%sH %s%sV)\n", 1482 mode->flags & VID_PHSYNC ? "+" : "", 1483 mode->flags & VID_NHSYNC ? "-" : "", 1484 mode->flags & VID_PVSYNC ? "+" : "", 1485 mode->flags & VID_NVSYNC ? "-" : "")); 1486 1487 /* We don't handle interlaced or doublescan (yet) */ 1488 if ((mode->flags & VID_INTERLACE) || (mode->flags & VID_DBLSCAN)) 1489 return 0; 1490 1491 /* Only Creator3D can be set to > 1280x1024 */ 1492 if(((sc->sc_type == FFB_CREATOR && !((btype & 7) == 3)) || 1493 sc->sc_type == FFB_AFB) 1494 && (mode->hdisplay > 1280 || mode->vdisplay > 1024)) 1495 return 0; 1496 /* Creator3D can be set to <= 1920x1360 */ 1497 if (mode->hdisplay > 1920 || mode->vdisplay > 1360) 1498 return 0; 1499 1500 /* 1501 * Look for a matching pixel clock and set PLL Control. 1502 * XXX: 640x480@60 is 25175000 in modelines but 25125000 in the 1503 * FFB PROM, and the closest match to 25175000 (0x4da9/25159090) 1504 * does not work. So, use the PROM value instead. 1505 */ 1506 if (mode->hdisplay == 640 && mode->vdisplay == 480 && 1507 mode->dot_clock == 25175) { 1508 DPRINTF(("ffb_set_vmode: 640x480@60: adjusted dot clock\n")); 1509 mode->dot_clock = 25125; 1510 } 1511 ffb_get_pclk(mode->dot_clock * 1000, &pll, &diff); 1512 if (diff > 250000) 1513 return 0; 1514 1515 /* Pixel Format Control, User Control and FBC Configuration. */ 1516 if (mode->hdisplay > 1280) { 1517 pfc = FFB_DAC_PIX_FMT_821; 1518 ucl = FFB_DAC_USR_CTRL_OVERLAY | FFB_DAC_USR_CTRL_WMODE_C; 1519 x = 4; 1520 fbcfg0 = FBC_READ(sc, FFB_FBC_FBCFG0) | FBC_CFG0_DOUBLE_BUF; 1521 } else { 1522 pfc = FFB_DAC_PIX_FMT_421; 1523 /* Only Creator3D and Elite3D can have double-buffer */ 1524 if ((sc->sc_type == FFB_CREATOR && !((btype & 7) == 3))) 1525 ucl = 0; 1526 else 1527 ucl = FFB_DAC_USR_CTRL_DOUBLE; 1528 ucl |= (FFB_DAC_USR_CTRL_OVERLAY | FFB_DAC_USR_CTRL_WMODE_S8); 1529 x = 2; 1530 fbcfg0 = FBC_READ(sc, FFB_FBC_FBCFG0) | FBC_CFG0_SINGLE_BUF; 1531 } 1532 1533 /* DAC Control and Timing Generator Control */ 1534 if (mode->flags & VID_PVSYNC) 1535 dcl = FFB_DAC_DAC_CTRL_POS_VSYNC; 1536 else 1537 dcl = 0; 1538 tgc = 0; 1539 #define EDID_VID_INP sc->sc_edid_info.edid_video_input 1540 if ((EDID_VID_INP & EDID_VIDEO_INPUT_COMPOSITE_SYNC)) { 1541 dcl |= FFB_DAC_DAC_CTRL_VSYNC_DIS; 1542 tgc = FFB_DAC_TGC_EQUAL_DISABLE; 1543 } else { 1544 dcl |= FFB_DAC_DAC_CTRL_SYNC_G; 1545 if (EDID_VID_INP & EDID_VIDEO_INPUT_SEPARATE_SYNCS) 1546 tgc |= FFB_DAC_TGC_VSYNC_DISABLE; 1547 else 1548 tgc = FFB_DAC_TGC_EQUAL_DISABLE; 1549 } 1550 if (EDID_VID_INP & EDID_VIDEO_INPUT_BLANK_TO_BLACK) 1551 dcl |= FFB_DAC_DAC_CTRL_PED_ENABLE; 1552 tgc |= (FFB_DAC_TGC_VIDEO_ENABLE | FFB_DAC_TGC_TIMING_ENABLE | 1553 FFB_DAC_TGC_MASTER_ENABLE); 1554 1555 /* Vertical timing */ 1556 fp = mode->vsync_start - mode->vdisplay; 1557 sp = mode->vsync_end - mode->vsync_start; 1558 bp = mode->vtotal - mode->vsync_end; 1559 1560 vbe = sp - 1 + bp; 1561 vbs = sp - 1 + bp + mode->vdisplay; 1562 vse = sp - 1; 1563 vss = sp - 1 + bp + mode->vdisplay + fp; 1564 1565 /* Horizontal timing */ 1566 fp = mode->hsync_start - mode->hdisplay; 1567 sp = mode->hsync_end - mode->hsync_start; 1568 bp = mode->htotal - mode->hsync_end; 1569 1570 hbe = (sp + bp) / x - 1; 1571 hbs = (sp + bp + mode->hdisplay) / x - 1; 1572 hse = sp / x - 1; 1573 hss = (sp + bp + mode->hdisplay + fp) / x -1; 1574 hre = hss - hse - 1; 1575 hce = hbs - 4; 1576 hcs = hbe - 4; 1577 1578 /* Equalisation (interlaced modes) */ 1579 epe = 0; 1580 eie = 0; 1581 eis = 0; 1582 1583 DPRINTF(("ffb_set_vmode: 0x%04x 0x%04x 0x%04x 0x%04x 0x%04x\n", 1584 pll, pfc, ucl, dcl, tgc)); 1585 DPRINTF(("\t0x%04x 0x%04x 0x%04x 0x%04x\n", vbe, vbs, vse, vss)); 1586 DPRINTF(("\t0x%04x 0x%04x 0x%04x 0x%04x 0x%04x 0x%04x 0x%04x\n", 1587 hre, hbe, hbs, hse, hss, hce, hcs)); 1588 DPRINTF(("\t0x%04x 0x%04x 0x%04x\n", epe, eie, eis)); 1589 1590 if (!ffb_tgc_disable(sc)) { 1591 DPRINTF(("ffb_set_vmode: failed to disable TGC register\n")); 1592 return 0; 1593 } 1594 1595 /* 1596 * Program the mode registers. 1597 * Program the timing generator last, as that re-enables output. 1598 * Note, that a read to/write from a register increments the 1599 * register address to the next register automatically. 1600 */ 1601 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_PLL_CTRL); 1602 DAC_WRITE(sc, FFB_DAC_VALUE, pll); 1603 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_PIX_FMT); 1604 DAC_WRITE(sc, FFB_DAC_VALUE, pfc); 1605 DAC_WRITE(sc, FFB_DAC_VALUE, ucl); 1606 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_DAC_CTRL); 1607 DAC_WRITE(sc, FFB_DAC_VALUE, dcl); 1608 1609 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_VBE); 1610 DAC_WRITE(sc, FFB_DAC_VALUE, vbe); 1611 DAC_WRITE(sc, FFB_DAC_VALUE, vbs); 1612 DAC_WRITE(sc, FFB_DAC_VALUE, vse); 1613 DAC_WRITE(sc, FFB_DAC_VALUE, vss); 1614 1615 DAC_WRITE(sc, FFB_DAC_VALUE, hre); 1616 DAC_WRITE(sc, FFB_DAC_VALUE, hbe); 1617 DAC_WRITE(sc, FFB_DAC_VALUE, hbs); 1618 DAC_WRITE(sc, FFB_DAC_VALUE, hse); 1619 DAC_WRITE(sc, FFB_DAC_VALUE, hss); 1620 DAC_WRITE(sc, FFB_DAC_VALUE, hce); 1621 DAC_WRITE(sc, FFB_DAC_VALUE, hcs); 1622 1623 DAC_WRITE(sc, FFB_DAC_VALUE, epe); 1624 DAC_WRITE(sc, FFB_DAC_VALUE, eie); 1625 DAC_WRITE(sc, FFB_DAC_VALUE, eis); 1626 1627 FBC_WRITE(sc, FFB_FBC_FBCFG0, fbcfg0); 1628 1629 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_TGC); 1630 DAC_WRITE(sc, FFB_DAC_VALUE, tgc); 1631 DPRINTF(("new tgc: %08x\n", tgc)); 1632 1633 *hres = mode->hdisplay; 1634 *vres = mode->vdisplay; 1635 1636 printf("%s: video mode set to %d x %d @ %dHz\n", 1637 device_xname(sc->sc_dev), 1638 mode->hdisplay, mode->vdisplay, 1639 DIVIDE(DIVIDE(mode->dot_clock * 1000, 1640 mode->htotal), mode->vtotal)); 1641 1642 return 1; 1643 } 1644
Indexes created Sun Sep 28 12:09:53 GMT 2025