ffb.c revision 1.62
1 /* $NetBSD: ffb.c,v 1.62 2018/03/26 10:31:10 jdc Exp $ */ 2 /* $OpenBSD: creator.c,v 1.20 2002/07/30 19:48:15 jason Exp $ */ 3 4 /* 5 * Copyright (c) 2002 Jason L. Wright (jason (at) thought.net) 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Jason L. Wright 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 25 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 26 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 27 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 30 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 31 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32 * POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: ffb.c,v 1.62 2018/03/26 10:31:10 jdc Exp $"); 37 38 #include <sys/types.h> 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/kernel.h> 42 #include <sys/device.h> 43 #include <sys/conf.h> 44 #include <sys/ioctl.h> 45 #include <sys/malloc.h> 46 #include <sys/mman.h> 47 48 #include <sys/bus.h> 49 #include <machine/autoconf.h> 50 #include <machine/openfirm.h> 51 #include <machine/vmparam.h> 52 53 #include <dev/wscons/wsconsio.h> 54 #include <dev/sun/fbio.h> 55 #include <dev/sun/fbvar.h> 56 57 #include <dev/wsfont/wsfont.h> 58 #include <dev/wscons/wsdisplay_vconsvar.h> 59 60 #include <prop/proplib.h> 61 62 #include <dev/i2c/i2cvar.h> 63 #include <dev/i2c/i2c_bitbang.h> 64 #include <dev/i2c/ddcvar.h> 65 66 #include <sparc64/dev/ffbreg.h> 67 #include <sparc64/dev/ffbvar.h> 68 69 #include "opt_wsdisplay_compat.h" 70 #include "opt_ffb.h" 71 72 #ifndef WS_DEFAULT_BG 73 /* Sun -> background should be white */ 74 #define WS_DEFAULT_BG 0xf 75 #endif 76 77 #ifdef FFB_SYNC 78 #define SYNC ffb_ras_wait(sc) 79 #else 80 #define SYNC 81 #endif 82 83 /* Debugging */ 84 #if !defined FFB_DEBUG 85 #define FFB_DEBUG 0 86 #endif 87 #define DPRINTF(x) if (ffb_debug) printf x 88 /* Patchable */ 89 extern int ffb_debug; 90 #if FFB_DEBUG > 0 91 int ffb_debug = 1; 92 #else 93 int ffb_debug = 0; 94 #endif 95 96 extern struct cfdriver ffb_cd; 97 98 struct wsscreen_descr ffb_stdscreen = { 99 "sunffb", 100 0, 0, /* will be filled in -- XXX shouldn't, it's global. */ 101 0, 102 0, 0, 103 WSSCREEN_REVERSE | WSSCREEN_WSCOLORS | WSSCREEN_UNDERLINE | 104 WSSCREEN_RESIZE, 105 NULL /* modecookie */ 106 }; 107 108 const struct wsscreen_descr *ffb_scrlist[] = { 109 &ffb_stdscreen, 110 /* XXX other formats? */ 111 }; 112 113 struct wsscreen_list ffb_screenlist = { 114 sizeof(ffb_scrlist) / sizeof(struct wsscreen_descr *), 115 ffb_scrlist 116 }; 117 118 static struct vcons_screen ffb_console_screen; 119 120 int ffb_ioctl(void *, void *, u_long, void *, int, struct lwp *); 121 static int ffb_blank(struct ffb_softc *, u_long, u_int *); 122 paddr_t ffb_mmap(void *, void *, off_t, int); 123 void ffb_ras_fifo_wait(struct ffb_softc *, int); 124 void ffb_ras_wait(struct ffb_softc *); 125 void ffb_ras_init(struct ffb_softc *); 126 void ffb_ras_copyrows(void *, int, int, int); 127 void ffb_ras_erasecols(void *, int, int, int, long int); 128 void ffb_ras_eraserows(void *, int, int, long int); 129 void ffb_ras_fill(struct ffb_softc *); 130 void ffb_ras_invert(struct ffb_softc *); 131 static void ffb_ras_setfg(struct ffb_softc *, int32_t); 132 static void ffb_ras_setbg(struct ffb_softc *, int32_t); 133 134 void ffb_clearscreen(struct ffb_softc *); 135 void ffb_init_screen(void *, struct vcons_screen *, int, 136 long *); 137 int ffb_allocattr(void *, int, int, int, long *); 138 void ffb_putchar_mono(void *, int, int, u_int, long); 139 void ffb_putchar_aa(void *, int, int, u_int, long); 140 void ffb_cursor(void *, int, int, int); 141 142 /* frame buffer generic driver */ 143 static void ffbfb_unblank(device_t); 144 dev_type_open(ffbfb_open); 145 dev_type_close(ffbfb_close); 146 dev_type_ioctl(ffbfb_ioctl); 147 dev_type_mmap(ffbfb_mmap); 148 149 static struct fbdriver ffb_fbdriver = { 150 ffbfb_unblank, ffbfb_open, ffbfb_close, ffbfb_ioctl, nopoll, 151 ffbfb_mmap, nokqfilter 152 }; 153 154 struct wsdisplay_accessops ffb_accessops = { 155 .ioctl = ffb_ioctl, 156 .mmap = ffb_mmap, 157 }; 158 159 /* I2C glue */ 160 static int ffb_i2c_acquire_bus(void *, int); 161 static void ffb_i2c_release_bus(void *, int); 162 static int ffb_i2c_send_start(void *, int); 163 static int ffb_i2c_send_stop(void *, int); 164 static int ffb_i2c_initiate_xfer(void *, i2c_addr_t, int); 165 static int ffb_i2c_read_byte(void *, uint8_t *, int); 166 static int ffb_i2c_write_byte(void *, uint8_t, int); 167 168 /* I2C bitbang glue */ 169 static void ffb_i2cbb_set_bits(void *, uint32_t); 170 static void ffb_i2cbb_set_dir(void *, uint32_t); 171 static uint32_t ffb_i2cbb_read(void *); 172 173 static const struct i2c_bitbang_ops ffb_i2cbb_ops = { 174 ffb_i2cbb_set_bits, 175 ffb_i2cbb_set_dir, 176 ffb_i2cbb_read, 177 { 178 FFB_DAC_CFG_MPDATA_SDA, 179 FFB_DAC_CFG_MPDATA_SCL, 180 0, 181 0 182 } 183 }; 184 185 void ffb_attach_i2c(struct ffb_softc *); 186 187 /* Video mode setting */ 188 int ffb_tgc_disable(struct ffb_softc *); 189 void ffb_get_pclk(int, uint32_t *, int *); 190 int ffb_set_vmode(struct ffb_softc *, struct videomode *, int, int *, int *); 191 192 193 void 194 ffb_attach(device_t self) 195 { 196 struct ffb_softc *sc = device_private(self); 197 struct wsemuldisplaydev_attach_args waa; 198 struct rasops_info *ri; 199 long defattr; 200 const char *model, *out_dev; 201 int btype; 202 uint32_t dac; 203 int maxrow; 204 u_int blank = WSDISPLAYIO_VIDEO_ON; 205 char buf[6+1]; 206 int i, try_edid; 207 prop_data_t data; 208 209 printf(":"); 210 211 if (sc->sc_type == FFB_CREATOR) { 212 btype = prom_getpropint(sc->sc_node, "board_type", 0); 213 if ((btype & 7) == 3) 214 printf(" Creator3D"); 215 else 216 printf(" Creator"); 217 } else { 218 printf(" Elite3D"); 219 btype = 0; 220 } 221 222 model = prom_getpropstring(sc->sc_node, "model"); 223 if (model == NULL || strlen(model) == 0) 224 model = "unknown"; 225 226 sc->sc_depth = 24; 227 sc->sc_linebytes = 8192; 228 /* We might alter these during EDID mode setting */ 229 sc->sc_height = prom_getpropint(sc->sc_node, "height", 0); 230 sc->sc_width = prom_getpropint(sc->sc_node, "width", 0); 231 232 sc->sc_locked = 0; 233 sc->sc_mode = WSDISPLAYIO_MODE_EMUL; 234 235 maxrow = (prom_getoption("screen-#rows", buf, sizeof buf) != 0) 236 ? strtoul(buf, NULL, 10) 237 : 34; 238 239 /* collect DAC version, as Elite3D cursor enable bit is reversed */ 240 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_DEVID); 241 dac = DAC_READ(sc, FFB_DAC_VALUE); 242 sc->sc_dacrev = (dac >> 28) & 0xf; 243 244 if (sc->sc_type == FFB_AFB) { 245 sc->sc_dacrev = 10; 246 sc->sc_needredraw = 0; 247 } else { 248 /* see what kind of DAC we have */ 249 int pnum = (dac & 0x0ffff000) >> 12; 250 if (pnum == 0x236e) { 251 sc->sc_needredraw = 0; 252 } else { 253 sc->sc_needredraw = 1; 254 } 255 } 256 printf(", model %s, dac %u\n", model, sc->sc_dacrev); 257 if (sc->sc_needredraw) 258 printf("%s: found old DAC, enabling redraw on unblank\n", 259 device_xname(sc->sc_dev)); 260 261 /* Check if a console resolution "<device>:r<res>" is set. */ 262 if (sc->sc_console) { 263 out_dev = prom_getpropstring(sc->sc_node, "output-device"); 264 if (out_dev != NULL && strlen(out_dev) != 0 && 265 strstr(out_dev, ":r") != NULL) 266 try_edid = 0; 267 else 268 try_edid = 1; 269 } else 270 try_edid = 1; 271 272 #if FFB_DEBUG > 0 273 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_TGC); 274 printf("tgc: %08x\n", DAC_READ(sc, FFB_DAC_VALUE)); 275 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_DAC_CTRL); 276 printf("dcl: %08x\n", DAC_READ(sc, FFB_DAC_VALUE)); 277 #endif 278 ffb_attach_i2c(sc); 279 280 /* Need to set asynchronous blank during DDC write/read */ 281 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_USR_CTRL); 282 dac = DAC_READ(sc, FFB_DAC_VALUE); 283 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_USR_CTRL); 284 DAC_WRITE(sc, FFB_DAC_VALUE, dac | FFB_DAC_USR_CTRL_BLANK); 285 286 /* Some monitors don't respond first time */ 287 i = 0; 288 while (sc->sc_edid_data[1] == 0 && i++ < 3) 289 ddc_read_edid(&sc->sc_i2c, sc->sc_edid_data, EDID_DATA_LEN); 290 291 /* Remove asynchronous blank */ 292 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_USR_CTRL); 293 DAC_WRITE(sc, FFB_DAC_VALUE, dac); 294 295 if (edid_parse(&sc->sc_edid_data[0], &sc->sc_edid_info) != -1) { 296 sort_modes(sc->sc_edid_info.edid_modes, 297 &sc->sc_edid_info.edid_preferred_mode, 298 sc->sc_edid_info.edid_nmodes); 299 DPRINTF(("%s: EDID data:\n ", device_xname(sc->sc_dev))); 300 for (i = 0; i < EDID_DATA_LEN; i++) { 301 if (i && !(i % 32)) 302 DPRINTF(("\n ")); 303 if (i && !(i % 4)) 304 DPRINTF((" ")); 305 DPRINTF(("%02x", sc->sc_edid_data[i])); 306 } 307 DPRINTF(("\n")); 308 if (ffb_debug) 309 edid_print(&sc->sc_edid_info); 310 311 data = prop_data_create_data(sc->sc_edid_data, EDID_DATA_LEN); 312 prop_dictionary_set(device_properties(self), "EDID", data); 313 prop_object_release(data); 314 315 if (try_edid) 316 for (i = 0; i < sc->sc_edid_info.edid_nmodes; i++) { 317 if (ffb_set_vmode(sc, 318 &(sc->sc_edid_info.edid_modes[i]), btype, 319 &(sc->sc_width), &(sc->sc_height))) 320 break; 321 } 322 } else { 323 DPRINTF(("%s: No EDID data.\n", device_xname(sc->sc_dev))); 324 } 325 326 ffb_ras_init(sc); 327 328 ffb_blank(sc, WSDISPLAYIO_SVIDEO, &blank); 329 330 sc->sc_accel = ((device_cfdata(sc->sc_dev)->cf_flags & 331 FFB_CFFLAG_NOACCEL) == 0); 332 333 wsfont_init(); 334 335 vcons_init(&sc->vd, sc, &ffb_stdscreen, &ffb_accessops); 336 sc->vd.init_screen = ffb_init_screen; 337 ri = &ffb_console_screen.scr_ri; 338 339 /* we mess with ffb_console_screen only once */ 340 if (sc->sc_console) { 341 ffb_console_screen.scr_flags = VCONS_SCREEN_IS_STATIC; 342 vcons_init_screen(&sc->vd, &ffb_console_screen, 1, &defattr); 343 SCREEN_VISIBLE((&ffb_console_screen)); 344 /* 345 * XXX we shouldn't use a global variable for the console 346 * screen 347 */ 348 sc->vd.active = &ffb_console_screen; 349 } else { 350 if (ffb_console_screen.scr_ri.ri_rows == 0) { 351 /* do some minimal setup to avoid weirdnesses later */ 352 vcons_init_screen(&sc->vd, &ffb_console_screen, 1, &defattr); 353 } else 354 (*ri->ri_ops.allocattr)(ri, 0, 0, 0, &defattr); 355 } 356 357 ffb_stdscreen.nrows = ri->ri_rows; 358 ffb_stdscreen.ncols = ri->ri_cols; 359 ffb_stdscreen.textops = &ri->ri_ops; 360 361 sc->sc_fb.fb_driver = &ffb_fbdriver; 362 sc->sc_fb.fb_type.fb_cmsize = 0; 363 sc->sc_fb.fb_type.fb_size = maxrow * sc->sc_linebytes; 364 sc->sc_fb.fb_type.fb_type = FBTYPE_CREATOR; 365 sc->sc_fb.fb_type.fb_width = sc->sc_width; 366 sc->sc_fb.fb_type.fb_depth = sc->sc_depth; 367 sc->sc_fb.fb_type.fb_height = sc->sc_height; 368 sc->sc_fb.fb_device = sc->sc_dev; 369 fb_attach(&sc->sc_fb, sc->sc_console); 370 371 ffb_clearscreen(sc); 372 373 if (sc->sc_console) { 374 wsdisplay_cnattach(&ffb_stdscreen, ri, 0, 0, defattr); 375 vcons_replay_msgbuf(&ffb_console_screen); 376 } 377 378 waa.console = sc->sc_console; 379 waa.scrdata = &ffb_screenlist; 380 waa.accessops = &ffb_accessops; 381 waa.accesscookie = &sc->vd; 382 config_found(sc->sc_dev, &waa, wsemuldisplaydevprint); 383 } 384 385 void 386 ffb_attach_i2c(struct ffb_softc *sc) 387 { 388 389 /* Fill in the i2c tag */ 390 sc->sc_i2c.ic_cookie = sc; 391 sc->sc_i2c.ic_acquire_bus = ffb_i2c_acquire_bus; 392 sc->sc_i2c.ic_release_bus = ffb_i2c_release_bus; 393 sc->sc_i2c.ic_send_start = ffb_i2c_send_start; 394 sc->sc_i2c.ic_send_stop = ffb_i2c_send_stop; 395 sc->sc_i2c.ic_initiate_xfer = ffb_i2c_initiate_xfer; 396 sc->sc_i2c.ic_read_byte = ffb_i2c_read_byte; 397 sc->sc_i2c.ic_write_byte = ffb_i2c_write_byte; 398 sc->sc_i2c.ic_exec = NULL; 399 } 400 401 int 402 ffb_ioctl(void *v, void *vs, u_long cmd, void *data, int flags, struct lwp *l) 403 { 404 struct vcons_data *vd = v; 405 struct ffb_softc *sc = vd->cookie; 406 struct wsdisplay_fbinfo *wdf; 407 struct vcons_screen *ms = vd->active; 408 409 DPRINTF(("ffb_ioctl: %s cmd _IO%s%s('%c', %lu)\n", 410 device_xname(sc->sc_dev), 411 (cmd & IOC_IN) ? "W" : "", (cmd & IOC_OUT) ? "R" : "", 412 (char)IOCGROUP(cmd), cmd & 0xff)); 413 414 switch (cmd) { 415 case FBIOGTYPE: 416 *(struct fbtype *)data = sc->sc_fb.fb_type; 417 break; 418 case FBIOGATTR: 419 #define fba ((struct fbgattr *)data) 420 fba->real_type = sc->sc_fb.fb_type.fb_type; 421 fba->owner = 0; /* XXX ??? */ 422 fba->fbtype = sc->sc_fb.fb_type; 423 fba->sattr.flags = 0; 424 fba->sattr.emu_type = sc->sc_fb.fb_type.fb_type; 425 fba->sattr.dev_specific[0] = -1; 426 fba->emu_types[0] = sc->sc_fb.fb_type.fb_type; 427 fba->emu_types[1] = -1; 428 #undef fba 429 break; 430 431 case FBIOGETCMAP: 432 case FBIOPUTCMAP: 433 return EIO; 434 435 case FBIOGVIDEO: 436 case FBIOSVIDEO: 437 return ffb_blank(sc, cmd == FBIOGVIDEO? 438 WSDISPLAYIO_GVIDEO : WSDISPLAYIO_SVIDEO, 439 (u_int *)data); 440 break; 441 case FBIOGCURSOR: 442 case FBIOSCURSOR: 443 /* the console driver is not using the hardware cursor */ 444 break; 445 case FBIOGCURPOS: 446 printf("%s: FBIOGCURPOS not implemented\n", 447 device_xname(sc->sc_dev)); 448 return EIO; 449 case FBIOSCURPOS: 450 printf("%s: FBIOSCURPOS not implemented\n", 451 device_xname(sc->sc_dev)); 452 return EIO; 453 case FBIOGCURMAX: 454 printf("%s: FBIOGCURMAX not implemented\n", 455 device_xname(sc->sc_dev)); 456 return EIO; 457 458 case WSDISPLAYIO_GTYPE: 459 *(u_int *)data = WSDISPLAY_TYPE_SUNFFB; 460 break; 461 case WSDISPLAYIO_SMODE: 462 { 463 if (sc->sc_mode != *(u_int *)data) { 464 sc->sc_mode = *(u_int *)data; 465 if ((sc->sc_mode == WSDISPLAYIO_MODE_EMUL) && 466 (sc->sc_locked == 0)) { 467 ffb_ras_init(sc); 468 vcons_redraw_screen(ms); 469 } else { 470 ffb_ras_wait(sc); 471 } 472 } 473 } 474 break; 475 case WSDISPLAYIO_GINFO: 476 wdf = (void *)data; 477 wdf->height = sc->sc_height; 478 wdf->width = sc->sc_width; 479 wdf->depth = 32; 480 wdf->cmsize = 256; /* XXX */ 481 break; 482 #ifdef WSDISPLAYIO_LINEBYTES 483 case WSDISPLAYIO_LINEBYTES: 484 *(u_int *)data = sc->sc_linebytes; 485 break; 486 #endif 487 case WSDISPLAYIO_GETCMAP: 488 break;/* XXX */ 489 490 case WSDISPLAYIO_PUTCMAP: 491 break;/* XXX */ 492 493 case WSDISPLAYIO_SVIDEO: 494 case WSDISPLAYIO_GVIDEO: 495 return(ffb_blank(sc, cmd, (u_int *)data)); 496 break; 497 498 case WSDISPLAYIO_GCURPOS: 499 case WSDISPLAYIO_SCURPOS: 500 case WSDISPLAYIO_GCURMAX: 501 case WSDISPLAYIO_GCURSOR: 502 case WSDISPLAYIO_SCURSOR: 503 return EIO; /* not supported yet */ 504 break; 505 506 case WSDISPLAYIO_GET_EDID: { 507 struct wsdisplayio_edid_info *d = data; 508 return wsdisplayio_get_edid(sc->sc_dev, d); 509 } 510 511 case WSDISPLAYIO_GET_FBINFO: { 512 struct wsdisplayio_fbinfo *fbi = data; 513 return wsdisplayio_get_fbinfo(&ms->scr_ri, fbi); 514 } 515 516 default: 517 return EPASSTHROUGH; 518 } 519 520 return (0); 521 } 522 523 /* blank/unblank the screen */ 524 static int 525 ffb_blank(struct ffb_softc *sc, u_long cmd, u_int *data) 526 { 527 struct vcons_screen *ms = sc->vd.active; 528 u_int val; 529 530 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_TGC); 531 val = DAC_READ(sc, FFB_DAC_VALUE); 532 533 switch (cmd) { 534 case WSDISPLAYIO_GVIDEO: 535 *data = val & 1; 536 return(0); 537 break; 538 case WSDISPLAYIO_SVIDEO: 539 if (*data == WSDISPLAYIO_VIDEO_OFF) 540 val &= ~1; 541 else if (*data == WSDISPLAYIO_VIDEO_ON) 542 val |= 1; 543 else 544 return(EINVAL); 545 break; 546 default: 547 return(EINVAL); 548 } 549 550 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_TGC); 551 DAC_WRITE(sc, FFB_DAC_VALUE, val); 552 553 if ((val & 1) && sc->sc_needredraw) { 554 if (ms != NULL) { 555 if ((sc->sc_mode == WSDISPLAYIO_MODE_EMUL) && 556 (sc->sc_locked == 0)) { 557 ffb_ras_init(sc); 558 vcons_redraw_screen(ms); 559 } 560 } 561 } 562 563 return(0); 564 } 565 566 paddr_t 567 ffb_mmap(void *vsc, void *vs, off_t off, int prot) 568 { 569 struct vcons_data *vd = vsc; 570 struct ffb_softc *sc = vd->cookie; 571 int i; 572 573 switch (sc->sc_mode) { 574 case WSDISPLAYIO_MODE_MAPPED: 575 for (i = 0; i < sc->sc_nreg; i++) { 576 /* Before this set? */ 577 if (off < sc->sc_addrs[i]) 578 continue; 579 /* After this set? */ 580 if (off >= (sc->sc_addrs[i] + sc->sc_sizes[i])) 581 continue; 582 583 return (bus_space_mmap(sc->sc_bt, sc->sc_addrs[i], 584 off - sc->sc_addrs[i], prot, BUS_SPACE_MAP_LINEAR)); 585 } 586 break; 587 #ifdef WSDISPLAYIO_MODE_DUMBFB 588 case WSDISPLAYIO_MODE_DUMBFB: 589 if (sc->sc_nreg < FFB_REG_DFB24) 590 break; 591 if (off >= 0 && off < sc->sc_sizes[FFB_REG_DFB24]) 592 return (bus_space_mmap(sc->sc_bt, 593 sc->sc_addrs[FFB_REG_DFB24], off, prot, 594 BUS_SPACE_MAP_LINEAR | BUS_SPACE_MAP_PREFETCHABLE)); 595 break; 596 #endif 597 } 598 return (-1); 599 } 600 601 void 602 ffb_ras_fifo_wait(struct ffb_softc *sc, int n) 603 { 604 int32_t cache = sc->sc_fifo_cache; 605 606 if (cache < n) { 607 do { 608 cache = FBC_READ(sc, FFB_FBC_UCSR); 609 cache = (cache & FBC_UCSR_FIFO_MASK) - 8; 610 } while (cache < n); 611 } 612 sc->sc_fifo_cache = cache - n; 613 } 614 615 void 616 ffb_ras_wait(struct ffb_softc *sc) 617 { 618 uint32_t ucsr, r; 619 620 while (1) { 621 ucsr = FBC_READ(sc, FFB_FBC_UCSR); 622 if ((ucsr & (FBC_UCSR_FB_BUSY|FBC_UCSR_RP_BUSY)) == 0) 623 break; 624 r = ucsr & (FBC_UCSR_READ_ERR | FBC_UCSR_FIFO_OVFL); 625 if (r != 0) 626 FBC_WRITE(sc, FFB_FBC_UCSR, r); 627 } 628 } 629 630 void 631 ffb_ras_init(struct ffb_softc *sc) 632 { 633 uint32_t fbc; 634 635 if (sc->sc_width > 1280) { 636 DPRINTF(("ffb_ras_init: high resolution.\n")); 637 fbc = FFB_FBC_WM_COMBINED | FFB_FBC_WE_FORCEON | 638 FFB_FBC_ZE_OFF | FFB_FBC_YE_OFF | FFB_FBC_XE_ON; 639 } else { 640 DPRINTF(("ffb_ras_init: standard resolution.\n")); 641 fbc = FFB_FBC_XE_OFF; 642 } 643 ffb_ras_fifo_wait(sc, 7); 644 DPRINTF(("WID: %08x\n", FBC_READ(sc, FFB_FBC_WID))); 645 FBC_WRITE(sc, FFB_FBC_WID, 0x0); 646 FBC_WRITE(sc, FFB_FBC_PPC, 647 FBC_PPC_VCE_DIS | FBC_PPC_TBE_OPAQUE | FBC_PPC_ACE_DIS | 648 FBC_PPC_APE_DIS | FBC_PPC_DCE_DIS | FBC_PPC_CS_CONST | 649 FBC_PPC_ABE_DIS | FBC_PPC_XS_WID); 650 651 fbc |= FFB_FBC_WB_A | FFB_FBC_RB_A | FFB_FBC_SB_BOTH | 652 FFB_FBC_RGBE_MASK; 653 DPRINTF(("%s: fbc is %08x\n", __func__, fbc)); 654 FBC_WRITE(sc, FFB_FBC_FBC, fbc); 655 FBC_WRITE(sc, FFB_FBC_ROP, FBC_ROP_NEW); 656 FBC_WRITE(sc, FFB_FBC_DRAWOP, FBC_DRAWOP_RECTANGLE); 657 FBC_WRITE(sc, FFB_FBC_PMASK, 0xffffffff); 658 FBC_WRITE(sc, FFB_FBC_FONTINC, 0x10000); 659 ffb_ras_fifo_wait(sc, 5); 660 sc->sc_fg_cache = 0; 661 FBC_WRITE(sc, FFB_FBC_FG, sc->sc_fg_cache); 662 sc->sc_bg_cache = 0; 663 FBC_WRITE(sc, FFB_FBC_BG, sc->sc_bg_cache); 664 FBC_WRITE(sc, FFB_FBC_BLENDC, FFB_BLENDC_FORCE_ONE | 665 FFB_BLENDC_DF_ONE_M_A | 666 FFB_BLENDC_SF_A); 667 FBC_WRITE(sc, FFB_FBC_BLENDC1, 0); 668 FBC_WRITE(sc, FFB_FBC_BLENDC2, 0); 669 ffb_ras_wait(sc); 670 } 671 672 void 673 ffb_ras_eraserows(void *cookie, int row, int n, long attr) 674 { 675 struct rasops_info *ri = cookie; 676 struct vcons_screen *scr = ri->ri_hw; 677 struct ffb_softc *sc = scr->scr_cookie; 678 679 if (row < 0) { 680 n += row; 681 row = 0; 682 } 683 if (row + n > ri->ri_rows) 684 n = ri->ri_rows - row; 685 if (n <= 0) 686 return; 687 688 ffb_ras_fill(sc); 689 ffb_ras_setfg(sc, ri->ri_devcmap[(attr >> 16) & 0xf]); 690 ffb_ras_fifo_wait(sc, 4); 691 if ((n == ri->ri_rows) && (ri->ri_flg & RI_FULLCLEAR)) { 692 FBC_WRITE(sc, FFB_FBC_BY, 0); 693 FBC_WRITE(sc, FFB_FBC_BX, 0); 694 FBC_WRITE(sc, FFB_FBC_BH, ri->ri_height); 695 FBC_WRITE(sc, FFB_FBC_BW, ri->ri_width); 696 ri->ri_flg &= ~RI_CURSOR; 697 } else { 698 row *= ri->ri_font->fontheight; 699 FBC_WRITE(sc, FFB_FBC_BY, ri->ri_yorigin + row); 700 FBC_WRITE(sc, FFB_FBC_BX, ri->ri_xorigin); 701 FBC_WRITE(sc, FFB_FBC_BH, n * ri->ri_font->fontheight); 702 FBC_WRITE(sc, FFB_FBC_BW, ri->ri_emuwidth); 703 } 704 SYNC; 705 } 706 707 void 708 ffb_ras_erasecols(void *cookie, int row, int col, int n, long attr) 709 { 710 struct rasops_info *ri = cookie; 711 struct vcons_screen *scr = ri->ri_hw; 712 struct ffb_softc *sc = scr->scr_cookie; 713 714 if ((row < 0) || (row >= ri->ri_rows)) 715 return; 716 if (col < 0) { 717 n += col; 718 col = 0; 719 } 720 if (col + n > ri->ri_cols) 721 n = ri->ri_cols - col; 722 if (n <= 0) 723 return; 724 725 n *= ri->ri_font->fontwidth; 726 col *= ri->ri_font->fontwidth; 727 row *= ri->ri_font->fontheight; 728 729 ffb_ras_fill(sc); 730 ffb_ras_setfg(sc, ri->ri_devcmap[(attr >> 16) & 0xf]); 731 ffb_ras_fifo_wait(sc, 4); 732 FBC_WRITE(sc, FFB_FBC_BY, ri->ri_yorigin + row); 733 FBC_WRITE(sc, FFB_FBC_BX, ri->ri_xorigin + col); 734 FBC_WRITE(sc, FFB_FBC_BH, ri->ri_font->fontheight); 735 FBC_WRITE(sc, FFB_FBC_BW, n); 736 SYNC; 737 } 738 739 void 740 ffb_ras_fill(struct ffb_softc *sc) 741 { 742 ffb_ras_fifo_wait(sc, 3); 743 FBC_WRITE(sc, FFB_FBC_PPC, 744 FBC_PPC_VCE_DIS | FBC_PPC_TBE_OPAQUE | FBC_PPC_ACE_DIS | 745 FBC_PPC_APE_DIS | FBC_PPC_DCE_DIS | FBC_PPC_CS_CONST | 746 FBC_PPC_ABE_DIS | FBC_PPC_XS_WID); 747 FBC_WRITE(sc, FFB_FBC_ROP, FBC_ROP_NEW); 748 FBC_WRITE(sc, FFB_FBC_DRAWOP, FBC_DRAWOP_RECTANGLE); 749 SYNC; 750 } 751 752 void 753 ffb_ras_invert(struct ffb_softc *sc) 754 { 755 ffb_ras_fifo_wait(sc, 3); 756 FBC_WRITE(sc, FFB_FBC_PPC, 757 FBC_PPC_VCE_DIS | FBC_PPC_TBE_OPAQUE | FBC_PPC_ACE_DIS | 758 FBC_PPC_APE_DIS | FBC_PPC_DCE_DIS | FBC_PPC_CS_CONST | 759 FBC_PPC_ABE_DIS | FBC_PPC_XS_WID); 760 FBC_WRITE(sc, FFB_FBC_ROP, FBC_ROP_INVERT); 761 FBC_WRITE(sc, FFB_FBC_DRAWOP, FBC_DRAWOP_RECTANGLE); 762 SYNC; 763 } 764 765 void 766 ffb_ras_copyrows(void *cookie, int src, int dst, int n) 767 { 768 struct rasops_info *ri = cookie; 769 struct vcons_screen *scr = ri->ri_hw; 770 struct ffb_softc *sc = scr->scr_cookie; 771 772 if (dst == src) 773 return; 774 if (src < 0) { 775 n += src; 776 src = 0; 777 } 778 if ((src + n) > ri->ri_rows) 779 n = ri->ri_rows - src; 780 if (dst < 0) { 781 n += dst; 782 dst = 0; 783 } 784 if ((dst + n) > ri->ri_rows) 785 n = ri->ri_rows - dst; 786 if (n <= 0) 787 return; 788 n *= ri->ri_font->fontheight; 789 src *= ri->ri_font->fontheight; 790 dst *= ri->ri_font->fontheight; 791 792 ffb_ras_fifo_wait(sc, 9); 793 FBC_WRITE(sc, FFB_FBC_PPC, 794 FBC_PPC_VCE_DIS | FBC_PPC_TBE_OPAQUE | FBC_PPC_ACE_DIS | 795 FBC_PPC_APE_DIS | FBC_PPC_DCE_DIS | FBC_PPC_CS_CONST | 796 FBC_PPC_ABE_DIS | FBC_PPC_XS_WID); 797 FBC_WRITE(sc, FFB_FBC_ROP, FBC_ROP_OLD | (FBC_ROP_OLD << 8)); 798 FBC_WRITE(sc, FFB_FBC_DRAWOP, FBC_DRAWOP_VSCROLL); 799 FBC_WRITE(sc, FFB_FBC_BY, ri->ri_yorigin + src); 800 FBC_WRITE(sc, FFB_FBC_BX, ri->ri_xorigin); 801 FBC_WRITE(sc, FFB_FBC_DY, ri->ri_yorigin + dst); 802 FBC_WRITE(sc, FFB_FBC_DX, ri->ri_xorigin); 803 FBC_WRITE(sc, FFB_FBC_BH, n); 804 FBC_WRITE(sc, FFB_FBC_BW, ri->ri_emuwidth); 805 SYNC; 806 } 807 808 static void 809 ffb_ras_setfg(struct ffb_softc *sc, int32_t fg) 810 { 811 ffb_ras_fifo_wait(sc, 1); 812 if (fg == sc->sc_fg_cache) 813 return; 814 sc->sc_fg_cache = fg; 815 FBC_WRITE(sc, FFB_FBC_FG, fg); 816 SYNC; 817 } 818 819 static void 820 ffb_ras_setbg(struct ffb_softc *sc, int32_t bg) 821 { 822 ffb_ras_fifo_wait(sc, 1); 823 if (bg == sc->sc_bg_cache) 824 return; 825 sc->sc_bg_cache = bg; 826 FBC_WRITE(sc, FFB_FBC_BG, bg); 827 SYNC; 828 } 829 830 /* frame buffer generic driver support functions */ 831 static void 832 ffbfb_unblank(device_t dev) 833 { 834 struct ffb_softc *sc = device_private(dev); 835 struct vcons_screen *ms = sc->vd.active; 836 u_int on = 1; 837 int redraw = 0; 838 839 ffb_ras_init(sc); 840 if (sc->sc_locked) { 841 sc->sc_locked = 0; 842 redraw = 1; 843 } 844 845 ffb_blank(sc, WSDISPLAYIO_SVIDEO, &on); 846 #if 0 847 if ((sc->vd.active != &ffb_console_screen) && 848 (ffb_console_screen.scr_flags & VCONS_SCREEN_IS_STATIC)) { 849 /* 850 * force-switch to the console screen. 851 * Caveat: the higher layer will think we're still on the 852 * other screen 853 */ 854 855 SCREEN_INVISIBLE(sc->vd.active); 856 sc->vd.active = &ffb_console_screen; 857 SCREEN_VISIBLE(sc->vd.active); 858 ms = sc->vd.active; 859 redraw = 1; 860 } 861 #endif 862 if (redraw) { 863 vcons_redraw_screen(ms); 864 } 865 } 866 867 int 868 ffbfb_open(dev_t dev, int flags, int mode, struct lwp *l) 869 { 870 struct ffb_softc *sc; 871 872 sc = device_lookup_private(&ffb_cd, minor(dev)); 873 if (sc == NULL) 874 return ENXIO; 875 876 sc->sc_locked = 1; 877 return 0; 878 } 879 880 int 881 ffbfb_close(dev_t dev, int flags, int mode, struct lwp *l) 882 { 883 struct ffb_softc *sc = device_lookup_private(&ffb_cd, minor(dev)); 884 struct vcons_screen *ms = sc->vd.active; 885 886 sc->sc_locked = 0; 887 if (ms != NULL) { 888 if ((sc->sc_mode == WSDISPLAYIO_MODE_EMUL) && 889 (sc->sc_locked == 0)) { 890 ffb_ras_init(sc); 891 vcons_redraw_screen(ms); 892 } 893 } 894 return 0; 895 } 896 897 int 898 ffbfb_ioctl(dev_t dev, u_long cmd, void *data, int flags, struct lwp *l) 899 { 900 struct ffb_softc *sc = device_lookup_private(&ffb_cd, minor(dev)); 901 902 return ffb_ioctl(&sc->vd, NULL, cmd, data, flags, l); 903 } 904 905 paddr_t 906 ffbfb_mmap(dev_t dev, off_t off, int prot) 907 { 908 struct ffb_softc *sc = device_lookup_private(&ffb_cd, minor(dev)); 909 uint64_t size; 910 int i, reg; 911 off_t o; 912 913 /* 914 * off is a magic cookie (see xfree86/drivers/sunffb/ffb.h), 915 * which we map to an index into the "reg" property, and use 916 * our copy of the firmware data as arguments for the real 917 * mapping. 918 */ 919 static struct { unsigned long voff; int reg; long flags; } map[] = { 920 { 0x00000000, FFB_REG_SFB8R, BUS_SPACE_MAP_PREFETCHABLE }, 921 { 0x00400000, FFB_REG_SFB8G, BUS_SPACE_MAP_PREFETCHABLE }, 922 { 0x00800000, FFB_REG_SFB8B, BUS_SPACE_MAP_PREFETCHABLE }, 923 { 0x00c00000, FFB_REG_SFB8X, BUS_SPACE_MAP_PREFETCHABLE }, 924 { 0x01000000, FFB_REG_SFB32, BUS_SPACE_MAP_PREFETCHABLE }, 925 { 0x02000000, FFB_REG_SFB64, BUS_SPACE_MAP_PREFETCHABLE }, 926 { 0x04000000, FFB_REG_FBC, 0 }, 927 { 0x04004000, FFB_REG_DFB8R, BUS_SPACE_MAP_PREFETCHABLE }, 928 { 0x04404000, FFB_REG_DFB8G, BUS_SPACE_MAP_PREFETCHABLE }, 929 { 0x04804000, FFB_REG_DFB8B, BUS_SPACE_MAP_PREFETCHABLE }, 930 { 0x04c04000, FFB_REG_DFB8X, BUS_SPACE_MAP_PREFETCHABLE }, 931 { 0x05004000, FFB_REG_DFB24, BUS_SPACE_MAP_PREFETCHABLE }, 932 { 0x06004000, FFB_REG_DFB32, BUS_SPACE_MAP_PREFETCHABLE }, 933 { 0x07004000, FFB_REG_DFB422A, BUS_SPACE_MAP_PREFETCHABLE }, 934 { 0x0bc06000, FFB_REG_DAC, 0 }, 935 { 0x0bc08000, FFB_REG_PROM, 0 }, 936 { 0x0bc18000, 0, 0 } 937 }; 938 939 /* special value "FFB_EXP_VOFF" - not backed by any "reg" entry */ 940 if (off == 0x0bc18000) 941 return bus_space_mmap(sc->sc_bt, sc->sc_addrs[FFB_REG_PROM], 942 0x00200000, prot, BUS_SPACE_MAP_LINEAR); 943 944 /* 945 * FFB_VOFF_FBC_KREGS - used by afbinit to upload firmware. We should 946 * probably mmap them only on afb boards 947 */ 948 if ((off >= 0x0bc04000) && (off < 0x0bc06000)) 949 return bus_space_mmap(sc->sc_bt, sc->sc_addrs[FFB_REG_PROM], 950 0x00610000 + (off - 0x0bc04000), prot, 951 BUS_SPACE_MAP_LINEAR); 952 953 #define NELEMS(arr) (sizeof(arr)/sizeof((arr)[0])) 954 955 /* the map is ordered by voff */ 956 for (i = 0; i < NELEMS(map)-1; i++) { 957 reg = map[i].reg; 958 /* the number of entries in reg seems to vary */ 959 if (reg < sc->sc_nreg) { 960 size = min((map[i + 1].voff - map[i].voff), 961 sc->sc_sizes[reg]); 962 if ((off >= map[i].voff) && 963 (off < (map[i].voff + size))) { 964 o = off - map[i].voff; 965 return bus_space_mmap(sc->sc_bt, 966 sc->sc_addrs[reg], o, prot, 967 BUS_SPACE_MAP_LINEAR | map[i].flags); 968 } 969 } 970 } 971 972 return -1; 973 } 974 975 void 976 ffb_clearscreen(struct ffb_softc *sc) 977 { 978 struct rasops_info *ri = &ffb_console_screen.scr_ri; 979 ffb_ras_fill(sc); 980 ffb_ras_setfg(sc, ri->ri_devcmap[WS_DEFAULT_BG]); 981 ffb_ras_fifo_wait(sc, 4); 982 FBC_WRITE(sc, FFB_FBC_BY, 0); 983 FBC_WRITE(sc, FFB_FBC_BX, 0); 984 FBC_WRITE(sc, FFB_FBC_BH, sc->sc_height); 985 FBC_WRITE(sc, FFB_FBC_BW, sc->sc_width); 986 } 987 988 void 989 ffb_cursor(void *cookie, int on, int row, int col) 990 { 991 struct rasops_info *ri = cookie; 992 struct vcons_screen *scr; 993 struct ffb_softc *sc; 994 int x, y, wi, he; 995 996 if (cookie != NULL) { 997 scr = ri->ri_hw; 998 sc = scr->scr_cookie; 999 1000 wi = ri->ri_font->fontwidth; 1001 he = ri->ri_font->fontheight; 1002 1003 if (sc->sc_mode == WSDISPLAYIO_MODE_EMUL) { 1004 1005 if (ri->ri_flg & RI_CURSOR) { 1006 1007 /* remove cursor */ 1008 x = ri->ri_ccol * wi + ri->ri_xorigin; 1009 y = ri->ri_crow * he + ri->ri_yorigin; 1010 1011 ffb_ras_invert(sc); 1012 ffb_ras_fifo_wait(sc, 4); 1013 FBC_WRITE(sc, FFB_FBC_BY, y); 1014 FBC_WRITE(sc, FFB_FBC_BX, x); 1015 FBC_WRITE(sc, FFB_FBC_BH, he); 1016 FBC_WRITE(sc, FFB_FBC_BW, wi); 1017 1018 ri->ri_flg &= ~RI_CURSOR; 1019 } 1020 ri->ri_crow = row; 1021 ri->ri_ccol = col; 1022 if (on) 1023 { 1024 x = ri->ri_ccol * wi + ri->ri_xorigin; 1025 y = ri->ri_crow * he + ri->ri_yorigin; 1026 1027 ffb_ras_invert(sc); 1028 ffb_ras_fifo_wait(sc, 4); 1029 FBC_WRITE(sc, FFB_FBC_BY, y); 1030 FBC_WRITE(sc, FFB_FBC_BX, x); 1031 FBC_WRITE(sc, FFB_FBC_BH, he); 1032 FBC_WRITE(sc, FFB_FBC_BW, wi); 1033 1034 ri->ri_flg |= RI_CURSOR; 1035 } 1036 } else { 1037 ri->ri_crow = row; 1038 ri->ri_ccol = col; 1039 ri->ri_flg &= ~RI_CURSOR; 1040 } 1041 } 1042 } 1043 1044 /* mono bitmap font */ 1045 void 1046 ffb_putchar_mono(void *cookie, int row, int col, u_int c, long attr) 1047 { 1048 struct rasops_info *ri = cookie; 1049 struct vcons_screen *scr = ri->ri_hw; 1050 struct wsdisplay_font *font = PICK_FONT(ri, c); 1051 struct ffb_softc *sc = scr->scr_cookie; 1052 void *data; 1053 uint32_t fg, bg; 1054 int i; 1055 int x, y, wi, he; 1056 1057 if (sc->sc_mode != WSDISPLAYIO_MODE_EMUL) 1058 return; 1059 1060 wi = font->fontwidth; 1061 he = font->fontheight; 1062 1063 if (!CHAR_IN_FONT(c, font)) 1064 return; 1065 1066 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 1067 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 1068 x = ri->ri_xorigin + col * wi; 1069 y = ri->ri_yorigin + row * he; 1070 1071 data = WSFONT_GLYPH(c, font); 1072 1073 ffb_ras_setbg(sc, bg); 1074 ffb_ras_setfg(sc, fg); 1075 ffb_ras_fifo_wait(sc, 4); 1076 FBC_WRITE(sc, FFB_FBC_ROP, FBC_ROP_NEW); 1077 FBC_WRITE(sc, FFB_FBC_FONTXY, (y << 16) | x); 1078 FBC_WRITE(sc, FFB_FBC_FONTW, wi); 1079 FBC_WRITE(sc, FFB_FBC_PPC, 1080 FBC_PPC_VCE_DIS | FBC_PPC_TBE_OPAQUE | FBC_PPC_ACE_DIS | 1081 FBC_PPC_APE_DIS | FBC_PPC_DCE_DIS | FBC_PPC_CS_CONST | 1082 FBC_PPC_ABE_DIS | FBC_PPC_XS_WID); 1083 1084 switch (font->stride) { 1085 case 1: { 1086 uint8_t *data8 = data; 1087 uint32_t reg; 1088 if (attr & WSATTR_UNDERLINE) { 1089 for (i = 0; i < he - 2; i++) { 1090 reg = *data8; 1091 FBC_WRITE(sc, FFB_FBC_FONT, reg << 24); 1092 data8++; 1093 } 1094 FBC_WRITE(sc, FFB_FBC_FONT, 0xff000000); 1095 data8++; 1096 reg = *data8; 1097 FBC_WRITE(sc, FFB_FBC_FONT, reg << 24); 1098 } else { 1099 for (i = 0; i < he; i++) { 1100 reg = *data8; 1101 FBC_WRITE(sc, FFB_FBC_FONT, reg << 24); 1102 data8++; 1103 } 1104 } 1105 break; 1106 } 1107 case 2: { 1108 uint16_t *data16 = data; 1109 uint32_t reg; 1110 if (attr & WSATTR_UNDERLINE) { 1111 for (i = 0; i < he - 2; i++) { 1112 reg = *data16; 1113 FBC_WRITE(sc, FFB_FBC_FONT, reg << 16); 1114 data16++; 1115 } 1116 FBC_WRITE(sc, FFB_FBC_FONT, 0xffff0000); 1117 data16++; 1118 reg = *data16; 1119 FBC_WRITE(sc, FFB_FBC_FONT, reg << 16); 1120 } else { 1121 for (i = 0; i < he; i++) { 1122 reg = *data16; 1123 FBC_WRITE(sc, FFB_FBC_FONT, reg << 16); 1124 data16++; 1125 } 1126 } 1127 break; 1128 } 1129 } 1130 } 1131 1132 /* alpha font */ 1133 void 1134 ffb_putchar_aa(void *cookie, int row, int col, u_int c, long attr) 1135 { 1136 struct rasops_info *ri = cookie; 1137 struct vcons_screen *scr = ri->ri_hw; 1138 struct wsdisplay_font *font = PICK_FONT(ri, c); 1139 struct ffb_softc *sc = scr->scr_cookie; 1140 volatile uint32_t *dest, *ddest; 1141 uint8_t *data8; 1142 uint32_t fg, bg; 1143 int i; 1144 int x, y, wi, he; 1145 uint32_t alpha = 0x80; 1146 int j; 1147 1148 if (sc->sc_mode != WSDISPLAYIO_MODE_EMUL) 1149 return; 1150 1151 wi = font->fontwidth; 1152 he = font->fontheight; 1153 1154 if (!CHAR_IN_FONT(c, font)) 1155 return; 1156 1157 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 1158 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 1159 x = ri->ri_xorigin + col * wi; 1160 y = ri->ri_yorigin + row * he; 1161 1162 data8 = WSFONT_GLYPH(c, font); 1163 1164 /* first we erase the background */ 1165 ffb_ras_fill(sc); 1166 ffb_ras_setfg(sc, bg); 1167 ffb_ras_fifo_wait(sc, 4); 1168 FBC_WRITE(sc, FFB_FBC_BY, y); 1169 FBC_WRITE(sc, FFB_FBC_BX, x); 1170 FBC_WRITE(sc, FFB_FBC_BH, he); 1171 FBC_WRITE(sc, FFB_FBC_BW, wi); 1172 1173 /* if we draw a space we're done */ 1174 if (c == ' ') goto out; 1175 1176 /* now enable alpha blending */ 1177 ffb_ras_setfg(sc, fg); 1178 ffb_ras_fifo_wait(sc, 2); 1179 FBC_WRITE(sc, FFB_FBC_ROP, FBC_ROP_NEW); 1180 1181 FBC_WRITE(sc, FFB_FBC_PPC, 1182 FBC_PPC_VCE_DIS | FBC_PPC_TBE_OPAQUE | FBC_PPC_ACE_DIS | 1183 FBC_PPC_APE_DIS | FBC_PPC_DCE_DIS | FBC_PPC_CS_CONST | 1184 FBC_PPC_ABE_ENA | FBC_PPC_XS_VAR); 1185 /* 1186 * we have to wait for both the rectangle drawing op above and the 1187 * FFB_FBC_PPC write to finish before mucking around in the SFB aperture 1188 */ 1189 ffb_ras_wait(sc); 1190 1191 /* ... and draw the character */ 1192 dest = sc->sc_sfb32 + (y << 11) + x; 1193 for (i = 0; i < he; i++) { 1194 ddest = dest; 1195 for (j = 0; j < wi; j++) { 1196 alpha = *data8; 1197 /* 1198 * We set the colour source to constant above so we only 1199 * have to write the alpha channel here and the colour 1200 * comes from the FG register. It would be nice if we 1201 * could just use the SFB8X aperture and memcpy() the 1202 * alpha map line by line but for some strange reason 1203 * that will take colour info from the framebuffer even 1204 * if we set the FBC_PPC_CS_CONST bit above. 1205 */ 1206 *ddest = alpha << 24; 1207 data8++; 1208 ddest++; 1209 } 1210 dest += 2048; 1211 } 1212 out: 1213 /* check if we need to draw an underline */ 1214 if (attr & WSATTR_UNDERLINE) { 1215 dest = sc->sc_sfb32 + ((y + he - 2) << 11) + x; 1216 for (i = 0; i < wi; i++) { 1217 *dest = 0xa0000000; 1218 dest++; 1219 } 1220 } 1221 } 1222 1223 int 1224 ffb_allocattr(void *cookie, int fg, int bg, int flags, long *attrp) 1225 { 1226 if ((fg == 0) && (bg == 0)) 1227 { 1228 fg = WS_DEFAULT_FG; 1229 bg = WS_DEFAULT_BG; 1230 } 1231 if (flags & WSATTR_REVERSE) { 1232 *attrp = (bg & 0xff) << 24 | (fg & 0xff) << 16; 1233 } else 1234 *attrp = (fg & 0xff) << 24 | (bg & 0xff) << 16; 1235 if (flags & WSATTR_UNDERLINE) 1236 *attrp |= WSATTR_UNDERLINE; 1237 return 0; 1238 } 1239 1240 void 1241 ffb_init_screen(void *cookie, struct vcons_screen *scr, 1242 int existing, long *defattr) 1243 { 1244 struct ffb_softc *sc = cookie; 1245 struct rasops_info *ri = &scr->scr_ri; 1246 1247 ri->ri_depth = 32; 1248 ri->ri_width = sc->sc_width; 1249 ri->ri_height = sc->sc_height; 1250 ri->ri_stride = sc->sc_linebytes; 1251 ri->ri_flg = RI_CENTER | RI_ENABLE_ALPHA | RI_PREFER_ALPHA; 1252 1253 /* 1254 * we can't accelerate copycols() so instead of falling back to 1255 * software use vcons' putchar() based implementation 1256 */ 1257 scr->scr_flags |= VCONS_NO_COPYCOLS | VCONS_LOADFONT; 1258 1259 #ifdef VCONS_DRAW_INTR 1260 scr->scr_flags |= VCONS_DONT_READ; 1261 #endif 1262 DPRINTF(("ffb_init_screen: addr: %08lx\n",(ulong)ri->ri_bits)); 1263 1264 /* explicitly request BGR in case the default changes */ 1265 ri->ri_rnum = 8; 1266 ri->ri_gnum = 8; 1267 ri->ri_bnum = 8; 1268 ri->ri_rpos = 0; 1269 ri->ri_gpos = 8; 1270 ri->ri_bpos = 16; 1271 1272 rasops_init(ri, 0, 0); 1273 rasops_reconfig(ri, sc->sc_height / ri->ri_font->fontheight, 1274 sc->sc_width / ri->ri_font->fontwidth); 1275 ri->ri_caps = WSSCREEN_WSCOLORS | WSSCREEN_UNDERLINE | 1276 WSSCREEN_REVERSE | WSSCREEN_RESIZE; 1277 1278 /* enable acceleration */ 1279 ri->ri_ops.copyrows = ffb_ras_copyrows; 1280 ri->ri_ops.eraserows = ffb_ras_eraserows; 1281 ri->ri_ops.erasecols = ffb_ras_erasecols; 1282 ri->ri_ops.cursor = ffb_cursor; 1283 ri->ri_ops.allocattr = ffb_allocattr; 1284 if (FONT_IS_ALPHA(ri->ri_font)) { 1285 ri->ri_ops.putchar = ffb_putchar_aa; 1286 } else 1287 ri->ri_ops.putchar = ffb_putchar_mono; 1288 } 1289 1290 /* I2C bitbanging */ 1291 static void ffb_i2cbb_set_bits(void *cookie, uint32_t bits) 1292 { 1293 struct ffb_softc *sc = cookie; 1294 1295 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_CFG_MPDATA); 1296 DAC_WRITE(sc, FFB_DAC_VALUE, bits); 1297 } 1298 1299 static void ffb_i2cbb_set_dir(void *cookie, uint32_t dir) 1300 { 1301 /* Nothing to do */ 1302 } 1303 1304 static uint32_t ffb_i2cbb_read(void *cookie) 1305 { 1306 struct ffb_softc *sc = cookie; 1307 uint32_t bits; 1308 1309 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_CFG_MPSENSE); 1310 bits = DAC_READ(sc, FFB_DAC_VALUE); 1311 1312 return bits; 1313 } 1314 1315 /* higher level I2C stuff */ 1316 static int 1317 ffb_i2c_acquire_bus(void *cookie, int flags) 1318 { 1319 /* private bus */ 1320 return (0); 1321 } 1322 1323 static void 1324 ffb_i2c_release_bus(void *cookie, int flags) 1325 { 1326 /* private bus */ 1327 } 1328 1329 static int 1330 ffb_i2c_send_start(void *cookie, int flags) 1331 { 1332 return (i2c_bitbang_send_start(cookie, flags, &ffb_i2cbb_ops)); 1333 } 1334 1335 static int 1336 ffb_i2c_send_stop(void *cookie, int flags) 1337 { 1338 1339 return (i2c_bitbang_send_stop(cookie, flags, &ffb_i2cbb_ops)); 1340 } 1341 1342 static int 1343 ffb_i2c_initiate_xfer(void *cookie, i2c_addr_t addr, int flags) 1344 { 1345 /* 1346 * for some reason i2c_bitbang_initiate_xfer left-shifts 1347 * the I2C-address and then sets the direction bit 1348 */ 1349 return (i2c_bitbang_initiate_xfer(cookie, addr, flags, 1350 &ffb_i2cbb_ops)); 1351 } 1352 1353 static int 1354 ffb_i2c_read_byte(void *cookie, uint8_t *valp, int flags) 1355 { 1356 return (i2c_bitbang_read_byte(cookie, valp, flags, &ffb_i2cbb_ops)); 1357 } 1358 1359 static int 1360 ffb_i2c_write_byte(void *cookie, uint8_t val, int flags) 1361 { 1362 return (i2c_bitbang_write_byte(cookie, val, flags, &ffb_i2cbb_ops)); 1363 } 1364 1365 1366 #define TVC_READ_LIMIT 100000 1367 int 1368 ffb_tgc_disable(struct ffb_softc *sc) 1369 { 1370 int i; 1371 1372 /* Is the timing generator disabled? */ 1373 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_TGC); 1374 if (!(DAC_READ(sc, FFB_DAC_VALUE) & FFB_DAC_TGC_TIMING_ENABLE)) 1375 return 1; 1376 1377 /* If not, disable it when the vertical counter reaches 0 */ 1378 for (i = 0; i < TVC_READ_LIMIT; i++) { 1379 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_TVC); 1380 if (!DAC_READ(sc, FFB_DAC_VALUE)) { 1381 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_TGC); 1382 DAC_WRITE(sc, FFB_DAC_VALUE, 0); 1383 return 1; 1384 } 1385 } 1386 return 0; 1387 } 1388 1389 /* 1390 * PLL Control Register values: 1391 * M)ultiplier = bits 0:6 + 1 1392 * D)ivisor = bits 7:10 + 1 1393 * P)ost divisor = bits 11:13 (000 = 1, 001 = 2, 010 = 4, 011 = 8) 1394 * Frequency = 13.5 * M / D / P 1395 */ 1396 #define FFB_PLL_FREQ 13500000 1397 void 1398 ffb_get_pclk(int request, uint32_t *pll, int *diff) 1399 { 1400 int m, d, p, f, hex = 0, curdiff; 1401 1402 *diff = 100000000; 1403 1404 for (m = 32; m <= 80; m++) { 1405 for (d = 4; d <= 11; d++) { 1406 for (p = 1; p <= 8; p = p << 1) { 1407 switch (p) { 1408 case 1: 1409 hex = 0x4000 + (d << 7) + m; 1410 break; 1411 case 2: 1412 hex = 0x4800 + (d << 7) + m; 1413 break; 1414 case 4: 1415 hex = 0x5000 + (d << 7) + m; 1416 break; 1417 case 8: 1418 hex = 0x6000 + (d << 7) + m; 1419 break; 1420 } 1421 f = 13500000 * m / d / p; 1422 if (f == request) { 1423 *diff = 0; 1424 *pll = hex; 1425 return; 1426 } else { 1427 curdiff = abs(request - f); 1428 if (curdiff < *diff) { 1429 *diff = curdiff; 1430 *pll = hex; 1431 } 1432 } 1433 } 1434 } 1435 } 1436 } 1437 1438 /* 1439 * Details of the FFB RAMDAC are contained in the Brooktree BT497/498 1440 * and in the Connexant BT497A/498A documentation. 1441 * 1442 * VESA timings to FFB register conversion: 1443 * If interleave = 4/2:1 then x = 2, if interleave = 8/2:1 then x = 4 1444 * VBE = VBS - vres = (sync pulse - 1) + back porch 1445 * VBS = VSS - front porch = (sync pulse - 1) + back porch + vres 1446 * VSE = sync pulse - 1 1447 * VSS = (sync pulse - 1) + back porch + vres + front porch 1448 * HRE = HSS - HSE - 1 1449 * HBE = (sync pulse + back porch) / x - 1 1450 * HBS = (sync pulse + back porch + hres) / x - 1 1451 * HSE = sync pulse / x - 1 1452 * HSS = (sync pulse + back porch + hres + front porch) / x - 1 1453 * HCE = HBS - 4 1454 * HCS = HBE - 4 1455 * EPE = EIE = EIS = 0 (for all non-interlaced modes) 1456 * 1457 * Note, that 8/2:1 Single Buffered Interleaving is only supported by the 1458 * double-buffered FFB (Creator3D), and at higher resolutions than 1280x1024 1459 * 1460 * Note, that the timing generator should be disabled and re-enabled when the 1461 * the timing parameter registers are being programmed. Stopping the timing 1462 * generator should only be done when the vertical counter is zero. 1463 */ 1464 #define DIVIDE(x,y) (((x) + ((y) / 2)) / (y)) 1465 int 1466 ffb_set_vmode(struct ffb_softc *sc, struct videomode *mode, int btype, 1467 int *hres, int *vres) 1468 { 1469 int diff; 1470 uint32_t fp, sp, bp, x; 1471 uint32_t pll, pfc, ucl, dcl, tgc; 1472 uint32_t vbe, vbs, vse, vss, hre, hbe, hbs, hse, hss, hce, hcs; 1473 uint32_t epe, eie, eis; 1474 uint32_t fbcfg0; 1475 1476 DPRINTF(("ffb_set_vmode: %dx%d@%d", mode->hdisplay, mode->vdisplay, 1477 DIVIDE(DIVIDE(mode->dot_clock * 1000, 1478 mode->htotal), mode->vtotal))); 1479 DPRINTF((" (%d %d %d %d %d %d %d", 1480 mode->dot_clock, mode->hsync_start, mode->hsync_end, mode->htotal, 1481 mode->vsync_start, mode->vsync_end, mode->vtotal)); 1482 DPRINTF((" %s%sH %s%sV)\n", 1483 mode->flags & VID_PHSYNC ? "+" : "", 1484 mode->flags & VID_NHSYNC ? "-" : "", 1485 mode->flags & VID_PVSYNC ? "+" : "", 1486 mode->flags & VID_NVSYNC ? "-" : "")); 1487 1488 /* We don't handle interlaced or doublescan (yet) */ 1489 if ((mode->flags & VID_INTERLACE) || (mode->flags & VID_DBLSCAN)) 1490 return 0; 1491 1492 /* Only Creator3D can be set to > 1280x1024 */ 1493 if(((sc->sc_type == FFB_CREATOR && !((btype & 7) == 3)) || 1494 sc->sc_type == FFB_AFB) 1495 && (mode->hdisplay > 1280 || mode->vdisplay > 1024)) 1496 return 0; 1497 /* Creator3D can be set to <= 1920x1360 */ 1498 if (mode->hdisplay > 1920 || mode->vdisplay > 1360) 1499 return 0; 1500 1501 /* 1502 * Look for a matching pixel clock and set PLL Control. 1503 * XXX: 640x480@60 is 25175000 in modelines but 25125000 in the 1504 * FFB PROM, and the closest match to 25175000 (0x4da9/25159090) 1505 * does not work. So, use the PROM value instead. 1506 */ 1507 if (mode->hdisplay == 640 && mode->vdisplay == 480 && 1508 mode->dot_clock == 25175) { 1509 DPRINTF(("ffb_set_vmode: 640x480@60: adjusted dot clock\n")); 1510 mode->dot_clock = 25125; 1511 } 1512 ffb_get_pclk(mode->dot_clock * 1000, &pll, &diff); 1513 if (diff > 250000) 1514 return 0; 1515 1516 /* Pixel Format Control, User Control and FBC Configuration. */ 1517 if (mode->hdisplay > 1280) { 1518 pfc = FFB_DAC_PIX_FMT_821; 1519 ucl = FFB_DAC_USR_CTRL_OVERLAY | FFB_DAC_USR_CTRL_WMODE_C; 1520 x = 4; 1521 fbcfg0 = FBC_READ(sc, FFB_FBC_FBCFG0) | FBC_CFG0_DOUBLE_BUF; 1522 } else { 1523 pfc = FFB_DAC_PIX_FMT_421; 1524 /* Only Creator3D and Elite3D can have double-buffer */ 1525 if ((sc->sc_type == FFB_CREATOR && !((btype & 7) == 3))) 1526 ucl = 0; 1527 else 1528 ucl = FFB_DAC_USR_CTRL_DOUBLE; 1529 ucl |= (FFB_DAC_USR_CTRL_OVERLAY | FFB_DAC_USR_CTRL_WMODE_S8); 1530 x = 2; 1531 fbcfg0 = FBC_READ(sc, FFB_FBC_FBCFG0) | FBC_CFG0_SINGLE_BUF; 1532 } 1533 1534 /* DAC Control and Timing Generator Control */ 1535 if (mode->flags & VID_PVSYNC) 1536 dcl = FFB_DAC_DAC_CTRL_POS_VSYNC; 1537 else 1538 dcl = 0; 1539 tgc = 0; 1540 #define EDID_VID_INP sc->sc_edid_info.edid_video_input 1541 if ((EDID_VID_INP & EDID_VIDEO_INPUT_COMPOSITE_SYNC)) { 1542 dcl |= FFB_DAC_DAC_CTRL_VSYNC_DIS; 1543 tgc = FFB_DAC_TGC_EQUAL_DISABLE; 1544 } else { 1545 dcl |= FFB_DAC_DAC_CTRL_SYNC_G; 1546 if (EDID_VID_INP & EDID_VIDEO_INPUT_SEPARATE_SYNCS) 1547 tgc |= FFB_DAC_TGC_VSYNC_DISABLE; 1548 else 1549 tgc = FFB_DAC_TGC_EQUAL_DISABLE; 1550 } 1551 if (EDID_VID_INP & EDID_VIDEO_INPUT_BLANK_TO_BLACK) 1552 dcl |= FFB_DAC_DAC_CTRL_PED_ENABLE; 1553 tgc |= (FFB_DAC_TGC_VIDEO_ENABLE | FFB_DAC_TGC_TIMING_ENABLE | 1554 FFB_DAC_TGC_MASTER_ENABLE); 1555 1556 /* Vertical timing */ 1557 fp = mode->vsync_start - mode->vdisplay; 1558 sp = mode->vsync_end - mode->vsync_start; 1559 bp = mode->vtotal - mode->vsync_end; 1560 1561 vbe = sp - 1 + bp; 1562 vbs = sp - 1 + bp + mode->vdisplay; 1563 vse = sp - 1; 1564 vss = sp - 1 + bp + mode->vdisplay + fp; 1565 1566 /* Horizontal timing */ 1567 fp = mode->hsync_start - mode->hdisplay; 1568 sp = mode->hsync_end - mode->hsync_start; 1569 bp = mode->htotal - mode->hsync_end; 1570 1571 hbe = (sp + bp) / x - 1; 1572 hbs = (sp + bp + mode->hdisplay) / x - 1; 1573 hse = sp / x - 1; 1574 hss = (sp + bp + mode->hdisplay + fp) / x -1; 1575 hre = hss - hse - 1; 1576 hce = hbs - 4; 1577 hcs = hbe - 4; 1578 1579 /* Equalisation (interlaced modes) */ 1580 epe = 0; 1581 eie = 0; 1582 eis = 0; 1583 1584 DPRINTF(("ffb_set_vmode: 0x%04x 0x%04x 0x%04x 0x%04x 0x%04x\n", 1585 pll, pfc, ucl, dcl, tgc)); 1586 DPRINTF(("\t0x%04x 0x%04x 0x%04x 0x%04x\n", vbe, vbs, vse, vss)); 1587 DPRINTF(("\t0x%04x 0x%04x 0x%04x 0x%04x 0x%04x 0x%04x 0x%04x\n", 1588 hre, hbe, hbs, hse, hss, hce, hcs)); 1589 DPRINTF(("\t0x%04x 0x%04x 0x%04x\n", epe, eie, eis)); 1590 1591 if (!ffb_tgc_disable(sc)) { 1592 DPRINTF(("ffb_set_vmode: failed to disable TGC register\n")); 1593 return 0; 1594 } 1595 1596 /* 1597 * Program the mode registers. 1598 * Program the timing generator last, as that re-enables output. 1599 * Note, that a read to/write from a register increments the 1600 * register address to the next register automatically. 1601 */ 1602 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_PLL_CTRL); 1603 DAC_WRITE(sc, FFB_DAC_VALUE, pll); 1604 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_PIX_FMT); 1605 DAC_WRITE(sc, FFB_DAC_VALUE, pfc); 1606 DAC_WRITE(sc, FFB_DAC_VALUE, ucl); 1607 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_DAC_CTRL); 1608 DAC_WRITE(sc, FFB_DAC_VALUE, dcl); 1609 1610 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_VBE); 1611 DAC_WRITE(sc, FFB_DAC_VALUE, vbe); 1612 DAC_WRITE(sc, FFB_DAC_VALUE, vbs); 1613 DAC_WRITE(sc, FFB_DAC_VALUE, vse); 1614 DAC_WRITE(sc, FFB_DAC_VALUE, vss); 1615 1616 DAC_WRITE(sc, FFB_DAC_VALUE, hre); 1617 DAC_WRITE(sc, FFB_DAC_VALUE, hbe); 1618 DAC_WRITE(sc, FFB_DAC_VALUE, hbs); 1619 DAC_WRITE(sc, FFB_DAC_VALUE, hse); 1620 DAC_WRITE(sc, FFB_DAC_VALUE, hss); 1621 DAC_WRITE(sc, FFB_DAC_VALUE, hce); 1622 DAC_WRITE(sc, FFB_DAC_VALUE, hcs); 1623 1624 DAC_WRITE(sc, FFB_DAC_VALUE, epe); 1625 DAC_WRITE(sc, FFB_DAC_VALUE, eie); 1626 DAC_WRITE(sc, FFB_DAC_VALUE, eis); 1627 1628 FBC_WRITE(sc, FFB_FBC_FBCFG0, fbcfg0); 1629 1630 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_TGC); 1631 DAC_WRITE(sc, FFB_DAC_VALUE, tgc); 1632 DPRINTF(("new tgc: %08x\n", tgc)); 1633 1634 *hres = mode->hdisplay; 1635 *vres = mode->vdisplay; 1636 1637 printf("%s: video mode set to %d x %d @ %dHz\n", 1638 device_xname(sc->sc_dev), 1639 mode->hdisplay, mode->vdisplay, 1640 DIVIDE(DIVIDE(mode->dot_clock * 1000, 1641 mode->htotal), mode->vtotal)); 1642 1643 return 1; 1644 } 1645
Indexes created Thu Sep 25 16:09:42 GMT 2025