ffb.c revision 1.65
1 /* $NetBSD: ffb.c,v 1.65 2020/07/05 09:55:07 martin Exp $ */ 2 /* $OpenBSD: creator.c,v 1.20 2002/07/30 19:48:15 jason Exp $ */ 3 4 /* 5 * Copyright (c) 2002 Jason L. Wright (jason (at) thought.net) 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Jason L. Wright 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 25 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 26 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 27 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 30 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 31 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32 * POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: ffb.c,v 1.65 2020/07/05 09:55:07 martin Exp $"); 37 38 #include <sys/types.h> 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/kernel.h> 42 #include <sys/device.h> 43 #include <sys/conf.h> 44 #include <sys/ioctl.h> 45 #include <sys/malloc.h> 46 #include <sys/mman.h> 47 48 #include <sys/bus.h> 49 #include <machine/autoconf.h> 50 #include <machine/openfirm.h> 51 #include <machine/vmparam.h> 52 53 #include <dev/wscons/wsconsio.h> 54 #include <dev/sun/fbio.h> 55 #include <dev/sun/fbvar.h> 56 57 #include <dev/wsfont/wsfont.h> 58 #include <dev/wscons/wsdisplay_vconsvar.h> 59 60 #include <prop/proplib.h> 61 62 #include <dev/i2c/i2cvar.h> 63 #include <dev/i2c/i2c_bitbang.h> 64 #include <dev/i2c/ddcvar.h> 65 66 #include <sparc64/dev/ffbreg.h> 67 #include <sparc64/dev/ffbvar.h> 68 69 #include "opt_wsdisplay_compat.h" 70 #include "opt_ffb.h" 71 72 #ifndef WS_DEFAULT_BG 73 /* Sun -> background should be white */ 74 #define WS_DEFAULT_BG 0xf 75 #endif 76 77 #ifdef FFB_SYNC 78 #define SYNC ffb_ras_wait(sc) 79 #else 80 #define SYNC 81 #endif 82 83 /* Debugging */ 84 #if !defined FFB_DEBUG 85 #define FFB_DEBUG 0 86 #endif 87 #define DPRINTF(x) if (ffb_debug) printf x 88 /* Patchable */ 89 extern int ffb_debug; 90 #if FFB_DEBUG > 0 91 int ffb_debug = 1; 92 #else 93 int ffb_debug = 0; 94 #endif 95 96 extern struct cfdriver ffb_cd; 97 98 struct wsscreen_descr ffb_stdscreen = { 99 "sunffb", 100 0, 0, /* will be filled in -- XXX shouldn't, it's global. */ 101 0, 102 0, 0, 103 WSSCREEN_REVERSE | WSSCREEN_WSCOLORS | WSSCREEN_UNDERLINE | 104 WSSCREEN_RESIZE, 105 NULL /* modecookie */ 106 }; 107 108 const struct wsscreen_descr *ffb_scrlist[] = { 109 &ffb_stdscreen, 110 /* XXX other formats? */ 111 }; 112 113 struct wsscreen_list ffb_screenlist = { 114 sizeof(ffb_scrlist) / sizeof(struct wsscreen_descr *), 115 ffb_scrlist 116 }; 117 118 static struct vcons_screen ffb_console_screen; 119 120 int ffb_ioctl(void *, void *, u_long, void *, int, struct lwp *); 121 static int ffb_blank(struct ffb_softc *, u_long, u_int *); 122 paddr_t ffb_mmap(void *, void *, off_t, int); 123 void ffb_ras_fifo_wait(struct ffb_softc *, int); 124 void ffb_ras_wait(struct ffb_softc *); 125 void ffb_ras_init(struct ffb_softc *); 126 void ffb_ras_copyrows(void *, int, int, int); 127 void ffb_ras_erasecols(void *, int, int, int, long int); 128 void ffb_ras_eraserows(void *, int, int, long int); 129 void ffb_ras_fill(struct ffb_softc *); 130 void ffb_ras_invert(struct ffb_softc *); 131 static void ffb_ras_setfg(struct ffb_softc *, int32_t); 132 static void ffb_ras_setbg(struct ffb_softc *, int32_t); 133 134 void ffb_clearscreen(struct ffb_softc *); 135 void ffb_init_screen(void *, struct vcons_screen *, int, 136 long *); 137 int ffb_allocattr(void *, int, int, int, long *); 138 void ffb_putchar_mono(void *, int, int, u_int, long); 139 void ffb_putchar_aa(void *, int, int, u_int, long); 140 void ffb_cursor(void *, int, int, int); 141 142 /* frame buffer generic driver */ 143 static void ffbfb_unblank(device_t); 144 dev_type_open(ffbfb_open); 145 dev_type_close(ffbfb_close); 146 dev_type_ioctl(ffbfb_ioctl); 147 dev_type_mmap(ffbfb_mmap); 148 149 static struct fbdriver ffb_fbdriver = { 150 ffbfb_unblank, ffbfb_open, ffbfb_close, ffbfb_ioctl, nopoll, 151 ffbfb_mmap, nokqfilter 152 }; 153 154 struct wsdisplay_accessops ffb_accessops = { 155 .ioctl = ffb_ioctl, 156 .mmap = ffb_mmap, 157 }; 158 159 /* I2C glue */ 160 static int ffb_i2c_send_start(void *, int); 161 static int ffb_i2c_send_stop(void *, int); 162 static int ffb_i2c_initiate_xfer(void *, i2c_addr_t, int); 163 static int ffb_i2c_read_byte(void *, uint8_t *, int); 164 static int ffb_i2c_write_byte(void *, uint8_t, int); 165 166 /* I2C bitbang glue */ 167 static void ffb_i2cbb_set_bits(void *, uint32_t); 168 static void ffb_i2cbb_set_dir(void *, uint32_t); 169 static uint32_t ffb_i2cbb_read(void *); 170 171 static const struct i2c_bitbang_ops ffb_i2cbb_ops = { 172 ffb_i2cbb_set_bits, 173 ffb_i2cbb_set_dir, 174 ffb_i2cbb_read, 175 { 176 FFB_DAC_CFG_MPDATA_SDA, 177 FFB_DAC_CFG_MPDATA_SCL, 178 0, 179 0 180 } 181 }; 182 183 void ffb_attach_i2c(struct ffb_softc *); 184 185 /* Video mode setting */ 186 int ffb_tgc_disable(struct ffb_softc *); 187 void ffb_get_pclk(int, uint32_t *, int *); 188 int ffb_set_vmode(struct ffb_softc *, struct videomode *, int, int *, int *); 189 190 191 void 192 ffb_attach(device_t self) 193 { 194 struct ffb_softc *sc = device_private(self); 195 struct wsemuldisplaydev_attach_args waa; 196 struct rasops_info *ri; 197 long defattr; 198 const char *model, *out_dev; 199 int btype; 200 uint32_t dac; 201 int maxrow; 202 u_int blank = WSDISPLAYIO_VIDEO_ON; 203 char buf[6+1]; 204 int i, try_edid; 205 prop_data_t data; 206 207 printf(":"); 208 209 if (sc->sc_type == FFB_CREATOR) { 210 btype = prom_getpropint(sc->sc_node, "board_type", 0); 211 if ((btype & 7) == 3) 212 printf(" Creator3D"); 213 else 214 printf(" Creator"); 215 } else { 216 printf(" Elite3D"); 217 btype = 0; 218 } 219 220 model = prom_getpropstring(sc->sc_node, "model"); 221 if (model == NULL || strlen(model) == 0) 222 model = "unknown"; 223 224 sc->sc_depth = 24; 225 sc->sc_linebytes = 8192; 226 /* We might alter these during EDID mode setting */ 227 sc->sc_height = prom_getpropint(sc->sc_node, "height", 0); 228 sc->sc_width = prom_getpropint(sc->sc_node, "width", 0); 229 230 sc->sc_locked = 0; 231 sc->sc_mode = WSDISPLAYIO_MODE_EMUL; 232 233 maxrow = (prom_getoption("screen-#rows", buf, sizeof buf) != 0) 234 ? strtoul(buf, NULL, 10) 235 : 34; 236 237 /* collect DAC version, as Elite3D cursor enable bit is reversed */ 238 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_DEVID); 239 dac = DAC_READ(sc, FFB_DAC_VALUE); 240 sc->sc_dacrev = (dac >> 28) & 0xf; 241 242 if (sc->sc_type == FFB_AFB) { 243 sc->sc_dacrev = 10; 244 sc->sc_needredraw = 0; 245 } else { 246 /* see what kind of DAC we have */ 247 int pnum = (dac & 0x0ffff000) >> 12; 248 if (pnum == 0x236e) { 249 sc->sc_needredraw = 0; 250 } else { 251 sc->sc_needredraw = 1; 252 } 253 } 254 printf(", model %s, dac %u\n", model, sc->sc_dacrev); 255 if (sc->sc_needredraw) 256 printf("%s: found old DAC, enabling redraw on unblank\n", 257 device_xname(sc->sc_dev)); 258 259 /* Check if a console resolution "<device>:r<res>" is set. */ 260 if (sc->sc_console) { 261 out_dev = prom_getpropstring(sc->sc_node, "output-device"); 262 if (out_dev != NULL && strlen(out_dev) != 0 && 263 strstr(out_dev, ":r") != NULL) 264 try_edid = 0; 265 else 266 try_edid = 1; 267 } else 268 try_edid = 1; 269 270 #if FFB_DEBUG > 0 271 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_TGC); 272 printf("tgc: %08x\n", DAC_READ(sc, FFB_DAC_VALUE)); 273 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_DAC_CTRL); 274 printf("dcl: %08x\n", DAC_READ(sc, FFB_DAC_VALUE)); 275 #endif 276 ffb_attach_i2c(sc); 277 278 /* Need to set asynchronous blank during DDC write/read */ 279 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_USR_CTRL); 280 dac = DAC_READ(sc, FFB_DAC_VALUE); 281 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_USR_CTRL); 282 DAC_WRITE(sc, FFB_DAC_VALUE, dac | FFB_DAC_USR_CTRL_BLANK); 283 284 /* Some monitors don't respond first time */ 285 i = 0; 286 while (sc->sc_edid_data[1] == 0 && i++ < 3) 287 ddc_read_edid(&sc->sc_i2c, sc->sc_edid_data, EDID_DATA_LEN); 288 289 /* Remove asynchronous blank */ 290 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_USR_CTRL); 291 DAC_WRITE(sc, FFB_DAC_VALUE, dac); 292 293 if (edid_parse(&sc->sc_edid_data[0], &sc->sc_edid_info) != -1) { 294 sort_modes(sc->sc_edid_info.edid_modes, 295 &sc->sc_edid_info.edid_preferred_mode, 296 sc->sc_edid_info.edid_nmodes); 297 DPRINTF(("%s: EDID data:\n ", device_xname(sc->sc_dev))); 298 for (i = 0; i < EDID_DATA_LEN; i++) { 299 if (i && !(i % 32)) 300 DPRINTF(("\n ")); 301 if (i && !(i % 4)) 302 DPRINTF((" ")); 303 DPRINTF(("%02x", sc->sc_edid_data[i])); 304 } 305 DPRINTF(("\n")); 306 if (ffb_debug) 307 edid_print(&sc->sc_edid_info); 308 309 data = prop_data_create_copy(sc->sc_edid_data, EDID_DATA_LEN); 310 prop_dictionary_set(device_properties(self), "EDID", data); 311 prop_object_release(data); 312 313 if (try_edid) 314 for (i = 0; i < sc->sc_edid_info.edid_nmodes; i++) { 315 if (ffb_set_vmode(sc, 316 &(sc->sc_edid_info.edid_modes[i]), btype, 317 &(sc->sc_width), &(sc->sc_height))) 318 break; 319 } 320 } else { 321 DPRINTF(("%s: No EDID data.\n", device_xname(sc->sc_dev))); 322 } 323 324 ffb_ras_init(sc); 325 326 ffb_blank(sc, WSDISPLAYIO_SVIDEO, &blank); 327 328 sc->sc_accel = ((device_cfdata(sc->sc_dev)->cf_flags & 329 FFB_CFFLAG_NOACCEL) == 0); 330 331 wsfont_init(); 332 333 vcons_init(&sc->vd, sc, &ffb_stdscreen, &ffb_accessops); 334 sc->vd.init_screen = ffb_init_screen; 335 ri = &ffb_console_screen.scr_ri; 336 337 /* we mess with ffb_console_screen only once */ 338 if (sc->sc_console) { 339 ffb_console_screen.scr_flags = VCONS_SCREEN_IS_STATIC; 340 vcons_init_screen(&sc->vd, &ffb_console_screen, 1, &defattr); 341 SCREEN_VISIBLE((&ffb_console_screen)); 342 /* 343 * XXX we shouldn't use a global variable for the console 344 * screen 345 */ 346 sc->vd.active = &ffb_console_screen; 347 } else { 348 if (ffb_console_screen.scr_ri.ri_rows == 0) { 349 /* do some minimal setup to avoid weirdnesses later */ 350 vcons_init_screen(&sc->vd, &ffb_console_screen, 1, &defattr); 351 } else 352 (*ri->ri_ops.allocattr)(ri, 0, 0, 0, &defattr); 353 } 354 355 ffb_stdscreen.nrows = ri->ri_rows; 356 ffb_stdscreen.ncols = ri->ri_cols; 357 ffb_stdscreen.textops = &ri->ri_ops; 358 359 sc->sc_fb.fb_driver = &ffb_fbdriver; 360 sc->sc_fb.fb_type.fb_cmsize = 0; 361 sc->sc_fb.fb_type.fb_size = maxrow * sc->sc_linebytes; 362 sc->sc_fb.fb_type.fb_type = FBTYPE_CREATOR; 363 sc->sc_fb.fb_type.fb_width = sc->sc_width; 364 sc->sc_fb.fb_type.fb_depth = sc->sc_depth; 365 sc->sc_fb.fb_type.fb_height = sc->sc_height; 366 sc->sc_fb.fb_device = sc->sc_dev; 367 fb_attach(&sc->sc_fb, sc->sc_console); 368 369 ffb_clearscreen(sc); 370 371 if (sc->sc_console) { 372 wsdisplay_cnattach(&ffb_stdscreen, ri, 0, 0, defattr); 373 vcons_replay_msgbuf(&ffb_console_screen); 374 } 375 376 waa.console = sc->sc_console; 377 waa.scrdata = &ffb_screenlist; 378 waa.accessops = &ffb_accessops; 379 waa.accesscookie = &sc->vd; 380 config_found(sc->sc_dev, &waa, wsemuldisplaydevprint); 381 } 382 383 void 384 ffb_attach_i2c(struct ffb_softc *sc) 385 { 386 387 /* Fill in the i2c tag */ 388 iic_tag_init(&sc->sc_i2c); 389 sc->sc_i2c.ic_cookie = sc; 390 sc->sc_i2c.ic_send_start = ffb_i2c_send_start; 391 sc->sc_i2c.ic_send_stop = ffb_i2c_send_stop; 392 sc->sc_i2c.ic_initiate_xfer = ffb_i2c_initiate_xfer; 393 sc->sc_i2c.ic_read_byte = ffb_i2c_read_byte; 394 sc->sc_i2c.ic_write_byte = ffb_i2c_write_byte; 395 } 396 397 int 398 ffb_ioctl(void *v, void *vs, u_long cmd, void *data, int flags, struct lwp *l) 399 { 400 struct vcons_data *vd = v; 401 struct ffb_softc *sc = vd->cookie; 402 struct wsdisplay_fbinfo *wdf; 403 struct vcons_screen *ms = vd->active; 404 405 DPRINTF(("ffb_ioctl: %s cmd _IO%s%s('%c', %lu)\n", 406 device_xname(sc->sc_dev), 407 (cmd & IOC_IN) ? "W" : "", (cmd & IOC_OUT) ? "R" : "", 408 (char)IOCGROUP(cmd), cmd & 0xff)); 409 410 switch (cmd) { 411 case FBIOGTYPE: 412 *(struct fbtype *)data = sc->sc_fb.fb_type; 413 break; 414 case FBIOGATTR: 415 #define fba ((struct fbgattr *)data) 416 fba->real_type = sc->sc_fb.fb_type.fb_type; 417 fba->owner = 0; /* XXX ??? */ 418 fba->fbtype = sc->sc_fb.fb_type; 419 fba->sattr.flags = 0; 420 fba->sattr.emu_type = sc->sc_fb.fb_type.fb_type; 421 fba->sattr.dev_specific[0] = -1; 422 fba->emu_types[0] = sc->sc_fb.fb_type.fb_type; 423 fba->emu_types[1] = -1; 424 #undef fba 425 break; 426 427 case FBIOGETCMAP: 428 case FBIOPUTCMAP: 429 return EIO; 430 431 case FBIOGVIDEO: 432 case FBIOSVIDEO: 433 return ffb_blank(sc, cmd == FBIOGVIDEO? 434 WSDISPLAYIO_GVIDEO : WSDISPLAYIO_SVIDEO, 435 (u_int *)data); 436 break; 437 case FBIOGCURSOR: 438 case FBIOSCURSOR: 439 /* the console driver is not using the hardware cursor */ 440 break; 441 case FBIOGCURPOS: 442 printf("%s: FBIOGCURPOS not implemented\n", 443 device_xname(sc->sc_dev)); 444 return EIO; 445 case FBIOSCURPOS: 446 printf("%s: FBIOSCURPOS not implemented\n", 447 device_xname(sc->sc_dev)); 448 return EIO; 449 case FBIOGCURMAX: 450 printf("%s: FBIOGCURMAX not implemented\n", 451 device_xname(sc->sc_dev)); 452 return EIO; 453 454 case WSDISPLAYIO_GTYPE: 455 *(u_int *)data = WSDISPLAY_TYPE_SUNFFB; 456 break; 457 case WSDISPLAYIO_SMODE: 458 { 459 if (sc->sc_mode != *(u_int *)data) { 460 sc->sc_mode = *(u_int *)data; 461 if ((sc->sc_mode == WSDISPLAYIO_MODE_EMUL) && 462 (sc->sc_locked == 0)) { 463 ffb_ras_init(sc); 464 vcons_redraw_screen(ms); 465 } else { 466 ffb_ras_wait(sc); 467 } 468 } 469 } 470 break; 471 case WSDISPLAYIO_GINFO: 472 wdf = (void *)data; 473 wdf->height = sc->sc_height; 474 wdf->width = sc->sc_width; 475 wdf->depth = 32; 476 wdf->cmsize = 256; /* XXX */ 477 break; 478 #ifdef WSDISPLAYIO_LINEBYTES 479 case WSDISPLAYIO_LINEBYTES: 480 *(u_int *)data = sc->sc_linebytes; 481 break; 482 #endif 483 case WSDISPLAYIO_GETCMAP: 484 break;/* XXX */ 485 486 case WSDISPLAYIO_PUTCMAP: 487 break;/* XXX */ 488 489 case WSDISPLAYIO_SVIDEO: 490 case WSDISPLAYIO_GVIDEO: 491 return(ffb_blank(sc, cmd, (u_int *)data)); 492 break; 493 494 case WSDISPLAYIO_GCURPOS: 495 case WSDISPLAYIO_SCURPOS: 496 case WSDISPLAYIO_GCURMAX: 497 case WSDISPLAYIO_GCURSOR: 498 case WSDISPLAYIO_SCURSOR: 499 return EIO; /* not supported yet */ 500 break; 501 502 case WSDISPLAYIO_GET_EDID: { 503 struct wsdisplayio_edid_info *d = data; 504 return wsdisplayio_get_edid(sc->sc_dev, d); 505 } 506 507 case WSDISPLAYIO_GET_FBINFO: { 508 struct wsdisplayio_fbinfo *fbi = data; 509 return wsdisplayio_get_fbinfo(&ms->scr_ri, fbi); 510 } 511 512 default: 513 return EPASSTHROUGH; 514 } 515 516 return (0); 517 } 518 519 /* blank/unblank the screen */ 520 static int 521 ffb_blank(struct ffb_softc *sc, u_long cmd, u_int *data) 522 { 523 struct vcons_screen *ms = sc->vd.active; 524 u_int val; 525 526 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_TGC); 527 val = DAC_READ(sc, FFB_DAC_VALUE); 528 529 switch (cmd) { 530 case WSDISPLAYIO_GVIDEO: 531 *data = val & 1; 532 return(0); 533 break; 534 case WSDISPLAYIO_SVIDEO: 535 if (*data == WSDISPLAYIO_VIDEO_OFF) 536 val &= ~1; 537 else if (*data == WSDISPLAYIO_VIDEO_ON) 538 val |= 1; 539 else 540 return(EINVAL); 541 break; 542 default: 543 return(EINVAL); 544 } 545 546 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_TGC); 547 DAC_WRITE(sc, FFB_DAC_VALUE, val); 548 549 if ((val & 1) && sc->sc_needredraw) { 550 if (ms != NULL) { 551 if ((sc->sc_mode == WSDISPLAYIO_MODE_EMUL) && 552 (sc->sc_locked == 0)) { 553 ffb_ras_init(sc); 554 vcons_redraw_screen(ms); 555 } 556 } 557 } 558 559 return(0); 560 } 561 562 paddr_t 563 ffb_mmap(void *vsc, void *vs, off_t off, int prot) 564 { 565 struct vcons_data *vd = vsc; 566 struct ffb_softc *sc = vd->cookie; 567 int i; 568 569 switch (sc->sc_mode) { 570 case WSDISPLAYIO_MODE_MAPPED: 571 for (i = 0; i < sc->sc_nreg; i++) { 572 /* Before this set? */ 573 if (off < sc->sc_addrs[i]) 574 continue; 575 /* After this set? */ 576 if (off >= (sc->sc_addrs[i] + sc->sc_sizes[i])) 577 continue; 578 579 return (bus_space_mmap(sc->sc_bt, sc->sc_addrs[i], 580 off - sc->sc_addrs[i], prot, BUS_SPACE_MAP_LINEAR)); 581 } 582 break; 583 #ifdef WSDISPLAYIO_MODE_DUMBFB 584 case WSDISPLAYIO_MODE_DUMBFB: 585 if (sc->sc_nreg < FFB_REG_DFB24) 586 break; 587 if (off >= 0 && off < sc->sc_sizes[FFB_REG_DFB24]) 588 return (bus_space_mmap(sc->sc_bt, 589 sc->sc_addrs[FFB_REG_DFB24], off, prot, 590 BUS_SPACE_MAP_LINEAR | BUS_SPACE_MAP_PREFETCHABLE)); 591 break; 592 #endif 593 } 594 return (-1); 595 } 596 597 void 598 ffb_ras_fifo_wait(struct ffb_softc *sc, int n) 599 { 600 int32_t cache = sc->sc_fifo_cache; 601 602 if (cache < n) { 603 do { 604 cache = FBC_READ(sc, FFB_FBC_UCSR); 605 cache = (cache & FBC_UCSR_FIFO_MASK) - 8; 606 } while (cache < n); 607 } 608 sc->sc_fifo_cache = cache - n; 609 } 610 611 void 612 ffb_ras_wait(struct ffb_softc *sc) 613 { 614 uint32_t ucsr, r; 615 616 while (1) { 617 ucsr = FBC_READ(sc, FFB_FBC_UCSR); 618 if ((ucsr & (FBC_UCSR_FB_BUSY|FBC_UCSR_RP_BUSY)) == 0) 619 break; 620 r = ucsr & (FBC_UCSR_READ_ERR | FBC_UCSR_FIFO_OVFL); 621 if (r != 0) 622 FBC_WRITE(sc, FFB_FBC_UCSR, r); 623 } 624 } 625 626 void 627 ffb_ras_init(struct ffb_softc *sc) 628 { 629 uint32_t fbc; 630 631 if (sc->sc_width > 1280) { 632 DPRINTF(("ffb_ras_init: high resolution.\n")); 633 fbc = FFB_FBC_WM_COMBINED | FFB_FBC_WE_FORCEON | 634 FFB_FBC_ZE_OFF | FFB_FBC_YE_OFF | FFB_FBC_XE_ON; 635 } else { 636 DPRINTF(("ffb_ras_init: standard resolution.\n")); 637 fbc = FFB_FBC_XE_OFF; 638 } 639 ffb_ras_fifo_wait(sc, 7); 640 DPRINTF(("WID: %08x\n", FBC_READ(sc, FFB_FBC_WID))); 641 FBC_WRITE(sc, FFB_FBC_WID, 0x0); 642 FBC_WRITE(sc, FFB_FBC_PPC, 643 FBC_PPC_VCE_DIS | FBC_PPC_TBE_OPAQUE | FBC_PPC_ACE_DIS | 644 FBC_PPC_APE_DIS | FBC_PPC_DCE_DIS | FBC_PPC_CS_CONST | 645 FBC_PPC_ABE_DIS | FBC_PPC_XS_WID); 646 647 fbc |= FFB_FBC_WB_A | FFB_FBC_RB_A | FFB_FBC_SB_BOTH | 648 FFB_FBC_RGBE_MASK; 649 DPRINTF(("%s: fbc is %08x\n", __func__, fbc)); 650 FBC_WRITE(sc, FFB_FBC_FBC, fbc); 651 FBC_WRITE(sc, FFB_FBC_ROP, FBC_ROP_NEW); 652 FBC_WRITE(sc, FFB_FBC_DRAWOP, FBC_DRAWOP_RECTANGLE); 653 FBC_WRITE(sc, FFB_FBC_PMASK, 0xffffffff); 654 FBC_WRITE(sc, FFB_FBC_FONTINC, 0x10000); 655 ffb_ras_fifo_wait(sc, 5); 656 sc->sc_fg_cache = 0; 657 FBC_WRITE(sc, FFB_FBC_FG, sc->sc_fg_cache); 658 sc->sc_bg_cache = 0; 659 FBC_WRITE(sc, FFB_FBC_BG, sc->sc_bg_cache); 660 FBC_WRITE(sc, FFB_FBC_BLENDC, FFB_BLENDC_FORCE_ONE | 661 FFB_BLENDC_DF_ONE_M_A | 662 FFB_BLENDC_SF_A); 663 FBC_WRITE(sc, FFB_FBC_BLENDC1, 0); 664 FBC_WRITE(sc, FFB_FBC_BLENDC2, 0); 665 ffb_ras_wait(sc); 666 } 667 668 void 669 ffb_ras_eraserows(void *cookie, int row, int n, long attr) 670 { 671 struct rasops_info *ri = cookie; 672 struct vcons_screen *scr = ri->ri_hw; 673 struct ffb_softc *sc = scr->scr_cookie; 674 675 if (row < 0) { 676 n += row; 677 row = 0; 678 } 679 if (row + n > ri->ri_rows) 680 n = ri->ri_rows - row; 681 if (n <= 0) 682 return; 683 684 ffb_ras_fill(sc); 685 ffb_ras_setfg(sc, ri->ri_devcmap[(attr >> 16) & 0xf]); 686 ffb_ras_fifo_wait(sc, 4); 687 if ((n == ri->ri_rows) && (ri->ri_flg & RI_FULLCLEAR)) { 688 FBC_WRITE(sc, FFB_FBC_BY, 0); 689 FBC_WRITE(sc, FFB_FBC_BX, 0); 690 FBC_WRITE(sc, FFB_FBC_BH, ri->ri_height); 691 FBC_WRITE(sc, FFB_FBC_BW, ri->ri_width); 692 ri->ri_flg &= ~RI_CURSOR; 693 } else { 694 row *= ri->ri_font->fontheight; 695 FBC_WRITE(sc, FFB_FBC_BY, ri->ri_yorigin + row); 696 FBC_WRITE(sc, FFB_FBC_BX, ri->ri_xorigin); 697 FBC_WRITE(sc, FFB_FBC_BH, n * ri->ri_font->fontheight); 698 FBC_WRITE(sc, FFB_FBC_BW, ri->ri_emuwidth); 699 } 700 SYNC; 701 } 702 703 void 704 ffb_ras_erasecols(void *cookie, int row, int col, int n, long attr) 705 { 706 struct rasops_info *ri = cookie; 707 struct vcons_screen *scr = ri->ri_hw; 708 struct ffb_softc *sc = scr->scr_cookie; 709 710 if ((row < 0) || (row >= ri->ri_rows)) 711 return; 712 if (col < 0) { 713 n += col; 714 col = 0; 715 } 716 if (col + n > ri->ri_cols) 717 n = ri->ri_cols - col; 718 if (n <= 0) 719 return; 720 721 n *= ri->ri_font->fontwidth; 722 col *= ri->ri_font->fontwidth; 723 row *= ri->ri_font->fontheight; 724 725 ffb_ras_fill(sc); 726 ffb_ras_setfg(sc, ri->ri_devcmap[(attr >> 16) & 0xf]); 727 ffb_ras_fifo_wait(sc, 4); 728 FBC_WRITE(sc, FFB_FBC_BY, ri->ri_yorigin + row); 729 FBC_WRITE(sc, FFB_FBC_BX, ri->ri_xorigin + col); 730 FBC_WRITE(sc, FFB_FBC_BH, ri->ri_font->fontheight); 731 FBC_WRITE(sc, FFB_FBC_BW, n); 732 SYNC; 733 } 734 735 void 736 ffb_ras_fill(struct ffb_softc *sc) 737 { 738 ffb_ras_fifo_wait(sc, 3); 739 FBC_WRITE(sc, FFB_FBC_PPC, 740 FBC_PPC_VCE_DIS | FBC_PPC_TBE_OPAQUE | FBC_PPC_ACE_DIS | 741 FBC_PPC_APE_DIS | FBC_PPC_DCE_DIS | FBC_PPC_CS_CONST | 742 FBC_PPC_ABE_DIS | FBC_PPC_XS_WID); 743 FBC_WRITE(sc, FFB_FBC_ROP, FBC_ROP_NEW); 744 FBC_WRITE(sc, FFB_FBC_DRAWOP, FBC_DRAWOP_RECTANGLE); 745 SYNC; 746 } 747 748 void 749 ffb_ras_invert(struct ffb_softc *sc) 750 { 751 ffb_ras_fifo_wait(sc, 3); 752 FBC_WRITE(sc, FFB_FBC_PPC, 753 FBC_PPC_VCE_DIS | FBC_PPC_TBE_OPAQUE | FBC_PPC_ACE_DIS | 754 FBC_PPC_APE_DIS | FBC_PPC_DCE_DIS | FBC_PPC_CS_CONST | 755 FBC_PPC_ABE_DIS | FBC_PPC_XS_WID); 756 FBC_WRITE(sc, FFB_FBC_ROP, FBC_ROP_INVERT); 757 FBC_WRITE(sc, FFB_FBC_DRAWOP, FBC_DRAWOP_RECTANGLE); 758 SYNC; 759 } 760 761 void 762 ffb_ras_copyrows(void *cookie, int src, int dst, int n) 763 { 764 struct rasops_info *ri = cookie; 765 struct vcons_screen *scr = ri->ri_hw; 766 struct ffb_softc *sc = scr->scr_cookie; 767 768 if (dst == src) 769 return; 770 if (src < 0) { 771 n += src; 772 src = 0; 773 } 774 if ((src + n) > ri->ri_rows) 775 n = ri->ri_rows - src; 776 if (dst < 0) { 777 n += dst; 778 dst = 0; 779 } 780 if ((dst + n) > ri->ri_rows) 781 n = ri->ri_rows - dst; 782 if (n <= 0) 783 return; 784 n *= ri->ri_font->fontheight; 785 src *= ri->ri_font->fontheight; 786 dst *= ri->ri_font->fontheight; 787 788 ffb_ras_fifo_wait(sc, 9); 789 FBC_WRITE(sc, FFB_FBC_PPC, 790 FBC_PPC_VCE_DIS | FBC_PPC_TBE_OPAQUE | FBC_PPC_ACE_DIS | 791 FBC_PPC_APE_DIS | FBC_PPC_DCE_DIS | FBC_PPC_CS_CONST | 792 FBC_PPC_ABE_DIS | FBC_PPC_XS_WID); 793 FBC_WRITE(sc, FFB_FBC_ROP, FBC_ROP_OLD | (FBC_ROP_OLD << 8)); 794 FBC_WRITE(sc, FFB_FBC_DRAWOP, FBC_DRAWOP_VSCROLL); 795 FBC_WRITE(sc, FFB_FBC_BY, ri->ri_yorigin + src); 796 FBC_WRITE(sc, FFB_FBC_BX, ri->ri_xorigin); 797 FBC_WRITE(sc, FFB_FBC_DY, ri->ri_yorigin + dst); 798 FBC_WRITE(sc, FFB_FBC_DX, ri->ri_xorigin); 799 FBC_WRITE(sc, FFB_FBC_BH, n); 800 FBC_WRITE(sc, FFB_FBC_BW, ri->ri_emuwidth); 801 SYNC; 802 } 803 804 static void 805 ffb_ras_setfg(struct ffb_softc *sc, int32_t fg) 806 { 807 ffb_ras_fifo_wait(sc, 1); 808 if (fg == sc->sc_fg_cache) 809 return; 810 sc->sc_fg_cache = fg; 811 FBC_WRITE(sc, FFB_FBC_FG, fg); 812 SYNC; 813 } 814 815 static void 816 ffb_ras_setbg(struct ffb_softc *sc, int32_t bg) 817 { 818 ffb_ras_fifo_wait(sc, 1); 819 if (bg == sc->sc_bg_cache) 820 return; 821 sc->sc_bg_cache = bg; 822 FBC_WRITE(sc, FFB_FBC_BG, bg); 823 SYNC; 824 } 825 826 /* frame buffer generic driver support functions */ 827 static void 828 ffbfb_unblank(device_t dev) 829 { 830 struct ffb_softc *sc = device_private(dev); 831 struct vcons_screen *ms = sc->vd.active; 832 u_int on = 1; 833 int redraw = 0; 834 835 ffb_ras_init(sc); 836 if (sc->sc_locked) { 837 sc->sc_locked = 0; 838 redraw = 1; 839 } 840 841 ffb_blank(sc, WSDISPLAYIO_SVIDEO, &on); 842 #if 0 843 if ((sc->vd.active != &ffb_console_screen) && 844 (ffb_console_screen.scr_flags & VCONS_SCREEN_IS_STATIC)) { 845 /* 846 * force-switch to the console screen. 847 * Caveat: the higher layer will think we're still on the 848 * other screen 849 */ 850 851 SCREEN_INVISIBLE(sc->vd.active); 852 sc->vd.active = &ffb_console_screen; 853 SCREEN_VISIBLE(sc->vd.active); 854 ms = sc->vd.active; 855 redraw = 1; 856 } 857 #endif 858 if (redraw) { 859 vcons_redraw_screen(ms); 860 } 861 } 862 863 int 864 ffbfb_open(dev_t dev, int flags, int mode, struct lwp *l) 865 { 866 struct ffb_softc *sc; 867 868 sc = device_lookup_private(&ffb_cd, minor(dev)); 869 if (sc == NULL) 870 return ENXIO; 871 872 sc->sc_locked = 1; 873 return 0; 874 } 875 876 int 877 ffbfb_close(dev_t dev, int flags, int mode, struct lwp *l) 878 { 879 struct ffb_softc *sc = device_lookup_private(&ffb_cd, minor(dev)); 880 struct vcons_screen *ms = sc->vd.active; 881 882 sc->sc_locked = 0; 883 if (ms != NULL) { 884 if ((sc->sc_mode == WSDISPLAYIO_MODE_EMUL) && 885 (sc->sc_locked == 0)) { 886 ffb_ras_init(sc); 887 vcons_redraw_screen(ms); 888 } 889 } 890 return 0; 891 } 892 893 int 894 ffbfb_ioctl(dev_t dev, u_long cmd, void *data, int flags, struct lwp *l) 895 { 896 struct ffb_softc *sc = device_lookup_private(&ffb_cd, minor(dev)); 897 898 return ffb_ioctl(&sc->vd, NULL, cmd, data, flags, l); 899 } 900 901 paddr_t 902 ffbfb_mmap(dev_t dev, off_t off, int prot) 903 { 904 struct ffb_softc *sc = device_lookup_private(&ffb_cd, minor(dev)); 905 uint64_t size; 906 int i, reg; 907 off_t o; 908 909 /* 910 * off is a magic cookie (see xfree86/drivers/sunffb/ffb.h), 911 * which we map to an index into the "reg" property, and use 912 * our copy of the firmware data as arguments for the real 913 * mapping. 914 */ 915 static struct { unsigned long voff; int reg; long flags; } map[] = { 916 { 0x00000000, FFB_REG_SFB8R, BUS_SPACE_MAP_PREFETCHABLE }, 917 { 0x00400000, FFB_REG_SFB8G, BUS_SPACE_MAP_PREFETCHABLE }, 918 { 0x00800000, FFB_REG_SFB8B, BUS_SPACE_MAP_PREFETCHABLE }, 919 { 0x00c00000, FFB_REG_SFB8X, BUS_SPACE_MAP_PREFETCHABLE }, 920 { 0x01000000, FFB_REG_SFB32, BUS_SPACE_MAP_PREFETCHABLE }, 921 { 0x02000000, FFB_REG_SFB64, BUS_SPACE_MAP_PREFETCHABLE }, 922 { 0x04000000, FFB_REG_FBC, 0 }, 923 { 0x04004000, FFB_REG_DFB8R, BUS_SPACE_MAP_PREFETCHABLE }, 924 { 0x04404000, FFB_REG_DFB8G, BUS_SPACE_MAP_PREFETCHABLE }, 925 { 0x04804000, FFB_REG_DFB8B, BUS_SPACE_MAP_PREFETCHABLE }, 926 { 0x04c04000, FFB_REG_DFB8X, BUS_SPACE_MAP_PREFETCHABLE }, 927 { 0x05004000, FFB_REG_DFB24, BUS_SPACE_MAP_PREFETCHABLE }, 928 { 0x06004000, FFB_REG_DFB32, BUS_SPACE_MAP_PREFETCHABLE }, 929 { 0x07004000, FFB_REG_DFB422A, BUS_SPACE_MAP_PREFETCHABLE }, 930 { 0x0bc06000, FFB_REG_DAC, 0 }, 931 { 0x0bc08000, FFB_REG_PROM, 0 }, 932 { 0x0bc18000, 0, 0 } 933 }; 934 935 /* special value "FFB_EXP_VOFF" - not backed by any "reg" entry */ 936 if (off == 0x0bc18000) 937 return bus_space_mmap(sc->sc_bt, sc->sc_addrs[FFB_REG_PROM], 938 0x00200000, prot, BUS_SPACE_MAP_LINEAR); 939 940 /* 941 * FFB_VOFF_FBC_KREGS - used by afbinit to upload firmware. We should 942 * probably mmap them only on afb boards 943 */ 944 if ((off >= 0x0bc04000) && (off < 0x0bc06000)) 945 return bus_space_mmap(sc->sc_bt, sc->sc_addrs[FFB_REG_PROM], 946 0x00610000 + (off - 0x0bc04000), prot, 947 BUS_SPACE_MAP_LINEAR); 948 949 #define NELEMS(arr) (sizeof(arr)/sizeof((arr)[0])) 950 951 /* the map is ordered by voff */ 952 for (i = 0; i < NELEMS(map)-1; i++) { 953 reg = map[i].reg; 954 /* the number of entries in reg seems to vary */ 955 if (reg < sc->sc_nreg) { 956 size = uimin((map[i + 1].voff - map[i].voff), 957 sc->sc_sizes[reg]); 958 if ((off >= map[i].voff) && 959 (off < (map[i].voff + size))) { 960 o = off - map[i].voff; 961 return bus_space_mmap(sc->sc_bt, 962 sc->sc_addrs[reg], o, prot, 963 BUS_SPACE_MAP_LINEAR | map[i].flags); 964 } 965 } 966 } 967 968 return -1; 969 } 970 971 void 972 ffb_clearscreen(struct ffb_softc *sc) 973 { 974 struct rasops_info *ri = &ffb_console_screen.scr_ri; 975 ffb_ras_fill(sc); 976 ffb_ras_setfg(sc, ri->ri_devcmap[WS_DEFAULT_BG]); 977 ffb_ras_fifo_wait(sc, 4); 978 FBC_WRITE(sc, FFB_FBC_BY, 0); 979 FBC_WRITE(sc, FFB_FBC_BX, 0); 980 FBC_WRITE(sc, FFB_FBC_BH, sc->sc_height); 981 FBC_WRITE(sc, FFB_FBC_BW, sc->sc_width); 982 } 983 984 void 985 ffb_cursor(void *cookie, int on, int row, int col) 986 { 987 struct rasops_info *ri = cookie; 988 struct vcons_screen *scr; 989 struct ffb_softc *sc; 990 int x, y, wi, he; 991 992 if (cookie != NULL) { 993 scr = ri->ri_hw; 994 sc = scr->scr_cookie; 995 996 wi = ri->ri_font->fontwidth; 997 he = ri->ri_font->fontheight; 998 999 if (sc->sc_mode == WSDISPLAYIO_MODE_EMUL) { 1000 1001 if (ri->ri_flg & RI_CURSOR) { 1002 1003 /* remove cursor */ 1004 x = ri->ri_ccol * wi + ri->ri_xorigin; 1005 y = ri->ri_crow * he + ri->ri_yorigin; 1006 1007 ffb_ras_invert(sc); 1008 ffb_ras_fifo_wait(sc, 4); 1009 FBC_WRITE(sc, FFB_FBC_BY, y); 1010 FBC_WRITE(sc, FFB_FBC_BX, x); 1011 FBC_WRITE(sc, FFB_FBC_BH, he); 1012 FBC_WRITE(sc, FFB_FBC_BW, wi); 1013 1014 ri->ri_flg &= ~RI_CURSOR; 1015 } 1016 ri->ri_crow = row; 1017 ri->ri_ccol = col; 1018 if (on) 1019 { 1020 x = ri->ri_ccol * wi + ri->ri_xorigin; 1021 y = ri->ri_crow * he + ri->ri_yorigin; 1022 1023 ffb_ras_invert(sc); 1024 ffb_ras_fifo_wait(sc, 4); 1025 FBC_WRITE(sc, FFB_FBC_BY, y); 1026 FBC_WRITE(sc, FFB_FBC_BX, x); 1027 FBC_WRITE(sc, FFB_FBC_BH, he); 1028 FBC_WRITE(sc, FFB_FBC_BW, wi); 1029 1030 ri->ri_flg |= RI_CURSOR; 1031 } 1032 } else { 1033 ri->ri_crow = row; 1034 ri->ri_ccol = col; 1035 ri->ri_flg &= ~RI_CURSOR; 1036 } 1037 } 1038 } 1039 1040 /* mono bitmap font */ 1041 void 1042 ffb_putchar_mono(void *cookie, int row, int col, u_int c, long attr) 1043 { 1044 struct rasops_info *ri = cookie; 1045 struct vcons_screen *scr = ri->ri_hw; 1046 struct wsdisplay_font *font = PICK_FONT(ri, c); 1047 struct ffb_softc *sc = scr->scr_cookie; 1048 void *data; 1049 uint32_t fg, bg; 1050 int i; 1051 int x, y, wi, he; 1052 1053 if (sc->sc_mode != WSDISPLAYIO_MODE_EMUL) 1054 return; 1055 1056 wi = font->fontwidth; 1057 he = font->fontheight; 1058 1059 if (!CHAR_IN_FONT(c, font)) 1060 return; 1061 1062 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 1063 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 1064 x = ri->ri_xorigin + col * wi; 1065 y = ri->ri_yorigin + row * he; 1066 1067 data = WSFONT_GLYPH(c, font); 1068 1069 ffb_ras_setbg(sc, bg); 1070 ffb_ras_setfg(sc, fg); 1071 ffb_ras_fifo_wait(sc, 4); 1072 FBC_WRITE(sc, FFB_FBC_ROP, FBC_ROP_NEW); 1073 FBC_WRITE(sc, FFB_FBC_FONTXY, (y << 16) | x); 1074 FBC_WRITE(sc, FFB_FBC_FONTW, wi); 1075 FBC_WRITE(sc, FFB_FBC_PPC, 1076 FBC_PPC_VCE_DIS | FBC_PPC_TBE_OPAQUE | FBC_PPC_ACE_DIS | 1077 FBC_PPC_APE_DIS | FBC_PPC_DCE_DIS | FBC_PPC_CS_CONST | 1078 FBC_PPC_ABE_DIS | FBC_PPC_XS_WID); 1079 1080 switch (font->stride) { 1081 case 1: { 1082 uint8_t *data8 = data; 1083 uint32_t reg; 1084 if (attr & WSATTR_UNDERLINE) { 1085 for (i = 0; i < he - 2; i++) { 1086 reg = *data8; 1087 FBC_WRITE(sc, FFB_FBC_FONT, reg << 24); 1088 data8++; 1089 } 1090 FBC_WRITE(sc, FFB_FBC_FONT, 0xff000000); 1091 data8++; 1092 reg = *data8; 1093 FBC_WRITE(sc, FFB_FBC_FONT, reg << 24); 1094 } else { 1095 for (i = 0; i < he; i++) { 1096 reg = *data8; 1097 FBC_WRITE(sc, FFB_FBC_FONT, reg << 24); 1098 data8++; 1099 } 1100 } 1101 break; 1102 } 1103 case 2: { 1104 uint16_t *data16 = data; 1105 uint32_t reg; 1106 if (attr & WSATTR_UNDERLINE) { 1107 for (i = 0; i < he - 2; i++) { 1108 reg = *data16; 1109 FBC_WRITE(sc, FFB_FBC_FONT, reg << 16); 1110 data16++; 1111 } 1112 FBC_WRITE(sc, FFB_FBC_FONT, 0xffff0000); 1113 data16++; 1114 reg = *data16; 1115 FBC_WRITE(sc, FFB_FBC_FONT, reg << 16); 1116 } else { 1117 for (i = 0; i < he; i++) { 1118 reg = *data16; 1119 FBC_WRITE(sc, FFB_FBC_FONT, reg << 16); 1120 data16++; 1121 } 1122 } 1123 break; 1124 } 1125 } 1126 } 1127 1128 /* alpha font */ 1129 void 1130 ffb_putchar_aa(void *cookie, int row, int col, u_int c, long attr) 1131 { 1132 struct rasops_info *ri = cookie; 1133 struct vcons_screen *scr = ri->ri_hw; 1134 struct wsdisplay_font *font = PICK_FONT(ri, c); 1135 struct ffb_softc *sc = scr->scr_cookie; 1136 volatile uint32_t *dest, *ddest; 1137 uint8_t *data8; 1138 uint32_t fg, bg; 1139 int i; 1140 int x, y, wi, he; 1141 uint32_t alpha = 0x80; 1142 int j; 1143 1144 if (sc->sc_mode != WSDISPLAYIO_MODE_EMUL) 1145 return; 1146 1147 wi = font->fontwidth; 1148 he = font->fontheight; 1149 1150 if (!CHAR_IN_FONT(c, font)) 1151 return; 1152 1153 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 1154 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 1155 x = ri->ri_xorigin + col * wi; 1156 y = ri->ri_yorigin + row * he; 1157 1158 data8 = WSFONT_GLYPH(c, font); 1159 1160 /* first we erase the background */ 1161 ffb_ras_fill(sc); 1162 ffb_ras_setfg(sc, bg); 1163 ffb_ras_fifo_wait(sc, 4); 1164 FBC_WRITE(sc, FFB_FBC_BY, y); 1165 FBC_WRITE(sc, FFB_FBC_BX, x); 1166 FBC_WRITE(sc, FFB_FBC_BH, he); 1167 FBC_WRITE(sc, FFB_FBC_BW, wi); 1168 1169 /* if we draw a space we're done */ 1170 if (c == ' ') goto out; 1171 1172 /* now enable alpha blending */ 1173 ffb_ras_setfg(sc, fg); 1174 ffb_ras_fifo_wait(sc, 2); 1175 FBC_WRITE(sc, FFB_FBC_ROP, FBC_ROP_NEW); 1176 1177 FBC_WRITE(sc, FFB_FBC_PPC, 1178 FBC_PPC_VCE_DIS | FBC_PPC_TBE_OPAQUE | FBC_PPC_ACE_DIS | 1179 FBC_PPC_APE_DIS | FBC_PPC_DCE_DIS | FBC_PPC_CS_CONST | 1180 FBC_PPC_ABE_ENA | FBC_PPC_XS_VAR); 1181 /* 1182 * we have to wait for both the rectangle drawing op above and the 1183 * FFB_FBC_PPC write to finish before mucking around in the SFB aperture 1184 */ 1185 ffb_ras_wait(sc); 1186 1187 /* ... and draw the character */ 1188 dest = sc->sc_sfb32 + (y << 11) + x; 1189 for (i = 0; i < he; i++) { 1190 ddest = dest; 1191 for (j = 0; j < wi; j++) { 1192 alpha = *data8; 1193 /* 1194 * We set the colour source to constant above so we only 1195 * have to write the alpha channel here and the colour 1196 * comes from the FG register. It would be nice if we 1197 * could just use the SFB8X aperture and memcpy() the 1198 * alpha map line by line but for some strange reason 1199 * that will take colour info from the framebuffer even 1200 * if we set the FBC_PPC_CS_CONST bit above. 1201 */ 1202 *ddest = alpha << 24; 1203 data8++; 1204 ddest++; 1205 } 1206 dest += 2048; 1207 } 1208 out: 1209 /* check if we need to draw an underline */ 1210 if (attr & WSATTR_UNDERLINE) { 1211 dest = sc->sc_sfb32 + ((y + he - 2) << 11) + x; 1212 for (i = 0; i < wi; i++) { 1213 *dest = 0xa0000000; 1214 dest++; 1215 } 1216 } 1217 } 1218 1219 int 1220 ffb_allocattr(void *cookie, int fg, int bg, int flags, long *attrp) 1221 { 1222 if ((fg == 0) && (bg == 0)) 1223 { 1224 fg = WS_DEFAULT_FG; 1225 bg = WS_DEFAULT_BG; 1226 } 1227 if (flags & WSATTR_REVERSE) { 1228 *attrp = (bg & 0xff) << 24 | (fg & 0xff) << 16; 1229 } else 1230 *attrp = (fg & 0xff) << 24 | (bg & 0xff) << 16; 1231 if (flags & WSATTR_UNDERLINE) 1232 *attrp |= WSATTR_UNDERLINE; 1233 return 0; 1234 } 1235 1236 void 1237 ffb_init_screen(void *cookie, struct vcons_screen *scr, 1238 int existing, long *defattr) 1239 { 1240 struct ffb_softc *sc = cookie; 1241 struct rasops_info *ri = &scr->scr_ri; 1242 1243 ri->ri_depth = 32; 1244 ri->ri_width = sc->sc_width; 1245 ri->ri_height = sc->sc_height; 1246 ri->ri_stride = sc->sc_linebytes; 1247 ri->ri_flg = RI_CENTER | RI_ENABLE_ALPHA | RI_PREFER_ALPHA; 1248 1249 /* 1250 * we can't accelerate copycols() so instead of falling back to 1251 * software use vcons' putchar() based implementation 1252 */ 1253 scr->scr_flags |= VCONS_NO_COPYCOLS | VCONS_LOADFONT; 1254 1255 #ifdef VCONS_DRAW_INTR 1256 scr->scr_flags |= VCONS_DONT_READ; 1257 #endif 1258 DPRINTF(("ffb_init_screen: addr: %08lx\n",(ulong)ri->ri_bits)); 1259 1260 /* explicitly request BGR in case the default changes */ 1261 ri->ri_rnum = 8; 1262 ri->ri_gnum = 8; 1263 ri->ri_bnum = 8; 1264 ri->ri_rpos = 0; 1265 ri->ri_gpos = 8; 1266 ri->ri_bpos = 16; 1267 1268 rasops_init(ri, 0, 0); 1269 rasops_reconfig(ri, sc->sc_height / ri->ri_font->fontheight, 1270 sc->sc_width / ri->ri_font->fontwidth); 1271 ri->ri_caps = WSSCREEN_WSCOLORS | WSSCREEN_UNDERLINE | 1272 WSSCREEN_REVERSE | WSSCREEN_RESIZE; 1273 1274 /* enable acceleration */ 1275 ri->ri_ops.copyrows = ffb_ras_copyrows; 1276 ri->ri_ops.eraserows = ffb_ras_eraserows; 1277 ri->ri_ops.erasecols = ffb_ras_erasecols; 1278 ri->ri_ops.cursor = ffb_cursor; 1279 ri->ri_ops.allocattr = ffb_allocattr; 1280 if (FONT_IS_ALPHA(ri->ri_font)) { 1281 ri->ri_ops.putchar = ffb_putchar_aa; 1282 } else 1283 ri->ri_ops.putchar = ffb_putchar_mono; 1284 } 1285 1286 /* I2C bitbanging */ 1287 static void ffb_i2cbb_set_bits(void *cookie, uint32_t bits) 1288 { 1289 struct ffb_softc *sc = cookie; 1290 1291 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_CFG_MPDATA); 1292 DAC_WRITE(sc, FFB_DAC_VALUE, bits); 1293 } 1294 1295 static void ffb_i2cbb_set_dir(void *cookie, uint32_t dir) 1296 { 1297 /* Nothing to do */ 1298 } 1299 1300 static uint32_t ffb_i2cbb_read(void *cookie) 1301 { 1302 struct ffb_softc *sc = cookie; 1303 uint32_t bits; 1304 1305 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_CFG_MPSENSE); 1306 bits = DAC_READ(sc, FFB_DAC_VALUE); 1307 1308 return bits; 1309 } 1310 1311 /* higher level I2C stuff */ 1312 static int 1313 ffb_i2c_send_start(void *cookie, int flags) 1314 { 1315 return (i2c_bitbang_send_start(cookie, flags, &ffb_i2cbb_ops)); 1316 } 1317 1318 static int 1319 ffb_i2c_send_stop(void *cookie, int flags) 1320 { 1321 1322 return (i2c_bitbang_send_stop(cookie, flags, &ffb_i2cbb_ops)); 1323 } 1324 1325 static int 1326 ffb_i2c_initiate_xfer(void *cookie, i2c_addr_t addr, int flags) 1327 { 1328 /* 1329 * for some reason i2c_bitbang_initiate_xfer left-shifts 1330 * the I2C-address and then sets the direction bit 1331 */ 1332 return (i2c_bitbang_initiate_xfer(cookie, addr, flags, 1333 &ffb_i2cbb_ops)); 1334 } 1335 1336 static int 1337 ffb_i2c_read_byte(void *cookie, uint8_t *valp, int flags) 1338 { 1339 return (i2c_bitbang_read_byte(cookie, valp, flags, &ffb_i2cbb_ops)); 1340 } 1341 1342 static int 1343 ffb_i2c_write_byte(void *cookie, uint8_t val, int flags) 1344 { 1345 return (i2c_bitbang_write_byte(cookie, val, flags, &ffb_i2cbb_ops)); 1346 } 1347 1348 1349 #define TVC_READ_LIMIT 100000 1350 int 1351 ffb_tgc_disable(struct ffb_softc *sc) 1352 { 1353 int i; 1354 1355 /* Is the timing generator disabled? */ 1356 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_TGC); 1357 if (!(DAC_READ(sc, FFB_DAC_VALUE) & FFB_DAC_TGC_TIMING_ENABLE)) 1358 return 1; 1359 1360 /* If not, disable it when the vertical counter reaches 0 */ 1361 for (i = 0; i < TVC_READ_LIMIT; i++) { 1362 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_TVC); 1363 if (!DAC_READ(sc, FFB_DAC_VALUE)) { 1364 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_TGC); 1365 DAC_WRITE(sc, FFB_DAC_VALUE, 0); 1366 return 1; 1367 } 1368 } 1369 return 0; 1370 } 1371 1372 /* 1373 * PLL Control Register values: 1374 * M)ultiplier = bits 0:6 + 1 1375 * D)ivisor = bits 7:10 + 1 1376 * P)ost divisor = bits 11:13 (000 = 1, 001 = 2, 010 = 4, 011 = 8) 1377 * Frequency = 13.5 * M / D / P 1378 */ 1379 #define FFB_PLL_FREQ 13500000 1380 void 1381 ffb_get_pclk(int request, uint32_t *pll, int *diff) 1382 { 1383 int m, d, p, f, hex = 0, curdiff; 1384 1385 *diff = 100000000; 1386 1387 for (m = 32; m <= 80; m++) { 1388 for (d = 4; d <= 11; d++) { 1389 for (p = 1; p <= 8; p = p << 1) { 1390 switch (p) { 1391 case 1: 1392 hex = 0x4000 + (d << 7) + m; 1393 break; 1394 case 2: 1395 hex = 0x4800 + (d << 7) + m; 1396 break; 1397 case 4: 1398 hex = 0x5000 + (d << 7) + m; 1399 break; 1400 case 8: 1401 hex = 0x6000 + (d << 7) + m; 1402 break; 1403 } 1404 f = 13500000 * m / d / p; 1405 if (f == request) { 1406 *diff = 0; 1407 *pll = hex; 1408 return; 1409 } else { 1410 curdiff = abs(request - f); 1411 if (curdiff < *diff) { 1412 *diff = curdiff; 1413 *pll = hex; 1414 } 1415 } 1416 } 1417 } 1418 } 1419 } 1420 1421 /* 1422 * Details of the FFB RAMDAC are contained in the Brooktree BT497/498 1423 * and in the Connexant BT497A/498A documentation. 1424 * 1425 * VESA timings to FFB register conversion: 1426 * If interleave = 4/2:1 then x = 2, if interleave = 8/2:1 then x = 4 1427 * VBE = VBS - vres = (sync pulse - 1) + back porch 1428 * VBS = VSS - front porch = (sync pulse - 1) + back porch + vres 1429 * VSE = sync pulse - 1 1430 * VSS = (sync pulse - 1) + back porch + vres + front porch 1431 * HRE = HSS - HSE - 1 1432 * HBE = (sync pulse + back porch) / x - 1 1433 * HBS = (sync pulse + back porch + hres) / x - 1 1434 * HSE = sync pulse / x - 1 1435 * HSS = (sync pulse + back porch + hres + front porch) / x - 1 1436 * HCE = HBS - 4 1437 * HCS = HBE - 4 1438 * EPE = EIE = EIS = 0 (for all non-interlaced modes) 1439 * 1440 * Note, that 8/2:1 Single Buffered Interleaving is only supported by the 1441 * double-buffered FFB (Creator3D), and at higher resolutions than 1280x1024 1442 * 1443 * Note, that the timing generator should be disabled and re-enabled when the 1444 * the timing parameter registers are being programmed. Stopping the timing 1445 * generator should only be done when the vertical counter is zero. 1446 */ 1447 #define DIVIDE(x,y) (((x) + ((y) / 2)) / (y)) 1448 int 1449 ffb_set_vmode(struct ffb_softc *sc, struct videomode *mode, int btype, 1450 int *hres, int *vres) 1451 { 1452 int diff; 1453 uint32_t fp, sp, bp, x; 1454 uint32_t pll, pfc, ucl, dcl, tgc; 1455 uint32_t vbe, vbs, vse, vss, hre, hbe, hbs, hse, hss, hce, hcs; 1456 uint32_t epe, eie, eis; 1457 uint32_t fbcfg0; 1458 1459 DPRINTF(("ffb_set_vmode: %dx%d@%d", mode->hdisplay, mode->vdisplay, 1460 DIVIDE(DIVIDE(mode->dot_clock * 1000, 1461 mode->htotal), mode->vtotal))); 1462 DPRINTF((" (%d %d %d %d %d %d %d", 1463 mode->dot_clock, mode->hsync_start, mode->hsync_end, mode->htotal, 1464 mode->vsync_start, mode->vsync_end, mode->vtotal)); 1465 DPRINTF((" %s%sH %s%sV)\n", 1466 mode->flags & VID_PHSYNC ? "+" : "", 1467 mode->flags & VID_NHSYNC ? "-" : "", 1468 mode->flags & VID_PVSYNC ? "+" : "", 1469 mode->flags & VID_NVSYNC ? "-" : "")); 1470 1471 /* We don't handle interlaced or doublescan (yet) */ 1472 if ((mode->flags & VID_INTERLACE) || (mode->flags & VID_DBLSCAN)) 1473 return 0; 1474 1475 /* Only Creator3D can be set to > 1280x1024 */ 1476 if(((sc->sc_type == FFB_CREATOR && !((btype & 7) == 3)) || 1477 sc->sc_type == FFB_AFB) 1478 && (mode->hdisplay > 1280 || mode->vdisplay > 1024)) 1479 return 0; 1480 /* Creator3D can be set to <= 1920x1360 */ 1481 if (mode->hdisplay > 1920 || mode->vdisplay > 1360) 1482 return 0; 1483 1484 /* 1485 * Look for a matching pixel clock and set PLL Control. 1486 * XXX: 640x480@60 is 25175000 in modelines but 25125000 in the 1487 * FFB PROM, and the closest match to 25175000 (0x4da9/25159090) 1488 * does not work. So, use the PROM value instead. 1489 */ 1490 if (mode->hdisplay == 640 && mode->vdisplay == 480 && 1491 mode->dot_clock == 25175) { 1492 DPRINTF(("ffb_set_vmode: 640x480@60: adjusted dot clock\n")); 1493 mode->dot_clock = 25125; 1494 } 1495 ffb_get_pclk(mode->dot_clock * 1000, &pll, &diff); 1496 if (diff > 250000) 1497 return 0; 1498 1499 /* Pixel Format Control, User Control and FBC Configuration. */ 1500 if (mode->hdisplay > 1280) { 1501 pfc = FFB_DAC_PIX_FMT_821; 1502 ucl = FFB_DAC_USR_CTRL_OVERLAY | FFB_DAC_USR_CTRL_WMODE_C; 1503 x = 4; 1504 fbcfg0 = FBC_READ(sc, FFB_FBC_FBCFG0) | FBC_CFG0_DOUBLE_BUF; 1505 } else { 1506 pfc = FFB_DAC_PIX_FMT_421; 1507 /* Only Creator3D and Elite3D can have double-buffer */ 1508 if ((sc->sc_type == FFB_CREATOR && !((btype & 7) == 3))) 1509 ucl = 0; 1510 else 1511 ucl = FFB_DAC_USR_CTRL_DOUBLE; 1512 ucl |= (FFB_DAC_USR_CTRL_OVERLAY | FFB_DAC_USR_CTRL_WMODE_S8); 1513 x = 2; 1514 fbcfg0 = FBC_READ(sc, FFB_FBC_FBCFG0) | FBC_CFG0_SINGLE_BUF; 1515 } 1516 1517 /* DAC Control and Timing Generator Control */ 1518 if (mode->flags & VID_PVSYNC) 1519 dcl = FFB_DAC_DAC_CTRL_POS_VSYNC; 1520 else 1521 dcl = 0; 1522 tgc = 0; 1523 #define EDID_VID_INP sc->sc_edid_info.edid_video_input 1524 if ((EDID_VID_INP & EDID_VIDEO_INPUT_COMPOSITE_SYNC)) { 1525 dcl |= FFB_DAC_DAC_CTRL_VSYNC_DIS; 1526 tgc = FFB_DAC_TGC_EQUAL_DISABLE; 1527 } else { 1528 dcl |= FFB_DAC_DAC_CTRL_SYNC_G; 1529 if (EDID_VID_INP & EDID_VIDEO_INPUT_SEPARATE_SYNCS) 1530 tgc |= FFB_DAC_TGC_VSYNC_DISABLE; 1531 else 1532 tgc = FFB_DAC_TGC_EQUAL_DISABLE; 1533 } 1534 if (EDID_VID_INP & EDID_VIDEO_INPUT_BLANK_TO_BLACK) 1535 dcl |= FFB_DAC_DAC_CTRL_PED_ENABLE; 1536 tgc |= (FFB_DAC_TGC_VIDEO_ENABLE | FFB_DAC_TGC_TIMING_ENABLE | 1537 FFB_DAC_TGC_MASTER_ENABLE); 1538 1539 /* Vertical timing */ 1540 fp = mode->vsync_start - mode->vdisplay; 1541 sp = mode->vsync_end - mode->vsync_start; 1542 bp = mode->vtotal - mode->vsync_end; 1543 1544 vbe = sp - 1 + bp; 1545 vbs = sp - 1 + bp + mode->vdisplay; 1546 vse = sp - 1; 1547 vss = sp - 1 + bp + mode->vdisplay + fp; 1548 1549 /* Horizontal timing */ 1550 fp = mode->hsync_start - mode->hdisplay; 1551 sp = mode->hsync_end - mode->hsync_start; 1552 bp = mode->htotal - mode->hsync_end; 1553 1554 hbe = (sp + bp) / x - 1; 1555 hbs = (sp + bp + mode->hdisplay) / x - 1; 1556 hse = sp / x - 1; 1557 hss = (sp + bp + mode->hdisplay + fp) / x -1; 1558 hre = hss - hse - 1; 1559 hce = hbs - 4; 1560 hcs = hbe - 4; 1561 1562 /* Equalisation (interlaced modes) */ 1563 epe = 0; 1564 eie = 0; 1565 eis = 0; 1566 1567 DPRINTF(("ffb_set_vmode: 0x%04x 0x%04x 0x%04x 0x%04x 0x%04x\n", 1568 pll, pfc, ucl, dcl, tgc)); 1569 DPRINTF(("\t0x%04x 0x%04x 0x%04x 0x%04x\n", vbe, vbs, vse, vss)); 1570 DPRINTF(("\t0x%04x 0x%04x 0x%04x 0x%04x 0x%04x 0x%04x 0x%04x\n", 1571 hre, hbe, hbs, hse, hss, hce, hcs)); 1572 DPRINTF(("\t0x%04x 0x%04x 0x%04x\n", epe, eie, eis)); 1573 1574 if (!ffb_tgc_disable(sc)) { 1575 DPRINTF(("ffb_set_vmode: failed to disable TGC register\n")); 1576 return 0; 1577 } 1578 1579 /* 1580 * Program the mode registers. 1581 * Program the timing generator last, as that re-enables output. 1582 * Note, that a read to/write from a register increments the 1583 * register address to the next register automatically. 1584 */ 1585 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_PLL_CTRL); 1586 DAC_WRITE(sc, FFB_DAC_VALUE, pll); 1587 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_PIX_FMT); 1588 DAC_WRITE(sc, FFB_DAC_VALUE, pfc); 1589 DAC_WRITE(sc, FFB_DAC_VALUE, ucl); 1590 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_DAC_CTRL); 1591 DAC_WRITE(sc, FFB_DAC_VALUE, dcl); 1592 1593 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_VBE); 1594 DAC_WRITE(sc, FFB_DAC_VALUE, vbe); 1595 DAC_WRITE(sc, FFB_DAC_VALUE, vbs); 1596 DAC_WRITE(sc, FFB_DAC_VALUE, vse); 1597 DAC_WRITE(sc, FFB_DAC_VALUE, vss); 1598 1599 DAC_WRITE(sc, FFB_DAC_VALUE, hre); 1600 DAC_WRITE(sc, FFB_DAC_VALUE, hbe); 1601 DAC_WRITE(sc, FFB_DAC_VALUE, hbs); 1602 DAC_WRITE(sc, FFB_DAC_VALUE, hse); 1603 DAC_WRITE(sc, FFB_DAC_VALUE, hss); 1604 DAC_WRITE(sc, FFB_DAC_VALUE, hce); 1605 DAC_WRITE(sc, FFB_DAC_VALUE, hcs); 1606 1607 DAC_WRITE(sc, FFB_DAC_VALUE, epe); 1608 DAC_WRITE(sc, FFB_DAC_VALUE, eie); 1609 DAC_WRITE(sc, FFB_DAC_VALUE, eis); 1610 1611 FBC_WRITE(sc, FFB_FBC_FBCFG0, fbcfg0); 1612 1613 DAC_WRITE(sc, FFB_DAC_TYPE, FFB_DAC_TGC); 1614 DAC_WRITE(sc, FFB_DAC_VALUE, tgc); 1615 DPRINTF(("new tgc: %08x\n", tgc)); 1616 1617 *hres = mode->hdisplay; 1618 *vres = mode->vdisplay; 1619 1620 printf("%s: video mode set to %d x %d @ %dHz\n", 1621 device_xname(sc->sc_dev), 1622 mode->hdisplay, mode->vdisplay, 1623 DIVIDE(DIVIDE(mode->dot_clock * 1000, 1624 mode->htotal), mode->vtotal)); 1625 1626 return 1; 1627 } 1628
Indexes created Thu Sep 25 15:09:46 GMT 2025