iommu.c revision 1.10
1 /* $NetBSD: iommu.c,v 1.10 2000/05/17 09:53:53 mrg Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000 Matthew R. Green 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 23 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 24 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 25 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 /*- 32 * Copyright (c) 1998 The NetBSD Foundation, Inc. 33 * All rights reserved. 34 * 35 * This code is derived from software contributed to The NetBSD Foundation 36 * by Paul Kranenburg. 37 * 38 * Redistribution and use in source and binary forms, with or without 39 * modification, are permitted provided that the following conditions 40 * are met: 41 * 1. Redistributions of source code must retain the above copyright 42 * notice, this list of conditions and the following disclaimer. 43 * 2. Redistributions in binary form must reproduce the above copyright 44 * notice, this list of conditions and the following disclaimer in the 45 * documentation and/or other materials provided with the distribution. 46 * 3. All advertising materials mentioning features or use of this software 47 * must display the following acknowledgement: 48 * This product includes software developed by the NetBSD 49 * Foundation, Inc. and its contributors. 50 * 4. Neither the name of The NetBSD Foundation nor the names of its 51 * contributors may be used to endorse or promote products derived 52 * from this software without specific prior written permission. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 55 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 56 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 57 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 58 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 59 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 60 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 61 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 62 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 63 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 64 * POSSIBILITY OF SUCH DAMAGE. 65 */ 66 67 /* 68 * Copyright (c) 1992, 1993 69 * The Regents of the University of California. All rights reserved. 70 * 71 * This software was developed by the Computer Systems Engineering group 72 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 73 * contributed to Berkeley. 74 * 75 * All advertising materials mentioning features or use of this software 76 * must display the following acknowledgement: 77 * This product includes software developed by the University of 78 * California, Lawrence Berkeley Laboratory. 79 * 80 * Redistribution and use in source and binary forms, with or without 81 * modification, are permitted provided that the following conditions 82 * are met: 83 * 1. Redistributions of source code must retain the above copyright 84 * notice, this list of conditions and the following disclaimer. 85 * 2. Redistributions in binary form must reproduce the above copyright 86 * notice, this list of conditions and the following disclaimer in the 87 * documentation and/or other materials provided with the distribution. 88 * 3. All advertising materials mentioning features or use of this software 89 * must display the following acknowledgement: 90 * This product includes software developed by the University of 91 * California, Berkeley and its contributors. 92 * 4. Neither the name of the University nor the names of its contributors 93 * may be used to endorse or promote products derived from this software 94 * without specific prior written permission. 95 * 96 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 97 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 98 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 99 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 100 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 101 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 102 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 103 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 104 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 105 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 106 * SUCH DAMAGE. 107 * 108 * from: NetBSD: sbus.c,v 1.13 1999/05/23 07:24:02 mrg Exp 109 * from: @(#)sbus.c 8.1 (Berkeley) 6/11/93 110 */ 111 112 /* 113 * UltraSPARC IOMMU support; used by both the sbus and pci code. 114 */ 115 116 #include "opt_ddb.h" 117 118 #include <sys/param.h> 119 #include <sys/extent.h> 120 #include <sys/malloc.h> 121 #include <sys/systm.h> 122 #include <sys/device.h> 123 #include <vm/vm.h> 124 #include <vm/vm_kern.h> 125 126 #include <machine/bus.h> 127 #include <sparc64/sparc64/cache.h> 128 #include <sparc64/sparc64/vaddrs.h> 129 #include <sparc64/dev/iommureg.h> 130 #include <sparc64/dev/iommuvar.h> 131 132 #include <machine/autoconf.h> 133 #include <machine/ctlreg.h> 134 #include <machine/cpu.h> 135 136 #ifdef DEBUG 137 #define IDB_DVMA 0x1 138 int iommudebug = 0x0; 139 #define DPRINTF(l, s) do { if (iommudebug & l) printf s; } while (0) 140 #else 141 #define DPRINTF(l, s) 142 #endif 143 144 /* 145 * initialise the UltraSPARC IOMMU (SBUS or PCI): 146 * - allocate and setup the iotsb. 147 * - enable the IOMMU 148 * - initialise the streaming buffers (if they exist) 149 * - create a private DVMA map. 150 */ 151 void 152 iommu_init(name, is, tsbsize) 153 char *name; 154 struct iommu_state *is; 155 int tsbsize; 156 { 157 158 /* 159 * Setup the iommu. 160 * 161 * The sun4u iommu is part of the SBUS or PCI controller so we 162 * will deal with it here.. 163 * 164 * First we need to allocate a IOTSB. Problem is that the IOMMU 165 * can only access the IOTSB by physical address, so all the 166 * pages must be contiguous. Luckily, the smallest IOTSB size 167 * is one 8K page. 168 */ 169 if (tsbsize != 0) 170 panic("tsbsize != 0; FIX ME"); /* XXX */ 171 172 /* we want 8K pages */ 173 is->is_cr = IOMMUCR_8KPG | IOMMUCR_EN; 174 /* 175 * 176 * The IOMMU address space always ends at 0xffffe000, but the starting 177 * address depends on the size of the map. The map size is 1024 * 2 ^ 178 * is->is_tsbsize entries, where each entry is 8 bytes. The start of 179 * the map can be calculated by (0xffffe000 << (8 + is->is_tsbsize)). 180 * 181 * Note: the stupid IOMMU ignores the high bits of an address, so a 182 * NULL DMA pointer will be translated by the first page of the IOTSB. 183 * To trap bugs we'll skip the first entry in the IOTSB. 184 */ 185 is->is_dvmabase = IOTSB_VSTART(is->is_tsbsize) + NBPG; 186 is->is_tsbsize = tsbsize; 187 is->is_tsb = malloc(NBPG, M_DMAMAP, M_WAITOK); /* XXX */ 188 (void) pmap_extract(pmap_kernel(), (vaddr_t)is->is_tsb, 189 (paddr_t *)&is->is_ptsb); 190 191 #ifdef DEBUG 192 if (iommudebug & IDB_DVMA) 193 { 194 /* Probe the iommu */ 195 struct iommureg *regs = is->is_iommu; 196 int64_t cr, tsb; 197 198 printf("iommu regs at: cr=%lx tsb=%lx flush=%lx\n", ®s->iommu_cr, 199 ®s->iommu_tsb, ®s->iommu_flush); 200 cr = regs->iommu_cr; 201 tsb = regs->iommu_tsb; 202 printf("iommu cr=%lx tsb=%lx\n", (long)cr, (long)tsb); 203 printf("TSB base %p phys %p\n", (long)is->is_tsb, (long)is->is_ptsb); 204 delay(1000000); /* 1 s */ 205 } 206 #endif 207 208 /* 209 * Initialize streaming buffer, if it is there. 210 */ 211 if (is->is_sb) 212 (void)pmap_extract(pmap_kernel(), (vaddr_t)&is->is_flush, 213 (paddr_t *)&is->is_flushpa); 214 215 /* 216 * now actually start up the IOMMU 217 */ 218 iommu_reset(is); 219 220 /* 221 * Now all the hardware's working we need to allocate a dvma map. 222 */ 223 is->is_dvmamap = extent_create(name, 224 is->is_dvmabase, IOTSB_VEND, 225 M_DEVBUF, 0, 0, EX_NOWAIT); 226 } 227 228 /* 229 * Streaming buffers don't exist on the UltraSPARC IIi; we should have 230 * detected that already and disabled them. If not, we will notice that 231 * they aren't there when the STRBUF_EN bit does not remain. 232 */ 233 void 234 iommu_reset(is) 235 struct iommu_state *is; 236 { 237 238 /* Need to do 64-bit stores */ 239 bus_space_write_8(is->is_bustag, &is->is_iommu->iommu_cr, 0, is->is_cr); 240 bus_space_write_8(is->is_bustag, &is->is_iommu->iommu_tsb, 0, is->is_ptsb); 241 242 if (!is->is_sb) 243 return; 244 245 /* Enable diagnostics mode? */ 246 bus_space_write_8(is->is_bustag, &is->is_sb->strbuf_ctl, 0, STRBUF_EN); 247 248 /* No streaming buffers? Disable them */ 249 if (bus_space_read_8(is->is_bustag, 250 (bus_space_handle_t)(u_long)&is->is_sb->strbuf_ctl, 0) == 0) 251 is->is_sb = 0; 252 } 253 254 /* 255 * Here are the iommu control routines. 256 */ 257 void 258 iommu_enter(is, va, pa, flags) 259 struct iommu_state *is; 260 vaddr_t va; 261 int64_t pa; 262 int flags; 263 { 264 int64_t tte; 265 266 #ifdef DIAGNOSTIC 267 if (va < is->is_dvmabase) 268 panic("iommu_enter: va 0x%lx not in DVMA space",va); 269 #endif 270 271 tte = MAKEIOTTE(pa, !(flags&BUS_DMA_NOWRITE), !(flags&BUS_DMA_NOCACHE), 272 !(flags&BUS_DMA_COHERENT)); 273 274 /* Is the streamcache flush really needed? */ 275 if (is->is_sb) { 276 bus_space_write_8(is->is_bustag, &is->is_sb->strbuf_pgflush, 0, 277 va); 278 iommu_flush(is); 279 } 280 DPRINTF(IDB_DVMA, ("Clearing TSB slot %d for va %p\n", 281 (int)IOTSBSLOT(va,is->is_tsbsize), va)); 282 is->is_tsb[IOTSBSLOT(va,is->is_tsbsize)] = tte; 283 bus_space_write_8(is->is_bustag, &is->is_iommu->iommu_flush, 284 0, va); 285 DPRINTF(IDB_DVMA, ("iommu_enter: va %lx pa %lx TSB[%lx]@%p=%lx\n", 286 va, (long)pa, IOTSBSLOT(va,is->is_tsbsize), 287 &is->is_tsb[IOTSBSLOT(va,is->is_tsbsize)], 288 (long)tte)); 289 } 290 291 /* 292 * iommu_remove: removes mappings created by iommu_enter 293 * 294 * Only demap from IOMMU if flag is set. 295 * 296 * XXX: this function needs better internal error checking. 297 */ 298 void 299 iommu_remove(is, va, len) 300 struct iommu_state *is; 301 vaddr_t va; 302 size_t len; 303 { 304 305 #ifdef DIAGNOSTIC 306 if (va < is->is_dvmabase) 307 panic("iommu_remove: va 0x%lx not in DVMA space", (long)va); 308 if ((long)(va + len) < (long)va) 309 panic("iommu_remove: va 0x%lx + len 0x%lx wraps", 310 (long) va, (long) len); 311 if (len & ~0xfffffff) 312 panic("iommu_remove: rediculous len 0x%lx", (long)len); 313 #endif 314 315 va = trunc_page(va); 316 DPRINTF(IDB_DVMA, ("iommu_remove: va %lx TSB[%lx]@%p\n", 317 va, IOTSBSLOT(va,is->is_tsbsize), 318 &is->is_tsb[IOTSBSLOT(va,is->is_tsbsize)])); 319 while (len > 0) { 320 DPRINTF(IDB_DVMA, ("iommu_remove: clearing TSB slot %d for va %p size %lx\n", 321 (int)IOTSBSLOT(va,is->is_tsbsize), va, (u_long)len)); 322 if (is->is_sb) { 323 DPRINTF(IDB_DVMA, ("iommu_remove: flushing va %p TSB[%lx]@%p=%lx, %lu bytes left\n", 324 (long)va, (long)IOTSBSLOT(va,is->is_tsbsize), 325 (long)&is->is_tsb[IOTSBSLOT(va,is->is_tsbsize)], 326 (long)(is->is_tsb[IOTSBSLOT(va,is->is_tsbsize)]), 327 (u_long)len)); 328 bus_space_write_8(is->is_bustag, 329 &is->is_sb->strbuf_pgflush, 0, va); 330 if (len <= NBPG) 331 iommu_flush(is); 332 DPRINTF(IDB_DVMA, ("iommu_remove: flushed va %p TSB[%lx]@%p=%lx, %lu bytes left\n", 333 (long)va, (long)IOTSBSLOT(va,is->is_tsbsize), 334 (long)&is->is_tsb[IOTSBSLOT(va,is->is_tsbsize)], 335 (long)(is->is_tsb[IOTSBSLOT(va,is->is_tsbsize)]), 336 (u_long)len)); 337 } else 338 membar_sync(); /* XXX */ 339 340 if (len <= NBPG) 341 len = 0; 342 else 343 len -= NBPG; 344 345 is->is_tsb[IOTSBSLOT(va,is->is_tsbsize)] = 0; 346 bus_space_write_8(is->is_bustag, &is->is_iommu->iommu_flush, 0, va); 347 va += NBPG; 348 } 349 } 350 351 int 352 iommu_flush(is) 353 struct iommu_state *is; 354 { 355 struct timeval cur, flushtimeout; 356 357 #define BUMPTIME(t, usec) { \ 358 register volatile struct timeval *tp = (t); \ 359 register long us; \ 360 \ 361 tp->tv_usec = us = tp->tv_usec + (usec); \ 362 if (us >= 1000000) { \ 363 tp->tv_usec = us - 1000000; \ 364 tp->tv_sec++; \ 365 } \ 366 } 367 368 if (!is->is_sb) 369 return (0); 370 371 /* 372 * Streaming buffer flushes: 373 * 374 * 1 Tell strbuf to flush by storing va to strbuf_pgflush. If 375 * we're not on a cache line boundary (64-bits): 376 * 2 Store 0 in flag 377 * 3 Store pointer to flag in flushsync 378 * 4 wait till flushsync becomes 0x1 379 * 380 * If it takes more than .5 sec, something 381 * went wrong. 382 */ 383 384 is->is_flush = 0; 385 membar_sync(); 386 bus_space_write_8(is->is_bustag, &is->is_sb->strbuf_flushsync, 0, is->is_flushpa); 387 membar_sync(); 388 389 microtime(&flushtimeout); 390 cur = flushtimeout; 391 BUMPTIME(&flushtimeout, 500000); /* 1/2 sec */ 392 393 DPRINTF(IDB_DVMA, ("iommu_flush: flush = %lx at va = %lx pa = %lx now=%lx:%lx until = %lx:%lx\n", 394 (long)is->is_flush, (long)&is->is_flush, 395 (long)is->is_flushpa, cur.tv_sec, cur.tv_usec, 396 flushtimeout.tv_sec, flushtimeout.tv_usec)); 397 /* Bypass non-coherent D$ */ 398 while (!ldxa(is->is_flushpa, ASI_PHYS_CACHED) && 399 ((cur.tv_sec <= flushtimeout.tv_sec) && 400 (cur.tv_usec <= flushtimeout.tv_usec))) 401 microtime(&cur); 402 403 #ifdef DIAGNOSTIC 404 if (!is->is_flush) { 405 printf("iommu_flush: flush timeout %p at %p\n", (long)is->is_flush, 406 (long)is->is_flushpa); /* panic? */ 407 #ifdef DDB 408 Debugger(); 409 #endif 410 } 411 #endif 412 DPRINTF(IDB_DVMA, ("iommu_flush: flushed\n")); 413 return (is->is_flush); 414 } 415 416 /* 417 * IOMMU DVMA operations, common to SBUS and PCI. 418 */ 419 int 420 iommu_dvmamap_load(t, is, map, buf, buflen, p, flags) 421 bus_dma_tag_t t; 422 struct iommu_state *is; 423 bus_dmamap_t map; 424 void *buf; 425 bus_size_t buflen; 426 struct proc *p; 427 int flags; 428 { 429 int s; 430 int err; 431 bus_size_t sgsize; 432 paddr_t curaddr; 433 u_long dvmaddr; 434 vaddr_t vaddr = (vaddr_t)buf; 435 pmap_t pmap; 436 437 if (map->dm_nsegs) { 438 /* Already in use?? */ 439 #ifdef DIAGNOSTIC 440 printf("iommu_dvmamap_load: map still in use\n"); 441 #endif 442 bus_dmamap_unload(t, map); 443 } 444 /* 445 * Make sure that on error condition we return "no valid mappings". 446 */ 447 map->dm_nsegs = 0; 448 449 if (buflen > map->_dm_size) { 450 DPRINTF(IDB_DVMA, 451 ("iommu_dvmamap_load(): error %d > %d -- " 452 "map size exceeded!\n", buflen, map->_dm_size)); 453 return (EINVAL); 454 } 455 456 #if 1 457 sgsize = round_page(buflen + ((int)vaddr & PGOFSET)); 458 #else 459 sgsize = buflen + ((int)vaddr & PGOFSET); 460 #endif 461 /* 462 * XXX Need to implement "don't dma across this boundry". 463 */ 464 s = splhigh(); 465 err = extent_alloc(is->is_dvmamap, sgsize, NBPG, 466 map->_dm_boundary, EX_NOWAIT, (u_long *)&dvmaddr); 467 splx(s); 468 469 if (err != 0) 470 return (err); 471 472 #ifdef DEBUG 473 if (dvmaddr == (bus_addr_t)-1) 474 { 475 printf("iommu_dvmamap_load(): extent_alloc(%d, %x) failed!\n", 476 sgsize, flags); 477 Debugger(); 478 } 479 #endif 480 if (dvmaddr == (bus_addr_t)-1) 481 return (ENOMEM); 482 483 /* 484 * We always use just one segment. 485 */ 486 map->dm_mapsize = buflen; 487 map->dm_nsegs = 1; 488 map->dm_segs[0].ds_addr = dvmaddr + (vaddr & PGOFSET); 489 map->dm_segs[0].ds_len = sgsize; 490 491 if (p != NULL) 492 pmap = p->p_vmspace->vm_map.pmap; 493 else 494 pmap = pmap_kernel(); 495 496 dvmaddr = trunc_page(map->dm_segs[0].ds_addr); 497 for (; buflen > 0; ) { 498 /* 499 * Get the physical address for this page. 500 */ 501 if (pmap_extract(pmap, (vaddr_t)vaddr, &curaddr) == FALSE) { 502 bus_dmamap_unload(t, map); 503 return (-1); 504 } 505 506 /* 507 * Compute the segment size, and adjust counts. 508 */ 509 sgsize = NBPG - ((u_long)vaddr & PGOFSET); 510 if (buflen < sgsize) 511 sgsize = buflen; 512 513 DPRINTF(IDB_DVMA, 514 ("iommu_dvmamap_load: map %p loading va %lx at pa %lx\n", 515 map, (long)dvmaddr, (long)(curaddr & ~(NBPG-1)))); 516 iommu_enter(is, trunc_page(dvmaddr), trunc_page(curaddr), 517 flags); 518 519 dvmaddr += PAGE_SIZE; 520 vaddr += sgsize; 521 buflen -= sgsize; 522 } 523 return (0); 524 } 525 526 527 void 528 iommu_dvmamap_unload(t, is, map) 529 bus_dma_tag_t t; 530 struct iommu_state *is; 531 bus_dmamap_t map; 532 { 533 vaddr_t addr; 534 size_t len; 535 int error, s; 536 bus_addr_t dvmaddr; 537 bus_size_t sgsize; 538 539 if (map->dm_nsegs != 1) 540 panic("iommu_dvmamap_unload: nsegs = %d", map->dm_nsegs); 541 542 addr = trunc_page(map->dm_segs[0].ds_addr); 543 len = map->dm_segs[0].ds_len; 544 545 DPRINTF(IDB_DVMA, 546 ("iommu_dvmamap_unload: map %p removing va %lx size %lx\n", 547 map, (long)addr, (long)len)); 548 iommu_remove(is, addr, len); 549 dvmaddr = (map->dm_segs[0].ds_addr & ~PGOFSET); 550 sgsize = map->dm_segs[0].ds_len; 551 552 /* Mark the mappings as invalid. */ 553 map->dm_mapsize = 0; 554 map->dm_nsegs = 0; 555 556 s = splhigh(); 557 error = extent_free(is->is_dvmamap, dvmaddr, sgsize, EX_NOWAIT); 558 splx(s); 559 if (error != 0) 560 printf("warning: %qd of DVMA space lost\n", (long long)sgsize); 561 cache_flush((caddr_t)(u_long)dvmaddr, (u_int)sgsize); 562 } 563 564 565 int 566 iommu_dvmamap_load_raw(t, is, map, segs, nsegs, size, flags) 567 bus_dma_tag_t t; 568 struct iommu_state *is; 569 bus_dmamap_t map; 570 bus_dma_segment_t *segs; 571 int nsegs; 572 bus_size_t size; 573 int flags; 574 { 575 vm_page_t m; 576 int s; 577 int err; 578 bus_size_t sgsize; 579 paddr_t pa; 580 u_long boundary; 581 u_long dvmaddr; 582 struct pglist *mlist; 583 int pagesz = PAGE_SIZE; 584 585 if (map->dm_nsegs) { 586 /* Already in use?? */ 587 #ifdef DIAGNOSTIC 588 printf("iommu_dvmamap_load_raw: map still in use\n"); 589 #endif 590 bus_dmamap_unload(t, map); 591 } 592 /* 593 * Make sure that on error condition we return "no valid mappings". 594 */ 595 map->dm_nsegs = 0; 596 #ifdef DIAGNOSTIC 597 /* XXX - unhelpful since we can't reset these in map_unload() */ 598 if (segs[0].ds_addr != 0) 599 panic("iommu_dvmamap_load_raw: segment already loaded: " 600 "addr %#llx, size %#llx", 601 (u_int64_t)segs[0].ds_addr, (u_int64_t)segs[0].ds_len); 602 if (segs[0].ds_len != size) 603 panic("iommu_dvmamap_load_raw: segment size changed: " 604 "ds_len %#llx size %#llx", segs[0].ds_len, size); 605 #endif 606 sgsize = round_page(size); 607 608 /* 609 * A boundary presented to bus_dmamem_alloc() takes precedence 610 * over boundary in the map. 611 */ 612 if ((boundary = segs[0]._ds_boundary) == 0) 613 boundary = map->_dm_boundary; 614 615 616 s = splhigh(); 617 err = extent_alloc(is->is_dvmamap, sgsize, NBPG, boundary, 618 (flags & BUS_DMA_NOWAIT) == 0 ? EX_WAITOK : EX_NOWAIT, 619 (u_long *)&dvmaddr); 620 splx(s); 621 622 if (err != 0) 623 return (err); 624 625 #ifdef DEBUG 626 if (dvmaddr == (bus_addr_t)-1) 627 { 628 printf("iommu_dvmamap_load_raw(): extent_alloc(%d, %x) failed!\n", 629 sgsize, flags); 630 Debugger(); 631 } 632 #endif 633 if (dvmaddr == (bus_addr_t)-1) 634 return (ENOMEM); 635 636 /* 637 * We always use just one segment. 638 */ 639 map->dm_mapsize = size; 640 map->dm_nsegs = 1; 641 map->dm_segs[0].ds_addr = dvmaddr; 642 map->dm_segs[0].ds_len = size; 643 644 mlist = segs[0]._ds_mlist; 645 for (m = TAILQ_FIRST(mlist); m != NULL; m = TAILQ_NEXT(m,pageq)) { 646 if (sgsize == 0) 647 panic("iommu_dmamap_load_raw: size botch"); 648 pa = VM_PAGE_TO_PHYS(m); 649 650 DPRINTF(IDB_DVMA, 651 ("iommu_dvmamap_load_raw: map %p loading va %lx at pa %lx\n", 652 map, (long)dvmaddr, (long)(pa))); 653 iommu_enter(is, dvmaddr, pa, flags); 654 655 dvmaddr += pagesz; 656 sgsize -= pagesz; 657 } 658 return (0); 659 } 660 661 void 662 iommu_dvmamap_sync(t, is, map, offset, len, ops) 663 bus_dma_tag_t t; 664 struct iommu_state *is; 665 bus_dmamap_t map; 666 bus_addr_t offset; 667 bus_size_t len; 668 int ops; 669 { 670 vaddr_t va = map->dm_segs[0].ds_addr + offset; 671 672 /* 673 * We only support one DMA segment; supporting more makes this code 674 * too unweildy. 675 */ 676 677 if (ops & BUS_DMASYNC_PREREAD) { 678 DPRINTF(IDB_DVMA, 679 ("iommu_dvmamap_sync: syncing va %p len %lu " 680 "BUS_DMASYNC_PREREAD\n", (long)va, (u_long)len)); 681 682 /* Nothing to do */; 683 } 684 if (ops & BUS_DMASYNC_POSTREAD) { 685 DPRINTF(IDB_DVMA, 686 ("iommu_dvmamap_sync: syncing va %p len %lu " 687 "BUS_DMASYNC_POSTREAD\n", (long)va, (u_long)len)); 688 /* if we have a streaming buffer, flush it here first */ 689 if (is->is_sb) 690 while (len > 0) { 691 DPRINTF(IDB_DVMA, 692 ("iommu_dvmamap_sync: flushing va %p, %lu " 693 "bytes left\n", (long)va, (u_long)len)); 694 bus_space_write_8(is->is_bustag, 695 &is->is_sb->strbuf_pgflush, 0, va); 696 if (len <= NBPG) { 697 iommu_flush(is); 698 len = 0; 699 } else 700 len -= NBPG; 701 va += NBPG; 702 } 703 } 704 if (ops & BUS_DMASYNC_PREWRITE) { 705 DPRINTF(IDB_DVMA, 706 ("iommu_dvmamap_sync: syncing va %p len %lu " 707 "BUS_DMASYNC_PREWRITE\n", (long)va, (u_long)len)); 708 /* Nothing to do */; 709 } 710 if (ops & BUS_DMASYNC_POSTWRITE) { 711 DPRINTF(IDB_DVMA, 712 ("iommu_dvmamap_sync: syncing va %p len %lu " 713 "BUS_DMASYNC_POSTWRITE\n", (long)va, (u_long)len)); 714 /* Nothing to do */; 715 } 716 } 717 718 int 719 iommu_dvmamem_alloc(t, is, size, alignment, boundary, segs, nsegs, rsegs, flags) 720 bus_dma_tag_t t; 721 struct iommu_state *is; 722 bus_size_t size, alignment, boundary; 723 bus_dma_segment_t *segs; 724 int nsegs; 725 int *rsegs; 726 int flags; 727 { 728 729 DPRINTF(IDB_DVMA, ("iommu_dvmamem_alloc: sz %qx align %qx bound %qx " 730 "segp %p flags %d\n", size, alignment, boundary, segs, flags)); 731 return (bus_dmamem_alloc(t->_parent, size, alignment, boundary, 732 segs, nsegs, rsegs, flags)); 733 } 734 735 void 736 iommu_dvmamem_free(t, is, segs, nsegs) 737 bus_dma_tag_t t; 738 struct iommu_state *is; 739 bus_dma_segment_t *segs; 740 int nsegs; 741 { 742 743 DPRINTF(IDB_DVMA, ("iommu_dvmamem_free: segp %p nsegs %d\n", 744 segs, nsegs)); 745 bus_dmamem_free(t->_parent, segs, nsegs); 746 } 747 748 /* 749 * Map the DVMA mappings into the kernel pmap. 750 * Check the flags to see whether we're streaming or coherent. 751 */ 752 int 753 iommu_dvmamem_map(t, is, segs, nsegs, size, kvap, flags) 754 bus_dma_tag_t t; 755 struct iommu_state *is; 756 bus_dma_segment_t *segs; 757 int nsegs; 758 size_t size; 759 caddr_t *kvap; 760 int flags; 761 { 762 vm_page_t m; 763 vaddr_t va; 764 bus_addr_t addr; 765 struct pglist *mlist; 766 int cbit; 767 768 DPRINTF(IDB_DVMA, ("iommu_dvmamem_map: segp %p nsegs %d size %lx\n", 769 segs, nsegs, size)); 770 771 /* 772 * Allocate some space in the kernel map, and then map these pages 773 * into this space. 774 */ 775 size = round_page(size); 776 va = uvm_km_valloc(kernel_map, size); 777 if (va == 0) 778 return (ENOMEM); 779 780 *kvap = (caddr_t)va; 781 782 /* 783 * digest flags: 784 */ 785 cbit = 0; 786 if (flags & BUS_DMA_COHERENT) /* Disable vcache */ 787 cbit |= PMAP_NVC; 788 if (flags & BUS_DMA_NOCACHE) /* sideffects */ 789 cbit |= PMAP_NC; 790 791 /* 792 * Now take this and map it into the CPU. 793 */ 794 mlist = segs[0]._ds_mlist; 795 for (m = mlist->tqh_first; m != NULL; m = m->pageq.tqe_next) { 796 #ifdef DIAGNOSTIC 797 if (size == 0) 798 panic("iommu_dvmamem_map: size botch"); 799 #endif 800 addr = VM_PAGE_TO_PHYS(m); 801 DPRINTF(IDB_DVMA, ("iommu_dvmamem_map: " 802 "mapping va %lx at %qx\n", va, addr | cbit)); 803 pmap_enter(pmap_kernel(), va, addr | cbit, 804 VM_PROT_READ | VM_PROT_WRITE, PMAP_WIRED); 805 va += PAGE_SIZE; 806 size -= PAGE_SIZE; 807 } 808 809 return (0); 810 } 811 812 /* 813 * Unmap DVMA mappings from kernel 814 */ 815 void 816 iommu_dvmamem_unmap(t, is, kva, size) 817 bus_dma_tag_t t; 818 struct iommu_state *is; 819 caddr_t kva; 820 size_t size; 821 { 822 823 DPRINTF(IDB_DVMA, ("iommu_dvmamem_unmap: kvm %p size %lx\n", 824 kva, size)); 825 826 #ifdef DIAGNOSTIC 827 if ((u_long)kva & PGOFSET) 828 panic("iommu_dvmamem_unmap"); 829 #endif 830 831 size = round_page(size); 832 pmap_remove(pmap_kernel(), (vaddr_t)kva, size); 833 #if 0 834 /* 835 * XXX ? is this necessary? i think so and i think other 836 * implementations are missing it. 837 */ 838 uvm_km_free(kernel_map, (vaddr_t)kva, size); 839 #endif 840 } 841
Indexes created Fri Sep 26 08:10:20 GMT 2025