iommu.c revision 1.13
1 /* $NetBSD: iommu.c,v 1.13 2000/06/18 07:05:09 mrg Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000 Matthew R. Green 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 23 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 24 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 25 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 /*- 32 * Copyright (c) 1998 The NetBSD Foundation, Inc. 33 * All rights reserved. 34 * 35 * This code is derived from software contributed to The NetBSD Foundation 36 * by Paul Kranenburg. 37 * 38 * Redistribution and use in source and binary forms, with or without 39 * modification, are permitted provided that the following conditions 40 * are met: 41 * 1. Redistributions of source code must retain the above copyright 42 * notice, this list of conditions and the following disclaimer. 43 * 2. Redistributions in binary form must reproduce the above copyright 44 * notice, this list of conditions and the following disclaimer in the 45 * documentation and/or other materials provided with the distribution. 46 * 3. All advertising materials mentioning features or use of this software 47 * must display the following acknowledgement: 48 * This product includes software developed by the NetBSD 49 * Foundation, Inc. and its contributors. 50 * 4. Neither the name of The NetBSD Foundation nor the names of its 51 * contributors may be used to endorse or promote products derived 52 * from this software without specific prior written permission. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 55 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 56 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 57 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 58 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 59 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 60 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 61 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 62 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 63 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 64 * POSSIBILITY OF SUCH DAMAGE. 65 */ 66 67 /* 68 * Copyright (c) 1992, 1993 69 * The Regents of the University of California. All rights reserved. 70 * 71 * This software was developed by the Computer Systems Engineering group 72 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 73 * contributed to Berkeley. 74 * 75 * All advertising materials mentioning features or use of this software 76 * must display the following acknowledgement: 77 * This product includes software developed by the University of 78 * California, Lawrence Berkeley Laboratory. 79 * 80 * Redistribution and use in source and binary forms, with or without 81 * modification, are permitted provided that the following conditions 82 * are met: 83 * 1. Redistributions of source code must retain the above copyright 84 * notice, this list of conditions and the following disclaimer. 85 * 2. Redistributions in binary form must reproduce the above copyright 86 * notice, this list of conditions and the following disclaimer in the 87 * documentation and/or other materials provided with the distribution. 88 * 3. All advertising materials mentioning features or use of this software 89 * must display the following acknowledgement: 90 * This product includes software developed by the University of 91 * California, Berkeley and its contributors. 92 * 4. Neither the name of the University nor the names of its contributors 93 * may be used to endorse or promote products derived from this software 94 * without specific prior written permission. 95 * 96 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 97 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 98 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 99 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 100 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 101 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 102 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 103 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 104 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 105 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 106 * SUCH DAMAGE. 107 * 108 * from: NetBSD: sbus.c,v 1.13 1999/05/23 07:24:02 mrg Exp 109 * from: @(#)sbus.c 8.1 (Berkeley) 6/11/93 110 */ 111 112 /* 113 * UltraSPARC IOMMU support; used by both the sbus and pci code. 114 */ 115 #include "opt_ddb.h" 116 117 #include <sys/param.h> 118 #include <sys/extent.h> 119 #include <sys/malloc.h> 120 #include <sys/systm.h> 121 #include <sys/device.h> 122 #include <vm/vm.h> 123 #include <vm/vm_kern.h> 124 125 #include <machine/bus.h> 126 #include <sparc64/sparc64/cache.h> 127 #include <sparc64/sparc64/vaddrs.h> 128 #include <sparc64/dev/iommureg.h> 129 #include <sparc64/dev/iommuvar.h> 130 131 #include <machine/autoconf.h> 132 #include <machine/ctlreg.h> 133 #include <machine/cpu.h> 134 135 #ifdef DEBUG 136 #define IDB_DVMA 0x1 137 int iommudebug = 0x0; 138 #define DPRINTF(l, s) do { if (iommudebug & l) printf s; } while (0) 139 #else 140 #define DPRINTF(l, s) 141 #endif 142 143 144 /* 145 * initialise the UltraSPARC IOMMU (SBUS or PCI): 146 * - allocate and setup the iotsb. 147 * - enable the IOMMU 148 * - initialise the streaming buffers (if they exist) 149 * - create a private DVMA map. 150 */ 151 void 152 iommu_init(name, is, tsbsize) 153 char *name; 154 struct iommu_state *is; 155 int tsbsize; 156 { 157 psize_t size; 158 vaddr_t va; 159 paddr_t pa; 160 vm_page_t m; 161 struct pglist mlist; 162 163 /* 164 * Setup the iommu. 165 * 166 * The sun4u iommu is part of the SBUS or PCI controller so we 167 * will deal with it here.. 168 * 169 * The IOMMU address space always ends at 0xffffe000, but the starting 170 * address depends on the size of the map. The map size is 1024 * 2 ^ 171 * is->is_tsbsize entries, where each entry is 8 bytes. The start of 172 * the map can be calculated by (0xffffe000 << (8 + is->is_tsbsize)). 173 * 174 * Note: the stupid IOMMU ignores the high bits of an address, so a 175 * NULL DMA pointer will be translated by the first page of the IOTSB. 176 * To trap bugs we'll skip the first entry in the IOTSB. 177 */ 178 is->is_cr = (tsbsize << 16) | IOMMUCR_EN; 179 is->is_tsbsize = tsbsize; 180 is->is_dvmabase = IOTSB_VSTART(is->is_tsbsize) + NBPG; 181 182 /* 183 * Allocate memory for I/O pagetables. 184 * This takes 64K of contiguous physical memory to map 64M of 185 * DVMA space (starting at IOMMU_DVMA_BASE). 186 * The table must be aligned on a (-IOMMU_DVMA_BASE/pagesize) 187 * boundary (i.e. 64K for 64M of DVMA space). 188 */ 189 190 size = NBPG<<(is->is_tsbsize); 191 TAILQ_INIT(&mlist); 192 if (uvm_pglistalloc((psize_t)size, (paddr_t)0, (paddr_t)-1, 193 (paddr_t)NBPG, (paddr_t)0, &mlist, 1, 0) != 0) 194 panic("iommu_init: no memory"); 195 196 va = uvm_km_valloc(kernel_map, size); 197 if (va == 0) 198 panic("iommu_init: no memory"); 199 is->is_tsb = (int64_t *)va; 200 201 m = TAILQ_FIRST(&mlist); 202 is->is_ptsb = VM_PAGE_TO_PHYS(m); 203 204 /* Map the pages */ 205 for (; m != NULL; m = TAILQ_NEXT(m,pageq)) { 206 pa = VM_PAGE_TO_PHYS(m); 207 pmap_enter(pmap_kernel(), va, pa | PMAP_NVC, 208 VM_PROT_READ|VM_PROT_WRITE, 209 VM_PROT_READ|VM_PROT_WRITE|PMAP_WIRED); 210 va += NBPG; 211 } 212 bzero(is->is_tsb, size); 213 214 #ifdef DEBUG 215 if (iommudebug & IDB_DVMA) 216 { 217 /* Probe the iommu */ 218 struct iommureg *regs = is->is_iommu; 219 int64_t cr, tsb; 220 221 printf("iommu regs at: cr=%lx tsb=%lx flush=%lx\n", ®s->iommu_cr, 222 ®s->iommu_tsb, ®s->iommu_flush); 223 cr = regs->iommu_cr; 224 tsb = regs->iommu_tsb; 225 printf("iommu cr=%qx tsb=%qx\n", cr, tsb); 226 printf("TSB base %p phys %qx\n", (void *)is->is_tsb, (u_int64_t)is->is_ptsb); 227 delay(1000000); /* 1 s */ 228 } 229 #endif 230 231 /* 232 * Initialize streaming buffer, if it is there. 233 */ 234 if (is->is_sb) 235 (void)pmap_extract(pmap_kernel(), (vaddr_t)&is->is_flush, 236 (paddr_t *)&is->is_flushpa); 237 238 /* 239 * now actually start up the IOMMU 240 */ 241 iommu_reset(is); 242 243 /* 244 * Now all the hardware's working we need to allocate a dvma map. 245 */ 246 printf("DVMA map: %x to %x\n", 247 (unsigned int)is->is_dvmabase, 248 (unsigned int)IOTSB_VEND); 249 is->is_dvmamap = extent_create(name, 250 is->is_dvmabase, IOTSB_VEND, 251 M_DEVBUF, 0, 0, EX_NOWAIT); 252 } 253 254 /* 255 * Streaming buffers don't exist on the UltraSPARC IIi; we should have 256 * detected that already and disabled them. If not, we will notice that 257 * they aren't there when the STRBUF_EN bit does not remain. 258 */ 259 void 260 iommu_reset(is) 261 struct iommu_state *is; 262 { 263 264 /* Need to do 64-bit stores */ 265 bus_space_write_8(is->is_bustag, &is->is_iommu->iommu_tsb, 0, is->is_ptsb); 266 /* Enable IOMMU in diagnostic mode */ 267 bus_space_write_8(is->is_bustag, &is->is_iommu->iommu_cr, 0, 268 is->is_cr|IOMMUCR_DE); 269 270 271 if (!is->is_sb) 272 return; 273 274 /* Enable diagnostics mode? */ 275 bus_space_write_8(is->is_bustag, &is->is_sb->strbuf_ctl, 0, STRBUF_EN); 276 277 /* No streaming buffers? Disable them */ 278 if (bus_space_read_8(is->is_bustag, 279 (bus_space_handle_t)(u_long)&is->is_sb->strbuf_ctl, 0) == 0) 280 is->is_sb = 0; 281 } 282 283 /* 284 * Here are the iommu control routines. 285 */ 286 void 287 iommu_enter(is, va, pa, flags) 288 struct iommu_state *is; 289 vaddr_t va; 290 int64_t pa; 291 int flags; 292 { 293 int64_t tte; 294 295 #ifdef DIAGNOSTIC 296 if (va < is->is_dvmabase) 297 panic("iommu_enter: va %#lx not in DVMA space", va); 298 #endif 299 300 tte = MAKEIOTTE(pa, !(flags&BUS_DMA_NOWRITE), !(flags&BUS_DMA_NOCACHE), 301 !(flags&BUS_DMA_COHERENT)); 302 303 /* Is the streamcache flush really needed? */ 304 if (is->is_sb) { 305 bus_space_write_8(is->is_bustag, &is->is_sb->strbuf_pgflush, 0, 306 va); 307 iommu_flush(is); 308 } 309 DPRINTF(IDB_DVMA, ("Clearing TSB slot %d for va %p\n", 310 (int)IOTSBSLOT(va,is->is_tsbsize), va)); 311 is->is_tsb[IOTSBSLOT(va,is->is_tsbsize)] = tte; 312 bus_space_write_8(is->is_bustag, &is->is_iommu->iommu_flush, 313 0, va); 314 DPRINTF(IDB_DVMA, ("iommu_enter: va %lx pa %lx TSB[%lx]@%p=%lx\n", 315 va, (long)pa, IOTSBSLOT(va,is->is_tsbsize), 316 &is->is_tsb[IOTSBSLOT(va,is->is_tsbsize)], 317 (long)tte)); 318 } 319 320 /* 321 * iommu_remove: removes mappings created by iommu_enter 322 * 323 * Only demap from IOMMU if flag is set. 324 * 325 * XXX: this function needs better internal error checking. 326 */ 327 void 328 iommu_remove(is, va, len) 329 struct iommu_state *is; 330 vaddr_t va; 331 size_t len; 332 { 333 334 #ifdef DIAGNOSTIC 335 if (va < is->is_dvmabase) 336 panic("iommu_remove: va 0x%lx not in DVMA space", (long)va); 337 if ((long)(va + len) < (long)va) 338 panic("iommu_remove: va 0x%lx + len 0x%lx wraps", 339 (long) va, (long) len); 340 if (len & ~0xfffffff) 341 panic("iommu_remove: rediculous len 0x%lx", (long)len); 342 #endif 343 344 va = trunc_page(va); 345 DPRINTF(IDB_DVMA, ("iommu_remove: va %lx TSB[%lx]@%p\n", 346 va, IOTSBSLOT(va,is->is_tsbsize), 347 &is->is_tsb[IOTSBSLOT(va,is->is_tsbsize)])); 348 while (len > 0) { 349 DPRINTF(IDB_DVMA, ("iommu_remove: clearing TSB slot %d for va %p size %lx\n", 350 (int)IOTSBSLOT(va,is->is_tsbsize), va, (u_long)len)); 351 if (is->is_sb) { 352 DPRINTF(IDB_DVMA, ("iommu_remove: flushing va %p TSB[%lx]@%p=%lx, %lu bytes left\n", 353 (long)va, (long)IOTSBSLOT(va,is->is_tsbsize), 354 (long)&is->is_tsb[IOTSBSLOT(va,is->is_tsbsize)], 355 (long)(is->is_tsb[IOTSBSLOT(va,is->is_tsbsize)]), 356 (u_long)len)); 357 bus_space_write_8(is->is_bustag, 358 &is->is_sb->strbuf_pgflush, 0, va); 359 if (len <= NBPG) 360 iommu_flush(is); 361 DPRINTF(IDB_DVMA, ("iommu_remove: flushed va %p TSB[%lx]@%p=%lx, %lu bytes left\n", 362 (long)va, (long)IOTSBSLOT(va,is->is_tsbsize), 363 (long)&is->is_tsb[IOTSBSLOT(va,is->is_tsbsize)], 364 (long)(is->is_tsb[IOTSBSLOT(va,is->is_tsbsize)]), 365 (u_long)len)); 366 } else 367 membar_sync(); /* XXX */ 368 369 if (len <= NBPG) 370 len = 0; 371 else 372 len -= NBPG; 373 374 is->is_tsb[IOTSBSLOT(va,is->is_tsbsize)] = 0; 375 bus_space_write_8(is->is_bustag, &is->is_iommu->iommu_flush, 0, va); 376 va += NBPG; 377 } 378 } 379 380 int 381 iommu_flush(is) 382 struct iommu_state *is; 383 { 384 struct timeval cur, flushtimeout; 385 386 #define BUMPTIME(t, usec) { \ 387 register volatile struct timeval *tp = (t); \ 388 register long us; \ 389 \ 390 tp->tv_usec = us = tp->tv_usec + (usec); \ 391 if (us >= 1000000) { \ 392 tp->tv_usec = us - 1000000; \ 393 tp->tv_sec++; \ 394 } \ 395 } 396 397 if (!is->is_sb) 398 return (0); 399 400 /* 401 * Streaming buffer flushes: 402 * 403 * 1 Tell strbuf to flush by storing va to strbuf_pgflush. If 404 * we're not on a cache line boundary (64-bits): 405 * 2 Store 0 in flag 406 * 3 Store pointer to flag in flushsync 407 * 4 wait till flushsync becomes 0x1 408 * 409 * If it takes more than .5 sec, something 410 * went wrong. 411 */ 412 413 is->is_flush = 0; 414 membar_sync(); 415 bus_space_write_8(is->is_bustag, &is->is_sb->strbuf_flushsync, 0, is->is_flushpa); 416 membar_sync(); 417 418 microtime(&flushtimeout); 419 cur = flushtimeout; 420 BUMPTIME(&flushtimeout, 500000); /* 1/2 sec */ 421 422 DPRINTF(IDB_DVMA, ("iommu_flush: flush = %lx at va = %lx pa = %lx now=%lx:%lx until = %lx:%lx\n", 423 (long)is->is_flush, (long)&is->is_flush, 424 (long)is->is_flushpa, cur.tv_sec, cur.tv_usec, 425 flushtimeout.tv_sec, flushtimeout.tv_usec)); 426 /* Bypass non-coherent D$ */ 427 while (!ldxa(is->is_flushpa, ASI_PHYS_CACHED) && 428 ((cur.tv_sec <= flushtimeout.tv_sec) && 429 (cur.tv_usec <= flushtimeout.tv_usec))) 430 microtime(&cur); 431 432 #ifdef DIAGNOSTIC 433 if (!is->is_flush) { 434 printf("iommu_flush: flush timeout %p at %p\n", (long)is->is_flush, 435 (long)is->is_flushpa); /* panic? */ 436 #ifdef DDB 437 Debugger(); 438 #endif 439 } 440 #endif 441 DPRINTF(IDB_DVMA, ("iommu_flush: flushed\n")); 442 return (is->is_flush); 443 } 444 445 /* 446 * IOMMU DVMA operations, common to SBUS and PCI. 447 */ 448 int 449 iommu_dvmamap_load(t, is, map, buf, buflen, p, flags) 450 bus_dma_tag_t t; 451 struct iommu_state *is; 452 bus_dmamap_t map; 453 void *buf; 454 bus_size_t buflen; 455 struct proc *p; 456 int flags; 457 { 458 int s; 459 int err; 460 bus_size_t sgsize; 461 paddr_t curaddr; 462 u_long dvmaddr; 463 vaddr_t vaddr = (vaddr_t)buf; 464 pmap_t pmap; 465 466 if (map->dm_nsegs) { 467 /* Already in use?? */ 468 #ifdef DIAGNOSTIC 469 printf("iommu_dvmamap_load: map still in use\n"); 470 #endif 471 bus_dmamap_unload(t, map); 472 } 473 /* 474 * Make sure that on error condition we return "no valid mappings". 475 */ 476 map->dm_nsegs = 0; 477 478 if (buflen > map->_dm_size) { 479 DPRINTF(IDB_DVMA, 480 ("iommu_dvmamap_load(): error %d > %d -- " 481 "map size exceeded!\n", buflen, map->_dm_size)); 482 return (EINVAL); 483 } 484 485 #if 1 486 sgsize = round_page(buflen + ((int)vaddr & PGOFSET)); 487 #else 488 sgsize = buflen + ((int)vaddr & PGOFSET); 489 #endif 490 /* 491 * XXX Need to implement "don't dma across this boundry". 492 */ 493 s = splhigh(); 494 err = extent_alloc(is->is_dvmamap, sgsize, NBPG, 495 map->_dm_boundary, EX_NOWAIT, (u_long *)&dvmaddr); 496 splx(s); 497 498 #ifdef DEBUG 499 if (err || (dvmaddr == (bus_addr_t)-1)) 500 { 501 printf("iommu_dvmamap_load(): extent_alloc(%d, %x) failed!\n", 502 sgsize, flags); 503 Debugger(); 504 } 505 #endif 506 if (err != 0) 507 return (err); 508 509 if (dvmaddr == (bus_addr_t)-1) 510 return (ENOMEM); 511 512 /* 513 * We always use just one segment. 514 */ 515 map->dm_mapsize = buflen; 516 map->dm_nsegs = 1; 517 map->dm_segs[0].ds_addr = dvmaddr + (vaddr & PGOFSET); 518 map->dm_segs[0].ds_len = sgsize; 519 520 if (p != NULL) 521 pmap = p->p_vmspace->vm_map.pmap; 522 else 523 pmap = pmap_kernel(); 524 525 dvmaddr = trunc_page(map->dm_segs[0].ds_addr); 526 for (; buflen > 0; ) { 527 /* 528 * Get the physical address for this page. 529 */ 530 if (pmap_extract(pmap, (vaddr_t)vaddr, &curaddr) == FALSE) { 531 bus_dmamap_unload(t, map); 532 return (-1); 533 } 534 535 /* 536 * Compute the segment size, and adjust counts. 537 */ 538 sgsize = NBPG - ((u_long)vaddr & PGOFSET); 539 if (buflen < sgsize) 540 sgsize = buflen; 541 542 DPRINTF(IDB_DVMA, 543 ("iommu_dvmamap_load: map %p loading va %p dva %lx at pa %lx\n", 544 map, (void *)vaddr, (long)dvmaddr, (long)(curaddr&~(NBPG-1)))); 545 iommu_enter(is, trunc_page(dvmaddr), trunc_page(curaddr), 546 flags); 547 548 dvmaddr += PAGE_SIZE; 549 vaddr += sgsize; 550 buflen -= sgsize; 551 } 552 return (0); 553 } 554 555 556 void 557 iommu_dvmamap_unload(t, is, map) 558 bus_dma_tag_t t; 559 struct iommu_state *is; 560 bus_dmamap_t map; 561 { 562 vaddr_t addr; 563 size_t len; 564 int error, s; 565 bus_addr_t dvmaddr; 566 bus_size_t sgsize; 567 568 if (map->dm_nsegs != 1) 569 panic("iommu_dvmamap_unload: nsegs = %d", map->dm_nsegs); 570 571 addr = trunc_page(map->dm_segs[0].ds_addr); 572 len = map->dm_segs[0].ds_len; 573 574 DPRINTF(IDB_DVMA, 575 ("iommu_dvmamap_unload: map %p removing va %lx size %lx\n", 576 map, (long)addr, (long)len)); 577 iommu_remove(is, addr, len); 578 dvmaddr = (map->dm_segs[0].ds_addr & ~PGOFSET); 579 sgsize = map->dm_segs[0].ds_len; 580 581 /* Mark the mappings as invalid. */ 582 map->dm_mapsize = 0; 583 map->dm_nsegs = 0; 584 585 s = splhigh(); 586 error = extent_free(is->is_dvmamap, dvmaddr, sgsize, EX_NOWAIT); 587 splx(s); 588 if (error != 0) 589 printf("warning: %qd of DVMA space lost\n", (long long)sgsize); 590 cache_flush((caddr_t)(u_long)dvmaddr, (u_int)sgsize); 591 } 592 593 594 int 595 iommu_dvmamap_load_raw(t, is, map, segs, nsegs, size, flags) 596 bus_dma_tag_t t; 597 struct iommu_state *is; 598 bus_dmamap_t map; 599 bus_dma_segment_t *segs; 600 int nsegs; 601 bus_size_t size; 602 int flags; 603 { 604 vm_page_t m; 605 int s; 606 int err; 607 bus_size_t sgsize; 608 paddr_t pa; 609 u_long boundary; 610 u_long dvmaddr; 611 struct pglist *mlist; 612 int pagesz = PAGE_SIZE; 613 614 if (map->dm_nsegs) { 615 /* Already in use?? */ 616 #ifdef DIAGNOSTIC 617 printf("iommu_dvmamap_load_raw: map still in use\n"); 618 #endif 619 bus_dmamap_unload(t, map); 620 } 621 /* 622 * Make sure that on error condition we return "no valid mappings". 623 */ 624 map->dm_nsegs = 0; 625 #ifdef DIAGNOSTIC 626 /* XXX - unhelpful since we can't reset these in map_unload() */ 627 if (segs[0].ds_addr != 0) 628 panic("iommu_dvmamap_load_raw: segment already loaded: " 629 "addr %#llx, size %#llx", 630 (u_int64_t)segs[0].ds_addr, (u_int64_t)segs[0].ds_len); 631 if (segs[0].ds_len != size) 632 panic("iommu_dvmamap_load_raw: segment size changed: " 633 "ds_len %#llx size %#llx", segs[0].ds_len, size); 634 #endif 635 sgsize = round_page(size); 636 637 /* 638 * A boundary presented to bus_dmamem_alloc() takes precedence 639 * over boundary in the map. 640 */ 641 if ((boundary = segs[0]._ds_boundary) == 0) 642 boundary = map->_dm_boundary; 643 644 s = splhigh(); 645 err = extent_alloc(is->is_dvmamap, sgsize, NBPG, boundary, 646 (flags & BUS_DMA_NOWAIT) == 0 ? EX_WAITOK : EX_NOWAIT, 647 (u_long *)&dvmaddr); 648 splx(s); 649 650 if (err != 0) 651 return (err); 652 653 #ifdef DEBUG 654 if (dvmaddr == (bus_addr_t)-1) 655 { 656 printf("iommu_dvmamap_load_raw(): extent_alloc(%d, %x) failed!\n", 657 sgsize, flags); 658 Debugger(); 659 } 660 #endif 661 if (dvmaddr == (bus_addr_t)-1) 662 return (ENOMEM); 663 664 /* 665 * We always use just one segment. 666 */ 667 map->dm_mapsize = size; 668 map->dm_nsegs = 1; 669 map->dm_segs[0].ds_addr = dvmaddr; 670 map->dm_segs[0].ds_len = size; 671 672 mlist = segs[0]._ds_mlist; 673 for (m = TAILQ_FIRST(mlist); m != NULL; m = TAILQ_NEXT(m,pageq)) { 674 if (sgsize == 0) 675 panic("iommu_dmamap_load_raw: size botch"); 676 pa = VM_PAGE_TO_PHYS(m); 677 678 DPRINTF(IDB_DVMA, 679 ("iommu_dvmamap_load_raw: map %p loading va %lx at pa %lx\n", 680 map, (long)dvmaddr, (long)(pa))); 681 iommu_enter(is, dvmaddr, pa, flags); 682 683 dvmaddr += pagesz; 684 sgsize -= pagesz; 685 } 686 return (0); 687 } 688 689 void 690 iommu_dvmamap_sync(t, is, map, offset, len, ops) 691 bus_dma_tag_t t; 692 struct iommu_state *is; 693 bus_dmamap_t map; 694 bus_addr_t offset; 695 bus_size_t len; 696 int ops; 697 { 698 vaddr_t va = map->dm_segs[0].ds_addr + offset; 699 700 /* 701 * We only support one DMA segment; supporting more makes this code 702 * too unweildy. 703 */ 704 705 if (ops & BUS_DMASYNC_PREREAD) { 706 DPRINTF(IDB_DVMA, 707 ("iommu_dvmamap_sync: syncing va %p len %lu " 708 "BUS_DMASYNC_PREREAD\n", (long)va, (u_long)len)); 709 710 /* Nothing to do */; 711 } 712 if (ops & BUS_DMASYNC_POSTREAD) { 713 DPRINTF(IDB_DVMA, 714 ("iommu_dvmamap_sync: syncing va %p len %lu " 715 "BUS_DMASYNC_POSTREAD\n", (long)va, (u_long)len)); 716 /* if we have a streaming buffer, flush it here first */ 717 if (is->is_sb) 718 while (len > 0) { 719 DPRINTF(IDB_DVMA, 720 ("iommu_dvmamap_sync: flushing va %p, %lu " 721 "bytes left\n", (long)va, (u_long)len)); 722 bus_space_write_8(is->is_bustag, 723 &is->is_sb->strbuf_pgflush, 0, va); 724 if (len <= NBPG) { 725 iommu_flush(is); 726 len = 0; 727 } else 728 len -= NBPG; 729 va += NBPG; 730 } 731 } 732 if (ops & BUS_DMASYNC_PREWRITE) { 733 DPRINTF(IDB_DVMA, 734 ("iommu_dvmamap_sync: syncing va %p len %lu " 735 "BUS_DMASYNC_PREWRITE\n", (long)va, (u_long)len)); 736 /* Nothing to do */; 737 } 738 if (ops & BUS_DMASYNC_POSTWRITE) { 739 DPRINTF(IDB_DVMA, 740 ("iommu_dvmamap_sync: syncing va %p len %lu " 741 "BUS_DMASYNC_POSTWRITE\n", (long)va, (u_long)len)); 742 /* Nothing to do */; 743 } 744 } 745 746 int 747 iommu_dvmamem_alloc(t, is, size, alignment, boundary, segs, nsegs, rsegs, flags) 748 bus_dma_tag_t t; 749 struct iommu_state *is; 750 bus_size_t size, alignment, boundary; 751 bus_dma_segment_t *segs; 752 int nsegs; 753 int *rsegs; 754 int flags; 755 { 756 757 DPRINTF(IDB_DVMA, ("iommu_dvmamem_alloc: sz %qx align %qx bound %qx " 758 "segp %p flags %d\n", size, alignment, boundary, segs, flags)); 759 return (bus_dmamem_alloc(t->_parent, size, alignment, boundary, 760 segs, nsegs, rsegs, flags)); 761 } 762 763 void 764 iommu_dvmamem_free(t, is, segs, nsegs) 765 bus_dma_tag_t t; 766 struct iommu_state *is; 767 bus_dma_segment_t *segs; 768 int nsegs; 769 { 770 771 DPRINTF(IDB_DVMA, ("iommu_dvmamem_free: segp %p nsegs %d\n", 772 segs, nsegs)); 773 bus_dmamem_free(t->_parent, segs, nsegs); 774 } 775 776 /* 777 * Map the DVMA mappings into the kernel pmap. 778 * Check the flags to see whether we're streaming or coherent. 779 */ 780 int 781 iommu_dvmamem_map(t, is, segs, nsegs, size, kvap, flags) 782 bus_dma_tag_t t; 783 struct iommu_state *is; 784 bus_dma_segment_t *segs; 785 int nsegs; 786 size_t size; 787 caddr_t *kvap; 788 int flags; 789 { 790 vm_page_t m; 791 vaddr_t va; 792 bus_addr_t addr; 793 struct pglist *mlist; 794 int cbit; 795 796 DPRINTF(IDB_DVMA, ("iommu_dvmamem_map: segp %p nsegs %d size %lx\n", 797 segs, nsegs, size)); 798 799 /* 800 * Allocate some space in the kernel map, and then map these pages 801 * into this space. 802 */ 803 size = round_page(size); 804 va = uvm_km_valloc(kernel_map, size); 805 if (va == 0) 806 return (ENOMEM); 807 808 *kvap = (caddr_t)va; 809 810 /* 811 * digest flags: 812 */ 813 cbit = 0; 814 if (flags & BUS_DMA_COHERENT) /* Disable vcache */ 815 cbit |= PMAP_NVC; 816 if (flags & BUS_DMA_NOCACHE) /* sideffects */ 817 cbit |= PMAP_NC; 818 819 /* 820 * Now take this and map it into the CPU. 821 */ 822 mlist = segs[0]._ds_mlist; 823 for (m = mlist->tqh_first; m != NULL; m = m->pageq.tqe_next) { 824 #ifdef DIAGNOSTIC 825 if (size == 0) 826 panic("iommu_dvmamem_map: size botch"); 827 #endif 828 addr = VM_PAGE_TO_PHYS(m); 829 DPRINTF(IDB_DVMA, ("iommu_dvmamem_map: " 830 "mapping va %lx at %qx\n", va, addr | cbit)); 831 pmap_enter(pmap_kernel(), va, addr | cbit, 832 VM_PROT_READ | VM_PROT_WRITE, PMAP_WIRED); 833 va += PAGE_SIZE; 834 size -= PAGE_SIZE; 835 } 836 837 return (0); 838 } 839 840 /* 841 * Unmap DVMA mappings from kernel 842 */ 843 void 844 iommu_dvmamem_unmap(t, is, kva, size) 845 bus_dma_tag_t t; 846 struct iommu_state *is; 847 caddr_t kva; 848 size_t size; 849 { 850 851 DPRINTF(IDB_DVMA, ("iommu_dvmamem_unmap: kvm %p size %lx\n", 852 kva, size)); 853 854 #ifdef DIAGNOSTIC 855 if ((u_long)kva & PGOFSET) 856 panic("iommu_dvmamem_unmap"); 857 #endif 858 859 size = round_page(size); 860 pmap_remove(pmap_kernel(), (vaddr_t)kva, size); 861 #if 0 862 /* 863 * XXX ? is this necessary? i think so and i think other 864 * implementations are missing it. 865 */ 866 uvm_km_free(kernel_map, (vaddr_t)kva, size); 867 #endif 868 } 869
Indexes created Tue Sep 23 07:09:52 GMT 2025