iommu.c revision 1.14
1 /* $NetBSD: iommu.c,v 1.14 2000/06/18 07:17:40 mrg Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000 Matthew R. Green 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 23 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 24 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 25 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 /*- 32 * Copyright (c) 1998 The NetBSD Foundation, Inc. 33 * All rights reserved. 34 * 35 * This code is derived from software contributed to The NetBSD Foundation 36 * by Paul Kranenburg. 37 * 38 * Redistribution and use in source and binary forms, with or without 39 * modification, are permitted provided that the following conditions 40 * are met: 41 * 1. Redistributions of source code must retain the above copyright 42 * notice, this list of conditions and the following disclaimer. 43 * 2. Redistributions in binary form must reproduce the above copyright 44 * notice, this list of conditions and the following disclaimer in the 45 * documentation and/or other materials provided with the distribution. 46 * 3. All advertising materials mentioning features or use of this software 47 * must display the following acknowledgement: 48 * This product includes software developed by the NetBSD 49 * Foundation, Inc. and its contributors. 50 * 4. Neither the name of The NetBSD Foundation nor the names of its 51 * contributors may be used to endorse or promote products derived 52 * from this software without specific prior written permission. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 55 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 56 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 57 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 58 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 59 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 60 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 61 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 62 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 63 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 64 * POSSIBILITY OF SUCH DAMAGE. 65 */ 66 67 /* 68 * Copyright (c) 1992, 1993 69 * The Regents of the University of California. All rights reserved. 70 * 71 * This software was developed by the Computer Systems Engineering group 72 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 73 * contributed to Berkeley. 74 * 75 * All advertising materials mentioning features or use of this software 76 * must display the following acknowledgement: 77 * This product includes software developed by the University of 78 * California, Lawrence Berkeley Laboratory. 79 * 80 * Redistribution and use in source and binary forms, with or without 81 * modification, are permitted provided that the following conditions 82 * are met: 83 * 1. Redistributions of source code must retain the above copyright 84 * notice, this list of conditions and the following disclaimer. 85 * 2. Redistributions in binary form must reproduce the above copyright 86 * notice, this list of conditions and the following disclaimer in the 87 * documentation and/or other materials provided with the distribution. 88 * 3. All advertising materials mentioning features or use of this software 89 * must display the following acknowledgement: 90 * This product includes software developed by the University of 91 * California, Berkeley and its contributors. 92 * 4. Neither the name of the University nor the names of its contributors 93 * may be used to endorse or promote products derived from this software 94 * without specific prior written permission. 95 * 96 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 97 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 98 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 99 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 100 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 101 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 102 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 103 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 104 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 105 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 106 * SUCH DAMAGE. 107 * 108 * from: NetBSD: sbus.c,v 1.13 1999/05/23 07:24:02 mrg Exp 109 * from: @(#)sbus.c 8.1 (Berkeley) 6/11/93 110 */ 111 112 /* 113 * UltraSPARC IOMMU support; used by both the sbus and pci code. 114 */ 115 #include "opt_ddb.h" 116 117 #include <sys/param.h> 118 #include <sys/extent.h> 119 #include <sys/malloc.h> 120 #include <sys/systm.h> 121 #include <sys/device.h> 122 #include <vm/vm.h> 123 #include <vm/vm_kern.h> 124 125 #include <machine/bus.h> 126 #include <sparc64/sparc64/cache.h> 127 #include <sparc64/sparc64/vaddrs.h> 128 #include <sparc64/dev/iommureg.h> 129 #include <sparc64/dev/iommuvar.h> 130 131 #include <machine/autoconf.h> 132 #include <machine/ctlreg.h> 133 #include <machine/cpu.h> 134 135 #ifdef DEBUG 136 #define IDB_DVMA 0x1 137 int iommudebug = 0x0; 138 #define DPRINTF(l, s) do { if (iommudebug & l) printf s; } while (0) 139 #else 140 #define DPRINTF(l, s) 141 #endif 142 143 static int iommu_strbuf_flush __P((struct iommu_state *)); 144 145 /* 146 * initialise the UltraSPARC IOMMU (SBUS or PCI): 147 * - allocate and setup the iotsb. 148 * - enable the IOMMU 149 * - initialise the streaming buffers (if they exist) 150 * - create a private DVMA map. 151 */ 152 void 153 iommu_init(name, is, tsbsize) 154 char *name; 155 struct iommu_state *is; 156 int tsbsize; 157 { 158 psize_t size; 159 vaddr_t va; 160 paddr_t pa; 161 vm_page_t m; 162 struct pglist mlist; 163 164 /* 165 * Setup the iommu. 166 * 167 * The sun4u iommu is part of the SBUS or PCI controller so we 168 * will deal with it here.. 169 * 170 * The IOMMU address space always ends at 0xffffe000, but the starting 171 * address depends on the size of the map. The map size is 1024 * 2 ^ 172 * is->is_tsbsize entries, where each entry is 8 bytes. The start of 173 * the map can be calculated by (0xffffe000 << (8 + is->is_tsbsize)). 174 * 175 * Note: the stupid IOMMU ignores the high bits of an address, so a 176 * NULL DMA pointer will be translated by the first page of the IOTSB. 177 * To trap bugs we'll skip the first entry in the IOTSB. 178 */ 179 is->is_cr = (tsbsize << 16) | IOMMUCR_EN; 180 is->is_tsbsize = tsbsize; 181 is->is_dvmabase = IOTSB_VSTART(is->is_tsbsize) + NBPG; 182 183 /* 184 * Allocate memory for I/O pagetables. 185 * This takes 64K of contiguous physical memory to map 64M of 186 * DVMA space (starting at IOMMU_DVMA_BASE). 187 * The table must be aligned on a (-IOMMU_DVMA_BASE/pagesize) 188 * boundary (i.e. 64K for 64M of DVMA space). 189 */ 190 191 size = NBPG<<(is->is_tsbsize); 192 TAILQ_INIT(&mlist); 193 if (uvm_pglistalloc((psize_t)size, (paddr_t)0, (paddr_t)-1, 194 (paddr_t)NBPG, (paddr_t)0, &mlist, 1, 0) != 0) 195 panic("iommu_init: no memory"); 196 197 va = uvm_km_valloc(kernel_map, size); 198 if (va == 0) 199 panic("iommu_init: no memory"); 200 is->is_tsb = (int64_t *)va; 201 202 m = TAILQ_FIRST(&mlist); 203 is->is_ptsb = VM_PAGE_TO_PHYS(m); 204 205 /* Map the pages */ 206 for (; m != NULL; m = TAILQ_NEXT(m,pageq)) { 207 pa = VM_PAGE_TO_PHYS(m); 208 pmap_enter(pmap_kernel(), va, pa | PMAP_NVC, 209 VM_PROT_READ|VM_PROT_WRITE, 210 VM_PROT_READ|VM_PROT_WRITE|PMAP_WIRED); 211 va += NBPG; 212 } 213 bzero(is->is_tsb, size); 214 215 #ifdef DEBUG 216 if (iommudebug & IDB_DVMA) 217 { 218 /* Probe the iommu */ 219 struct iommureg *regs = is->is_iommu; 220 221 printf("iommu regs at: cr=%lx tsb=%lx flush=%lx\n", ®s->iommu_cr, 222 ®s->iommu_tsb, ®s->iommu_flush); 223 printf("iommu cr=%qx tsb=%qx\n", regs->iommu_cr, regs->iommu_tsb); 224 printf("TSB base %p phys %qx\n", (void *)is->is_tsb, (u_int64_t)is->is_ptsb); 225 delay(1000000); /* 1 s */ 226 } 227 #endif 228 229 /* 230 * Initialize streaming buffer, if it is there. 231 */ 232 if (is->is_sb) 233 (void)pmap_extract(pmap_kernel(), (vaddr_t)&is->is_flush, 234 (paddr_t *)&is->is_flushpa); 235 236 /* 237 * now actually start up the IOMMU 238 */ 239 iommu_reset(is); 240 241 /* 242 * Now all the hardware's working we need to allocate a dvma map. 243 */ 244 printf("DVMA map: %x to %x\n", 245 (unsigned int)is->is_dvmabase, 246 (unsigned int)IOTSB_VEND); 247 is->is_dvmamap = extent_create(name, 248 is->is_dvmabase, IOTSB_VEND, 249 M_DEVBUF, 0, 0, EX_NOWAIT); 250 } 251 252 /* 253 * Streaming buffers don't exist on the UltraSPARC IIi; we should have 254 * detected that already and disabled them. If not, we will notice that 255 * they aren't there when the STRBUF_EN bit does not remain. 256 */ 257 void 258 iommu_reset(is) 259 struct iommu_state *is; 260 { 261 262 /* Need to do 64-bit stores */ 263 bus_space_write_8(is->is_bustag, &is->is_iommu->iommu_tsb, 0, is->is_ptsb); 264 /* Enable IOMMU in diagnostic mode */ 265 bus_space_write_8(is->is_bustag, &is->is_iommu->iommu_cr, 0, 266 is->is_cr|IOMMUCR_DE); 267 268 269 if (!is->is_sb) 270 return; 271 272 /* Enable diagnostics mode? */ 273 bus_space_write_8(is->is_bustag, &is->is_sb->strbuf_ctl, 0, STRBUF_EN); 274 275 /* No streaming buffers? Disable them */ 276 if (bus_space_read_8(is->is_bustag, 277 (bus_space_handle_t)(u_long)&is->is_sb->strbuf_ctl, 0) == 0) 278 is->is_sb = 0; 279 } 280 281 /* 282 * Here are the iommu control routines. 283 */ 284 void 285 iommu_enter(is, va, pa, flags) 286 struct iommu_state *is; 287 vaddr_t va; 288 int64_t pa; 289 int flags; 290 { 291 int64_t tte; 292 293 #ifdef DIAGNOSTIC 294 if (va < is->is_dvmabase) 295 panic("iommu_enter: va %#lx not in DVMA space", va); 296 #endif 297 298 tte = MAKEIOTTE(pa, !(flags&BUS_DMA_NOWRITE), !(flags&BUS_DMA_NOCACHE), 299 !(flags&BUS_DMA_COHERENT)); 300 301 /* Is the streamcache flush really needed? */ 302 if (is->is_sb) { 303 bus_space_write_8(is->is_bustag, &is->is_sb->strbuf_pgflush, 0, 304 va); 305 iommu_strbuf_flush(is); 306 } 307 DPRINTF(IDB_DVMA, ("Clearing TSB slot %d for va %p\n", 308 (int)IOTSBSLOT(va,is->is_tsbsize), va)); 309 is->is_tsb[IOTSBSLOT(va,is->is_tsbsize)] = tte; 310 bus_space_write_8(is->is_bustag, &is->is_iommu->iommu_flush, 311 0, va); 312 DPRINTF(IDB_DVMA, ("iommu_enter: va %lx pa %lx TSB[%lx]@%p=%lx\n", 313 va, (long)pa, IOTSBSLOT(va,is->is_tsbsize), 314 &is->is_tsb[IOTSBSLOT(va,is->is_tsbsize)], 315 (long)tte)); 316 } 317 318 /* 319 * iommu_remove: removes mappings created by iommu_enter 320 * 321 * Only demap from IOMMU if flag is set. 322 * 323 * XXX: this function needs better internal error checking. 324 */ 325 void 326 iommu_remove(is, va, len) 327 struct iommu_state *is; 328 vaddr_t va; 329 size_t len; 330 { 331 332 #ifdef DIAGNOSTIC 333 if (va < is->is_dvmabase) 334 panic("iommu_remove: va 0x%lx not in DVMA space", (long)va); 335 if ((long)(va + len) < (long)va) 336 panic("iommu_remove: va 0x%lx + len 0x%lx wraps", 337 (long) va, (long) len); 338 if (len & ~0xfffffff) 339 panic("iommu_remove: rediculous len 0x%lx", (long)len); 340 #endif 341 342 va = trunc_page(va); 343 DPRINTF(IDB_DVMA, ("iommu_remove: va %lx TSB[%lx]@%p\n", 344 va, IOTSBSLOT(va,is->is_tsbsize), 345 &is->is_tsb[IOTSBSLOT(va,is->is_tsbsize)])); 346 while (len > 0) { 347 DPRINTF(IDB_DVMA, ("iommu_remove: clearing TSB slot %d for va %p size %lx\n", 348 (int)IOTSBSLOT(va,is->is_tsbsize), va, (u_long)len)); 349 if (is->is_sb) { 350 DPRINTF(IDB_DVMA, ("iommu_remove: flushing va %p TSB[%lx]@%p=%lx, %lu bytes left\n", 351 (long)va, (long)IOTSBSLOT(va,is->is_tsbsize), 352 (long)&is->is_tsb[IOTSBSLOT(va,is->is_tsbsize)], 353 (long)(is->is_tsb[IOTSBSLOT(va,is->is_tsbsize)]), 354 (u_long)len)); 355 bus_space_write_8(is->is_bustag, 356 &is->is_sb->strbuf_pgflush, 0, va); 357 if (len <= NBPG) 358 iommu_strbuf_flush(is); 359 DPRINTF(IDB_DVMA, ("iommu_remove: flushed va %p TSB[%lx]@%p=%lx, %lu bytes left\n", 360 (long)va, (long)IOTSBSLOT(va,is->is_tsbsize), 361 (long)&is->is_tsb[IOTSBSLOT(va,is->is_tsbsize)], 362 (long)(is->is_tsb[IOTSBSLOT(va,is->is_tsbsize)]), 363 (u_long)len)); 364 } else 365 membar_sync(); /* XXX */ 366 367 if (len <= NBPG) 368 len = 0; 369 else 370 len -= NBPG; 371 372 is->is_tsb[IOTSBSLOT(va,is->is_tsbsize)] = 0; 373 bus_space_write_8(is->is_bustag, &is->is_iommu->iommu_flush, 0, va); 374 va += NBPG; 375 } 376 } 377 378 static int 379 iommu_strbuf_flush(is) 380 struct iommu_state *is; 381 { 382 struct timeval cur, flushtimeout; 383 384 #define BUMPTIME(t, usec) { \ 385 register volatile struct timeval *tp = (t); \ 386 register long us; \ 387 \ 388 tp->tv_usec = us = tp->tv_usec + (usec); \ 389 if (us >= 1000000) { \ 390 tp->tv_usec = us - 1000000; \ 391 tp->tv_sec++; \ 392 } \ 393 } 394 395 if (!is->is_sb) 396 return (0); 397 398 /* 399 * Streaming buffer flushes: 400 * 401 * 1 Tell strbuf to flush by storing va to strbuf_pgflush. If 402 * we're not on a cache line boundary (64-bits): 403 * 2 Store 0 in flag 404 * 3 Store pointer to flag in flushsync 405 * 4 wait till flushsync becomes 0x1 406 * 407 * If it takes more than .5 sec, something 408 * went wrong. 409 */ 410 411 is->is_flush = 0; 412 membar_sync(); 413 bus_space_write_8(is->is_bustag, &is->is_sb->strbuf_flushsync, 0, is->is_flushpa); 414 membar_sync(); 415 416 microtime(&flushtimeout); 417 cur = flushtimeout; 418 BUMPTIME(&flushtimeout, 500000); /* 1/2 sec */ 419 420 DPRINTF(IDB_DVMA, ("iommu_strbuf_flush: flush = %lx at va = %lx pa = %lx now=%lx:%lx until = %lx:%lx\n", 421 (long)is->is_flush, (long)&is->is_flush, 422 (long)is->is_flushpa, cur.tv_sec, cur.tv_usec, 423 flushtimeout.tv_sec, flushtimeout.tv_usec)); 424 /* Bypass non-coherent D$ */ 425 while (!ldxa(is->is_flushpa, ASI_PHYS_CACHED) && 426 ((cur.tv_sec <= flushtimeout.tv_sec) && 427 (cur.tv_usec <= flushtimeout.tv_usec))) 428 microtime(&cur); 429 430 #ifdef DIAGNOSTIC 431 if (!is->is_flush) { 432 printf("iommu_strbuf_flush: flush timeout %p at %p\n", (long)is->is_flush, 433 (long)is->is_flushpa); /* panic? */ 434 #ifdef DDB 435 Debugger(); 436 #endif 437 } 438 #endif 439 DPRINTF(IDB_DVMA, ("iommu_strbuf_flush: flushed\n")); 440 return (is->is_flush); 441 } 442 443 /* 444 * IOMMU DVMA operations, common to SBUS and PCI. 445 */ 446 int 447 iommu_dvmamap_load(t, is, map, buf, buflen, p, flags) 448 bus_dma_tag_t t; 449 struct iommu_state *is; 450 bus_dmamap_t map; 451 void *buf; 452 bus_size_t buflen; 453 struct proc *p; 454 int flags; 455 { 456 int s; 457 int err; 458 bus_size_t sgsize; 459 paddr_t curaddr; 460 u_long dvmaddr; 461 vaddr_t vaddr = (vaddr_t)buf; 462 pmap_t pmap; 463 464 if (map->dm_nsegs) { 465 /* Already in use?? */ 466 #ifdef DIAGNOSTIC 467 printf("iommu_dvmamap_load: map still in use\n"); 468 #endif 469 bus_dmamap_unload(t, map); 470 } 471 /* 472 * Make sure that on error condition we return "no valid mappings". 473 */ 474 map->dm_nsegs = 0; 475 476 if (buflen > map->_dm_size) { 477 DPRINTF(IDB_DVMA, 478 ("iommu_dvmamap_load(): error %d > %d -- " 479 "map size exceeded!\n", buflen, map->_dm_size)); 480 return (EINVAL); 481 } 482 483 #if 1 484 sgsize = round_page(buflen + ((int)vaddr & PGOFSET)); 485 #else 486 sgsize = buflen + ((int)vaddr & PGOFSET); 487 #endif 488 /* 489 * XXX Need to implement "don't dma across this boundry". 490 */ 491 s = splhigh(); 492 err = extent_alloc(is->is_dvmamap, sgsize, NBPG, 493 map->_dm_boundary, EX_NOWAIT, (u_long *)&dvmaddr); 494 splx(s); 495 496 #ifdef DEBUG 497 if (err || (dvmaddr == (bus_addr_t)-1)) 498 { 499 printf("iommu_dvmamap_load(): extent_alloc(%d, %x) failed!\n", 500 sgsize, flags); 501 Debugger(); 502 } 503 #endif 504 if (err != 0) 505 return (err); 506 507 if (dvmaddr == (bus_addr_t)-1) 508 return (ENOMEM); 509 510 /* 511 * We always use just one segment. 512 */ 513 map->dm_mapsize = buflen; 514 map->dm_nsegs = 1; 515 map->dm_segs[0].ds_addr = dvmaddr + (vaddr & PGOFSET); 516 map->dm_segs[0].ds_len = sgsize; 517 518 if (p != NULL) 519 pmap = p->p_vmspace->vm_map.pmap; 520 else 521 pmap = pmap_kernel(); 522 523 dvmaddr = trunc_page(map->dm_segs[0].ds_addr); 524 for (; buflen > 0; ) { 525 /* 526 * Get the physical address for this page. 527 */ 528 if (pmap_extract(pmap, (vaddr_t)vaddr, &curaddr) == FALSE) { 529 bus_dmamap_unload(t, map); 530 return (-1); 531 } 532 533 /* 534 * Compute the segment size, and adjust counts. 535 */ 536 sgsize = NBPG - ((u_long)vaddr & PGOFSET); 537 if (buflen < sgsize) 538 sgsize = buflen; 539 540 DPRINTF(IDB_DVMA, 541 ("iommu_dvmamap_load: map %p loading va %p dva %lx at pa %lx\n", 542 map, (void *)vaddr, (long)dvmaddr, (long)(curaddr&~(NBPG-1)))); 543 iommu_enter(is, trunc_page(dvmaddr), trunc_page(curaddr), 544 flags); 545 546 dvmaddr += PAGE_SIZE; 547 vaddr += sgsize; 548 buflen -= sgsize; 549 } 550 return (0); 551 } 552 553 554 void 555 iommu_dvmamap_unload(t, is, map) 556 bus_dma_tag_t t; 557 struct iommu_state *is; 558 bus_dmamap_t map; 559 { 560 vaddr_t addr; 561 size_t len; 562 int error, s; 563 bus_addr_t dvmaddr; 564 bus_size_t sgsize; 565 566 if (map->dm_nsegs != 1) 567 panic("iommu_dvmamap_unload: nsegs = %d", map->dm_nsegs); 568 569 addr = trunc_page(map->dm_segs[0].ds_addr); 570 len = map->dm_segs[0].ds_len; 571 572 DPRINTF(IDB_DVMA, 573 ("iommu_dvmamap_unload: map %p removing va %lx size %lx\n", 574 map, (long)addr, (long)len)); 575 iommu_remove(is, addr, len); 576 dvmaddr = (map->dm_segs[0].ds_addr & ~PGOFSET); 577 sgsize = map->dm_segs[0].ds_len; 578 579 /* Mark the mappings as invalid. */ 580 map->dm_mapsize = 0; 581 map->dm_nsegs = 0; 582 583 s = splhigh(); 584 error = extent_free(is->is_dvmamap, dvmaddr, sgsize, EX_NOWAIT); 585 splx(s); 586 if (error != 0) 587 printf("warning: %qd of DVMA space lost\n", (long long)sgsize); 588 cache_flush((caddr_t)(u_long)dvmaddr, (u_int)sgsize); 589 } 590 591 592 int 593 iommu_dvmamap_load_raw(t, is, map, segs, nsegs, size, flags) 594 bus_dma_tag_t t; 595 struct iommu_state *is; 596 bus_dmamap_t map; 597 bus_dma_segment_t *segs; 598 int nsegs; 599 bus_size_t size; 600 int flags; 601 { 602 vm_page_t m; 603 int s; 604 int err; 605 bus_size_t sgsize; 606 paddr_t pa; 607 u_long boundary; 608 u_long dvmaddr; 609 struct pglist *mlist; 610 int pagesz = PAGE_SIZE; 611 612 if (map->dm_nsegs) { 613 /* Already in use?? */ 614 #ifdef DIAGNOSTIC 615 printf("iommu_dvmamap_load_raw: map still in use\n"); 616 #endif 617 bus_dmamap_unload(t, map); 618 } 619 /* 620 * Make sure that on error condition we return "no valid mappings". 621 */ 622 map->dm_nsegs = 0; 623 #ifdef DIAGNOSTIC 624 /* XXX - unhelpful since we can't reset these in map_unload() */ 625 if (segs[0].ds_addr != 0) 626 panic("iommu_dvmamap_load_raw: segment already loaded: " 627 "addr %#llx, size %#llx", 628 (u_int64_t)segs[0].ds_addr, (u_int64_t)segs[0].ds_len); 629 if (segs[0].ds_len != size) 630 panic("iommu_dvmamap_load_raw: segment size changed: " 631 "ds_len %#llx size %#llx", segs[0].ds_len, size); 632 #endif 633 sgsize = round_page(size); 634 635 /* 636 * A boundary presented to bus_dmamem_alloc() takes precedence 637 * over boundary in the map. 638 */ 639 if ((boundary = segs[0]._ds_boundary) == 0) 640 boundary = map->_dm_boundary; 641 642 s = splhigh(); 643 err = extent_alloc(is->is_dvmamap, sgsize, NBPG, boundary, 644 (flags & BUS_DMA_NOWAIT) == 0 ? EX_WAITOK : EX_NOWAIT, 645 (u_long *)&dvmaddr); 646 splx(s); 647 648 if (err != 0) 649 return (err); 650 651 #ifdef DEBUG 652 if (dvmaddr == (bus_addr_t)-1) 653 { 654 printf("iommu_dvmamap_load_raw(): extent_alloc(%d, %x) failed!\n", 655 sgsize, flags); 656 Debugger(); 657 } 658 #endif 659 if (dvmaddr == (bus_addr_t)-1) 660 return (ENOMEM); 661 662 /* 663 * We always use just one segment. 664 */ 665 map->dm_mapsize = size; 666 map->dm_nsegs = 1; 667 map->dm_segs[0].ds_addr = dvmaddr; 668 map->dm_segs[0].ds_len = size; 669 670 mlist = segs[0]._ds_mlist; 671 for (m = TAILQ_FIRST(mlist); m != NULL; m = TAILQ_NEXT(m,pageq)) { 672 if (sgsize == 0) 673 panic("iommu_dmamap_load_raw: size botch"); 674 pa = VM_PAGE_TO_PHYS(m); 675 676 DPRINTF(IDB_DVMA, 677 ("iommu_dvmamap_load_raw: map %p loading va %lx at pa %lx\n", 678 map, (long)dvmaddr, (long)(pa))); 679 iommu_enter(is, dvmaddr, pa, flags); 680 681 dvmaddr += pagesz; 682 sgsize -= pagesz; 683 } 684 return (0); 685 } 686 687 void 688 iommu_dvmamap_sync(t, is, map, offset, len, ops) 689 bus_dma_tag_t t; 690 struct iommu_state *is; 691 bus_dmamap_t map; 692 bus_addr_t offset; 693 bus_size_t len; 694 int ops; 695 { 696 vaddr_t va = map->dm_segs[0].ds_addr + offset; 697 698 /* 699 * We only support one DMA segment; supporting more makes this code 700 * too unweildy. 701 */ 702 703 if (ops & BUS_DMASYNC_PREREAD) { 704 DPRINTF(IDB_DVMA, 705 ("iommu_dvmamap_sync: syncing va %p len %lu " 706 "BUS_DMASYNC_PREREAD\n", (long)va, (u_long)len)); 707 708 /* Nothing to do */; 709 } 710 if (ops & BUS_DMASYNC_POSTREAD) { 711 DPRINTF(IDB_DVMA, 712 ("iommu_dvmamap_sync: syncing va %p len %lu " 713 "BUS_DMASYNC_POSTREAD\n", (long)va, (u_long)len)); 714 /* if we have a streaming buffer, flush it here first */ 715 if (is->is_sb) 716 while (len > 0) { 717 DPRINTF(IDB_DVMA, 718 ("iommu_dvmamap_sync: flushing va %p, %lu " 719 "bytes left\n", (long)va, (u_long)len)); 720 bus_space_write_8(is->is_bustag, 721 &is->is_sb->strbuf_pgflush, 0, va); 722 if (len <= NBPG) { 723 iommu_strbuf_flush(is); 724 len = 0; 725 } else 726 len -= NBPG; 727 va += NBPG; 728 } 729 } 730 if (ops & BUS_DMASYNC_PREWRITE) { 731 DPRINTF(IDB_DVMA, 732 ("iommu_dvmamap_sync: syncing va %p len %lu " 733 "BUS_DMASYNC_PREWRITE\n", (long)va, (u_long)len)); 734 /* Nothing to do */; 735 } 736 if (ops & BUS_DMASYNC_POSTWRITE) { 737 DPRINTF(IDB_DVMA, 738 ("iommu_dvmamap_sync: syncing va %p len %lu " 739 "BUS_DMASYNC_POSTWRITE\n", (long)va, (u_long)len)); 740 /* Nothing to do */; 741 } 742 } 743 744 int 745 iommu_dvmamem_alloc(t, is, size, alignment, boundary, segs, nsegs, rsegs, flags) 746 bus_dma_tag_t t; 747 struct iommu_state *is; 748 bus_size_t size, alignment, boundary; 749 bus_dma_segment_t *segs; 750 int nsegs; 751 int *rsegs; 752 int flags; 753 { 754 755 DPRINTF(IDB_DVMA, ("iommu_dvmamem_alloc: sz %qx align %qx bound %qx " 756 "segp %p flags %d\n", size, alignment, boundary, segs, flags)); 757 return (bus_dmamem_alloc(t->_parent, size, alignment, boundary, 758 segs, nsegs, rsegs, flags)); 759 } 760 761 void 762 iommu_dvmamem_free(t, is, segs, nsegs) 763 bus_dma_tag_t t; 764 struct iommu_state *is; 765 bus_dma_segment_t *segs; 766 int nsegs; 767 { 768 769 DPRINTF(IDB_DVMA, ("iommu_dvmamem_free: segp %p nsegs %d\n", 770 segs, nsegs)); 771 bus_dmamem_free(t->_parent, segs, nsegs); 772 } 773 774 /* 775 * Map the DVMA mappings into the kernel pmap. 776 * Check the flags to see whether we're streaming or coherent. 777 */ 778 int 779 iommu_dvmamem_map(t, is, segs, nsegs, size, kvap, flags) 780 bus_dma_tag_t t; 781 struct iommu_state *is; 782 bus_dma_segment_t *segs; 783 int nsegs; 784 size_t size; 785 caddr_t *kvap; 786 int flags; 787 { 788 vm_page_t m; 789 vaddr_t va; 790 bus_addr_t addr; 791 struct pglist *mlist; 792 int cbit; 793 794 DPRINTF(IDB_DVMA, ("iommu_dvmamem_map: segp %p nsegs %d size %lx\n", 795 segs, nsegs, size)); 796 797 /* 798 * Allocate some space in the kernel map, and then map these pages 799 * into this space. 800 */ 801 size = round_page(size); 802 va = uvm_km_valloc(kernel_map, size); 803 if (va == 0) 804 return (ENOMEM); 805 806 *kvap = (caddr_t)va; 807 808 /* 809 * digest flags: 810 */ 811 cbit = 0; 812 if (flags & BUS_DMA_COHERENT) /* Disable vcache */ 813 cbit |= PMAP_NVC; 814 if (flags & BUS_DMA_NOCACHE) /* sideffects */ 815 cbit |= PMAP_NC; 816 817 /* 818 * Now take this and map it into the CPU. 819 */ 820 mlist = segs[0]._ds_mlist; 821 for (m = mlist->tqh_first; m != NULL; m = m->pageq.tqe_next) { 822 #ifdef DIAGNOSTIC 823 if (size == 0) 824 panic("iommu_dvmamem_map: size botch"); 825 #endif 826 addr = VM_PAGE_TO_PHYS(m); 827 DPRINTF(IDB_DVMA, ("iommu_dvmamem_map: " 828 "mapping va %lx at %qx\n", va, addr | cbit)); 829 pmap_enter(pmap_kernel(), va, addr | cbit, 830 VM_PROT_READ | VM_PROT_WRITE, PMAP_WIRED); 831 va += PAGE_SIZE; 832 size -= PAGE_SIZE; 833 } 834 835 return (0); 836 } 837 838 /* 839 * Unmap DVMA mappings from kernel 840 */ 841 void 842 iommu_dvmamem_unmap(t, is, kva, size) 843 bus_dma_tag_t t; 844 struct iommu_state *is; 845 caddr_t kva; 846 size_t size; 847 { 848 849 DPRINTF(IDB_DVMA, ("iommu_dvmamem_unmap: kvm %p size %lx\n", 850 kva, size)); 851 852 #ifdef DIAGNOSTIC 853 if ((u_long)kva & PGOFSET) 854 panic("iommu_dvmamem_unmap"); 855 #endif 856 857 size = round_page(size); 858 pmap_remove(pmap_kernel(), (vaddr_t)kva, size); 859 #if 0 860 /* 861 * XXX ? is this necessary? i think so and i think other 862 * implementations are missing it. 863 */ 864 uvm_km_free(kernel_map, (vaddr_t)kva, size); 865 #endif 866 } 867
Indexes created Tue Sep 23 07:09:52 GMT 2025