iommu.c revision 1.18
1 /* $NetBSD: iommu.c,v 1.18 2000/06/26 14:21:00 mrg Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000 Matthew R. Green 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 23 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 24 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 25 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 /*- 32 * Copyright (c) 1998 The NetBSD Foundation, Inc. 33 * All rights reserved. 34 * 35 * This code is derived from software contributed to The NetBSD Foundation 36 * by Paul Kranenburg. 37 * 38 * Redistribution and use in source and binary forms, with or without 39 * modification, are permitted provided that the following conditions 40 * are met: 41 * 1. Redistributions of source code must retain the above copyright 42 * notice, this list of conditions and the following disclaimer. 43 * 2. Redistributions in binary form must reproduce the above copyright 44 * notice, this list of conditions and the following disclaimer in the 45 * documentation and/or other materials provided with the distribution. 46 * 3. All advertising materials mentioning features or use of this software 47 * must display the following acknowledgement: 48 * This product includes software developed by the NetBSD 49 * Foundation, Inc. and its contributors. 50 * 4. Neither the name of The NetBSD Foundation nor the names of its 51 * contributors may be used to endorse or promote products derived 52 * from this software without specific prior written permission. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 55 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 56 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 57 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 58 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 59 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 60 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 61 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 62 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 63 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 64 * POSSIBILITY OF SUCH DAMAGE. 65 */ 66 67 /* 68 * Copyright (c) 1992, 1993 69 * The Regents of the University of California. All rights reserved. 70 * 71 * This software was developed by the Computer Systems Engineering group 72 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 73 * contributed to Berkeley. 74 * 75 * All advertising materials mentioning features or use of this software 76 * must display the following acknowledgement: 77 * This product includes software developed by the University of 78 * California, Lawrence Berkeley Laboratory. 79 * 80 * Redistribution and use in source and binary forms, with or without 81 * modification, are permitted provided that the following conditions 82 * are met: 83 * 1. Redistributions of source code must retain the above copyright 84 * notice, this list of conditions and the following disclaimer. 85 * 2. Redistributions in binary form must reproduce the above copyright 86 * notice, this list of conditions and the following disclaimer in the 87 * documentation and/or other materials provided with the distribution. 88 * 3. All advertising materials mentioning features or use of this software 89 * must display the following acknowledgement: 90 * This product includes software developed by the University of 91 * California, Berkeley and its contributors. 92 * 4. Neither the name of the University nor the names of its contributors 93 * may be used to endorse or promote products derived from this software 94 * without specific prior written permission. 95 * 96 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 97 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 98 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 99 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 100 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 101 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 102 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 103 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 104 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 105 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 106 * SUCH DAMAGE. 107 * 108 * from: NetBSD: sbus.c,v 1.13 1999/05/23 07:24:02 mrg Exp 109 * from: @(#)sbus.c 8.1 (Berkeley) 6/11/93 110 */ 111 112 /* 113 * UltraSPARC IOMMU support; used by both the sbus and pci code. 114 */ 115 #include "opt_ddb.h" 116 117 #include <sys/param.h> 118 #include <sys/extent.h> 119 #include <sys/malloc.h> 120 #include <sys/systm.h> 121 #include <sys/device.h> 122 #include <vm/vm.h> 123 124 #include <uvm/uvm_extern.h> 125 126 #include <machine/bus.h> 127 #include <sparc64/sparc64/cache.h> 128 #include <sparc64/dev/iommureg.h> 129 #include <sparc64/dev/iommuvar.h> 130 131 #include <machine/autoconf.h> 132 #include <machine/cpu.h> 133 134 #ifdef DEBUG 135 #define IDB_DVMA 0x1 136 int iommudebug = 0x0; 137 #define DPRINTF(l, s) do { if (iommudebug & l) printf s; } while (0) 138 #else 139 #define DPRINTF(l, s) 140 #endif 141 142 static int iommu_strbuf_flush __P((struct iommu_state *)); 143 144 /* 145 * initialise the UltraSPARC IOMMU (SBUS or PCI): 146 * - allocate and setup the iotsb. 147 * - enable the IOMMU 148 * - initialise the streaming buffers (if they exist) 149 * - create a private DVMA map. 150 */ 151 void 152 iommu_init(name, is, tsbsize) 153 char *name; 154 struct iommu_state *is; 155 int tsbsize; 156 { 157 psize_t size; 158 vaddr_t va; 159 paddr_t pa; 160 vm_page_t m; 161 struct pglist mlist; 162 163 /* 164 * Setup the iommu. 165 * 166 * The sun4u iommu is part of the SBUS or PCI controller so we 167 * will deal with it here.. 168 * 169 * The IOMMU address space always ends at 0xffffe000, but the starting 170 * address depends on the size of the map. The map size is 1024 * 2 ^ 171 * is->is_tsbsize entries, where each entry is 8 bytes. The start of 172 * the map can be calculated by (0xffffe000 << (8 + is->is_tsbsize)). 173 * 174 * Note: the stupid IOMMU ignores the high bits of an address, so a 175 * NULL DMA pointer will be translated by the first page of the IOTSB. 176 * To trap bugs we'll skip the first entry in the IOTSB. 177 */ 178 is->is_cr = (tsbsize << 16) | IOMMUCR_EN; 179 is->is_tsbsize = tsbsize; 180 is->is_dvmabase = IOTSB_VSTART(is->is_tsbsize) + NBPG; 181 182 /* 183 * Allocate memory for I/O pagetables. They need to be physically 184 * contiguous. 185 */ 186 187 size = NBPG<<(is->is_tsbsize); 188 TAILQ_INIT(&mlist); 189 if (uvm_pglistalloc((psize_t)size, (paddr_t)0, (paddr_t)-1, 190 (paddr_t)NBPG, (paddr_t)0, &mlist, 1, 0) != 0) 191 panic("iommu_init: no memory"); 192 193 va = uvm_km_valloc(kernel_map, size); 194 if (va == 0) 195 panic("iommu_init: no memory"); 196 is->is_tsb = (int64_t *)va; 197 198 m = TAILQ_FIRST(&mlist); 199 is->is_ptsb = VM_PAGE_TO_PHYS(m); 200 201 /* Map the pages */ 202 for (; m != NULL; m = TAILQ_NEXT(m,pageq)) { 203 pa = VM_PAGE_TO_PHYS(m); 204 pmap_enter(pmap_kernel(), va, pa | PMAP_NVC, 205 VM_PROT_READ|VM_PROT_WRITE, 206 VM_PROT_READ|VM_PROT_WRITE|PMAP_WIRED); 207 va += NBPG; 208 } 209 bzero(is->is_tsb, size); 210 211 #ifdef DEBUG 212 if (iommudebug & IDB_DVMA) 213 { 214 /* Probe the iommu */ 215 struct iommureg *regs = is->is_iommu; 216 217 printf("iommu regs at: cr=%lx tsb=%lx flush=%lx\n", ®s->iommu_cr, 218 ®s->iommu_tsb, ®s->iommu_flush); 219 printf("iommu cr=%qx tsb=%qx\n", regs->iommu_cr, regs->iommu_tsb); 220 printf("TSB base %p phys %qx\n", (void *)is->is_tsb, (u_int64_t)is->is_ptsb); 221 delay(1000000); /* 1 s */ 222 } 223 #endif 224 225 /* 226 * Initialize streaming buffer, if it is there. 227 */ 228 if (is->is_sb) 229 (void)pmap_extract(pmap_kernel(), (vaddr_t)&is->is_flush, 230 (paddr_t *)&is->is_flushpa); 231 232 /* 233 * now actually start up the IOMMU 234 */ 235 iommu_reset(is); 236 237 /* 238 * Now all the hardware's working we need to allocate a dvma map. 239 */ 240 printf("DVMA map: %x to %x\n", 241 (unsigned int)is->is_dvmabase, 242 (unsigned int)IOTSB_VEND); 243 is->is_dvmamap = extent_create(name, 244 is->is_dvmabase, IOTSB_VEND, 245 M_DEVBUF, 0, 0, EX_NOWAIT); 246 } 247 248 /* 249 * Streaming buffers don't exist on the UltraSPARC IIi; we should have 250 * detected that already and disabled them. If not, we will notice that 251 * they aren't there when the STRBUF_EN bit does not remain. 252 */ 253 void 254 iommu_reset(is) 255 struct iommu_state *is; 256 { 257 258 /* Need to do 64-bit stores */ 259 bus_space_write_8(is->is_bustag, &is->is_iommu->iommu_tsb, 0, is->is_ptsb); 260 /* Enable IOMMU in diagnostic mode */ 261 bus_space_write_8(is->is_bustag, &is->is_iommu->iommu_cr, 0, 262 is->is_cr|IOMMUCR_DE); 263 264 265 if (!is->is_sb) 266 return; 267 268 /* Enable diagnostics mode? */ 269 bus_space_write_8(is->is_bustag, &is->is_sb->strbuf_ctl, 0, STRBUF_EN); 270 271 /* No streaming buffers? Disable them */ 272 if (bus_space_read_8(is->is_bustag, 273 (bus_space_handle_t)(u_long)&is->is_sb->strbuf_ctl, 0) == 0) 274 is->is_sb = 0; 275 } 276 277 /* 278 * Here are the iommu control routines. 279 */ 280 void 281 iommu_enter(is, va, pa, flags) 282 struct iommu_state *is; 283 vaddr_t va; 284 int64_t pa; 285 int flags; 286 { 287 int64_t tte; 288 289 #ifdef DIAGNOSTIC 290 if (va < is->is_dvmabase) 291 panic("iommu_enter: va %#lx not in DVMA space", va); 292 #endif 293 294 tte = MAKEIOTTE(pa, !(flags&BUS_DMA_NOWRITE), !(flags&BUS_DMA_NOCACHE), 295 !(flags&BUS_DMA_COHERENT)); 296 297 /* Is the streamcache flush really needed? */ 298 if (is->is_sb) { 299 bus_space_write_8(is->is_bustag, &is->is_sb->strbuf_pgflush, 0, 300 va); 301 iommu_strbuf_flush(is); 302 } 303 DPRINTF(IDB_DVMA, ("Clearing TSB slot %d for va %p\n", 304 (int)IOTSBSLOT(va,is->is_tsbsize), va)); 305 is->is_tsb[IOTSBSLOT(va,is->is_tsbsize)] = tte; 306 bus_space_write_8(is->is_bustag, &is->is_iommu->iommu_flush, 307 0, va); 308 DPRINTF(IDB_DVMA, ("iommu_enter: va %lx pa %lx TSB[%lx]@%p=%lx\n", 309 va, (long)pa, IOTSBSLOT(va,is->is_tsbsize), 310 &is->is_tsb[IOTSBSLOT(va,is->is_tsbsize)], 311 (long)tte)); 312 } 313 314 /* 315 * iommu_remove: removes mappings created by iommu_enter 316 * 317 * Only demap from IOMMU if flag is set. 318 * 319 * XXX: this function needs better internal error checking. 320 */ 321 void 322 iommu_remove(is, va, len) 323 struct iommu_state *is; 324 vaddr_t va; 325 size_t len; 326 { 327 328 #ifdef DIAGNOSTIC 329 if (va < is->is_dvmabase) 330 panic("iommu_remove: va 0x%lx not in DVMA space", (long)va); 331 if ((long)(va + len) < (long)va) 332 panic("iommu_remove: va 0x%lx + len 0x%lx wraps", 333 (long) va, (long) len); 334 if (len & ~0xfffffff) 335 panic("iommu_remove: rediculous len 0x%lx", (long)len); 336 #endif 337 338 va = trunc_page(va); 339 DPRINTF(IDB_DVMA, ("iommu_remove: va %lx TSB[%lx]@%p\n", 340 va, IOTSBSLOT(va,is->is_tsbsize), 341 &is->is_tsb[IOTSBSLOT(va,is->is_tsbsize)])); 342 while (len > 0) { 343 DPRINTF(IDB_DVMA, ("iommu_remove: clearing TSB slot %d for va %p size %lx\n", 344 (int)IOTSBSLOT(va,is->is_tsbsize), va, (u_long)len)); 345 if (is->is_sb) { 346 DPRINTF(IDB_DVMA, ("iommu_remove: flushing va %p TSB[%lx]@%p=%lx, %lu bytes left\n", 347 (long)va, (long)IOTSBSLOT(va,is->is_tsbsize), 348 (long)&is->is_tsb[IOTSBSLOT(va,is->is_tsbsize)], 349 (long)(is->is_tsb[IOTSBSLOT(va,is->is_tsbsize)]), 350 (u_long)len)); 351 bus_space_write_8(is->is_bustag, 352 &is->is_sb->strbuf_pgflush, 0, va); 353 if (len <= NBPG) 354 iommu_strbuf_flush(is); 355 DPRINTF(IDB_DVMA, ("iommu_remove: flushed va %p TSB[%lx]@%p=%lx, %lu bytes left\n", 356 (long)va, (long)IOTSBSLOT(va,is->is_tsbsize), 357 (long)&is->is_tsb[IOTSBSLOT(va,is->is_tsbsize)], 358 (long)(is->is_tsb[IOTSBSLOT(va,is->is_tsbsize)]), 359 (u_long)len)); 360 } else 361 membar_sync(); /* XXX */ 362 363 if (len <= NBPG) 364 len = 0; 365 else 366 len -= NBPG; 367 368 is->is_tsb[IOTSBSLOT(va,is->is_tsbsize)] = 0; 369 bus_space_write_8(is->is_bustag, &is->is_iommu->iommu_flush, 0, va); 370 va += NBPG; 371 } 372 } 373 374 static int 375 iommu_strbuf_flush(is) 376 struct iommu_state *is; 377 { 378 struct timeval cur, flushtimeout; 379 380 #define BUMPTIME(t, usec) { \ 381 register volatile struct timeval *tp = (t); \ 382 register long us; \ 383 \ 384 tp->tv_usec = us = tp->tv_usec + (usec); \ 385 if (us >= 1000000) { \ 386 tp->tv_usec = us - 1000000; \ 387 tp->tv_sec++; \ 388 } \ 389 } 390 391 if (!is->is_sb) 392 return (0); 393 394 /* 395 * Streaming buffer flushes: 396 * 397 * 1 Tell strbuf to flush by storing va to strbuf_pgflush. If 398 * we're not on a cache line boundary (64-bits): 399 * 2 Store 0 in flag 400 * 3 Store pointer to flag in flushsync 401 * 4 wait till flushsync becomes 0x1 402 * 403 * If it takes more than .5 sec, something 404 * went wrong. 405 */ 406 407 is->is_flush = 0; 408 membar_sync(); 409 bus_space_write_8(is->is_bustag, &is->is_sb->strbuf_flushsync, 0, is->is_flushpa); 410 membar_sync(); 411 412 microtime(&flushtimeout); 413 cur = flushtimeout; 414 BUMPTIME(&flushtimeout, 500000); /* 1/2 sec */ 415 416 DPRINTF(IDB_DVMA, ("iommu_strbuf_flush: flush = %lx at va = %lx pa = %lx now=%lx:%lx until = %lx:%lx\n", 417 (long)is->is_flush, (long)&is->is_flush, 418 (long)is->is_flushpa, cur.tv_sec, cur.tv_usec, 419 flushtimeout.tv_sec, flushtimeout.tv_usec)); 420 /* Bypass non-coherent D$ */ 421 while (!ldxa(is->is_flushpa, ASI_PHYS_CACHED) && 422 ((cur.tv_sec <= flushtimeout.tv_sec) && 423 (cur.tv_usec <= flushtimeout.tv_usec))) 424 microtime(&cur); 425 426 #ifdef DIAGNOSTIC 427 if (!is->is_flush) { 428 printf("iommu_strbuf_flush: flush timeout %p at %p\n", (long)is->is_flush, 429 (long)is->is_flushpa); /* panic? */ 430 #ifdef DDB 431 Debugger(); 432 #endif 433 } 434 #endif 435 DPRINTF(IDB_DVMA, ("iommu_strbuf_flush: flushed\n")); 436 return (is->is_flush); 437 } 438 439 /* 440 * IOMMU DVMA operations, common to SBUS and PCI. 441 */ 442 int 443 iommu_dvmamap_load(t, is, map, buf, buflen, p, flags) 444 bus_dma_tag_t t; 445 struct iommu_state *is; 446 bus_dmamap_t map; 447 void *buf; 448 bus_size_t buflen; 449 struct proc *p; 450 int flags; 451 { 452 int s; 453 int err; 454 bus_size_t sgsize; 455 paddr_t curaddr; 456 u_long dvmaddr; 457 vaddr_t vaddr = (vaddr_t)buf; 458 pmap_t pmap; 459 460 if (map->dm_nsegs) { 461 /* Already in use?? */ 462 #ifdef DIAGNOSTIC 463 printf("iommu_dvmamap_load: map still in use\n"); 464 #endif 465 bus_dmamap_unload(t, map); 466 } 467 /* 468 * Make sure that on error condition we return "no valid mappings". 469 */ 470 map->dm_nsegs = 0; 471 472 if (buflen > map->_dm_size) { 473 DPRINTF(IDB_DVMA, 474 ("iommu_dvmamap_load(): error %d > %d -- " 475 "map size exceeded!\n", buflen, map->_dm_size)); 476 return (EINVAL); 477 } 478 479 #if 1 480 sgsize = round_page(buflen + ((int)vaddr & PGOFSET)); 481 #else 482 sgsize = buflen + ((int)vaddr & PGOFSET); 483 #endif 484 /* 485 * XXX Need to implement "don't dma across this boundry". 486 */ 487 s = splhigh(); 488 err = extent_alloc(is->is_dvmamap, sgsize, NBPG, 489 map->_dm_boundary, EX_NOWAIT, (u_long *)&dvmaddr); 490 splx(s); 491 492 #ifdef DEBUG 493 if (err || (dvmaddr == (bus_addr_t)-1)) 494 { 495 printf("iommu_dvmamap_load(): extent_alloc(%d, %x) failed!\n", 496 sgsize, flags); 497 Debugger(); 498 } 499 #endif 500 if (err != 0) 501 return (err); 502 503 if (dvmaddr == (bus_addr_t)-1) 504 return (ENOMEM); 505 506 /* 507 * We always use just one segment. 508 */ 509 map->dm_mapsize = buflen; 510 map->dm_nsegs = 1; 511 map->dm_segs[0].ds_addr = dvmaddr + (vaddr & PGOFSET); 512 map->dm_segs[0].ds_len = buflen; 513 514 if (p != NULL) 515 pmap = p->p_vmspace->vm_map.pmap; 516 else 517 pmap = pmap_kernel(); 518 519 dvmaddr = trunc_page(map->dm_segs[0].ds_addr); 520 for (; buflen > 0; ) { 521 /* 522 * Get the physical address for this page. 523 */ 524 if (pmap_extract(pmap, (vaddr_t)vaddr, &curaddr) == FALSE) { 525 bus_dmamap_unload(t, map); 526 return (-1); 527 } 528 529 /* 530 * Compute the segment size, and adjust counts. 531 */ 532 sgsize = NBPG - ((u_long)vaddr & PGOFSET); 533 if (buflen < sgsize) 534 sgsize = buflen; 535 536 DPRINTF(IDB_DVMA, 537 ("iommu_dvmamap_load: map %p loading va %p dva %lx at pa %lx\n", 538 map, (void *)vaddr, (long)dvmaddr, (long)(curaddr&~(NBPG-1)))); 539 iommu_enter(is, trunc_page(dvmaddr), trunc_page(curaddr), 540 flags); 541 542 dvmaddr += PAGE_SIZE; 543 vaddr += sgsize; 544 buflen -= sgsize; 545 } 546 return (0); 547 } 548 549 550 void 551 iommu_dvmamap_unload(t, is, map) 552 bus_dma_tag_t t; 553 struct iommu_state *is; 554 bus_dmamap_t map; 555 { 556 vaddr_t addr; 557 size_t len; 558 int error, s; 559 bus_addr_t dvmaddr; 560 bus_size_t sgsize; 561 562 if (map->dm_nsegs != 1) 563 panic("iommu_dvmamap_unload: nsegs = %d", map->dm_nsegs); 564 565 addr = trunc_page(map->dm_segs[0].ds_addr); 566 len = map->dm_segs[0].ds_len; 567 568 DPRINTF(IDB_DVMA, 569 ("iommu_dvmamap_unload: map %p removing va %lx size %lx\n", 570 map, (long)addr, (long)len)); 571 iommu_remove(is, addr, len); 572 dvmaddr = (map->dm_segs[0].ds_addr & ~PGOFSET); 573 sgsize = round_page(map->dm_segs[0].ds_len + 574 ((int)map->dm_segs[0].ds_addr & PGOFSET)); 575 576 /* Mark the mappings as invalid. */ 577 map->dm_mapsize = 0; 578 map->dm_nsegs = 0; 579 580 s = splhigh(); 581 error = extent_free(is->is_dvmamap, dvmaddr, sgsize, EX_NOWAIT); 582 splx(s); 583 if (error != 0) 584 printf("warning: %qd of DVMA space lost\n", (long long)sgsize); 585 cache_flush((caddr_t)(u_long)dvmaddr, (u_int)sgsize); 586 } 587 588 589 int 590 iommu_dvmamap_load_raw(t, is, map, segs, nsegs, size, flags) 591 bus_dma_tag_t t; 592 struct iommu_state *is; 593 bus_dmamap_t map; 594 bus_dma_segment_t *segs; 595 int nsegs; 596 bus_size_t size; 597 int flags; 598 { 599 vm_page_t m; 600 int s; 601 int err; 602 bus_size_t sgsize; 603 paddr_t pa; 604 u_long boundary; 605 u_long dvmaddr; 606 struct pglist *mlist; 607 int pagesz = PAGE_SIZE; 608 609 if (map->dm_nsegs) { 610 /* Already in use?? */ 611 #ifdef DIAGNOSTIC 612 printf("iommu_dvmamap_load_raw: map still in use\n"); 613 #endif 614 bus_dmamap_unload(t, map); 615 } 616 /* 617 * Make sure that on error condition we return "no valid mappings". 618 */ 619 map->dm_nsegs = 0; 620 #ifdef DIAGNOSTIC 621 /* XXX - unhelpful since we can't reset these in map_unload() */ 622 if (segs[0].ds_addr != 0) 623 panic("iommu_dvmamap_load_raw: segment already loaded: " 624 "addr %#llx, size %#llx", 625 (u_int64_t)segs[0].ds_addr, (u_int64_t)segs[0].ds_len); 626 if (segs[0].ds_len != size) 627 panic("iommu_dvmamap_load_raw: segment size changed: " 628 "ds_len %#llx size %#llx", segs[0].ds_len, size); 629 #endif 630 sgsize = round_page(size); 631 632 /* 633 * A boundary presented to bus_dmamem_alloc() takes precedence 634 * over boundary in the map. 635 */ 636 if ((boundary = segs[0]._ds_boundary) == 0) 637 boundary = map->_dm_boundary; 638 639 s = splhigh(); 640 err = extent_alloc(is->is_dvmamap, sgsize, NBPG, boundary, 641 (flags & BUS_DMA_NOWAIT) == 0 ? EX_WAITOK : EX_NOWAIT, 642 (u_long *)&dvmaddr); 643 splx(s); 644 645 if (err != 0) 646 return (err); 647 648 #ifdef DEBUG 649 if (dvmaddr == (bus_addr_t)-1) 650 { 651 printf("iommu_dvmamap_load_raw(): extent_alloc(%d, %x) failed!\n", 652 sgsize, flags); 653 Debugger(); 654 } 655 #endif 656 if (dvmaddr == (bus_addr_t)-1) 657 return (ENOMEM); 658 659 /* 660 * We always use just one segment. 661 */ 662 map->dm_mapsize = size; 663 map->dm_nsegs = 1; 664 map->dm_segs[0].ds_addr = dvmaddr; 665 map->dm_segs[0].ds_len = size; 666 667 mlist = segs[0]._ds_mlist; 668 for (m = TAILQ_FIRST(mlist); m != NULL; m = TAILQ_NEXT(m,pageq)) { 669 if (sgsize == 0) 670 panic("iommu_dmamap_load_raw: size botch"); 671 pa = VM_PAGE_TO_PHYS(m); 672 673 DPRINTF(IDB_DVMA, 674 ("iommu_dvmamap_load_raw: map %p loading va %lx at pa %lx\n", 675 map, (long)dvmaddr, (long)(pa))); 676 iommu_enter(is, dvmaddr, pa, flags); 677 678 dvmaddr += pagesz; 679 sgsize -= pagesz; 680 } 681 return (0); 682 } 683 684 void 685 iommu_dvmamap_sync(t, is, map, offset, len, ops) 686 bus_dma_tag_t t; 687 struct iommu_state *is; 688 bus_dmamap_t map; 689 bus_addr_t offset; 690 bus_size_t len; 691 int ops; 692 { 693 vaddr_t va = map->dm_segs[0].ds_addr + offset; 694 695 /* 696 * We only support one DMA segment; supporting more makes this code 697 * too unweildy. 698 */ 699 700 if (ops & BUS_DMASYNC_PREREAD) { 701 DPRINTF(IDB_DVMA, 702 ("iommu_dvmamap_sync: syncing va %p len %lu " 703 "BUS_DMASYNC_PREREAD\n", (long)va, (u_long)len)); 704 705 /* Nothing to do */; 706 } 707 if (ops & BUS_DMASYNC_POSTREAD) { 708 DPRINTF(IDB_DVMA, 709 ("iommu_dvmamap_sync: syncing va %p len %lu " 710 "BUS_DMASYNC_POSTREAD\n", (long)va, (u_long)len)); 711 /* if we have a streaming buffer, flush it here first */ 712 if (is->is_sb) 713 while (len > 0) { 714 DPRINTF(IDB_DVMA, 715 ("iommu_dvmamap_sync: flushing va %p, %lu " 716 "bytes left\n", (long)va, (u_long)len)); 717 bus_space_write_8(is->is_bustag, 718 &is->is_sb->strbuf_pgflush, 0, va); 719 if (len <= NBPG) { 720 iommu_strbuf_flush(is); 721 len = 0; 722 } else 723 len -= NBPG; 724 va += NBPG; 725 } 726 } 727 if (ops & BUS_DMASYNC_PREWRITE) { 728 DPRINTF(IDB_DVMA, 729 ("iommu_dvmamap_sync: syncing va %p len %lu " 730 "BUS_DMASYNC_PREWRITE\n", (long)va, (u_long)len)); 731 /* Nothing to do */; 732 } 733 if (ops & BUS_DMASYNC_POSTWRITE) { 734 DPRINTF(IDB_DVMA, 735 ("iommu_dvmamap_sync: syncing va %p len %lu " 736 "BUS_DMASYNC_POSTWRITE\n", (long)va, (u_long)len)); 737 /* Nothing to do */; 738 } 739 } 740 741 int 742 iommu_dvmamem_alloc(t, is, size, alignment, boundary, segs, nsegs, rsegs, flags) 743 bus_dma_tag_t t; 744 struct iommu_state *is; 745 bus_size_t size, alignment, boundary; 746 bus_dma_segment_t *segs; 747 int nsegs; 748 int *rsegs; 749 int flags; 750 { 751 752 DPRINTF(IDB_DVMA, ("iommu_dvmamem_alloc: sz %qx align %qx bound %qx " 753 "segp %p flags %d\n", size, alignment, boundary, segs, flags)); 754 return (bus_dmamem_alloc(t->_parent, size, alignment, boundary, 755 segs, nsegs, rsegs, flags)); 756 } 757 758 void 759 iommu_dvmamem_free(t, is, segs, nsegs) 760 bus_dma_tag_t t; 761 struct iommu_state *is; 762 bus_dma_segment_t *segs; 763 int nsegs; 764 { 765 766 DPRINTF(IDB_DVMA, ("iommu_dvmamem_free: segp %p nsegs %d\n", 767 segs, nsegs)); 768 bus_dmamem_free(t->_parent, segs, nsegs); 769 } 770 771 /* 772 * Map the DVMA mappings into the kernel pmap. 773 * Check the flags to see whether we're streaming or coherent. 774 */ 775 int 776 iommu_dvmamem_map(t, is, segs, nsegs, size, kvap, flags) 777 bus_dma_tag_t t; 778 struct iommu_state *is; 779 bus_dma_segment_t *segs; 780 int nsegs; 781 size_t size; 782 caddr_t *kvap; 783 int flags; 784 { 785 vm_page_t m; 786 vaddr_t va; 787 bus_addr_t addr; 788 struct pglist *mlist; 789 int cbit; 790 791 DPRINTF(IDB_DVMA, ("iommu_dvmamem_map: segp %p nsegs %d size %lx\n", 792 segs, nsegs, size)); 793 794 /* 795 * Allocate some space in the kernel map, and then map these pages 796 * into this space. 797 */ 798 size = round_page(size); 799 va = uvm_km_valloc(kernel_map, size); 800 if (va == 0) 801 return (ENOMEM); 802 803 *kvap = (caddr_t)va; 804 805 /* 806 * digest flags: 807 */ 808 cbit = 0; 809 if (flags & BUS_DMA_COHERENT) /* Disable vcache */ 810 cbit |= PMAP_NVC; 811 if (flags & BUS_DMA_NOCACHE) /* sideffects */ 812 cbit |= PMAP_NC; 813 814 /* 815 * Now take this and map it into the CPU. 816 */ 817 mlist = segs[0]._ds_mlist; 818 for (m = mlist->tqh_first; m != NULL; m = m->pageq.tqe_next) { 819 #ifdef DIAGNOSTIC 820 if (size == 0) 821 panic("iommu_dvmamem_map: size botch"); 822 #endif 823 addr = VM_PAGE_TO_PHYS(m); 824 DPRINTF(IDB_DVMA, ("iommu_dvmamem_map: " 825 "mapping va %lx at %qx\n", va, addr | cbit)); 826 pmap_enter(pmap_kernel(), va, addr | cbit, 827 VM_PROT_READ | VM_PROT_WRITE, PMAP_WIRED); 828 va += PAGE_SIZE; 829 size -= PAGE_SIZE; 830 } 831 832 return (0); 833 } 834 835 /* 836 * Unmap DVMA mappings from kernel 837 */ 838 void 839 iommu_dvmamem_unmap(t, is, kva, size) 840 bus_dma_tag_t t; 841 struct iommu_state *is; 842 caddr_t kva; 843 size_t size; 844 { 845 846 DPRINTF(IDB_DVMA, ("iommu_dvmamem_unmap: kvm %p size %lx\n", 847 kva, size)); 848 849 #ifdef DIAGNOSTIC 850 if ((u_long)kva & PGOFSET) 851 panic("iommu_dvmamem_unmap"); 852 #endif 853 854 size = round_page(size); 855 pmap_remove(pmap_kernel(), (vaddr_t)kva, size); 856 #if 0 857 /* 858 * XXX ? is this necessary? i think so and i think other 859 * implementations are missing it. 860 */ 861 uvm_km_free(kernel_map, (vaddr_t)kva, size); 862 #endif 863 } 864
Indexes created Thu Sep 25 16:09:42 GMT 2025