iommu.c revision 1.20
1 /* $NetBSD: iommu.c,v 1.20 2000/07/02 14:00:38 mrg Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000 Matthew R. Green 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 23 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 24 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 25 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 /*- 32 * Copyright (c) 1998 The NetBSD Foundation, Inc. 33 * All rights reserved. 34 * 35 * This code is derived from software contributed to The NetBSD Foundation 36 * by Paul Kranenburg. 37 * 38 * Redistribution and use in source and binary forms, with or without 39 * modification, are permitted provided that the following conditions 40 * are met: 41 * 1. Redistributions of source code must retain the above copyright 42 * notice, this list of conditions and the following disclaimer. 43 * 2. Redistributions in binary form must reproduce the above copyright 44 * notice, this list of conditions and the following disclaimer in the 45 * documentation and/or other materials provided with the distribution. 46 * 3. All advertising materials mentioning features or use of this software 47 * must display the following acknowledgement: 48 * This product includes software developed by the NetBSD 49 * Foundation, Inc. and its contributors. 50 * 4. Neither the name of The NetBSD Foundation nor the names of its 51 * contributors may be used to endorse or promote products derived 52 * from this software without specific prior written permission. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 55 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 56 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 57 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 58 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 59 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 60 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 61 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 62 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 63 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 64 * POSSIBILITY OF SUCH DAMAGE. 65 */ 66 67 /* 68 * Copyright (c) 1992, 1993 69 * The Regents of the University of California. All rights reserved. 70 * 71 * This software was developed by the Computer Systems Engineering group 72 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 73 * contributed to Berkeley. 74 * 75 * All advertising materials mentioning features or use of this software 76 * must display the following acknowledgement: 77 * This product includes software developed by the University of 78 * California, Lawrence Berkeley Laboratory. 79 * 80 * Redistribution and use in source and binary forms, with or without 81 * modification, are permitted provided that the following conditions 82 * are met: 83 * 1. Redistributions of source code must retain the above copyright 84 * notice, this list of conditions and the following disclaimer. 85 * 2. Redistributions in binary form must reproduce the above copyright 86 * notice, this list of conditions and the following disclaimer in the 87 * documentation and/or other materials provided with the distribution. 88 * 3. All advertising materials mentioning features or use of this software 89 * must display the following acknowledgement: 90 * This product includes software developed by the University of 91 * California, Berkeley and its contributors. 92 * 4. Neither the name of the University nor the names of its contributors 93 * may be used to endorse or promote products derived from this software 94 * without specific prior written permission. 95 * 96 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 97 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 98 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 99 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 100 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 101 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 102 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 103 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 104 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 105 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 106 * SUCH DAMAGE. 107 * 108 * from: NetBSD: sbus.c,v 1.13 1999/05/23 07:24:02 mrg Exp 109 * from: @(#)sbus.c 8.1 (Berkeley) 6/11/93 110 */ 111 112 /* 113 * UltraSPARC IOMMU support; used by both the sbus and pci code. 114 */ 115 #include "opt_ddb.h" 116 117 #include <sys/param.h> 118 #include <sys/extent.h> 119 #include <sys/malloc.h> 120 #include <sys/systm.h> 121 #include <sys/device.h> 122 123 #include <uvm/uvm_extern.h> 124 125 #include <machine/bus.h> 126 #include <sparc64/sparc64/cache.h> 127 #include <sparc64/dev/iommureg.h> 128 #include <sparc64/dev/iommuvar.h> 129 130 #include <machine/autoconf.h> 131 #include <machine/cpu.h> 132 133 #ifdef DEBUG 134 #define IDB_DVMA 0x1 135 int iommudebug = 0x0; 136 #define DPRINTF(l, s) do { if (iommudebug & l) printf s; } while (0) 137 #else 138 #define DPRINTF(l, s) 139 #endif 140 141 static int iommu_strbuf_flush __P((struct iommu_state *)); 142 143 /* 144 * initialise the UltraSPARC IOMMU (SBUS or PCI): 145 * - allocate and setup the iotsb. 146 * - enable the IOMMU 147 * - initialise the streaming buffers (if they exist) 148 * - create a private DVMA map. 149 */ 150 void 151 iommu_init(name, is, tsbsize) 152 char *name; 153 struct iommu_state *is; 154 int tsbsize; 155 { 156 psize_t size; 157 vaddr_t va; 158 paddr_t pa; 159 vm_page_t m; 160 struct pglist mlist; 161 162 /* 163 * Setup the iommu. 164 * 165 * The sun4u iommu is part of the SBUS or PCI controller so we 166 * will deal with it here.. 167 * 168 * The IOMMU address space always ends at 0xffffe000, but the starting 169 * address depends on the size of the map. The map size is 1024 * 2 ^ 170 * is->is_tsbsize entries, where each entry is 8 bytes. The start of 171 * the map can be calculated by (0xffffe000 << (8 + is->is_tsbsize)). 172 * 173 * Note: the stupid IOMMU ignores the high bits of an address, so a 174 * NULL DMA pointer will be translated by the first page of the IOTSB. 175 * To trap bugs we'll skip the first entry in the IOTSB. 176 */ 177 is->is_cr = (tsbsize << 16) | IOMMUCR_EN; 178 is->is_tsbsize = tsbsize; 179 is->is_dvmabase = IOTSB_VSTART(is->is_tsbsize) + NBPG; 180 181 /* 182 * Allocate memory for I/O pagetables. They need to be physically 183 * contiguous. 184 */ 185 186 size = NBPG<<(is->is_tsbsize); 187 TAILQ_INIT(&mlist); 188 if (uvm_pglistalloc((psize_t)size, (paddr_t)0, (paddr_t)-1, 189 (paddr_t)NBPG, (paddr_t)0, &mlist, 1, 0) != 0) 190 panic("iommu_init: no memory"); 191 192 va = uvm_km_valloc(kernel_map, size); 193 if (va == 0) 194 panic("iommu_init: no memory"); 195 is->is_tsb = (int64_t *)va; 196 197 m = TAILQ_FIRST(&mlist); 198 is->is_ptsb = VM_PAGE_TO_PHYS(m); 199 200 /* Map the pages */ 201 for (; m != NULL; m = TAILQ_NEXT(m,pageq)) { 202 pa = VM_PAGE_TO_PHYS(m); 203 pmap_enter(pmap_kernel(), va, pa | PMAP_NVC, 204 VM_PROT_READ|VM_PROT_WRITE, 205 VM_PROT_READ|VM_PROT_WRITE|PMAP_WIRED); 206 va += NBPG; 207 } 208 bzero(is->is_tsb, size); 209 210 #ifdef DEBUG 211 if (iommudebug & IDB_DVMA) 212 { 213 /* Probe the iommu */ 214 struct iommureg *regs = is->is_iommu; 215 216 printf("iommu regs at: cr=%lx tsb=%lx flush=%lx\n", ®s->iommu_cr, 217 ®s->iommu_tsb, ®s->iommu_flush); 218 printf("iommu cr=%qx tsb=%qx\n", regs->iommu_cr, regs->iommu_tsb); 219 printf("TSB base %p phys %qx\n", (void *)is->is_tsb, (u_int64_t)is->is_ptsb); 220 delay(1000000); /* 1 s */ 221 } 222 #endif 223 224 /* 225 * Initialize streaming buffer, if it is there. 226 */ 227 if (is->is_sb) 228 (void)pmap_extract(pmap_kernel(), (vaddr_t)&is->is_flush, 229 (paddr_t *)&is->is_flushpa); 230 231 /* 232 * now actually start up the IOMMU 233 */ 234 iommu_reset(is); 235 236 /* 237 * Now all the hardware's working we need to allocate a dvma map. 238 */ 239 printf("DVMA map: %x to %x\n", 240 (unsigned int)is->is_dvmabase, 241 (unsigned int)IOTSB_VEND); 242 is->is_dvmamap = extent_create(name, 243 is->is_dvmabase, IOTSB_VEND, 244 M_DEVBUF, 0, 0, EX_NOWAIT); 245 } 246 247 /* 248 * Streaming buffers don't exist on the UltraSPARC IIi; we should have 249 * detected that already and disabled them. If not, we will notice that 250 * they aren't there when the STRBUF_EN bit does not remain. 251 */ 252 void 253 iommu_reset(is) 254 struct iommu_state *is; 255 { 256 257 /* Need to do 64-bit stores */ 258 bus_space_write_8(is->is_bustag, &is->is_iommu->iommu_tsb, 0, is->is_ptsb); 259 /* Enable IOMMU in diagnostic mode */ 260 bus_space_write_8(is->is_bustag, &is->is_iommu->iommu_cr, 0, 261 is->is_cr|IOMMUCR_DE); 262 263 264 if (!is->is_sb) 265 return; 266 267 /* Enable diagnostics mode? */ 268 bus_space_write_8(is->is_bustag, &is->is_sb->strbuf_ctl, 0, STRBUF_EN); 269 270 /* No streaming buffers? Disable them */ 271 if (bus_space_read_8(is->is_bustag, 272 (bus_space_handle_t)(u_long)&is->is_sb->strbuf_ctl, 0) == 0) 273 is->is_sb = 0; 274 } 275 276 /* 277 * Here are the iommu control routines. 278 */ 279 void 280 iommu_enter(is, va, pa, flags) 281 struct iommu_state *is; 282 vaddr_t va; 283 int64_t pa; 284 int flags; 285 { 286 int64_t tte; 287 288 #ifdef DIAGNOSTIC 289 if (va < is->is_dvmabase) 290 panic("iommu_enter: va %#lx not in DVMA space", va); 291 #endif 292 293 tte = MAKEIOTTE(pa, !(flags&BUS_DMA_NOWRITE), !(flags&BUS_DMA_NOCACHE), 294 !(flags&BUS_DMA_COHERENT)); 295 296 /* Is the streamcache flush really needed? */ 297 if (is->is_sb) { 298 bus_space_write_8(is->is_bustag, &is->is_sb->strbuf_pgflush, 0, 299 va); 300 iommu_strbuf_flush(is); 301 } 302 DPRINTF(IDB_DVMA, ("Clearing TSB slot %d for va %p\n", 303 (int)IOTSBSLOT(va,is->is_tsbsize), va)); 304 is->is_tsb[IOTSBSLOT(va,is->is_tsbsize)] = tte; 305 bus_space_write_8(is->is_bustag, &is->is_iommu->iommu_flush, 306 0, va); 307 DPRINTF(IDB_DVMA, ("iommu_enter: va %lx pa %lx TSB[%lx]@%p=%lx\n", 308 va, (long)pa, IOTSBSLOT(va,is->is_tsbsize), 309 &is->is_tsb[IOTSBSLOT(va,is->is_tsbsize)], 310 (long)tte)); 311 } 312 313 /* 314 * iommu_remove: removes mappings created by iommu_enter 315 * 316 * Only demap from IOMMU if flag is set. 317 * 318 * XXX: this function needs better internal error checking. 319 */ 320 void 321 iommu_remove(is, va, len) 322 struct iommu_state *is; 323 vaddr_t va; 324 size_t len; 325 { 326 327 #ifdef DIAGNOSTIC 328 if (va < is->is_dvmabase) 329 panic("iommu_remove: va 0x%lx not in DVMA space", (long)va); 330 if ((long)(va + len) < (long)va) 331 panic("iommu_remove: va 0x%lx + len 0x%lx wraps", 332 (long) va, (long) len); 333 if (len & ~0xfffffff) 334 panic("iommu_remove: rediculous len 0x%lx", (long)len); 335 #endif 336 337 va = trunc_page(va); 338 DPRINTF(IDB_DVMA, ("iommu_remove: va %lx TSB[%lx]@%p\n", 339 va, IOTSBSLOT(va,is->is_tsbsize), 340 &is->is_tsb[IOTSBSLOT(va,is->is_tsbsize)])); 341 while (len > 0) { 342 DPRINTF(IDB_DVMA, ("iommu_remove: clearing TSB slot %d for va %p size %lx\n", 343 (int)IOTSBSLOT(va,is->is_tsbsize), va, (u_long)len)); 344 if (is->is_sb) { 345 DPRINTF(IDB_DVMA, ("iommu_remove: flushing va %p TSB[%lx]@%p=%lx, %lu bytes left\n", 346 (long)va, (long)IOTSBSLOT(va,is->is_tsbsize), 347 (long)&is->is_tsb[IOTSBSLOT(va,is->is_tsbsize)], 348 (long)(is->is_tsb[IOTSBSLOT(va,is->is_tsbsize)]), 349 (u_long)len)); 350 bus_space_write_8(is->is_bustag, 351 &is->is_sb->strbuf_pgflush, 0, va); 352 if (len <= NBPG) 353 iommu_strbuf_flush(is); 354 DPRINTF(IDB_DVMA, ("iommu_remove: flushed va %p TSB[%lx]@%p=%lx, %lu bytes left\n", 355 (long)va, (long)IOTSBSLOT(va,is->is_tsbsize), 356 (long)&is->is_tsb[IOTSBSLOT(va,is->is_tsbsize)], 357 (long)(is->is_tsb[IOTSBSLOT(va,is->is_tsbsize)]), 358 (u_long)len)); 359 } else 360 membar_sync(); /* XXX */ 361 362 if (len <= NBPG) 363 len = 0; 364 else 365 len -= NBPG; 366 367 is->is_tsb[IOTSBSLOT(va,is->is_tsbsize)] = 0; 368 bus_space_write_8(is->is_bustag, &is->is_iommu->iommu_flush, 0, va); 369 va += NBPG; 370 } 371 } 372 373 static int 374 iommu_strbuf_flush(is) 375 struct iommu_state *is; 376 { 377 struct timeval cur, flushtimeout; 378 379 #define BUMPTIME(t, usec) { \ 380 register volatile struct timeval *tp = (t); \ 381 register long us; \ 382 \ 383 tp->tv_usec = us = tp->tv_usec + (usec); \ 384 if (us >= 1000000) { \ 385 tp->tv_usec = us - 1000000; \ 386 tp->tv_sec++; \ 387 } \ 388 } 389 390 if (!is->is_sb) 391 return (0); 392 393 /* 394 * Streaming buffer flushes: 395 * 396 * 1 Tell strbuf to flush by storing va to strbuf_pgflush. If 397 * we're not on a cache line boundary (64-bits): 398 * 2 Store 0 in flag 399 * 3 Store pointer to flag in flushsync 400 * 4 wait till flushsync becomes 0x1 401 * 402 * If it takes more than .5 sec, something 403 * went wrong. 404 */ 405 406 is->is_flush = 0; 407 membar_sync(); 408 bus_space_write_8(is->is_bustag, &is->is_sb->strbuf_flushsync, 0, is->is_flushpa); 409 membar_sync(); 410 411 microtime(&flushtimeout); 412 cur = flushtimeout; 413 BUMPTIME(&flushtimeout, 500000); /* 1/2 sec */ 414 415 DPRINTF(IDB_DVMA, ("iommu_strbuf_flush: flush = %lx at va = %lx pa = %lx now=%lx:%lx until = %lx:%lx\n", 416 (long)is->is_flush, (long)&is->is_flush, 417 (long)is->is_flushpa, cur.tv_sec, cur.tv_usec, 418 flushtimeout.tv_sec, flushtimeout.tv_usec)); 419 /* Bypass non-coherent D$ */ 420 while (!ldxa(is->is_flushpa, ASI_PHYS_CACHED) && 421 ((cur.tv_sec <= flushtimeout.tv_sec) && 422 (cur.tv_usec <= flushtimeout.tv_usec))) 423 microtime(&cur); 424 425 #ifdef DIAGNOSTIC 426 if (!is->is_flush) { 427 printf("iommu_strbuf_flush: flush timeout %p at %p\n", (long)is->is_flush, 428 (long)is->is_flushpa); /* panic? */ 429 #ifdef DDB 430 Debugger(); 431 #endif 432 } 433 #endif 434 DPRINTF(IDB_DVMA, ("iommu_strbuf_flush: flushed\n")); 435 return (is->is_flush); 436 } 437 438 /* 439 * IOMMU DVMA operations, common to SBUS and PCI. 440 */ 441 int 442 iommu_dvmamap_load(t, is, map, buf, buflen, p, flags) 443 bus_dma_tag_t t; 444 struct iommu_state *is; 445 bus_dmamap_t map; 446 void *buf; 447 bus_size_t buflen; 448 struct proc *p; 449 int flags; 450 { 451 int s; 452 int err; 453 bus_size_t sgsize; 454 paddr_t curaddr; 455 u_long dvmaddr, align; 456 vaddr_t vaddr = (vaddr_t)buf; 457 pmap_t pmap; 458 459 if (map->dm_nsegs) { 460 /* Already in use?? */ 461 #ifdef DIAGNOSTIC 462 printf("iommu_dvmamap_load: map still in use\n"); 463 #endif 464 bus_dmamap_unload(t, map); 465 } 466 /* 467 * Make sure that on error condition we return "no valid mappings". 468 */ 469 map->dm_nsegs = 0; 470 471 if (buflen > map->_dm_size) { 472 DPRINTF(IDB_DVMA, 473 ("iommu_dvmamap_load(): error %d > %d -- " 474 "map size exceeded!\n", buflen, map->_dm_size)); 475 return (EINVAL); 476 } 477 478 sgsize = round_page(buflen + ((int)vaddr & PGOFSET)); 479 480 /* 481 * XXX Need to implement "don't dma across this boundry". 482 */ 483 align = max(map->_dm_boundary, NBPG); 484 s = splhigh(); 485 err = extent_alloc(is->is_dvmamap, sgsize, align, 486 map->_dm_boundary, EX_NOWAIT|EX_BOUNDZERO, (u_long *)&dvmaddr); 487 splx(s); 488 489 #ifdef DEBUG 490 if (err || (dvmaddr == (bus_addr_t)-1)) 491 { 492 printf("iommu_dvmamap_load(): extent_alloc(%d, %x) failed!\n", 493 sgsize, flags); 494 Debugger(); 495 } 496 #endif 497 if (err != 0) 498 return (err); 499 500 if (dvmaddr == (bus_addr_t)-1) 501 return (ENOMEM); 502 503 /* 504 * We always use just one segment. 505 */ 506 map->dm_mapsize = buflen; 507 map->dm_nsegs = 1; 508 map->dm_segs[0].ds_addr = dvmaddr + (vaddr & PGOFSET); 509 map->dm_segs[0].ds_len = buflen; 510 511 if (p != NULL) 512 pmap = p->p_vmspace->vm_map.pmap; 513 else 514 pmap = pmap_kernel(); 515 516 dvmaddr = trunc_page(map->dm_segs[0].ds_addr); 517 for (; buflen > 0; ) { 518 /* 519 * Get the physical address for this page. 520 */ 521 if (pmap_extract(pmap, (vaddr_t)vaddr, &curaddr) == FALSE) { 522 bus_dmamap_unload(t, map); 523 return (-1); 524 } 525 526 /* 527 * Compute the segment size, and adjust counts. 528 */ 529 sgsize = NBPG - ((u_long)vaddr & PGOFSET); 530 if (buflen < sgsize) 531 sgsize = buflen; 532 533 DPRINTF(IDB_DVMA, 534 ("iommu_dvmamap_load: map %p loading va %p dva %lx at pa %lx\n", 535 map, (void *)vaddr, (long)dvmaddr, (long)(curaddr&~(NBPG-1)))); 536 iommu_enter(is, trunc_page(dvmaddr), trunc_page(curaddr), 537 flags); 538 539 dvmaddr += PAGE_SIZE; 540 vaddr += sgsize; 541 buflen -= sgsize; 542 } 543 return (0); 544 } 545 546 547 void 548 iommu_dvmamap_unload(t, is, map) 549 bus_dma_tag_t t; 550 struct iommu_state *is; 551 bus_dmamap_t map; 552 { 553 vaddr_t addr; 554 size_t len; 555 int error, s; 556 bus_addr_t dvmaddr; 557 bus_size_t sgsize; 558 559 if (map->dm_nsegs != 1) 560 panic("iommu_dvmamap_unload: nsegs = %d", map->dm_nsegs); 561 562 addr = trunc_page(map->dm_segs[0].ds_addr); 563 len = map->dm_segs[0].ds_len; 564 565 DPRINTF(IDB_DVMA, 566 ("iommu_dvmamap_unload: map %p removing va %lx size %lx\n", 567 map, (long)addr, (long)len)); 568 iommu_remove(is, addr, len); 569 dvmaddr = (map->dm_segs[0].ds_addr & ~PGOFSET); 570 sgsize = round_page(map->dm_segs[0].ds_len + 571 ((int)map->dm_segs[0].ds_addr & PGOFSET)); 572 573 /* Mark the mappings as invalid. */ 574 map->dm_mapsize = 0; 575 map->dm_nsegs = 0; 576 577 s = splhigh(); 578 error = extent_free(is->is_dvmamap, dvmaddr, sgsize, EX_NOWAIT); 579 splx(s); 580 if (error != 0) 581 printf("warning: %qd of DVMA space lost\n", (long long)sgsize); 582 cache_flush((caddr_t)(u_long)dvmaddr, (u_int)sgsize); 583 } 584 585 586 int 587 iommu_dvmamap_load_raw(t, is, map, segs, nsegs, size, flags) 588 bus_dma_tag_t t; 589 struct iommu_state *is; 590 bus_dmamap_t map; 591 bus_dma_segment_t *segs; 592 int nsegs; 593 bus_size_t size; 594 int flags; 595 { 596 vm_page_t m; 597 int s; 598 int err; 599 bus_size_t sgsize; 600 paddr_t pa; 601 u_long boundary, align; 602 u_long dvmaddr; 603 struct pglist *mlist; 604 int pagesz = PAGE_SIZE; 605 606 if (map->dm_nsegs) { 607 /* Already in use?? */ 608 #ifdef DIAGNOSTIC 609 printf("iommu_dvmamap_load_raw: map still in use\n"); 610 #endif 611 bus_dmamap_unload(t, map); 612 } 613 /* 614 * Make sure that on error condition we return "no valid mappings". 615 */ 616 map->dm_nsegs = 0; 617 #ifdef DIAGNOSTIC 618 /* XXX - unhelpful since we can't reset these in map_unload() */ 619 if (segs[0].ds_addr != 0) 620 panic("iommu_dvmamap_load_raw: segment already loaded: " 621 "addr %#llx, size %#llx", 622 (u_int64_t)segs[0].ds_addr, (u_int64_t)segs[0].ds_len); 623 if (segs[0].ds_len != size) 624 panic("iommu_dvmamap_load_raw: segment size changed: " 625 "ds_len %#llx size %#llx", segs[0].ds_len, size); 626 #endif 627 sgsize = round_page(size); 628 629 /* 630 * A boundary presented to bus_dmamem_alloc() takes precedence 631 * over boundary in the map. 632 */ 633 if ((boundary = segs[0]._ds_boundary) == 0) 634 boundary = map->_dm_boundary; 635 636 align = max(map->_dm_boundary, NBPG); 637 s = splhigh(); 638 err = extent_alloc(is->is_dvmamap, sgsize, align, boundary, 639 ((flags & BUS_DMA_NOWAIT) == 0 ? EX_WAITOK : EX_NOWAIT)|EX_BOUNDZERO, 640 (u_long *)&dvmaddr); 641 splx(s); 642 643 if (err != 0) 644 return (err); 645 646 #ifdef DEBUG 647 if (dvmaddr == (bus_addr_t)-1) 648 { 649 printf("iommu_dvmamap_load_raw(): extent_alloc(%d, %x) failed!\n", 650 sgsize, flags); 651 Debugger(); 652 } 653 #endif 654 if (dvmaddr == (bus_addr_t)-1) 655 return (ENOMEM); 656 657 /* 658 * We always use just one segment. 659 */ 660 map->dm_mapsize = size; 661 map->dm_nsegs = 1; 662 map->dm_segs[0].ds_addr = dvmaddr; 663 map->dm_segs[0].ds_len = size; 664 665 mlist = segs[0]._ds_mlist; 666 for (m = TAILQ_FIRST(mlist); m != NULL; m = TAILQ_NEXT(m,pageq)) { 667 if (sgsize == 0) 668 panic("iommu_dmamap_load_raw: size botch"); 669 pa = VM_PAGE_TO_PHYS(m); 670 671 DPRINTF(IDB_DVMA, 672 ("iommu_dvmamap_load_raw: map %p loading va %lx at pa %lx\n", 673 map, (long)dvmaddr, (long)(pa))); 674 iommu_enter(is, dvmaddr, pa, flags); 675 676 dvmaddr += pagesz; 677 sgsize -= pagesz; 678 } 679 return (0); 680 } 681 682 void 683 iommu_dvmamap_sync(t, is, map, offset, len, ops) 684 bus_dma_tag_t t; 685 struct iommu_state *is; 686 bus_dmamap_t map; 687 bus_addr_t offset; 688 bus_size_t len; 689 int ops; 690 { 691 vaddr_t va = map->dm_segs[0].ds_addr + offset; 692 693 /* 694 * We only support one DMA segment; supporting more makes this code 695 * too unweildy. 696 */ 697 698 if (ops & BUS_DMASYNC_PREREAD) { 699 DPRINTF(IDB_DVMA, 700 ("iommu_dvmamap_sync: syncing va %p len %lu " 701 "BUS_DMASYNC_PREREAD\n", (long)va, (u_long)len)); 702 703 /* Nothing to do */; 704 } 705 if (ops & BUS_DMASYNC_POSTREAD) { 706 DPRINTF(IDB_DVMA, 707 ("iommu_dvmamap_sync: syncing va %p len %lu " 708 "BUS_DMASYNC_POSTREAD\n", (long)va, (u_long)len)); 709 /* if we have a streaming buffer, flush it here first */ 710 if (is->is_sb) 711 while (len > 0) { 712 DPRINTF(IDB_DVMA, 713 ("iommu_dvmamap_sync: flushing va %p, %lu " 714 "bytes left\n", (long)va, (u_long)len)); 715 bus_space_write_8(is->is_bustag, 716 &is->is_sb->strbuf_pgflush, 0, va); 717 if (len <= NBPG) { 718 iommu_strbuf_flush(is); 719 len = 0; 720 } else 721 len -= NBPG; 722 va += NBPG; 723 } 724 } 725 if (ops & BUS_DMASYNC_PREWRITE) { 726 DPRINTF(IDB_DVMA, 727 ("iommu_dvmamap_sync: syncing va %p len %lu " 728 "BUS_DMASYNC_PREWRITE\n", (long)va, (u_long)len)); 729 /* Nothing to do */; 730 } 731 if (ops & BUS_DMASYNC_POSTWRITE) { 732 DPRINTF(IDB_DVMA, 733 ("iommu_dvmamap_sync: syncing va %p len %lu " 734 "BUS_DMASYNC_POSTWRITE\n", (long)va, (u_long)len)); 735 /* Nothing to do */; 736 } 737 } 738 739 int 740 iommu_dvmamem_alloc(t, is, size, alignment, boundary, segs, nsegs, rsegs, flags) 741 bus_dma_tag_t t; 742 struct iommu_state *is; 743 bus_size_t size, alignment, boundary; 744 bus_dma_segment_t *segs; 745 int nsegs; 746 int *rsegs; 747 int flags; 748 { 749 750 DPRINTF(IDB_DVMA, ("iommu_dvmamem_alloc: sz %qx align %qx bound %qx " 751 "segp %p flags %d\n", size, alignment, boundary, segs, flags)); 752 return (bus_dmamem_alloc(t->_parent, size, alignment, boundary, 753 segs, nsegs, rsegs, flags)); 754 } 755 756 void 757 iommu_dvmamem_free(t, is, segs, nsegs) 758 bus_dma_tag_t t; 759 struct iommu_state *is; 760 bus_dma_segment_t *segs; 761 int nsegs; 762 { 763 764 DPRINTF(IDB_DVMA, ("iommu_dvmamem_free: segp %p nsegs %d\n", 765 segs, nsegs)); 766 bus_dmamem_free(t->_parent, segs, nsegs); 767 } 768 769 /* 770 * Map the DVMA mappings into the kernel pmap. 771 * Check the flags to see whether we're streaming or coherent. 772 */ 773 int 774 iommu_dvmamem_map(t, is, segs, nsegs, size, kvap, flags) 775 bus_dma_tag_t t; 776 struct iommu_state *is; 777 bus_dma_segment_t *segs; 778 int nsegs; 779 size_t size; 780 caddr_t *kvap; 781 int flags; 782 { 783 vm_page_t m; 784 vaddr_t va; 785 bus_addr_t addr; 786 struct pglist *mlist; 787 int cbit; 788 789 DPRINTF(IDB_DVMA, ("iommu_dvmamem_map: segp %p nsegs %d size %lx\n", 790 segs, nsegs, size)); 791 792 /* 793 * Allocate some space in the kernel map, and then map these pages 794 * into this space. 795 */ 796 size = round_page(size); 797 va = uvm_km_valloc(kernel_map, size); 798 if (va == 0) 799 return (ENOMEM); 800 801 *kvap = (caddr_t)va; 802 803 /* 804 * digest flags: 805 */ 806 cbit = 0; 807 if (flags & BUS_DMA_COHERENT) /* Disable vcache */ 808 cbit |= PMAP_NVC; 809 if (flags & BUS_DMA_NOCACHE) /* sideffects */ 810 cbit |= PMAP_NC; 811 812 /* 813 * Now take this and map it into the CPU. 814 */ 815 mlist = segs[0]._ds_mlist; 816 for (m = mlist->tqh_first; m != NULL; m = m->pageq.tqe_next) { 817 #ifdef DIAGNOSTIC 818 if (size == 0) 819 panic("iommu_dvmamem_map: size botch"); 820 #endif 821 addr = VM_PAGE_TO_PHYS(m); 822 DPRINTF(IDB_DVMA, ("iommu_dvmamem_map: " 823 "mapping va %lx at %qx\n", va, addr | cbit)); 824 pmap_enter(pmap_kernel(), va, addr | cbit, 825 VM_PROT_READ | VM_PROT_WRITE, PMAP_WIRED); 826 va += PAGE_SIZE; 827 size -= PAGE_SIZE; 828 } 829 830 return (0); 831 } 832 833 /* 834 * Unmap DVMA mappings from kernel 835 */ 836 void 837 iommu_dvmamem_unmap(t, is, kva, size) 838 bus_dma_tag_t t; 839 struct iommu_state *is; 840 caddr_t kva; 841 size_t size; 842 { 843 844 DPRINTF(IDB_DVMA, ("iommu_dvmamem_unmap: kvm %p size %lx\n", 845 kva, size)); 846 847 #ifdef DIAGNOSTIC 848 if ((u_long)kva & PGOFSET) 849 panic("iommu_dvmamem_unmap"); 850 #endif 851 852 size = round_page(size); 853 pmap_remove(pmap_kernel(), (vaddr_t)kva, size); 854 #if 0 855 /* 856 * XXX ? is this necessary? i think so and i think other 857 * implementations are missing it. 858 */ 859 uvm_km_free(kernel_map, (vaddr_t)kva, size); 860 #endif 861 } 862
Indexes created Thu Sep 25 08:09:54 GMT 2025