iommu.c revision 1.22
1 /* $NetBSD: iommu.c,v 1.22 2000/07/07 13:10:34 mrg Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000 Matthew R. Green 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 23 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 24 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 25 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 /*- 32 * Copyright (c) 1998 The NetBSD Foundation, Inc. 33 * All rights reserved. 34 * 35 * This code is derived from software contributed to The NetBSD Foundation 36 * by Paul Kranenburg. 37 * 38 * Redistribution and use in source and binary forms, with or without 39 * modification, are permitted provided that the following conditions 40 * are met: 41 * 1. Redistributions of source code must retain the above copyright 42 * notice, this list of conditions and the following disclaimer. 43 * 2. Redistributions in binary form must reproduce the above copyright 44 * notice, this list of conditions and the following disclaimer in the 45 * documentation and/or other materials provided with the distribution. 46 * 3. All advertising materials mentioning features or use of this software 47 * must display the following acknowledgement: 48 * This product includes software developed by the NetBSD 49 * Foundation, Inc. and its contributors. 50 * 4. Neither the name of The NetBSD Foundation nor the names of its 51 * contributors may be used to endorse or promote products derived 52 * from this software without specific prior written permission. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 55 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 56 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 57 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 58 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 59 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 60 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 61 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 62 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 63 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 64 * POSSIBILITY OF SUCH DAMAGE. 65 */ 66 67 /* 68 * Copyright (c) 1992, 1993 69 * The Regents of the University of California. All rights reserved. 70 * 71 * This software was developed by the Computer Systems Engineering group 72 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 73 * contributed to Berkeley. 74 * 75 * All advertising materials mentioning features or use of this software 76 * must display the following acknowledgement: 77 * This product includes software developed by the University of 78 * California, Lawrence Berkeley Laboratory. 79 * 80 * Redistribution and use in source and binary forms, with or without 81 * modification, are permitted provided that the following conditions 82 * are met: 83 * 1. Redistributions of source code must retain the above copyright 84 * notice, this list of conditions and the following disclaimer. 85 * 2. Redistributions in binary form must reproduce the above copyright 86 * notice, this list of conditions and the following disclaimer in the 87 * documentation and/or other materials provided with the distribution. 88 * 3. All advertising materials mentioning features or use of this software 89 * must display the following acknowledgement: 90 * This product includes software developed by the University of 91 * California, Berkeley and its contributors. 92 * 4. Neither the name of the University nor the names of its contributors 93 * may be used to endorse or promote products derived from this software 94 * without specific prior written permission. 95 * 96 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 97 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 98 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 99 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 100 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 101 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 102 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 103 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 104 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 105 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 106 * SUCH DAMAGE. 107 * 108 * from: NetBSD: sbus.c,v 1.13 1999/05/23 07:24:02 mrg Exp 109 * from: @(#)sbus.c 8.1 (Berkeley) 6/11/93 110 */ 111 112 /* 113 * UltraSPARC IOMMU support; used by both the sbus and pci code. 114 */ 115 #include "opt_ddb.h" 116 117 #include <sys/param.h> 118 #include <sys/extent.h> 119 #include <sys/malloc.h> 120 #include <sys/systm.h> 121 #include <sys/device.h> 122 123 #include <uvm/uvm_extern.h> 124 125 #include <machine/bus.h> 126 #include <sparc64/sparc64/cache.h> 127 #include <sparc64/dev/iommureg.h> 128 #include <sparc64/dev/iommuvar.h> 129 130 #include <machine/autoconf.h> 131 #include <machine/cpu.h> 132 133 #ifdef DEBUG 134 #define IDB_BUSDMA 0x1 135 #define IDB_IOMMU 0x2 136 #define IDB_INFO 0x4 137 int iommudebug = 0x0; 138 #define DPRINTF(l, s) do { if (iommudebug & l) printf s; } while (0) 139 #else 140 #define DPRINTF(l, s) 141 #endif 142 143 static int iommu_strbuf_flush __P((struct iommu_state *)); 144 145 /* 146 * initialise the UltraSPARC IOMMU (SBUS or PCI): 147 * - allocate and setup the iotsb. 148 * - enable the IOMMU 149 * - initialise the streaming buffers (if they exist) 150 * - create a private DVMA map. 151 */ 152 void 153 iommu_init(name, is, tsbsize) 154 char *name; 155 struct iommu_state *is; 156 int tsbsize; 157 { 158 psize_t size; 159 vaddr_t va; 160 paddr_t pa; 161 vm_page_t m; 162 struct pglist mlist; 163 164 /* 165 * Setup the iommu. 166 * 167 * The sun4u iommu is part of the SBUS or PCI controller so we 168 * will deal with it here.. 169 * 170 * The IOMMU address space always ends at 0xffffe000, but the starting 171 * address depends on the size of the map. The map size is 1024 * 2 ^ 172 * is->is_tsbsize entries, where each entry is 8 bytes. The start of 173 * the map can be calculated by (0xffffe000 << (8 + is->is_tsbsize)). 174 * 175 * Note: the stupid IOMMU ignores the high bits of an address, so a 176 * NULL DMA pointer will be translated by the first page of the IOTSB. 177 * To trap bugs we'll skip the first entry in the IOTSB. 178 */ 179 is->is_cr = (tsbsize << 16) | IOMMUCR_EN; 180 is->is_tsbsize = tsbsize; 181 is->is_dvmabase = IOTSB_VSTART(is->is_tsbsize) + NBPG; 182 183 /* 184 * Allocate memory for I/O pagetables. They need to be physically 185 * contiguous. 186 */ 187 188 size = NBPG<<(is->is_tsbsize); 189 TAILQ_INIT(&mlist); 190 if (uvm_pglistalloc((psize_t)size, (paddr_t)0, (paddr_t)-1, 191 (paddr_t)NBPG, (paddr_t)0, &mlist, 1, 0) != 0) 192 panic("iommu_init: no memory"); 193 194 va = uvm_km_valloc(kernel_map, size); 195 if (va == 0) 196 panic("iommu_init: no memory"); 197 is->is_tsb = (int64_t *)va; 198 199 m = TAILQ_FIRST(&mlist); 200 is->is_ptsb = VM_PAGE_TO_PHYS(m); 201 202 /* Map the pages */ 203 for (; m != NULL; m = TAILQ_NEXT(m,pageq)) { 204 pa = VM_PAGE_TO_PHYS(m); 205 pmap_enter(pmap_kernel(), va, pa | PMAP_NVC, 206 VM_PROT_READ|VM_PROT_WRITE, 207 VM_PROT_READ|VM_PROT_WRITE|PMAP_WIRED); 208 va += NBPG; 209 } 210 bzero(is->is_tsb, size); 211 212 #ifdef DEBUG 213 if (iommudebug & IDB_INFO) 214 { 215 /* Probe the iommu */ 216 struct iommureg *regs = is->is_iommu; 217 218 printf("iommu regs at: cr=%lx tsb=%lx flush=%lx\n", ®s->iommu_cr, 219 ®s->iommu_tsb, ®s->iommu_flush); 220 printf("iommu cr=%qx tsb=%qx\n", regs->iommu_cr, regs->iommu_tsb); 221 printf("TSB base %p phys %qx\n", (void *)is->is_tsb, (u_int64_t)is->is_ptsb); 222 delay(1000000); /* 1 s */ 223 } 224 #endif 225 226 /* 227 * Initialize streaming buffer, if it is there. 228 */ 229 if (is->is_sb) 230 (void)pmap_extract(pmap_kernel(), (vaddr_t)&is->is_flush, 231 (paddr_t *)&is->is_flushpa); 232 233 /* 234 * now actually start up the IOMMU 235 */ 236 iommu_reset(is); 237 238 /* 239 * Now all the hardware's working we need to allocate a dvma map. 240 */ 241 printf("DVMA map: %x to %x\n", 242 (unsigned int)is->is_dvmabase, 243 (unsigned int)IOTSB_VEND); 244 is->is_dvmamap = extent_create(name, 245 is->is_dvmabase, (u_long)IOTSB_VEND, 246 M_DEVBUF, 0, 0, EX_NOWAIT); 247 } 248 249 /* 250 * Streaming buffers don't exist on the UltraSPARC IIi; we should have 251 * detected that already and disabled them. If not, we will notice that 252 * they aren't there when the STRBUF_EN bit does not remain. 253 */ 254 void 255 iommu_reset(is) 256 struct iommu_state *is; 257 { 258 259 /* Need to do 64-bit stores */ 260 bus_space_write_8(is->is_bustag, 261 (bus_space_handle_t)(u_long)&is->is_iommu->iommu_tsb, 262 0, is->is_ptsb); 263 /* Enable IOMMU in diagnostic mode */ 264 bus_space_write_8(is->is_bustag, 265 (bus_space_handle_t)(u_long)&is->is_iommu->iommu_cr, 0, 266 is->is_cr|IOMMUCR_DE); 267 268 269 if (!is->is_sb) 270 return; 271 272 /* Enable diagnostics mode? */ 273 bus_space_write_8(is->is_bustag, 274 (bus_space_handle_t)(u_long)&is->is_sb->strbuf_ctl, 275 0, STRBUF_EN); 276 277 /* No streaming buffers? Disable them */ 278 if (bus_space_read_8(is->is_bustag, 279 (bus_space_handle_t)(u_long)&is->is_sb->strbuf_ctl, 280 0) == 0) 281 is->is_sb = 0; 282 } 283 284 /* 285 * Here are the iommu control routines. 286 */ 287 void 288 iommu_enter(is, va, pa, flags) 289 struct iommu_state *is; 290 vaddr_t va; 291 int64_t pa; 292 int flags; 293 { 294 int64_t tte; 295 296 #ifdef DIAGNOSTIC 297 if (va < is->is_dvmabase) 298 panic("iommu_enter: va %#lx not in DVMA space", va); 299 #endif 300 301 tte = MAKEIOTTE(pa, !(flags&BUS_DMA_NOWRITE), !(flags&BUS_DMA_NOCACHE), 302 !(flags&BUS_DMA_COHERENT)); 303 304 /* Is the streamcache flush really needed? */ 305 if (is->is_sb) { 306 bus_space_write_8(is->is_bustag, (bus_space_handle_t)(u_long) 307 &is->is_sb->strbuf_pgflush, 0, va); 308 iommu_strbuf_flush(is); 309 } 310 DPRINTF(IDB_IOMMU, ("Clearing TSB slot %d for va %p\n", 311 (int)IOTSBSLOT(va,is->is_tsbsize), va)); 312 is->is_tsb[IOTSBSLOT(va,is->is_tsbsize)] = tte; 313 bus_space_write_8(is->is_bustag, (bus_space_handle_t)(u_long) 314 &is->is_iommu->iommu_flush, 0, va); 315 DPRINTF(IDB_IOMMU, ("iommu_enter: va %lx pa %lx TSB[%lx]@%p=%lx\n", 316 va, (long)pa, IOTSBSLOT(va,is->is_tsbsize), 317 &is->is_tsb[IOTSBSLOT(va,is->is_tsbsize)], 318 (long)tte)); 319 } 320 321 /* 322 * iommu_remove: removes mappings created by iommu_enter 323 * 324 * Only demap from IOMMU if flag is set. 325 * 326 * XXX: this function needs better internal error checking. 327 */ 328 void 329 iommu_remove(is, va, len) 330 struct iommu_state *is; 331 vaddr_t va; 332 size_t len; 333 { 334 335 #ifdef DIAGNOSTIC 336 if (va < is->is_dvmabase) 337 panic("iommu_remove: va 0x%lx not in DVMA space", (long)va); 338 if ((long)(va + len) < (long)va) 339 panic("iommu_remove: va 0x%lx + len 0x%lx wraps", 340 (long) va, (long) len); 341 if (len & ~0xfffffff) 342 panic("iommu_remove: rediculous len 0x%lx", (long)len); 343 #endif 344 345 va = trunc_page(va); 346 DPRINTF(IDB_IOMMU, ("iommu_remove: va %lx TSB[%lx]@%p\n", 347 va, IOTSBSLOT(va,is->is_tsbsize), 348 &is->is_tsb[IOTSBSLOT(va,is->is_tsbsize)])); 349 while (len > 0) { 350 DPRINTF(IDB_IOMMU, ("iommu_remove: clearing TSB slot %d for va %p size %lx\n", 351 (int)IOTSBSLOT(va,is->is_tsbsize), va, (u_long)len)); 352 if (is->is_sb) { 353 DPRINTF(IDB_IOMMU, ("iommu_remove: flushing va %p TSB[%lx]@%p=%lx, %lu bytes left\n", 354 (long)va, (long)IOTSBSLOT(va,is->is_tsbsize), 355 (long)&is->is_tsb[IOTSBSLOT(va,is->is_tsbsize)], 356 (long)(is->is_tsb[IOTSBSLOT(va,is->is_tsbsize)]), 357 (u_long)len)); 358 bus_space_write_8(is->is_bustag, (bus_space_handle_t)(u_long) 359 &is->is_sb->strbuf_pgflush, 0, va); 360 if (len <= NBPG) 361 iommu_strbuf_flush(is); 362 DPRINTF(IDB_IOMMU, ("iommu_remove: flushed va %p TSB[%lx]@%p=%lx, %lu bytes left\n", 363 (long)va, (long)IOTSBSLOT(va,is->is_tsbsize), 364 (long)&is->is_tsb[IOTSBSLOT(va,is->is_tsbsize)], 365 (long)(is->is_tsb[IOTSBSLOT(va,is->is_tsbsize)]), 366 (u_long)len)); 367 } else 368 membar_sync(); /* XXX */ 369 370 if (len <= NBPG) 371 len = 0; 372 else 373 len -= NBPG; 374 375 is->is_tsb[IOTSBSLOT(va,is->is_tsbsize)] = 0; 376 bus_space_write_8(is->is_bustag, (bus_space_handle_t)(u_long) 377 &is->is_iommu->iommu_flush, 0, va); 378 va += NBPG; 379 } 380 } 381 382 static int 383 iommu_strbuf_flush(is) 384 struct iommu_state *is; 385 { 386 struct timeval cur, flushtimeout; 387 388 #define BUMPTIME(t, usec) { \ 389 register volatile struct timeval *tp = (t); \ 390 register long us; \ 391 \ 392 tp->tv_usec = us = tp->tv_usec + (usec); \ 393 if (us >= 1000000) { \ 394 tp->tv_usec = us - 1000000; \ 395 tp->tv_sec++; \ 396 } \ 397 } 398 399 if (!is->is_sb) 400 return (0); 401 402 /* 403 * Streaming buffer flushes: 404 * 405 * 1 Tell strbuf to flush by storing va to strbuf_pgflush. If 406 * we're not on a cache line boundary (64-bits): 407 * 2 Store 0 in flag 408 * 3 Store pointer to flag in flushsync 409 * 4 wait till flushsync becomes 0x1 410 * 411 * If it takes more than .5 sec, something 412 * went wrong. 413 */ 414 415 is->is_flush = 0; 416 membar_sync(); 417 bus_space_write_8(is->is_bustag, (bus_space_handle_t)(u_long) 418 &is->is_sb->strbuf_flushsync, 0, is->is_flushpa); 419 membar_sync(); 420 421 microtime(&flushtimeout); 422 cur = flushtimeout; 423 BUMPTIME(&flushtimeout, 500000); /* 1/2 sec */ 424 425 DPRINTF(IDB_IOMMU, ("iommu_strbuf_flush: flush = %lx at va = %lx pa = %lx now=%lx:%lx until = %lx:%lx\n", 426 (long)is->is_flush, (long)&is->is_flush, 427 (long)is->is_flushpa, cur.tv_sec, cur.tv_usec, 428 flushtimeout.tv_sec, flushtimeout.tv_usec)); 429 /* Bypass non-coherent D$ */ 430 while (!ldxa(is->is_flushpa, ASI_PHYS_CACHED) && 431 ((cur.tv_sec <= flushtimeout.tv_sec) && 432 (cur.tv_usec <= flushtimeout.tv_usec))) 433 microtime(&cur); 434 435 #ifdef DIAGNOSTIC 436 if (!is->is_flush) { 437 printf("iommu_strbuf_flush: flush timeout %p at %p\n", (long)is->is_flush, 438 (long)is->is_flushpa); /* panic? */ 439 #ifdef DDB 440 Debugger(); 441 #endif 442 } 443 #endif 444 DPRINTF(IDB_IOMMU, ("iommu_strbuf_flush: flushed\n")); 445 return (is->is_flush); 446 } 447 448 /* 449 * IOMMU DVMA operations, common to SBUS and PCI. 450 */ 451 int 452 iommu_dvmamap_load(t, is, map, buf, buflen, p, flags) 453 bus_dma_tag_t t; 454 struct iommu_state *is; 455 bus_dmamap_t map; 456 void *buf; 457 bus_size_t buflen; 458 struct proc *p; 459 int flags; 460 { 461 int s; 462 int err; 463 bus_size_t sgsize; 464 paddr_t curaddr; 465 u_long dvmaddr; 466 bus_size_t align, boundary; 467 vaddr_t vaddr = (vaddr_t)buf; 468 pmap_t pmap; 469 470 if (map->dm_nsegs) { 471 /* Already in use?? */ 472 #ifdef DIAGNOSTIC 473 printf("iommu_dvmamap_load: map still in use\n"); 474 #endif 475 bus_dmamap_unload(t, map); 476 } 477 /* 478 * Make sure that on error condition we return "no valid mappings". 479 */ 480 map->dm_nsegs = 0; 481 482 if (buflen > map->_dm_size) { 483 DPRINTF(IDB_BUSDMA, 484 ("iommu_dvmamap_load(): error %d > %d -- " 485 "map size exceeded!\n", buflen, map->_dm_size)); 486 return (EINVAL); 487 } 488 489 sgsize = round_page(buflen + ((int)vaddr & PGOFSET)); 490 491 /* 492 * A boundary presented to bus_dmamem_alloc() takes precedence 493 * over boundary in the map. 494 */ 495 if ((boundary = (map->dm_segs[0]._ds_boundary)) == 0) 496 boundary = map->_dm_boundary; 497 align = max(map->dm_segs[0]._ds_align, NBPG); 498 s = splhigh(); 499 err = extent_alloc(is->is_dvmamap, sgsize, align, 500 boundary, EX_NOWAIT|EX_BOUNDZERO, (u_long *)&dvmaddr); 501 splx(s); 502 503 #ifdef DEBUG 504 if (err || (dvmaddr == (bus_addr_t)-1)) 505 { 506 printf("iommu_dvmamap_load(): extent_alloc(%d, %x) failed!\n", 507 sgsize, flags); 508 Debugger(); 509 } 510 #endif 511 if (err != 0) 512 return (err); 513 514 if (dvmaddr == (bus_addr_t)-1) 515 return (ENOMEM); 516 517 /* 518 * We always use just one segment. 519 */ 520 map->dm_mapsize = buflen; 521 map->dm_nsegs = 1; 522 map->dm_segs[0].ds_addr = dvmaddr + (vaddr & PGOFSET); 523 map->dm_segs[0].ds_len = buflen; 524 525 if (p != NULL) 526 pmap = p->p_vmspace->vm_map.pmap; 527 else 528 pmap = pmap_kernel(); 529 530 dvmaddr = trunc_page(map->dm_segs[0].ds_addr); 531 for (; buflen > 0; ) { 532 /* 533 * Get the physical address for this page. 534 */ 535 if (pmap_extract(pmap, (vaddr_t)vaddr, &curaddr) == FALSE) { 536 bus_dmamap_unload(t, map); 537 return (-1); 538 } 539 540 /* 541 * Compute the segment size, and adjust counts. 542 */ 543 sgsize = NBPG - ((u_long)vaddr & PGOFSET); 544 if (buflen < sgsize) 545 sgsize = buflen; 546 547 DPRINTF(IDB_BUSDMA, 548 ("iommu_dvmamap_load: map %p loading va %p dva %lx at pa %lx\n", 549 map, (void *)vaddr, (long)dvmaddr, (long)(curaddr&~(NBPG-1)))); 550 iommu_enter(is, trunc_page(dvmaddr), trunc_page(curaddr), 551 flags); 552 553 dvmaddr += PAGE_SIZE; 554 vaddr += sgsize; 555 buflen -= sgsize; 556 } 557 return (0); 558 } 559 560 561 void 562 iommu_dvmamap_unload(t, is, map) 563 bus_dma_tag_t t; 564 struct iommu_state *is; 565 bus_dmamap_t map; 566 { 567 vaddr_t addr; 568 size_t len; 569 int error, s; 570 bus_addr_t dvmaddr; 571 bus_size_t sgsize; 572 573 if (map->dm_nsegs != 1) 574 panic("iommu_dvmamap_unload: nsegs = %d", map->dm_nsegs); 575 576 addr = trunc_page(map->dm_segs[0].ds_addr); 577 len = map->dm_segs[0].ds_len; 578 579 DPRINTF(IDB_BUSDMA, 580 ("iommu_dvmamap_unload: map %p removing va %lx size %lx\n", 581 map, (long)addr, (long)len)); 582 iommu_remove(is, addr, len); 583 dvmaddr = (map->dm_segs[0].ds_addr & ~PGOFSET); 584 sgsize = round_page(map->dm_segs[0].ds_len + 585 ((int)map->dm_segs[0].ds_addr & PGOFSET)); 586 587 /* Mark the mappings as invalid. */ 588 map->dm_mapsize = 0; 589 map->dm_nsegs = 0; 590 591 s = splhigh(); 592 error = extent_free(is->is_dvmamap, dvmaddr, sgsize, EX_NOWAIT); 593 splx(s); 594 if (error != 0) 595 printf("warning: %qd of DVMA space lost\n", (long long)sgsize); 596 cache_flush((caddr_t)(u_long)dvmaddr, (u_int)sgsize); 597 } 598 599 600 int 601 iommu_dvmamap_load_raw(t, is, map, segs, nsegs, flags, size) 602 bus_dma_tag_t t; 603 struct iommu_state *is; 604 bus_dmamap_t map; 605 bus_dma_segment_t *segs; 606 int nsegs; 607 int flags; 608 bus_size_t size; 609 { 610 vm_page_t m; 611 int s; 612 int err; 613 bus_size_t sgsize; 614 paddr_t pa; 615 bus_size_t boundary, align; 616 u_long dvmaddr; 617 struct pglist *mlist; 618 int pagesz = PAGE_SIZE; 619 620 if (map->dm_nsegs) { 621 /* Already in use?? */ 622 #ifdef DIAGNOSTIC 623 printf("iommu_dvmamap_load_raw: map still in use\n"); 624 #endif 625 bus_dmamap_unload(t, map); 626 } 627 /* 628 * Make sure that on error condition we return "no valid mappings". 629 */ 630 map->dm_nsegs = 0; 631 #ifdef DIAGNOSTIC 632 /* XXX - unhelpful since we can't reset these in map_unload() */ 633 if (segs[0].ds_addr != 0) 634 panic("iommu_dvmamap_load_raw: segment already loaded: " 635 "addr %#llx, size %#llx", 636 (u_int64_t)segs[0].ds_addr, (u_int64_t)segs[0].ds_len); 637 if (segs[0].ds_len != size) 638 panic("iommu_dvmamap_load_raw: segment size changed: " 639 "ds_len %#llx size %#llx", segs[0].ds_len, size); 640 #endif 641 sgsize = round_page(size); 642 643 /* 644 * A boundary presented to bus_dmamem_alloc() takes precedence 645 * over boundary in the map. 646 */ 647 if ((boundary = segs[0]._ds_boundary) == 0) 648 boundary = map->_dm_boundary; 649 650 align = max(segs[0]._ds_align, NBPG); 651 s = splhigh(); 652 err = extent_alloc(is->is_dvmamap, sgsize, align, boundary, 653 ((flags & BUS_DMA_NOWAIT) == 0 ? EX_WAITOK : EX_NOWAIT)|EX_BOUNDZERO, 654 (u_long *)&dvmaddr); 655 splx(s); 656 657 if (err != 0) 658 return (err); 659 660 #ifdef DEBUG 661 if (dvmaddr == (bus_addr_t)-1) 662 { 663 printf("iommu_dvmamap_load_raw(): extent_alloc(%d, %x) failed!\n", 664 sgsize, flags); 665 Debugger(); 666 } 667 #endif 668 if (dvmaddr == (bus_addr_t)-1) 669 return (ENOMEM); 670 671 /* 672 * We always use just one segment. 673 */ 674 map->dm_mapsize = size; 675 map->dm_nsegs = 1; 676 map->dm_segs[0].ds_addr = dvmaddr; 677 map->dm_segs[0].ds_len = size; 678 679 mlist = segs[0]._ds_mlist; 680 for (m = TAILQ_FIRST(mlist); m != NULL; m = TAILQ_NEXT(m,pageq)) { 681 if (sgsize == 0) 682 panic("iommu_dmamap_load_raw: size botch"); 683 pa = VM_PAGE_TO_PHYS(m); 684 685 DPRINTF(IDB_BUSDMA, 686 ("iommu_dvmamap_load_raw: map %p loading va %lx at pa %lx\n", 687 map, (long)dvmaddr, (long)(pa))); 688 iommu_enter(is, dvmaddr, pa, flags); 689 690 dvmaddr += pagesz; 691 sgsize -= pagesz; 692 } 693 return (0); 694 } 695 696 void 697 iommu_dvmamap_sync(t, is, map, offset, len, ops) 698 bus_dma_tag_t t; 699 struct iommu_state *is; 700 bus_dmamap_t map; 701 bus_addr_t offset; 702 bus_size_t len; 703 int ops; 704 { 705 vaddr_t va = map->dm_segs[0].ds_addr + offset; 706 707 /* 708 * We only support one DMA segment; supporting more makes this code 709 * too unweildy. 710 */ 711 712 if (ops & BUS_DMASYNC_PREREAD) { 713 DPRINTF(IDB_BUSDMA, 714 ("iommu_dvmamap_sync: syncing va %p len %lu " 715 "BUS_DMASYNC_PREREAD\n", (long)va, (u_long)len)); 716 717 /* Nothing to do */; 718 } 719 if (ops & BUS_DMASYNC_POSTREAD) { 720 DPRINTF(IDB_BUSDMA, 721 ("iommu_dvmamap_sync: syncing va %p len %lu " 722 "BUS_DMASYNC_POSTREAD\n", (long)va, (u_long)len)); 723 /* if we have a streaming buffer, flush it here first */ 724 if (is->is_sb) 725 while (len > 0) { 726 DPRINTF(IDB_BUSDMA, 727 ("iommu_dvmamap_sync: flushing va %p, %lu " 728 "bytes left\n", (long)va, (u_long)len)); 729 bus_space_write_8(is->is_bustag, 730 (bus_space_handle_t)(u_long) 731 &is->is_sb->strbuf_pgflush, 0, va); 732 if (len <= NBPG) { 733 iommu_strbuf_flush(is); 734 len = 0; 735 } else 736 len -= NBPG; 737 va += NBPG; 738 } 739 } 740 if (ops & BUS_DMASYNC_PREWRITE) { 741 DPRINTF(IDB_BUSDMA, 742 ("iommu_dvmamap_sync: syncing va %p len %lu " 743 "BUS_DMASYNC_PREWRITE\n", (long)va, (u_long)len)); 744 /* Nothing to do */; 745 } 746 if (ops & BUS_DMASYNC_POSTWRITE) { 747 DPRINTF(IDB_BUSDMA, 748 ("iommu_dvmamap_sync: syncing va %p len %lu " 749 "BUS_DMASYNC_POSTWRITE\n", (long)va, (u_long)len)); 750 /* Nothing to do */; 751 } 752 } 753 754 int 755 iommu_dvmamem_alloc(t, is, size, alignment, boundary, segs, nsegs, rsegs, flags) 756 bus_dma_tag_t t; 757 struct iommu_state *is; 758 bus_size_t size, alignment, boundary; 759 bus_dma_segment_t *segs; 760 int nsegs; 761 int *rsegs; 762 int flags; 763 { 764 765 DPRINTF(IDB_BUSDMA, ("iommu_dvmamem_alloc: sz %qx align %qx bound %qx " 766 "segp %p flags %d\n", size, alignment, boundary, segs, flags)); 767 return (bus_dmamem_alloc(t->_parent, size, alignment, boundary, 768 segs, nsegs, rsegs, flags|BUS_DMA_DVMA)); 769 } 770 771 void 772 iommu_dvmamem_free(t, is, segs, nsegs) 773 bus_dma_tag_t t; 774 struct iommu_state *is; 775 bus_dma_segment_t *segs; 776 int nsegs; 777 { 778 779 DPRINTF(IDB_BUSDMA, ("iommu_dvmamem_free: segp %p nsegs %d\n", 780 segs, nsegs)); 781 bus_dmamem_free(t->_parent, segs, nsegs); 782 } 783 784 /* 785 * Map the DVMA mappings into the kernel pmap. 786 * Check the flags to see whether we're streaming or coherent. 787 */ 788 int 789 iommu_dvmamem_map(t, is, segs, nsegs, size, kvap, flags) 790 bus_dma_tag_t t; 791 struct iommu_state *is; 792 bus_dma_segment_t *segs; 793 int nsegs; 794 size_t size; 795 caddr_t *kvap; 796 int flags; 797 { 798 vm_page_t m; 799 vaddr_t va; 800 bus_addr_t addr; 801 struct pglist *mlist; 802 int cbit; 803 804 DPRINTF(IDB_BUSDMA, ("iommu_dvmamem_map: segp %p nsegs %d size %lx\n", 805 segs, nsegs, size)); 806 807 /* 808 * Allocate some space in the kernel map, and then map these pages 809 * into this space. 810 */ 811 size = round_page(size); 812 va = uvm_km_valloc(kernel_map, size); 813 if (va == 0) 814 return (ENOMEM); 815 816 *kvap = (caddr_t)va; 817 818 /* 819 * digest flags: 820 */ 821 cbit = 0; 822 if (flags & BUS_DMA_COHERENT) /* Disable vcache */ 823 cbit |= PMAP_NVC; 824 if (flags & BUS_DMA_NOCACHE) /* sideffects */ 825 cbit |= PMAP_NC; 826 827 /* 828 * Now take this and map it into the CPU. 829 */ 830 mlist = segs[0]._ds_mlist; 831 for (m = mlist->tqh_first; m != NULL; m = m->pageq.tqe_next) { 832 #ifdef DIAGNOSTIC 833 if (size == 0) 834 panic("iommu_dvmamem_map: size botch"); 835 #endif 836 addr = VM_PAGE_TO_PHYS(m); 837 DPRINTF(IDB_BUSDMA, ("iommu_dvmamem_map: " 838 "mapping va %lx at %qx\n", va, addr | cbit)); 839 pmap_enter(pmap_kernel(), va, addr | cbit, 840 VM_PROT_READ | VM_PROT_WRITE, PMAP_WIRED); 841 va += PAGE_SIZE; 842 size -= PAGE_SIZE; 843 } 844 845 return (0); 846 } 847 848 /* 849 * Unmap DVMA mappings from kernel 850 */ 851 void 852 iommu_dvmamem_unmap(t, is, kva, size) 853 bus_dma_tag_t t; 854 struct iommu_state *is; 855 caddr_t kva; 856 size_t size; 857 { 858 859 DPRINTF(IDB_BUSDMA, ("iommu_dvmamem_unmap: kvm %p size %lx\n", 860 kva, size)); 861 862 #ifdef DIAGNOSTIC 863 if ((u_long)kva & PGOFSET) 864 panic("iommu_dvmamem_unmap"); 865 #endif 866 867 size = round_page(size); 868 pmap_remove(pmap_kernel(), (vaddr_t)kva, size); 869 #if 0 870 /* 871 * XXX ? is this necessary? i think so and i think other 872 * implementations are missing it. 873 */ 874 uvm_km_free(kernel_map, (vaddr_t)kva, size); 875 #endif 876 } 877
Indexes created Thu Sep 25 16:09:42 GMT 2025