iommu.c revision 1.25
1 /* $NetBSD: iommu.c,v 1.25 2000/12/06 01:47:49 mrg Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000 Matthew R. Green 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 23 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 24 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 25 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 /*- 32 * Copyright (c) 1998 The NetBSD Foundation, Inc. 33 * All rights reserved. 34 * 35 * This code is derived from software contributed to The NetBSD Foundation 36 * by Paul Kranenburg. 37 * 38 * Redistribution and use in source and binary forms, with or without 39 * modification, are permitted provided that the following conditions 40 * are met: 41 * 1. Redistributions of source code must retain the above copyright 42 * notice, this list of conditions and the following disclaimer. 43 * 2. Redistributions in binary form must reproduce the above copyright 44 * notice, this list of conditions and the following disclaimer in the 45 * documentation and/or other materials provided with the distribution. 46 * 3. All advertising materials mentioning features or use of this software 47 * must display the following acknowledgement: 48 * This product includes software developed by the NetBSD 49 * Foundation, Inc. and its contributors. 50 * 4. Neither the name of The NetBSD Foundation nor the names of its 51 * contributors may be used to endorse or promote products derived 52 * from this software without specific prior written permission. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 55 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 56 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 57 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 58 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 59 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 60 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 61 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 62 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 63 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 64 * POSSIBILITY OF SUCH DAMAGE. 65 */ 66 67 /* 68 * Copyright (c) 1992, 1993 69 * The Regents of the University of California. All rights reserved. 70 * 71 * This software was developed by the Computer Systems Engineering group 72 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 73 * contributed to Berkeley. 74 * 75 * All advertising materials mentioning features or use of this software 76 * must display the following acknowledgement: 77 * This product includes software developed by the University of 78 * California, Lawrence Berkeley Laboratory. 79 * 80 * Redistribution and use in source and binary forms, with or without 81 * modification, are permitted provided that the following conditions 82 * are met: 83 * 1. Redistributions of source code must retain the above copyright 84 * notice, this list of conditions and the following disclaimer. 85 * 2. Redistributions in binary form must reproduce the above copyright 86 * notice, this list of conditions and the following disclaimer in the 87 * documentation and/or other materials provided with the distribution. 88 * 3. All advertising materials mentioning features or use of this software 89 * must display the following acknowledgement: 90 * This product includes software developed by the University of 91 * California, Berkeley and its contributors. 92 * 4. Neither the name of the University nor the names of its contributors 93 * may be used to endorse or promote products derived from this software 94 * without specific prior written permission. 95 * 96 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 97 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 98 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 99 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 100 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 101 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 102 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 103 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 104 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 105 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 106 * SUCH DAMAGE. 107 * 108 * from: NetBSD: sbus.c,v 1.13 1999/05/23 07:24:02 mrg Exp 109 * from: @(#)sbus.c 8.1 (Berkeley) 6/11/93 110 */ 111 112 /* 113 * UltraSPARC IOMMU support; used by both the sbus and pci code. 114 */ 115 #include "opt_ddb.h" 116 117 #include <sys/param.h> 118 #include <sys/extent.h> 119 #include <sys/malloc.h> 120 #include <sys/systm.h> 121 #include <sys/device.h> 122 123 #include <uvm/uvm_extern.h> 124 125 #include <machine/bus.h> 126 #include <sparc64/sparc64/cache.h> 127 #include <sparc64/dev/iommureg.h> 128 #include <sparc64/dev/iommuvar.h> 129 130 #include <machine/autoconf.h> 131 #include <machine/cpu.h> 132 133 #ifdef DEBUG 134 #define IDB_BUSDMA 0x1 135 #define IDB_IOMMU 0x2 136 #define IDB_INFO 0x4 137 int iommudebug = 0x0; 138 #define DPRINTF(l, s) do { if (iommudebug & l) printf s; } while (0) 139 #else 140 #define DPRINTF(l, s) 141 #endif 142 143 static int iommu_strbuf_flush __P((struct iommu_state *)); 144 145 /* 146 * initialise the UltraSPARC IOMMU (SBUS or PCI): 147 * - allocate and setup the iotsb. 148 * - enable the IOMMU 149 * - initialise the streaming buffers (if they exist) 150 * - create a private DVMA map. 151 */ 152 void 153 iommu_init(name, is, tsbsize) 154 char *name; 155 struct iommu_state *is; 156 int tsbsize; 157 { 158 psize_t size; 159 vaddr_t va; 160 paddr_t pa; 161 vm_page_t m; 162 struct pglist mlist; 163 164 /* 165 * Setup the iommu. 166 * 167 * The sun4u iommu is part of the SBUS or PCI controller so we 168 * will deal with it here.. 169 * 170 * The IOMMU address space always ends at 0xffffe000, but the starting 171 * address depends on the size of the map. The map size is 1024 * 2 ^ 172 * is->is_tsbsize entries, where each entry is 8 bytes. The start of 173 * the map can be calculated by (0xffffe000 << (8 + is->is_tsbsize)). 174 * 175 * Note: the stupid IOMMU ignores the high bits of an address, so a 176 * NULL DMA pointer will be translated by the first page of the IOTSB. 177 * To trap bugs we'll skip the first entry in the IOTSB. 178 */ 179 is->is_cr = (tsbsize << 16) | IOMMUCR_EN; 180 is->is_tsbsize = tsbsize; 181 is->is_dvmabase = IOTSB_VSTART(is->is_tsbsize) + NBPG; 182 183 /* 184 * Allocate memory for I/O pagetables. They need to be physically 185 * contiguous. 186 */ 187 188 size = NBPG<<(is->is_tsbsize); 189 TAILQ_INIT(&mlist); 190 if (uvm_pglistalloc((psize_t)size, (paddr_t)0, (paddr_t)-1, 191 (paddr_t)NBPG, (paddr_t)0, &mlist, 1, 0) != 0) 192 panic("iommu_init: no memory"); 193 194 va = uvm_km_valloc(kernel_map, size); 195 if (va == 0) 196 panic("iommu_init: no memory"); 197 is->is_tsb = (int64_t *)va; 198 199 m = TAILQ_FIRST(&mlist); 200 is->is_ptsb = VM_PAGE_TO_PHYS(m); 201 202 /* Map the pages */ 203 for (; m != NULL; m = TAILQ_NEXT(m,pageq)) { 204 pa = VM_PAGE_TO_PHYS(m); 205 pmap_enter(pmap_kernel(), va, pa | PMAP_NVC, 206 VM_PROT_READ|VM_PROT_WRITE, 207 VM_PROT_READ|VM_PROT_WRITE|PMAP_WIRED); 208 va += NBPG; 209 } 210 bzero(is->is_tsb, size); 211 212 #ifdef DEBUG 213 if (iommudebug & IDB_INFO) 214 { 215 /* Probe the iommu */ 216 struct iommureg *regs = is->is_iommu; 217 218 printf("iommu regs at: cr=%lx tsb=%lx flush=%lx\n", 219 (u_long)®s->iommu_cr, 220 (u_long)®s->iommu_tsb, 221 (u_long)®s->iommu_flush); 222 printf("iommu cr=%llx tsb=%llx\n", (unsigned long long)regs->iommu_cr, (unsigned long long)regs->iommu_tsb); 223 printf("TSB base %p phys %llx\n", (void *)is->is_tsb, (unsigned long long)is->is_ptsb); 224 delay(1000000); /* 1 s */ 225 } 226 #endif 227 228 /* 229 * Initialize streaming buffer, if it is there. 230 */ 231 if (is->is_sb) 232 (void)pmap_extract(pmap_kernel(), (vaddr_t)&is->is_flush, 233 (paddr_t *)&is->is_flushpa); 234 235 /* 236 * now actually start up the IOMMU 237 */ 238 iommu_reset(is); 239 240 /* 241 * Now all the hardware's working we need to allocate a dvma map. 242 */ 243 printf("DVMA map: %x to %x\n", 244 (unsigned int)is->is_dvmabase, 245 (unsigned int)IOTSB_VEND); 246 is->is_dvmamap = extent_create(name, 247 is->is_dvmabase, (u_long)IOTSB_VEND, 248 M_DEVBUF, 0, 0, EX_NOWAIT); 249 } 250 251 /* 252 * Streaming buffers don't exist on the UltraSPARC IIi; we should have 253 * detected that already and disabled them. If not, we will notice that 254 * they aren't there when the STRBUF_EN bit does not remain. 255 */ 256 void 257 iommu_reset(is) 258 struct iommu_state *is; 259 { 260 261 /* Need to do 64-bit stores */ 262 bus_space_write_8(is->is_bustag, 263 (bus_space_handle_t)(u_long)&is->is_iommu->iommu_tsb, 264 0, is->is_ptsb); 265 /* Enable IOMMU in diagnostic mode */ 266 bus_space_write_8(is->is_bustag, 267 (bus_space_handle_t)(u_long)&is->is_iommu->iommu_cr, 0, 268 is->is_cr|IOMMUCR_DE); 269 270 271 if (!is->is_sb) 272 return; 273 274 /* Enable diagnostics mode? */ 275 bus_space_write_8(is->is_bustag, 276 (bus_space_handle_t)(u_long)&is->is_sb->strbuf_ctl, 277 0, STRBUF_EN); 278 279 /* No streaming buffers? Disable them */ 280 if (bus_space_read_8(is->is_bustag, 281 (bus_space_handle_t)(u_long)&is->is_sb->strbuf_ctl, 282 0) == 0) 283 is->is_sb = 0; 284 } 285 286 /* 287 * Here are the iommu control routines. 288 */ 289 void 290 iommu_enter(is, va, pa, flags) 291 struct iommu_state *is; 292 vaddr_t va; 293 int64_t pa; 294 int flags; 295 { 296 int64_t tte; 297 298 #ifdef DIAGNOSTIC 299 if (va < is->is_dvmabase) 300 panic("iommu_enter: va %#lx not in DVMA space", va); 301 #endif 302 303 tte = MAKEIOTTE(pa, !(flags&BUS_DMA_NOWRITE), !(flags&BUS_DMA_NOCACHE), 304 !(flags&BUS_DMA_COHERENT)); 305 306 /* Is the streamcache flush really needed? */ 307 if (is->is_sb) { 308 bus_space_write_8(is->is_bustag, (bus_space_handle_t)(u_long) 309 &is->is_sb->strbuf_pgflush, 0, va); 310 iommu_strbuf_flush(is); 311 } 312 DPRINTF(IDB_IOMMU, ("Clearing TSB slot %d for va %p\n", 313 (int)IOTSBSLOT(va,is->is_tsbsize), (void *)(u_long)va)); 314 is->is_tsb[IOTSBSLOT(va,is->is_tsbsize)] = tte; 315 bus_space_write_8(is->is_bustag, (bus_space_handle_t)(u_long) 316 &is->is_iommu->iommu_flush, 0, va); 317 DPRINTF(IDB_IOMMU, ("iommu_enter: va %lx pa %lx TSB[%lx]@%p=%lx\n", 318 va, (long)pa, (u_long)IOTSBSLOT(va,is->is_tsbsize), 319 (void *)(u_long)&is->is_tsb[IOTSBSLOT(va,is->is_tsbsize)], 320 (u_long)tte)); 321 } 322 323 /* 324 * iommu_remove: removes mappings created by iommu_enter 325 * 326 * Only demap from IOMMU if flag is set. 327 * 328 * XXX: this function needs better internal error checking. 329 */ 330 void 331 iommu_remove(is, va, len) 332 struct iommu_state *is; 333 vaddr_t va; 334 size_t len; 335 { 336 337 #ifdef DIAGNOSTIC 338 if (va < is->is_dvmabase) 339 panic("iommu_remove: va 0x%lx not in DVMA space", (u_long)va); 340 if ((long)(va + len) < (long)va) 341 panic("iommu_remove: va 0x%lx + len 0x%lx wraps", 342 (long) va, (long) len); 343 if (len & ~0xfffffff) 344 panic("iommu_remove: rediculous len 0x%lx", (u_long)len); 345 #endif 346 347 va = trunc_page(va); 348 DPRINTF(IDB_IOMMU, ("iommu_remove: va %lx TSB[%lx]@%p\n", 349 va, (u_long)IOTSBSLOT(va,is->is_tsbsize), 350 &is->is_tsb[IOTSBSLOT(va,is->is_tsbsize)])); 351 while (len > 0) { 352 DPRINTF(IDB_IOMMU, ("iommu_remove: clearing TSB slot %d for va %p size %lx\n", 353 (int)IOTSBSLOT(va,is->is_tsbsize), (void *)(u_long)va, (u_long)len)); 354 if (is->is_sb) { 355 DPRINTF(IDB_IOMMU, ("iommu_remove: flushing va %p TSB[%lx]@%p=%lx, %lu bytes left\n", 356 (void *)(u_long)va, (long)IOTSBSLOT(va,is->is_tsbsize), 357 (void *)(u_long)&is->is_tsb[IOTSBSLOT(va,is->is_tsbsize)], 358 (long)(is->is_tsb[IOTSBSLOT(va,is->is_tsbsize)]), 359 (u_long)len)); 360 bus_space_write_8(is->is_bustag, (bus_space_handle_t)(u_long) 361 &is->is_sb->strbuf_pgflush, 0, va); 362 if (len <= NBPG) 363 iommu_strbuf_flush(is); 364 DPRINTF(IDB_IOMMU, ("iommu_remove: flushed va %p TSB[%lx]@%p=%lx, %lu bytes left\n", 365 (void *)(u_long)va, (long)IOTSBSLOT(va,is->is_tsbsize), 366 (void *)(u_long)&is->is_tsb[IOTSBSLOT(va,is->is_tsbsize)], 367 (long)(is->is_tsb[IOTSBSLOT(va,is->is_tsbsize)]), 368 (u_long)len)); 369 } else 370 membar_sync(); /* XXX */ 371 372 if (len <= NBPG) 373 len = 0; 374 else 375 len -= NBPG; 376 377 is->is_tsb[IOTSBSLOT(va,is->is_tsbsize)] = 0; 378 bus_space_write_8(is->is_bustag, (bus_space_handle_t)(u_long) 379 &is->is_iommu->iommu_flush, 0, va); 380 va += NBPG; 381 } 382 } 383 384 static int 385 iommu_strbuf_flush(is) 386 struct iommu_state *is; 387 { 388 struct timeval cur, flushtimeout; 389 390 #define BUMPTIME(t, usec) { \ 391 register volatile struct timeval *tp = (t); \ 392 register long us; \ 393 \ 394 tp->tv_usec = us = tp->tv_usec + (usec); \ 395 if (us >= 1000000) { \ 396 tp->tv_usec = us - 1000000; \ 397 tp->tv_sec++; \ 398 } \ 399 } 400 401 if (!is->is_sb) 402 return (0); 403 404 /* 405 * Streaming buffer flushes: 406 * 407 * 1 Tell strbuf to flush by storing va to strbuf_pgflush. If 408 * we're not on a cache line boundary (64-bits): 409 * 2 Store 0 in flag 410 * 3 Store pointer to flag in flushsync 411 * 4 wait till flushsync becomes 0x1 412 * 413 * If it takes more than .5 sec, something 414 * went wrong. 415 */ 416 417 is->is_flush = 0; 418 membar_sync(); 419 bus_space_write_8(is->is_bustag, (bus_space_handle_t)(u_long) 420 &is->is_sb->strbuf_flushsync, 0, is->is_flushpa); 421 membar_sync(); 422 423 microtime(&flushtimeout); 424 cur = flushtimeout; 425 BUMPTIME(&flushtimeout, 500000); /* 1/2 sec */ 426 427 DPRINTF(IDB_IOMMU, ("iommu_strbuf_flush: flush = %lx at va = %lx pa = %lx now=%lx:%lx until = %lx:%lx\n", 428 (long)is->is_flush, (long)&is->is_flush, 429 (long)is->is_flushpa, cur.tv_sec, cur.tv_usec, 430 flushtimeout.tv_sec, flushtimeout.tv_usec)); 431 /* Bypass non-coherent D$ */ 432 while (!ldxa(is->is_flushpa, ASI_PHYS_CACHED) && 433 ((cur.tv_sec <= flushtimeout.tv_sec) && 434 (cur.tv_usec <= flushtimeout.tv_usec))) 435 microtime(&cur); 436 437 #ifdef DIAGNOSTIC 438 if (!is->is_flush) { 439 printf("iommu_strbuf_flush: flush timeout %p at %p\n", 440 (void *)(u_long)is->is_flush, 441 (void *)(u_long)is->is_flushpa); /* panic? */ 442 #ifdef DDB 443 Debugger(); 444 #endif 445 } 446 #endif 447 DPRINTF(IDB_IOMMU, ("iommu_strbuf_flush: flushed\n")); 448 return (is->is_flush); 449 } 450 451 /* 452 * IOMMU DVMA operations, common to SBUS and PCI. 453 */ 454 int 455 iommu_dvmamap_load(t, is, map, buf, buflen, p, flags) 456 bus_dma_tag_t t; 457 struct iommu_state *is; 458 bus_dmamap_t map; 459 void *buf; 460 bus_size_t buflen; 461 struct proc *p; 462 int flags; 463 { 464 int s; 465 int err; 466 bus_size_t sgsize; 467 paddr_t curaddr; 468 u_long dvmaddr; 469 bus_size_t align, boundary; 470 vaddr_t vaddr = (vaddr_t)buf; 471 pmap_t pmap; 472 473 if (map->dm_nsegs) { 474 /* Already in use?? */ 475 #ifdef DIAGNOSTIC 476 printf("iommu_dvmamap_load: map still in use\n"); 477 #endif 478 bus_dmamap_unload(t, map); 479 } 480 /* 481 * Make sure that on error condition we return "no valid mappings". 482 */ 483 map->dm_nsegs = 0; 484 485 if (buflen > map->_dm_size) { 486 DPRINTF(IDB_BUSDMA, 487 ("iommu_dvmamap_load(): error %d > %d -- " 488 "map size exceeded!\n", (int)buflen, (int)map->_dm_size)); 489 return (EINVAL); 490 } 491 492 sgsize = round_page(buflen + ((int)vaddr & PGOFSET)); 493 494 /* 495 * A boundary presented to bus_dmamem_alloc() takes precedence 496 * over boundary in the map. 497 */ 498 if ((boundary = (map->dm_segs[0]._ds_boundary)) == 0) 499 boundary = map->_dm_boundary; 500 align = max(map->dm_segs[0]._ds_align, NBPG); 501 s = splhigh(); 502 err = extent_alloc(is->is_dvmamap, sgsize, align, 503 boundary, EX_NOWAIT|EX_BOUNDZERO, (u_long *)&dvmaddr); 504 splx(s); 505 506 #ifdef DEBUG 507 if (err || (dvmaddr == (bus_addr_t)-1)) 508 { 509 printf("iommu_dvmamap_load(): extent_alloc(%d, %x) failed!\n", 510 (int)sgsize, flags); 511 Debugger(); 512 } 513 #endif 514 if (err != 0) 515 return (err); 516 517 if (dvmaddr == (bus_addr_t)-1) 518 return (ENOMEM); 519 520 /* 521 * We always use just one segment. 522 */ 523 map->dm_mapsize = buflen; 524 map->dm_nsegs = 1; 525 map->dm_segs[0].ds_addr = dvmaddr + (vaddr & PGOFSET); 526 map->dm_segs[0].ds_len = buflen; 527 528 if (p != NULL) 529 pmap = p->p_vmspace->vm_map.pmap; 530 else 531 pmap = pmap_kernel(); 532 533 dvmaddr = trunc_page(map->dm_segs[0].ds_addr); 534 for (; buflen > 0; ) { 535 /* 536 * Get the physical address for this page. 537 */ 538 if (pmap_extract(pmap, (vaddr_t)vaddr, &curaddr) == FALSE) { 539 bus_dmamap_unload(t, map); 540 return (-1); 541 } 542 543 /* 544 * Compute the segment size, and adjust counts. 545 */ 546 sgsize = NBPG - ((u_long)vaddr & PGOFSET); 547 if (buflen < sgsize) 548 sgsize = buflen; 549 550 DPRINTF(IDB_BUSDMA, 551 ("iommu_dvmamap_load: map %p loading va %p dva %lx at pa %lx\n", 552 map, (void *)vaddr, (long)dvmaddr, (long)(curaddr&~(NBPG-1)))); 553 iommu_enter(is, trunc_page(dvmaddr), trunc_page(curaddr), 554 flags); 555 556 dvmaddr += PAGE_SIZE; 557 vaddr += sgsize; 558 buflen -= sgsize; 559 } 560 return (0); 561 } 562 563 564 void 565 iommu_dvmamap_unload(t, is, map) 566 bus_dma_tag_t t; 567 struct iommu_state *is; 568 bus_dmamap_t map; 569 { 570 vaddr_t addr; 571 size_t len; 572 int error, s; 573 bus_addr_t dvmaddr; 574 bus_size_t sgsize; 575 576 if (map->dm_nsegs != 1) 577 panic("iommu_dvmamap_unload: nsegs = %d", map->dm_nsegs); 578 579 addr = trunc_page(map->dm_segs[0].ds_addr); 580 len = map->dm_segs[0].ds_len; 581 582 DPRINTF(IDB_BUSDMA, 583 ("iommu_dvmamap_unload: map %p removing va %lx size %lx\n", 584 map, (long)addr, (long)len)); 585 iommu_remove(is, addr, len); 586 dvmaddr = (map->dm_segs[0].ds_addr & ~PGOFSET); 587 sgsize = round_page(map->dm_segs[0].ds_len + 588 ((int)map->dm_segs[0].ds_addr & PGOFSET)); 589 590 /* Flush the caches */ 591 bus_dmamap_unload(t->_parent, map); 592 593 /* Mark the mappings as invalid. */ 594 map->dm_mapsize = 0; 595 map->dm_nsegs = 0; 596 597 s = splhigh(); 598 error = extent_free(is->is_dvmamap, dvmaddr, sgsize, EX_NOWAIT); 599 splx(s); 600 if (error != 0) 601 printf("warning: %qd of DVMA space lost\n", (long long)sgsize); 602 } 603 604 605 int 606 iommu_dvmamap_load_raw(t, is, map, segs, nsegs, flags, size) 607 bus_dma_tag_t t; 608 struct iommu_state *is; 609 bus_dmamap_t map; 610 bus_dma_segment_t *segs; 611 int nsegs; 612 int flags; 613 bus_size_t size; 614 { 615 vm_page_t m; 616 int s; 617 int err; 618 bus_size_t sgsize; 619 paddr_t pa; 620 bus_size_t boundary, align; 621 u_long dvmaddr; 622 struct pglist *mlist; 623 int pagesz = PAGE_SIZE; 624 625 if (map->dm_nsegs) { 626 /* Already in use?? */ 627 #ifdef DIAGNOSTIC 628 printf("iommu_dvmamap_load_raw: map still in use\n"); 629 #endif 630 bus_dmamap_unload(t, map); 631 } 632 /* 633 * Make sure that on error condition we return "no valid mappings". 634 */ 635 map->dm_nsegs = 0; 636 #ifdef DIAGNOSTIC 637 /* XXX - unhelpful since we can't reset these in map_unload() */ 638 if (segs[0].ds_addr != 0) 639 panic("iommu_dvmamap_load_raw: segment already loaded: " 640 "addr %#llx, size %#llx", 641 (unsigned long long)segs[0].ds_addr, 642 (unsigned long long)segs[0].ds_len); 643 if (segs[0].ds_len != size) 644 panic("iommu_dvmamap_load_raw: segment size changed: " 645 "ds_len %#llx size %#llx", 646 (unsigned long long)segs[0].ds_len, 647 (unsigned long long)size); 648 #endif 649 sgsize = round_page(size); 650 651 /* 652 * A boundary presented to bus_dmamem_alloc() takes precedence 653 * over boundary in the map. 654 */ 655 if ((boundary = segs[0]._ds_boundary) == 0) 656 boundary = map->_dm_boundary; 657 658 align = max(segs[0]._ds_align, NBPG); 659 s = splhigh(); 660 err = extent_alloc(is->is_dvmamap, sgsize, align, boundary, 661 ((flags & BUS_DMA_NOWAIT) == 0 ? EX_WAITOK : EX_NOWAIT)|EX_BOUNDZERO, 662 (u_long *)&dvmaddr); 663 splx(s); 664 665 if (err != 0) 666 return (err); 667 668 #ifdef DEBUG 669 if (dvmaddr == (bus_addr_t)-1) 670 { 671 printf("iommu_dvmamap_load_raw(): extent_alloc(%d, %x) failed!\n", 672 (int)sgsize, flags); 673 Debugger(); 674 } 675 #endif 676 if (dvmaddr == (bus_addr_t)-1) 677 return (ENOMEM); 678 679 /* 680 * We always use just one segment. 681 */ 682 map->dm_mapsize = size; 683 map->dm_nsegs = 1; 684 map->dm_segs[0].ds_addr = dvmaddr; 685 map->dm_segs[0].ds_len = size; 686 687 mlist = segs[0]._ds_mlist; 688 for (m = TAILQ_FIRST(mlist); m != NULL; m = TAILQ_NEXT(m,pageq)) { 689 if (sgsize == 0) 690 panic("iommu_dmamap_load_raw: size botch"); 691 pa = VM_PAGE_TO_PHYS(m); 692 693 DPRINTF(IDB_BUSDMA, 694 ("iommu_dvmamap_load_raw: map %p loading va %lx at pa %lx\n", 695 map, (long)dvmaddr, (long)(pa))); 696 iommu_enter(is, dvmaddr, pa, flags); 697 698 dvmaddr += pagesz; 699 sgsize -= pagesz; 700 } 701 return (0); 702 } 703 704 void 705 iommu_dvmamap_sync(t, is, map, offset, len, ops) 706 bus_dma_tag_t t; 707 struct iommu_state *is; 708 bus_dmamap_t map; 709 bus_addr_t offset; 710 bus_size_t len; 711 int ops; 712 { 713 vaddr_t va = map->dm_segs[0].ds_addr + offset; 714 715 /* 716 * We only support one DMA segment; supporting more makes this code 717 * too unweildy. 718 */ 719 720 if (ops & BUS_DMASYNC_PREREAD) { 721 DPRINTF(IDB_BUSDMA, 722 ("iommu_dvmamap_sync: syncing va %p len %lu " 723 "BUS_DMASYNC_PREREAD\n", (void *)(u_long)va, (u_long)len)); 724 725 /* Nothing to do */; 726 } 727 if (ops & BUS_DMASYNC_POSTREAD) { 728 DPRINTF(IDB_BUSDMA, 729 ("iommu_dvmamap_sync: syncing va %p len %lu " 730 "BUS_DMASYNC_POSTREAD\n", (void *)(u_long)va, (u_long)len)); 731 /* if we have a streaming buffer, flush it here first */ 732 if (is->is_sb) 733 while (len > 0) { 734 DPRINTF(IDB_BUSDMA, 735 ("iommu_dvmamap_sync: flushing va %p, %lu " 736 "bytes left\n", (void *)(u_long)va, (u_long)len)); 737 bus_space_write_8(is->is_bustag, 738 (bus_space_handle_t)(u_long) 739 &is->is_sb->strbuf_pgflush, 0, va); 740 if (len <= NBPG) { 741 iommu_strbuf_flush(is); 742 len = 0; 743 } else 744 len -= NBPG; 745 va += NBPG; 746 } 747 } 748 if (ops & BUS_DMASYNC_PREWRITE) { 749 DPRINTF(IDB_BUSDMA, 750 ("iommu_dvmamap_sync: syncing va %p len %lu " 751 "BUS_DMASYNC_PREWRITE\n", (void *)(u_long)va, (u_long)len)); 752 /* Nothing to do */; 753 } 754 if (ops & BUS_DMASYNC_POSTWRITE) { 755 DPRINTF(IDB_BUSDMA, 756 ("iommu_dvmamap_sync: syncing va %p len %lu " 757 "BUS_DMASYNC_POSTWRITE\n", (void *)(u_long)va, (u_long)len)); 758 /* Nothing to do */; 759 } 760 } 761 762 int 763 iommu_dvmamem_alloc(t, is, size, alignment, boundary, segs, nsegs, rsegs, flags) 764 bus_dma_tag_t t; 765 struct iommu_state *is; 766 bus_size_t size, alignment, boundary; 767 bus_dma_segment_t *segs; 768 int nsegs; 769 int *rsegs; 770 int flags; 771 { 772 773 DPRINTF(IDB_BUSDMA, ("iommu_dvmamem_alloc: sz %llx align %llx bound %llx " 774 "segp %p flags %d\n", (unsigned long long)size, 775 (unsigned long long)alignment, (unsigned long long)boundary, 776 segs, flags)); 777 return (bus_dmamem_alloc(t->_parent, size, alignment, boundary, 778 segs, nsegs, rsegs, flags|BUS_DMA_DVMA)); 779 } 780 781 void 782 iommu_dvmamem_free(t, is, segs, nsegs) 783 bus_dma_tag_t t; 784 struct iommu_state *is; 785 bus_dma_segment_t *segs; 786 int nsegs; 787 { 788 789 DPRINTF(IDB_BUSDMA, ("iommu_dvmamem_free: segp %p nsegs %d\n", 790 segs, nsegs)); 791 bus_dmamem_free(t->_parent, segs, nsegs); 792 } 793 794 /* 795 * Map the DVMA mappings into the kernel pmap. 796 * Check the flags to see whether we're streaming or coherent. 797 */ 798 int 799 iommu_dvmamem_map(t, is, segs, nsegs, size, kvap, flags) 800 bus_dma_tag_t t; 801 struct iommu_state *is; 802 bus_dma_segment_t *segs; 803 int nsegs; 804 size_t size; 805 caddr_t *kvap; 806 int flags; 807 { 808 vm_page_t m; 809 vaddr_t va; 810 bus_addr_t addr; 811 struct pglist *mlist; 812 int cbit; 813 814 DPRINTF(IDB_BUSDMA, ("iommu_dvmamem_map: segp %p nsegs %d size %lx\n", 815 segs, nsegs, size)); 816 817 /* 818 * Allocate some space in the kernel map, and then map these pages 819 * into this space. 820 */ 821 size = round_page(size); 822 va = uvm_km_valloc(kernel_map, size); 823 if (va == 0) 824 return (ENOMEM); 825 826 *kvap = (caddr_t)va; 827 828 /* 829 * digest flags: 830 */ 831 cbit = 0; 832 if (flags & BUS_DMA_COHERENT) /* Disable vcache */ 833 cbit |= PMAP_NVC; 834 if (flags & BUS_DMA_NOCACHE) /* sideffects */ 835 cbit |= PMAP_NC; 836 837 /* 838 * Now take this and map it into the CPU. 839 */ 840 mlist = segs[0]._ds_mlist; 841 for (m = mlist->tqh_first; m != NULL; m = m->pageq.tqe_next) { 842 #ifdef DIAGNOSTIC 843 if (size == 0) 844 panic("iommu_dvmamem_map: size botch"); 845 #endif 846 addr = VM_PAGE_TO_PHYS(m); 847 DPRINTF(IDB_BUSDMA, ("iommu_dvmamem_map: " 848 "mapping va %lx at %llx\n", va, (unsigned long long)addr | cbit)); 849 pmap_enter(pmap_kernel(), va, addr | cbit, 850 VM_PROT_READ | VM_PROT_WRITE, 851 VM_PROT_READ | VM_PROT_WRITE | PMAP_WIRED); 852 va += PAGE_SIZE; 853 size -= PAGE_SIZE; 854 } 855 856 return (0); 857 } 858 859 /* 860 * Unmap DVMA mappings from kernel 861 */ 862 void 863 iommu_dvmamem_unmap(t, is, kva, size) 864 bus_dma_tag_t t; 865 struct iommu_state *is; 866 caddr_t kva; 867 size_t size; 868 { 869 870 DPRINTF(IDB_BUSDMA, ("iommu_dvmamem_unmap: kvm %p size %lx\n", 871 kva, size)); 872 873 #ifdef DIAGNOSTIC 874 if ((u_long)kva & PGOFSET) 875 panic("iommu_dvmamem_unmap"); 876 #endif 877 878 size = round_page(size); 879 pmap_remove(pmap_kernel(), (vaddr_t)kva, size); 880 #if 0 881 /* 882 * XXX ? is this necessary? i think so and i think other 883 * implementations are missing it. 884 */ 885 uvm_km_free(kernel_map, (vaddr_t)kva, size); 886 #endif 887 } 888
Indexes created Sat Sep 27 14:09:57 GMT 2025