iommu.c revision 1.3
1 /* $NetBSD: iommu.c,v 1.3 1999/07/08 18:08:59 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Copyright (c) 1992, 1993 41 * The Regents of the University of California. All rights reserved. 42 * 43 * This software was developed by the Computer Systems Engineering group 44 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 45 * contributed to Berkeley. 46 * 47 * All advertising materials mentioning features or use of this software 48 * must display the following acknowledgement: 49 * This product includes software developed by the University of 50 * California, Lawrence Berkeley Laboratory. 51 * 52 * Redistribution and use in source and binary forms, with or without 53 * modification, are permitted provided that the following conditions 54 * are met: 55 * 1. Redistributions of source code must retain the above copyright 56 * notice, this list of conditions and the following disclaimer. 57 * 2. Redistributions in binary form must reproduce the above copyright 58 * notice, this list of conditions and the following disclaimer in the 59 * documentation and/or other materials provided with the distribution. 60 * 3. All advertising materials mentioning features or use of this software 61 * must display the following acknowledgement: 62 * This product includes software developed by the University of 63 * California, Berkeley and its contributors. 64 * 4. Neither the name of the University nor the names of its contributors 65 * may be used to endorse or promote products derived from this software 66 * without specific prior written permission. 67 * 68 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 69 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 70 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 71 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 72 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 73 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 74 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 75 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 76 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 77 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 78 * SUCH DAMAGE. 79 * 80 * from: NetBSD: sbus.c,v 1.13 1999/05/23 07:24:02 mrg Exp 81 * from: @(#)sbus.c 8.1 (Berkeley) 6/11/93 82 */ 83 84 #include <sys/param.h> 85 #include <sys/extent.h> 86 #include <sys/malloc.h> 87 #include <sys/systm.h> 88 #include <sys/device.h> 89 #include <vm/vm.h> 90 91 #include <machine/bus.h> 92 #include <sparc64/sparc64/vaddrs.h> 93 #include <sparc64/dev/iommureg.h> 94 #include <sparc64/dev/iommuvar.h> 95 96 #include <machine/autoconf.h> 97 #include <machine/ctlreg.h> 98 #include <machine/cpu.h> 99 100 #ifdef DEBUG 101 #define IDB_DVMA 0x1 102 #define IDB_INTR 0x2 103 int iommudebug = 0; 104 #endif 105 106 /* 107 * initialise the UltraSPARC IOMMU (SBUS or PCI): 108 * - allocate and setup the iotsb. 109 * - enable the IOMMU 110 * - initialise the streaming buffers 111 * - create a private DVMA map. 112 * 113 */ 114 void 115 iommu_init(name, is, tsbsize) 116 char *name; 117 struct iommu_state *is; 118 int tsbsize; 119 { 120 121 /* 122 * Setup the iommu. 123 * 124 * The sun4u iommu is part of the SBUS controller so we will 125 * deal with it here. We could try to fake a device node so 126 * we can eventually share it with the PCI bus run by psycho, 127 * but I don't want to get into that sort of cruft. 128 * 129 * First we need to allocate a IOTSB. Problem is that the IOMMU 130 * can only access the IOTSB by physical address, so all the 131 * pages must be contiguous. Luckily, the smallest IOTSB size 132 * is one 8K page. 133 */ 134 if (tsbsize != 0) 135 panic("tsbsize != 0; FIX ME"); /* XXX */ 136 137 /* we want 8K pages */ 138 is->is_cr = IOMMUCR_8KPG | IOMMUCR_EN; 139 /* 140 * 141 * The IOMMU address space always ends at 0xffffe000, but the starting 142 * address depends on the size of the map. The map size is 1024 * 2 ^ 143 * is->is_tsbsize entries, where each entry is 8 bytes. The start of 144 * the map can be calculated by (0xffffe000 << (8 + is->is_tsbsize)). 145 * 146 * Note: the stupid IOMMU ignores the high bits of an address, so a 147 * NULL DMA pointer will be translated by the first page of the IOTSB. 148 * To trap bugs we'll skip the first entry in the IOTSB. 149 */ 150 is->is_dvmabase = IOTSB_VSTART(is->is_tsbsize) + NBPG; 151 is->is_tsbsize = tsbsize; 152 is->is_tsb = malloc(NBPG, M_DMAMAP, M_WAITOK); /* XXX */ 153 (void) pmap_extract(pmap_kernel(), (vaddr_t)is->is_tsb, 154 (paddr_t *)&is->is_ptsb); 155 156 #ifdef DEBUG 157 if (iommudebug & IDB_DVMA) 158 { 159 /* Probe the iommu */ 160 struct iommureg *regs = is->is_iommu; 161 int64_t cr, tsb; 162 163 printf("iommu regs at: cr=%lx tsb=%lx flush=%lx\n", ®s->iommu_cr, 164 ®s->iommu_tsb, ®s->iommu_flush); 165 cr = regs->iommu_cr; 166 tsb = regs->iommu_tsb; 167 printf("iommu cr=%lx tsb=%lx\n", (long)cr, (long)tsb); 168 printf("TSB base %p phys %p\n", (long)is->is_tsb, (long)is->is_ptsb); 169 delay(1000000); /* 1 s */ 170 } 171 #endif 172 173 /* 174 * Initialize streaming buffer. 175 */ 176 (void) pmap_extract(pmap_kernel(), (vaddr_t)&is->is_flush, 177 (paddr_t *)&is->is_flushpa); 178 179 /* 180 * now actually start up the IOMMU 181 */ 182 iommu_reset(is); 183 184 /* 185 * Now all the hardware's working we need to allocate a dvma map. 186 */ 187 is->is_dvmamap = extent_create(name, 188 is->is_dvmabase, IOTSB_VEND, 189 M_DEVBUF, 0, 0, EX_NOWAIT); 190 } 191 192 void 193 iommu_reset(is) 194 struct iommu_state *is; 195 { 196 197 /* Need to do 64-bit stores */ 198 bus_space_write_8(is->is_bustag, &is->is_iommu->iommu_cr, 0, is->is_cr); 199 bus_space_write_8(is->is_bustag, &is->is_iommu->iommu_tsb, 0, is->is_ptsb); 200 /* Enable diagnostics mode? */ 201 bus_space_write_8(is->is_bustag, &is->is_sb->strbuf_ctl, 0, STRBUF_EN); 202 } 203 204 /* 205 * Here are the iommu control routines. 206 */ 207 void 208 iommu_enter(is, va, pa, flags) 209 struct iommu_state *is; 210 vaddr_t va; 211 int64_t pa; 212 int flags; 213 { 214 int64_t tte; 215 216 #ifdef DIAGNOSTIC 217 if (va < is->is_dvmabase) 218 panic("sbus_enter: va 0x%lx not in DVMA space",va); 219 #endif 220 221 tte = MAKEIOTTE(pa, !(flags&BUS_DMA_NOWRITE), !(flags&BUS_DMA_NOCACHE), 222 !(flags&BUS_DMA_COHERENT)); 223 224 /* Is the streamcache flush really needed? */ 225 bus_space_write_8(is->is_bustag, &is->is_sb->strbuf_pgflush, 226 0, va); 227 iommu_flush(is); 228 #ifdef DEBUG 229 if (iommudebug & IDB_DVMA) 230 printf("Clearing TSB slot %d for va %p\n", 231 (int)IOTSBSLOT(va,is->is_tsbsize), va); 232 #endif 233 is->is_tsb[IOTSBSLOT(va,is->is_tsbsize)] = tte; 234 bus_space_write_8(is->is_bustag, &is->is_iommu->iommu_flush, 235 0, va); 236 #ifdef DEBUG 237 if (iommudebug & IDB_DVMA) 238 printf("sbus_enter: va %lx pa %lx TSB[%lx]@%p=%lx\n", 239 va, (long)pa, IOTSBSLOT(va,is->is_tsbsize), 240 &is->is_tsb[IOTSBSLOT(va,is->is_tsbsize)], 241 (long)tte); 242 #endif 243 } 244 245 /* 246 * iommu_remove: removes mappings created by iommu_enter 247 * 248 * Only demap from IOMMU if flag is set. 249 */ 250 void 251 iommu_remove(is, va, len) 252 struct iommu_state *is; 253 vaddr_t va; 254 size_t len; 255 { 256 257 #ifdef DIAGNOSTIC 258 if (va < is->is_dvmabase) 259 panic("sbus_remove: va 0x%lx not in DVMA space", (long)va); 260 if ((long)(va + len) < (long)va) 261 panic("sbus_remove: va 0x%lx + len 0x%lx wraps", 262 (long) va, (long) len); 263 if (len & ~0xfffffff) 264 panic("sbus_remove: rediculous len 0x%lx", (long)len); 265 #endif 266 267 va = trunc_page(va); 268 while (len > 0) { 269 270 /* 271 * Streaming buffer flushes: 272 * 273 * 1 Tell strbuf to flush by storing va to strbuf_pgflush 274 * If we're not on a cache line boundary (64-bits): 275 * 2 Store 0 in flag 276 * 3 Store pointer to flag in flushsync 277 * 4 wait till flushsync becomes 0x1 278 * 279 * If it takes more than .5 sec, something went wrong. 280 */ 281 #ifdef DEBUG 282 if (iommudebug & IDB_DVMA) 283 printf("sbus_remove: flushing va %p TSB[%lx]@%p=%lx, %lu bytes left\n", 284 (long)va, (long)IOTSBSLOT(va,is->is_tsbsize), 285 (long)&is->is_tsb[IOTSBSLOT(va,is->is_tsbsize)], 286 (long)(is->is_tsb[IOTSBSLOT(va,is->is_tsbsize)]), 287 (u_long)len); 288 #endif 289 bus_space_write_8(is->is_bustag, &is->is_sb->strbuf_pgflush, 0, va); 290 if (len <= NBPG) { 291 iommu_flush(is); 292 len = 0; 293 } else len -= NBPG; 294 #ifdef DEBUG 295 if (iommudebug & IDB_DVMA) 296 printf("sbus_remove: flushed va %p TSB[%lx]@%p=%lx, %lu bytes left\n", 297 (long)va, (long)IOTSBSLOT(va,is->is_tsbsize), 298 (long)&is->is_tsb[IOTSBSLOT(va,is->is_tsbsize)], 299 (long)(is->is_tsb[IOTSBSLOT(va,is->is_tsbsize)]), 300 (u_long)len); 301 #endif 302 is->is_tsb[IOTSBSLOT(va,is->is_tsbsize)] = 0; 303 bus_space_write_8(is->is_bustag, &is->is_iommu->iommu_flush, 0, va); 304 va += NBPG; 305 } 306 } 307 308 int 309 iommu_flush(is) 310 struct iommu_state *is; 311 { 312 struct timeval cur, flushtimeout; 313 314 #define BUMPTIME(t, usec) { \ 315 register volatile struct timeval *tp = (t); \ 316 register long us; \ 317 \ 318 tp->tv_usec = us = tp->tv_usec + (usec); \ 319 if (us >= 1000000) { \ 320 tp->tv_usec = us - 1000000; \ 321 tp->tv_sec++; \ 322 } \ 323 } 324 325 is->is_flush = 0; 326 membar_sync(); 327 bus_space_write_8(is->is_bustag, &is->is_sb->strbuf_flushsync, 0, is->is_flushpa); 328 membar_sync(); 329 330 microtime(&flushtimeout); 331 cur = flushtimeout; 332 BUMPTIME(&flushtimeout, 500000); /* 1/2 sec */ 333 334 #ifdef DEBUG 335 if (iommudebug & IDB_DVMA) 336 printf("sbus_flush: flush = %lx at va = %lx pa = %lx now=%lx:%lx until = %lx:%lx\n", 337 (long)is->is_flush, (long)&is->is_flush, 338 (long)is->is_flushpa, cur.tv_sec, cur.tv_usec, 339 flushtimeout.tv_sec, flushtimeout.tv_usec); 340 #endif 341 /* Bypass non-coherent D$ */ 342 while (!ldxa(is->is_flushpa, ASI_PHYS_CACHED) && 343 ((cur.tv_sec <= flushtimeout.tv_sec) && 344 (cur.tv_usec <= flushtimeout.tv_usec))) 345 microtime(&cur); 346 347 #ifdef DIAGNOSTIC 348 if (!is->is_flush) { 349 printf("sbus_flush: flush timeout %p at %p\n", (long)is->is_flush, 350 (long)is->is_flushpa); /* panic? */ 351 #ifdef DDB 352 Debugger(); 353 #endif 354 } 355 #endif 356 #ifdef DEBUG 357 if (iommudebug & IDB_DVMA) 358 printf("sbus_flush: flushed\n"); 359 #endif 360 return (is->is_flush); 361 } 362
Indexes created Tue Sep 23 23:09:58 GMT 2025