iommu.c revision 1.32
1 /* $NetBSD: iommu.c,v 1.32 2001/03/09 20:05:39 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000 Matthew R. Green 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 23 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 24 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 25 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 /*- 32 * Copyright (c) 1998 The NetBSD Foundation, Inc. 33 * All rights reserved. 34 * 35 * This code is derived from software contributed to The NetBSD Foundation 36 * by Paul Kranenburg. 37 * 38 * Redistribution and use in source and binary forms, with or without 39 * modification, are permitted provided that the following conditions 40 * are met: 41 * 1. Redistributions of source code must retain the above copyright 42 * notice, this list of conditions and the following disclaimer. 43 * 2. Redistributions in binary form must reproduce the above copyright 44 * notice, this list of conditions and the following disclaimer in the 45 * documentation and/or other materials provided with the distribution. 46 * 3. All advertising materials mentioning features or use of this software 47 * must display the following acknowledgement: 48 * This product includes software developed by the NetBSD 49 * Foundation, Inc. and its contributors. 50 * 4. Neither the name of The NetBSD Foundation nor the names of its 51 * contributors may be used to endorse or promote products derived 52 * from this software without specific prior written permission. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 55 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 56 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 57 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 58 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 59 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 60 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 61 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 62 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 63 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 64 * POSSIBILITY OF SUCH DAMAGE. 65 */ 66 67 /* 68 * Copyright (c) 1992, 1993 69 * The Regents of the University of California. All rights reserved. 70 * 71 * This software was developed by the Computer Systems Engineering group 72 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 73 * contributed to Berkeley. 74 * 75 * All advertising materials mentioning features or use of this software 76 * must display the following acknowledgement: 77 * This product includes software developed by the University of 78 * California, Lawrence Berkeley Laboratory. 79 * 80 * Redistribution and use in source and binary forms, with or without 81 * modification, are permitted provided that the following conditions 82 * are met: 83 * 1. Redistributions of source code must retain the above copyright 84 * notice, this list of conditions and the following disclaimer. 85 * 2. Redistributions in binary form must reproduce the above copyright 86 * notice, this list of conditions and the following disclaimer in the 87 * documentation and/or other materials provided with the distribution. 88 * 3. All advertising materials mentioning features or use of this software 89 * must display the following acknowledgement: 90 * This product includes software developed by the University of 91 * California, Berkeley and its contributors. 92 * 4. Neither the name of the University nor the names of its contributors 93 * may be used to endorse or promote products derived from this software 94 * without specific prior written permission. 95 * 96 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 97 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 98 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 99 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 100 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 101 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 102 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 103 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 104 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 105 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 106 * SUCH DAMAGE. 107 * 108 * from: NetBSD: sbus.c,v 1.13 1999/05/23 07:24:02 mrg Exp 109 * from: @(#)sbus.c 8.1 (Berkeley) 6/11/93 110 */ 111 112 /* 113 * UltraSPARC IOMMU support; used by both the sbus and pci code. 114 */ 115 #include "opt_ddb.h" 116 117 #include <sys/param.h> 118 #include <sys/extent.h> 119 #include <sys/malloc.h> 120 #include <sys/systm.h> 121 #include <sys/device.h> 122 123 #include <uvm/uvm_extern.h> 124 125 #include <machine/bus.h> 126 #include <sparc64/sparc64/cache.h> 127 #include <sparc64/dev/iommureg.h> 128 #include <sparc64/dev/iommuvar.h> 129 130 #include <machine/autoconf.h> 131 #include <machine/cpu.h> 132 133 #ifdef DEBUG 134 #define IDB_BUSDMA 0x1 135 #define IDB_IOMMU 0x2 136 #define IDB_INFO 0x4 137 int iommudebug = 0x0; 138 #define DPRINTF(l, s) do { if (iommudebug & l) printf s; } while (0) 139 #else 140 #define DPRINTF(l, s) 141 #endif 142 143 #define iommu_strbuf_flush(i,v) bus_space_write_8((i)->is_bustag, \ 144 (bus_space_handle_t)(u_long)&(i)->is_sb->strbuf_pgflush, 0, (v)) 145 static int iommu_strbuf_flush_done __P((struct iommu_state *)); 146 147 /* 148 * initialise the UltraSPARC IOMMU (SBUS or PCI): 149 * - allocate and setup the iotsb. 150 * - enable the IOMMU 151 * - initialise the streaming buffers (if they exist) 152 * - create a private DVMA map. 153 */ 154 void 155 iommu_init(name, is, tsbsize) 156 char *name; 157 struct iommu_state *is; 158 int tsbsize; 159 { 160 psize_t size; 161 vaddr_t va; 162 paddr_t pa; 163 vm_page_t m; 164 struct pglist mlist; 165 166 /* 167 * Setup the iommu. 168 * 169 * The sun4u iommu is part of the SBUS or PCI controller so we 170 * will deal with it here.. 171 * 172 * The IOMMU address space always ends at 0xffffe000, but the starting 173 * address depends on the size of the map. The map size is 1024 * 2 ^ 174 * is->is_tsbsize entries, where each entry is 8 bytes. The start of 175 * the map can be calculated by (0xffffe000 << (8 + is->is_tsbsize)). 176 * 177 * Note: the stupid IOMMU ignores the high bits of an address, so a 178 * NULL DMA pointer will be translated by the first page of the IOTSB. 179 * To trap bugs we'll skip the first entry in the IOTSB. 180 */ 181 is->is_cr = (tsbsize << 16) | IOMMUCR_EN; 182 is->is_tsbsize = tsbsize; 183 is->is_dvmabase = IOTSB_VSTART(is->is_tsbsize) + NBPG; 184 185 /* 186 * Allocate memory for I/O pagetables. They need to be physically 187 * contiguous. 188 */ 189 190 size = NBPG<<(is->is_tsbsize); 191 TAILQ_INIT(&mlist); 192 if (uvm_pglistalloc((psize_t)size, (paddr_t)0, (paddr_t)-1, 193 (paddr_t)NBPG, (paddr_t)0, &mlist, 1, 0) != 0) 194 panic("iommu_init: no memory"); 195 196 va = uvm_km_valloc(kernel_map, size); 197 if (va == 0) 198 panic("iommu_init: no memory"); 199 is->is_tsb = (int64_t *)va; 200 201 m = TAILQ_FIRST(&mlist); 202 is->is_ptsb = VM_PAGE_TO_PHYS(m); 203 204 /* Map the pages */ 205 for (; m != NULL; m = TAILQ_NEXT(m,pageq)) { 206 pa = VM_PAGE_TO_PHYS(m); 207 pmap_enter(pmap_kernel(), va, pa | PMAP_NVC, 208 VM_PROT_READ|VM_PROT_WRITE, 209 VM_PROT_READ|VM_PROT_WRITE|PMAP_WIRED); 210 va += NBPG; 211 } 212 bzero(is->is_tsb, size); 213 214 #ifdef DEBUG 215 if (iommudebug & IDB_INFO) 216 { 217 /* Probe the iommu */ 218 struct iommureg *regs = is->is_iommu; 219 220 printf("iommu regs at: cr=%lx tsb=%lx flush=%lx\n", 221 (u_long)®s->iommu_cr, 222 (u_long)®s->iommu_tsb, 223 (u_long)®s->iommu_flush); 224 printf("iommu cr=%llx tsb=%llx\n", (unsigned long long)regs->iommu_cr, (unsigned long long)regs->iommu_tsb); 225 printf("TSB base %p phys %llx\n", (void *)is->is_tsb, (unsigned long long)is->is_ptsb); 226 delay(1000000); /* 1 s */ 227 } 228 #endif 229 230 /* 231 * Initialize streaming buffer, if it is there. 232 */ 233 if (is->is_sb) 234 (void)pmap_extract(pmap_kernel(), (vaddr_t)&is->is_flush, 235 (paddr_t *)&is->is_flushpa); 236 237 /* 238 * now actually start up the IOMMU 239 */ 240 iommu_reset(is); 241 242 /* 243 * Now all the hardware's working we need to allocate a dvma map. 244 */ 245 printf("DVMA map: %x to %x\n", 246 (unsigned int)is->is_dvmabase, 247 (unsigned int)IOTSB_VEND); 248 is->is_dvmamap = extent_create(name, 249 is->is_dvmabase, (u_long)IOTSB_VEND, 250 M_DEVBUF, 0, 0, EX_NOWAIT); 251 } 252 253 /* 254 * Streaming buffers don't exist on the UltraSPARC IIi; we should have 255 * detected that already and disabled them. If not, we will notice that 256 * they aren't there when the STRBUF_EN bit does not remain. 257 */ 258 void 259 iommu_reset(is) 260 struct iommu_state *is; 261 { 262 263 /* Need to do 64-bit stores */ 264 bus_space_write_8(is->is_bustag, 265 (bus_space_handle_t)(u_long)&is->is_iommu->iommu_tsb, 266 0, is->is_ptsb); 267 /* Enable IOMMU in diagnostic mode */ 268 bus_space_write_8(is->is_bustag, 269 (bus_space_handle_t)(u_long)&is->is_iommu->iommu_cr, 0, 270 is->is_cr|IOMMUCR_DE); 271 272 273 if (!is->is_sb) 274 return; 275 276 /* Enable diagnostics mode? */ 277 bus_space_write_8(is->is_bustag, 278 (bus_space_handle_t)(u_long)&is->is_sb->strbuf_ctl, 279 0, STRBUF_EN); 280 281 /* No streaming buffers? Disable them */ 282 if (bus_space_read_8(is->is_bustag, 283 (bus_space_handle_t)(u_long)&is->is_sb->strbuf_ctl, 284 0) == 0) 285 is->is_sb = 0; 286 } 287 288 /* 289 * Here are the iommu control routines. 290 */ 291 void 292 iommu_enter(is, va, pa, flags) 293 struct iommu_state *is; 294 vaddr_t va; 295 int64_t pa; 296 int flags; 297 { 298 int64_t tte; 299 300 #ifdef DIAGNOSTIC 301 if (va < is->is_dvmabase) 302 panic("iommu_enter: va %#lx not in DVMA space", va); 303 #endif 304 305 tte = MAKEIOTTE(pa, !(flags&BUS_DMA_NOWRITE), !(flags&BUS_DMA_NOCACHE), 306 (flags&BUS_DMA_STREAMING)); 307 308 /* Is the streamcache flush really needed? */ 309 if (is->is_sb) { 310 iommu_strbuf_flush(is, va); 311 iommu_strbuf_flush_done(is); 312 } 313 DPRINTF(IDB_IOMMU, ("Clearing TSB slot %d for va %p\n", 314 (int)IOTSBSLOT(va,is->is_tsbsize), (void *)(u_long)va)); 315 is->is_tsb[IOTSBSLOT(va,is->is_tsbsize)] = tte; 316 bus_space_write_8(is->is_bustag, (bus_space_handle_t)(u_long) 317 &is->is_iommu->iommu_flush, 0, va); 318 DPRINTF(IDB_IOMMU, ("iommu_enter: va %lx pa %lx TSB[%lx]@%p=%lx\n", 319 va, (long)pa, (u_long)IOTSBSLOT(va,is->is_tsbsize), 320 (void *)(u_long)&is->is_tsb[IOTSBSLOT(va,is->is_tsbsize)], 321 (u_long)tte)); 322 } 323 324 /* 325 * iommu_remove: removes mappings created by iommu_enter 326 * 327 * Only demap from IOMMU if flag is set. 328 * 329 * XXX: this function needs better internal error checking. 330 */ 331 void 332 iommu_remove(is, va, len) 333 struct iommu_state *is; 334 vaddr_t va; 335 size_t len; 336 { 337 338 #ifdef DIAGNOSTIC 339 if (va < is->is_dvmabase) 340 panic("iommu_remove: va 0x%lx not in DVMA space", (u_long)va); 341 if ((long)(va + len) < (long)va) 342 panic("iommu_remove: va 0x%lx + len 0x%lx wraps", 343 (long) va, (long) len); 344 if (len & ~0xfffffff) 345 panic("iommu_remove: rediculous len 0x%lx", (u_long)len); 346 #endif 347 348 va = trunc_page(va); 349 DPRINTF(IDB_IOMMU, ("iommu_remove: va %lx TSB[%lx]@%p\n", 350 va, (u_long)IOTSBSLOT(va,is->is_tsbsize), 351 &is->is_tsb[IOTSBSLOT(va,is->is_tsbsize)])); 352 while (len > 0) { 353 DPRINTF(IDB_IOMMU, ("iommu_remove: clearing TSB slot %d for va %p size %lx\n", 354 (int)IOTSBSLOT(va,is->is_tsbsize), (void *)(u_long)va, (u_long)len)); 355 if (is->is_sb) { 356 DPRINTF(IDB_IOMMU, ("iommu_remove: flushing va %p TSB[%lx]@%p=%lx, %lu bytes left\n", 357 (void *)(u_long)va, (long)IOTSBSLOT(va,is->is_tsbsize), 358 (void *)(u_long)&is->is_tsb[IOTSBSLOT(va,is->is_tsbsize)], 359 (long)(is->is_tsb[IOTSBSLOT(va,is->is_tsbsize)]), 360 (u_long)len)); 361 iommu_strbuf_flush(is, va); 362 if (len <= NBPG) 363 iommu_strbuf_flush_done(is); 364 DPRINTF(IDB_IOMMU, ("iommu_remove: flushed va %p TSB[%lx]@%p=%lx, %lu bytes left\n", 365 (void *)(u_long)va, (long)IOTSBSLOT(va,is->is_tsbsize), 366 (void *)(u_long)&is->is_tsb[IOTSBSLOT(va,is->is_tsbsize)], 367 (long)(is->is_tsb[IOTSBSLOT(va,is->is_tsbsize)]), 368 (u_long)len)); 369 } else 370 membar_sync(); /* XXX */ 371 372 if (len <= NBPG) 373 len = 0; 374 else 375 len -= NBPG; 376 377 is->is_tsb[IOTSBSLOT(va,is->is_tsbsize)] = 0; 378 bus_space_write_8(is->is_bustag, (bus_space_handle_t)(u_long) 379 &is->is_iommu->iommu_flush, 0, va); 380 va += NBPG; 381 } 382 } 383 384 static int 385 iommu_strbuf_flush_done(is) 386 struct iommu_state *is; 387 { 388 struct timeval cur, flushtimeout; 389 390 #define BUMPTIME(t, usec) { \ 391 register volatile struct timeval *tp = (t); \ 392 register long us; \ 393 \ 394 tp->tv_usec = us = tp->tv_usec + (usec); \ 395 if (us >= 1000000) { \ 396 tp->tv_usec = us - 1000000; \ 397 tp->tv_sec++; \ 398 } \ 399 } 400 401 if (!is->is_sb) 402 return (0); 403 404 /* 405 * Streaming buffer flushes: 406 * 407 * 1 Tell strbuf to flush by storing va to strbuf_pgflush. If 408 * we're not on a cache line boundary (64-bits): 409 * 2 Store 0 in flag 410 * 3 Store pointer to flag in flushsync 411 * 4 wait till flushsync becomes 0x1 412 * 413 * If it takes more than .5 sec, something 414 * went wrong. 415 */ 416 417 is->is_flush = 0; 418 membar_sync(); 419 bus_space_write_8(is->is_bustag, (bus_space_handle_t)(u_long) 420 &is->is_sb->strbuf_flushsync, 0, is->is_flushpa); 421 membar_sync(); 422 423 microtime(&flushtimeout); 424 cur = flushtimeout; 425 BUMPTIME(&flushtimeout, 500000); /* 1/2 sec */ 426 427 DPRINTF(IDB_IOMMU, ("iommu_strbuf_flush_done: flush = %lx at va = %lx pa = %lx now=%lx:%lx until = %lx:%lx\n", 428 (long)is->is_flush, (long)&is->is_flush, 429 (long)is->is_flushpa, cur.tv_sec, cur.tv_usec, 430 flushtimeout.tv_sec, flushtimeout.tv_usec)); 431 /* Bypass non-coherent D$ */ 432 while (!ldxa(is->is_flushpa, ASI_PHYS_CACHED) && 433 ((cur.tv_sec <= flushtimeout.tv_sec) && 434 (cur.tv_usec <= flushtimeout.tv_usec))) 435 microtime(&cur); 436 437 #ifdef DIAGNOSTIC 438 if (!ldxa(is->is_flushpa, ASI_PHYS_CACHED)) { 439 printf("iommu_strbuf_flush_done: flush timeout %p at %p\n", 440 (void *)(u_long)is->is_flush, 441 (void *)(u_long)is->is_flushpa); /* panic? */ 442 #ifdef DDB 443 Debugger(); 444 #endif 445 } 446 #endif 447 DPRINTF(IDB_IOMMU, ("iommu_strbuf_flush_done: flushed\n")); 448 return (is->is_flush); 449 } 450 451 /* 452 * IOMMU DVMA operations, common to SBUS and PCI. 453 */ 454 int 455 iommu_dvmamap_load(t, is, map, buf, buflen, p, flags) 456 bus_dma_tag_t t; 457 struct iommu_state *is; 458 bus_dmamap_t map; 459 void *buf; 460 bus_size_t buflen; 461 struct proc *p; 462 int flags; 463 { 464 int s; 465 int err; 466 bus_size_t sgsize; 467 paddr_t curaddr; 468 u_long dvmaddr; 469 bus_size_t align, boundary; 470 vaddr_t vaddr = (vaddr_t)buf; 471 pmap_t pmap; 472 473 if (map->dm_nsegs) { 474 /* Already in use?? */ 475 #ifdef DIAGNOSTIC 476 printf("iommu_dvmamap_load: map still in use\n"); 477 #endif 478 bus_dmamap_unload(t, map); 479 } 480 /* 481 * Make sure that on error condition we return "no valid mappings". 482 */ 483 map->dm_nsegs = 0; 484 485 if (buflen > map->_dm_size) { 486 DPRINTF(IDB_BUSDMA, 487 ("iommu_dvmamap_load(): error %d > %d -- " 488 "map size exceeded!\n", (int)buflen, (int)map->_dm_size)); 489 return (EINVAL); 490 } 491 492 sgsize = round_page(buflen + ((int)vaddr & PGOFSET)); 493 494 /* 495 * A boundary presented to bus_dmamem_alloc() takes precedence 496 * over boundary in the map. 497 */ 498 if ((boundary = (map->dm_segs[0]._ds_boundary)) == 0) 499 boundary = map->_dm_boundary; 500 align = max(map->dm_segs[0]._ds_align, NBPG); 501 s = splhigh(); 502 err = extent_alloc(is->is_dvmamap, sgsize, align, 503 boundary, EX_NOWAIT|EX_BOUNDZERO, (u_long *)&dvmaddr); 504 splx(s); 505 506 #ifdef DEBUG 507 if (err || (dvmaddr == (bus_addr_t)-1)) 508 { 509 printf("iommu_dvmamap_load(): extent_alloc(%d, %x) failed!\n", 510 (int)sgsize, flags); 511 Debugger(); 512 } 513 #endif 514 if (err != 0) 515 return (err); 516 517 if (dvmaddr == (bus_addr_t)-1) 518 return (ENOMEM); 519 520 /* 521 * We always use just one segment. 522 */ 523 map->dm_mapsize = buflen; 524 map->dm_nsegs = 1; 525 map->dm_segs[0].ds_addr = dvmaddr + (vaddr & PGOFSET); 526 map->dm_segs[0].ds_len = buflen; 527 528 if (p != NULL) 529 pmap = p->p_vmspace->vm_map.pmap; 530 else 531 pmap = pmap_kernel(); 532 533 dvmaddr = trunc_page(map->dm_segs[0].ds_addr); 534 for (; buflen > 0; ) { 535 /* 536 * Get the physical address for this page. 537 */ 538 if (pmap_extract(pmap, (vaddr_t)vaddr, &curaddr) == FALSE) { 539 bus_dmamap_unload(t, map); 540 return (-1); 541 } 542 543 /* 544 * Compute the segment size, and adjust counts. 545 */ 546 sgsize = NBPG - ((u_long)vaddr & PGOFSET); 547 if (buflen < sgsize) 548 sgsize = buflen; 549 550 DPRINTF(IDB_BUSDMA, 551 ("iommu_dvmamap_load: map %p loading va %p dva %lx at pa %lx\n", 552 map, (void *)vaddr, (long)dvmaddr, (long)(curaddr&~(NBPG-1)))); 553 iommu_enter(is, trunc_page(dvmaddr), trunc_page(curaddr), 554 flags); 555 556 dvmaddr += PAGE_SIZE; 557 vaddr += sgsize; 558 buflen -= sgsize; 559 } 560 return (0); 561 } 562 563 564 void 565 iommu_dvmamap_unload(t, is, map) 566 bus_dma_tag_t t; 567 struct iommu_state *is; 568 bus_dmamap_t map; 569 { 570 vaddr_t addr, offset; 571 size_t len; 572 int error, s, i; 573 bus_addr_t dvmaddr; 574 bus_size_t sgsize; 575 paddr_t pa; 576 577 dvmaddr = (map->dm_segs[0].ds_addr & ~PGOFSET); 578 pa = 0; 579 sgsize = 0; 580 for (i = 0; i<map->dm_nsegs; i++) { 581 582 addr = trunc_page(map->dm_segs[i].ds_addr); 583 offset = map->dm_segs[i].ds_addr & PGOFSET; 584 len = map->dm_segs[i].ds_len; 585 if (len == 0 || addr == 0) 586 printf("iommu_dvmamap_unload: map = %p, i = %d, len = %d, addr = %lx\n", 587 map, (int)i, (int)len, (unsigned long)addr); 588 589 DPRINTF(IDB_BUSDMA, 590 ("iommu_dvmamap_unload: map %p removing va %lx size %lx\n", 591 map, (long)addr, (long)len)); 592 iommu_remove(is, addr, len); 593 594 if (trunc_page(pa) == addr) 595 sgsize += trunc_page(len + offset); 596 else 597 sgsize += round_page(len + offset); 598 pa = addr + offset + len; 599 600 } 601 /* Flush the caches */ 602 bus_dmamap_unload(t->_parent, map); 603 604 /* Mark the mappings as invalid. */ 605 map->dm_mapsize = 0; 606 map->dm_nsegs = 0; 607 608 s = splhigh(); 609 error = extent_free(is->is_dvmamap, dvmaddr, sgsize, EX_NOWAIT); 610 splx(s); 611 if (error != 0) 612 printf("warning: %qd of DVMA space lost\n", (long long)sgsize); 613 } 614 615 616 int 617 iommu_dvmamap_load_raw(t, is, map, segs, nsegs, flags, size) 618 bus_dma_tag_t t; 619 struct iommu_state *is; 620 bus_dmamap_t map; 621 bus_dma_segment_t *segs; 622 int nsegs; 623 int flags; 624 bus_size_t size; 625 { 626 vm_page_t m; 627 int i, s; 628 int left; 629 int err; 630 bus_size_t sgsize; 631 paddr_t pa; 632 bus_size_t boundary, align; 633 u_long dvmaddr; 634 struct pglist *mlist; 635 int pagesz = PAGE_SIZE; 636 637 if (map->dm_nsegs) { 638 /* Already in use?? */ 639 #ifdef DIAGNOSTIC 640 printf("iommu_dvmamap_load_raw: map still in use\n"); 641 #endif 642 bus_dmamap_unload(t, map); 643 } 644 /* 645 * Make sure that on error condition we return "no valid mappings". 646 */ 647 map->dm_nsegs = 0; 648 /* Count up the total number of pages we need */ 649 pa = segs[0].ds_addr; 650 sgsize = 0; 651 for (i=0; i<nsegs; i++) { 652 sgsize += segs[i].ds_len; 653 if (round_page(pa) != round_page(segs[i].ds_addr)) 654 sgsize = round_page(sgsize); 655 pa = segs[i].ds_addr + segs[i].ds_len; 656 } 657 sgsize = round_page(sgsize); 658 659 /* 660 * A boundary presented to bus_dmamem_alloc() takes precedence 661 * over boundary in the map. 662 */ 663 if ((boundary = segs[0]._ds_boundary) == 0) 664 boundary = map->_dm_boundary; 665 666 align = max(segs[0]._ds_align, NBPG); 667 s = splhigh(); 668 err = extent_alloc(is->is_dvmamap, sgsize, align, boundary, 669 ((flags & BUS_DMA_NOWAIT) == 0 ? EX_WAITOK : EX_NOWAIT)|EX_BOUNDZERO, 670 (u_long *)&dvmaddr); 671 splx(s); 672 673 if (err != 0) 674 return (err); 675 676 #ifdef DEBUG 677 if (dvmaddr == (bus_addr_t)-1) 678 { 679 printf("iommu_dvmamap_load_raw(): extent_alloc(%d, %x) failed!\n", 680 (int)sgsize, flags); 681 Debugger(); 682 } 683 #endif 684 if (dvmaddr == (bus_addr_t)-1) 685 return (ENOMEM); 686 687 if ((mlist = segs[0]._ds_mlist) == NULL) { 688 u_long prev_va = NULL; 689 /* 690 * This segs is made up of individual physical pages, 691 * probably by _bus_dmamap_load_uio() or 692 * _bus_dmamap_load_mbuf(). Ignore the mlist and 693 * load each segment individually. 694 */ 695 696 /* We'll never end up with less segments than we got as input. 697 this gives us a chance to fail quickly */ 698 if (nsegs > map->_dm_segcnt) 699 return (E2BIG); 700 701 i = 0; 702 dvmaddr += (segs[i].ds_addr & PGOFSET); 703 map->dm_segs[i].ds_addr = dvmaddr; 704 map->dm_segs[i].ds_len = left = segs[i].ds_len; 705 pa = segs[i].ds_addr; 706 707 while (left > 0) { 708 int incr; 709 710 if (sgsize == 0) 711 panic("iommu_dmamap_load_raw: size botch"); 712 DPRINTF(IDB_BUSDMA, 713 ("iommu_dvmamap_load_raw: map %p loading va %lx at pa %lx\n", 714 map, (long)dvmaddr, (long)(pa))); 715 /* Enter it if we haven't before. */ 716 if (prev_va != trunc_page(dvmaddr)) 717 iommu_enter(is, prev_va = trunc_page(dvmaddr), 718 trunc_page(pa), flags); 719 incr = min(pagesz, left); 720 dvmaddr += incr; 721 pa += incr; 722 left -= incr; 723 724 /* Next segment */ 725 if (left <= 0 && ++i < nsegs) { 726 u_long offset; 727 728 /* 729 * If the two segs are on different physical pages 730 * move to a new virtual page. 731 */ 732 offset = (segs[i].ds_addr & PGOFSET); 733 if (trunc_page(pa) != trunc_page(segs[i].ds_addr)) 734 dvmaddr += NBPG; 735 736 pa = segs[i].ds_addr; 737 dvmaddr = trunc_page(dvmaddr) + offset; 738 739 map->dm_segs[i].ds_len = left = segs[i].ds_len; 740 map->dm_segs[i].ds_addr = dvmaddr; 741 } 742 } 743 map->dm_nsegs = i; 744 745 /* bail out if we created more segments than the dmamap is 746 allowed to carry */ 747 if (i > map->_dm_segcnt) { 748 iommu_dvmamap_unload(t, is, map); 749 return (E2BIG); 750 } 751 752 return (0); 753 } 754 /* 755 * This was allocated with bus_dmamem_alloc. We only 756 * have one segment, and the pages are on an `mlist'. 757 */ 758 map->dm_mapsize = size; 759 i = 0; 760 map->dm_segs[0].ds_addr = dvmaddr; 761 map->dm_segs[0].ds_len = size; 762 763 for (m = TAILQ_FIRST(mlist); m != NULL; m = TAILQ_NEXT(m,pageq)) { 764 if (sgsize == 0) 765 panic("iommu_dmamap_load_raw: size botch"); 766 pa = VM_PAGE_TO_PHYS(m); 767 768 DPRINTF(IDB_BUSDMA, 769 ("iommu_dvmamap_load_raw: map %p loading va %lx at pa %lx\n", 770 map, (long)dvmaddr, (long)(pa))); 771 iommu_enter(is, dvmaddr, pa, flags); 772 773 dvmaddr += pagesz; 774 sgsize -= pagesz; 775 } 776 map->dm_nsegs = i; 777 return (0); 778 } 779 780 void 781 iommu_dvmamap_sync(t, is, map, offset, len, ops) 782 bus_dma_tag_t t; 783 struct iommu_state *is; 784 bus_dmamap_t map; 785 bus_addr_t offset; 786 bus_size_t len; 787 int ops; 788 { 789 vaddr_t va = map->dm_segs[0].ds_addr + offset; 790 791 /* 792 * We only support one DMA segment; supporting more makes this code 793 * too unweildy. 794 */ 795 796 if (ops & BUS_DMASYNC_PREREAD) { 797 DPRINTF(IDB_BUSDMA, 798 ("iommu_dvmamap_sync: syncing va %p len %lu " 799 "BUS_DMASYNC_PREREAD\n", (void *)(u_long)va, (u_long)len)); 800 801 /* Nothing to do */; 802 } 803 if (ops & BUS_DMASYNC_POSTREAD) { 804 DPRINTF(IDB_BUSDMA, 805 ("iommu_dvmamap_sync: syncing va %p len %lu " 806 "BUS_DMASYNC_POSTREAD\n", (void *)(u_long)va, (u_long)len)); 807 /* if we have a streaming buffer, flush it here first */ 808 if (is->is_sb) 809 while (len > 0) { 810 DPRINTF(IDB_BUSDMA, 811 ("iommu_dvmamap_sync: flushing va %p, %lu " 812 "bytes left\n", (void *)(u_long)va, (u_long)len)); 813 iommu_strbuf_flush(is, va); 814 if (len <= NBPG) { 815 iommu_strbuf_flush_done(is); 816 len = 0; 817 } else 818 len -= NBPG; 819 va += NBPG; 820 } 821 } 822 if (ops & BUS_DMASYNC_PREWRITE) { 823 DPRINTF(IDB_BUSDMA, 824 ("iommu_dvmamap_sync: syncing va %p len %lu " 825 "BUS_DMASYNC_PREWRITE\n", (void *)(u_long)va, (u_long)len)); 826 /* if we have a streaming buffer, flush it here first */ 827 if (is->is_sb) 828 while (len > 0) { 829 DPRINTF(IDB_BUSDMA, 830 ("iommu_dvmamap_sync: flushing va %p, %lu " 831 "bytes left\n", (void *)(u_long)va, (u_long)len)); 832 iommu_strbuf_flush(is, va); 833 if (len <= NBPG) { 834 iommu_strbuf_flush_done(is); 835 len = 0; 836 } else 837 len -= NBPG; 838 va += NBPG; 839 } 840 } 841 if (ops & BUS_DMASYNC_POSTWRITE) { 842 DPRINTF(IDB_BUSDMA, 843 ("iommu_dvmamap_sync: syncing va %p len %lu " 844 "BUS_DMASYNC_POSTWRITE\n", (void *)(u_long)va, (u_long)len)); 845 /* Nothing to do */; 846 } 847 } 848 849 int 850 iommu_dvmamem_alloc(t, is, size, alignment, boundary, segs, nsegs, rsegs, flags) 851 bus_dma_tag_t t; 852 struct iommu_state *is; 853 bus_size_t size, alignment, boundary; 854 bus_dma_segment_t *segs; 855 int nsegs; 856 int *rsegs; 857 int flags; 858 { 859 860 DPRINTF(IDB_BUSDMA, ("iommu_dvmamem_alloc: sz %llx align %llx bound %llx " 861 "segp %p flags %d\n", (unsigned long long)size, 862 (unsigned long long)alignment, (unsigned long long)boundary, 863 segs, flags)); 864 return (bus_dmamem_alloc(t->_parent, size, alignment, boundary, 865 segs, nsegs, rsegs, flags|BUS_DMA_DVMA)); 866 } 867 868 void 869 iommu_dvmamem_free(t, is, segs, nsegs) 870 bus_dma_tag_t t; 871 struct iommu_state *is; 872 bus_dma_segment_t *segs; 873 int nsegs; 874 { 875 876 DPRINTF(IDB_BUSDMA, ("iommu_dvmamem_free: segp %p nsegs %d\n", 877 segs, nsegs)); 878 bus_dmamem_free(t->_parent, segs, nsegs); 879 } 880 881 /* 882 * Map the DVMA mappings into the kernel pmap. 883 * Check the flags to see whether we're streaming or coherent. 884 */ 885 int 886 iommu_dvmamem_map(t, is, segs, nsegs, size, kvap, flags) 887 bus_dma_tag_t t; 888 struct iommu_state *is; 889 bus_dma_segment_t *segs; 890 int nsegs; 891 size_t size; 892 caddr_t *kvap; 893 int flags; 894 { 895 vm_page_t m; 896 vaddr_t va; 897 bus_addr_t addr; 898 struct pglist *mlist; 899 int cbit; 900 901 DPRINTF(IDB_BUSDMA, ("iommu_dvmamem_map: segp %p nsegs %d size %lx\n", 902 segs, nsegs, size)); 903 904 /* 905 * Allocate some space in the kernel map, and then map these pages 906 * into this space. 907 */ 908 size = round_page(size); 909 va = uvm_km_valloc(kernel_map, size); 910 if (va == 0) 911 return (ENOMEM); 912 913 *kvap = (caddr_t)va; 914 915 /* 916 * digest flags: 917 */ 918 cbit = 0; 919 if (flags & BUS_DMA_COHERENT) /* Disable vcache */ 920 cbit |= PMAP_NVC; 921 if (flags & BUS_DMA_NOCACHE) /* sideffects */ 922 cbit |= PMAP_NC; 923 924 /* 925 * Now take this and map it into the CPU. 926 */ 927 mlist = segs[0]._ds_mlist; 928 for (m = mlist->tqh_first; m != NULL; m = m->pageq.tqe_next) { 929 #ifdef DIAGNOSTIC 930 if (size == 0) 931 panic("iommu_dvmamem_map: size botch"); 932 #endif 933 addr = VM_PAGE_TO_PHYS(m); 934 DPRINTF(IDB_BUSDMA, ("iommu_dvmamem_map: " 935 "mapping va %lx at %llx\n", va, (unsigned long long)addr | cbit)); 936 pmap_enter(pmap_kernel(), va, addr | cbit, 937 VM_PROT_READ | VM_PROT_WRITE, 938 VM_PROT_READ | VM_PROT_WRITE | PMAP_WIRED); 939 va += PAGE_SIZE; 940 size -= PAGE_SIZE; 941 } 942 943 return (0); 944 } 945 946 /* 947 * Unmap DVMA mappings from kernel 948 */ 949 void 950 iommu_dvmamem_unmap(t, is, kva, size) 951 bus_dma_tag_t t; 952 struct iommu_state *is; 953 caddr_t kva; 954 size_t size; 955 { 956 957 DPRINTF(IDB_BUSDMA, ("iommu_dvmamem_unmap: kvm %p size %lx\n", 958 kva, size)); 959 960 #ifdef DIAGNOSTIC 961 if ((u_long)kva & PGOFSET) 962 panic("iommu_dvmamem_unmap"); 963 #endif 964 965 size = round_page(size); 966 pmap_remove(pmap_kernel(), (vaddr_t)kva, size); 967 #if 0 968 /* 969 * XXX ? is this necessary? i think so and i think other 970 * implementations are missing it. 971 */ 972 uvm_km_free(kernel_map, (vaddr_t)kva, size); 973 #endif 974 } 975
Indexes created Wed Sep 24 05:09:52 GMT 2025