iommu.c revision 1.46
1 /* $NetBSD: iommu.c,v 1.46 2002/02/08 00:47:04 eeh Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000 Matthew R. Green 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 23 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 24 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 25 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 /*- 32 * Copyright (c) 1998 The NetBSD Foundation, Inc. 33 * All rights reserved. 34 * 35 * This code is derived from software contributed to The NetBSD Foundation 36 * by Paul Kranenburg. 37 * 38 * Redistribution and use in source and binary forms, with or without 39 * modification, are permitted provided that the following conditions 40 * are met: 41 * 1. Redistributions of source code must retain the above copyright 42 * notice, this list of conditions and the following disclaimer. 43 * 2. Redistributions in binary form must reproduce the above copyright 44 * notice, this list of conditions and the following disclaimer in the 45 * documentation and/or other materials provided with the distribution. 46 * 3. All advertising materials mentioning features or use of this software 47 * must display the following acknowledgement: 48 * This product includes software developed by the NetBSD 49 * Foundation, Inc. and its contributors. 50 * 4. Neither the name of The NetBSD Foundation nor the names of its 51 * contributors may be used to endorse or promote products derived 52 * from this software without specific prior written permission. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 55 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 56 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 57 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 58 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 59 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 60 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 61 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 62 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 63 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 64 * POSSIBILITY OF SUCH DAMAGE. 65 */ 66 67 /* 68 * Copyright (c) 1992, 1993 69 * The Regents of the University of California. All rights reserved. 70 * 71 * This software was developed by the Computer Systems Engineering group 72 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 73 * contributed to Berkeley. 74 * 75 * All advertising materials mentioning features or use of this software 76 * must display the following acknowledgement: 77 * This product includes software developed by the University of 78 * California, Lawrence Berkeley Laboratory. 79 * 80 * Redistribution and use in source and binary forms, with or without 81 * modification, are permitted provided that the following conditions 82 * are met: 83 * 1. Redistributions of source code must retain the above copyright 84 * notice, this list of conditions and the following disclaimer. 85 * 2. Redistributions in binary form must reproduce the above copyright 86 * notice, this list of conditions and the following disclaimer in the 87 * documentation and/or other materials provided with the distribution. 88 * 3. All advertising materials mentioning features or use of this software 89 * must display the following acknowledgement: 90 * This product includes software developed by the University of 91 * California, Berkeley and its contributors. 92 * 4. Neither the name of the University nor the names of its contributors 93 * may be used to endorse or promote products derived from this software 94 * without specific prior written permission. 95 * 96 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 97 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 98 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 99 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 100 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 101 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 102 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 103 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 104 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 105 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 106 * SUCH DAMAGE. 107 * 108 * from: NetBSD: sbus.c,v 1.13 1999/05/23 07:24:02 mrg Exp 109 * from: @(#)sbus.c 8.1 (Berkeley) 6/11/93 110 */ 111 112 /* 113 * UltraSPARC IOMMU support; used by both the sbus and pci code. 114 */ 115 #include "opt_ddb.h" 116 117 #include <sys/param.h> 118 #include <sys/extent.h> 119 #include <sys/malloc.h> 120 #include <sys/systm.h> 121 #include <sys/device.h> 122 #include <sys/proc.h> 123 124 #include <uvm/uvm_extern.h> 125 126 #include <machine/bus.h> 127 #include <sparc64/sparc64/cache.h> 128 #include <sparc64/dev/iommureg.h> 129 #include <sparc64/dev/iommuvar.h> 130 131 #include <machine/autoconf.h> 132 #include <machine/cpu.h> 133 134 #ifdef DEBUG 135 #define IDB_BUSDMA 0x1 136 #define IDB_IOMMU 0x2 137 #define IDB_INFO 0x4 138 #define IDB_SYNC 0x8 139 int iommudebug = 0x0; 140 #define DPRINTF(l, s) do { if (iommudebug & l) printf s; } while (0) 141 #else 142 #define DPRINTF(l, s) 143 #endif 144 145 #define iommu_strbuf_flush(i,v) do { \ 146 if ((i)->is_sb[0]) \ 147 bus_space_write_8((i)->is_bustag, \ 148 (bus_space_handle_t)(u_long) \ 149 &(i)->is_sb[0]->strbuf_pgflush, \ 150 0, (v)); \ 151 if ((i)->is_sb[1]) \ 152 bus_space_write_8((i)->is_bustag, \ 153 (bus_space_handle_t)(u_long) \ 154 &(i)->is_sb[1]->strbuf_pgflush, \ 155 0, (v)); \ 156 } while (0) 157 158 static int iommu_strbuf_flush_done __P((struct iommu_state *)); 159 160 /* 161 * initialise the UltraSPARC IOMMU (SBUS or PCI): 162 * - allocate and setup the iotsb. 163 * - enable the IOMMU 164 * - initialise the streaming buffers (if they exist) 165 * - create a private DVMA map. 166 */ 167 void 168 iommu_init(name, is, tsbsize, iovabase) 169 char *name; 170 struct iommu_state *is; 171 int tsbsize; 172 u_int32_t iovabase; 173 { 174 psize_t size; 175 vaddr_t va; 176 paddr_t pa; 177 struct vm_page *m; 178 struct pglist mlist; 179 180 /* 181 * Setup the iommu. 182 * 183 * The sun4u iommu is part of the SBUS or PCI controller so we will 184 * deal with it here.. 185 * 186 * For sysio and psycho/psycho+ the IOMMU address space always ends at 187 * 0xffffe000, but the starting address depends on the size of the 188 * map. The map size is 1024 * 2 ^ is->is_tsbsize entries, where each 189 * entry is 8 bytes. The start of the map can be calculated by 190 * (0xffffe000 << (8 + is->is_tsbsize)). 191 * 192 * But sabre and hummingbird use a different scheme that seems to 193 * be hard-wired, so we read the start and size from the PROM and 194 * just use those values. 195 */ 196 is->is_cr = (tsbsize << 16) | IOMMUCR_EN; 197 is->is_tsbsize = tsbsize; 198 if (iovabase == -1) { 199 is->is_dvmabase = IOTSB_VSTART(is->is_tsbsize); 200 is->is_dvmaend = IOTSB_VEND; 201 } else { 202 is->is_dvmabase = iovabase; 203 is->is_dvmaend = iovabase + IOTSB_VSIZE(tsbsize); 204 } 205 206 /* 207 * Allocate memory for I/O pagetables. They need to be physically 208 * contiguous. 209 */ 210 211 size = NBPG<<(is->is_tsbsize); 212 TAILQ_INIT(&mlist); 213 if (uvm_pglistalloc((psize_t)size, (paddr_t)0, (paddr_t)-1, 214 (paddr_t)NBPG, (paddr_t)0, &mlist, 1, 0) != 0) 215 panic("iommu_init: no memory"); 216 217 va = uvm_km_valloc(kernel_map, size); 218 if (va == 0) 219 panic("iommu_init: no memory"); 220 is->is_tsb = (int64_t *)va; 221 222 m = TAILQ_FIRST(&mlist); 223 is->is_ptsb = VM_PAGE_TO_PHYS(m); 224 225 /* Map the pages */ 226 for (; m != NULL; m = TAILQ_NEXT(m,pageq)) { 227 pa = VM_PAGE_TO_PHYS(m); 228 pmap_enter(pmap_kernel(), va, pa | PMAP_NVC, 229 VM_PROT_READ|VM_PROT_WRITE, 230 VM_PROT_READ|VM_PROT_WRITE|PMAP_WIRED); 231 va += NBPG; 232 } 233 pmap_update(pmap_kernel()); 234 bzero(is->is_tsb, size); 235 236 #ifdef DEBUG 237 if (iommudebug & IDB_INFO) 238 { 239 /* Probe the iommu */ 240 struct iommureg *regs = is->is_iommu; 241 242 printf("iommu regs at: cr=%lx tsb=%lx flush=%lx\n", 243 (u_long)®s->iommu_cr, 244 (u_long)®s->iommu_tsb, 245 (u_long)®s->iommu_flush); 246 printf("iommu cr=%llx tsb=%llx\n", (unsigned long long)regs->iommu_cr, (unsigned long long)regs->iommu_tsb); 247 printf("TSB base %p phys %llx\n", (void *)is->is_tsb, (unsigned long long)is->is_ptsb); 248 delay(1000000); /* 1 s */ 249 } 250 #endif 251 252 /* 253 * Initialize streaming buffer, if it is there. 254 */ 255 if (is->is_sb[0] || is->is_sb[1]) 256 (void)pmap_extract(pmap_kernel(), (vaddr_t)&is->is_flush[0], 257 (paddr_t *)&is->is_flushpa); 258 259 /* 260 * now actually start up the IOMMU 261 */ 262 iommu_reset(is); 263 264 /* 265 * Now all the hardware's working we need to allocate a dvma map. 266 */ 267 printf("DVMA map: %x to %x\n", 268 (unsigned int)is->is_dvmabase, 269 (unsigned int)is->is_dvmaend); 270 printf("IOTSB: %lx to %lx\n", is->is_ptsb, is->is_ptsb+size); 271 is->is_dvmamap = extent_create(name, 272 is->is_dvmabase, is->is_dvmaend - NBPG, 273 M_DEVBUF, 0, 0, EX_NOWAIT); 274 } 275 276 /* 277 * Streaming buffers don't exist on the UltraSPARC IIi; we should have 278 * detected that already and disabled them. If not, we will notice that 279 * they aren't there when the STRBUF_EN bit does not remain. 280 */ 281 void 282 iommu_reset(is) 283 struct iommu_state *is; 284 { 285 struct iommu_strbuf *sb; 286 int i; 287 288 /* Need to do 64-bit stores */ 289 bus_space_write_8(is->is_bustag, 290 (bus_space_handle_t)(u_long)&is->is_iommu->iommu_tsb, 291 0, is->is_ptsb); 292 /* Enable IOMMU in diagnostic mode */ 293 bus_space_write_8(is->is_bustag, 294 (bus_space_handle_t)(u_long)&is->is_iommu->iommu_cr, 295 0, is->is_cr|IOMMUCR_DE); 296 297 for (i=0; i<2; i++) { 298 if ((sb = is->is_sb[i]) != NULL) { 299 300 /* Enable diagnostics mode? */ 301 bus_space_write_8(is->is_bustag, 302 (bus_space_handle_t)(u_long)&sb->strbuf_ctl, 303 0, STRBUF_EN); 304 305 /* No streaming buffers? Disable them */ 306 if (bus_space_read_8(is->is_bustag, 307 (bus_space_handle_t)(u_long)&sb->strbuf_ctl, 308 0) == 0) 309 is->is_sb[i] = 0; 310 } 311 } 312 } 313 314 /* 315 * Here are the iommu control routines. 316 */ 317 void 318 iommu_enter(is, va, pa, flags) 319 struct iommu_state *is; 320 vaddr_t va; 321 int64_t pa; 322 int flags; 323 { 324 int64_t tte; 325 326 #ifdef DIAGNOSTIC 327 if (va < is->is_dvmabase || va > is->is_dvmaend) 328 panic("iommu_enter: va %#lx not in DVMA space", va); 329 #endif 330 331 tte = MAKEIOTTE(pa, !(flags&BUS_DMA_NOWRITE), !(flags&BUS_DMA_NOCACHE), 332 (flags&BUS_DMA_STREAMING)); 333 tte |= (flags & 0xff000LL)<<(4*8);/* DEBUG */ 334 335 /* Is the streamcache flush really needed? */ 336 if (is->is_sb[0] || is->is_sb[1]) { 337 iommu_strbuf_flush(is, va); 338 iommu_strbuf_flush_done(is); 339 } 340 DPRINTF(IDB_IOMMU, ("Clearing TSB slot %d for va %p\n", 341 (int)IOTSBSLOT(va,is->is_tsbsize), (void *)(u_long)va)); 342 is->is_tsb[IOTSBSLOT(va,is->is_tsbsize)] = tte; 343 bus_space_write_8(is->is_bustag, (bus_space_handle_t)(u_long) 344 &is->is_iommu->iommu_flush, 0, va); 345 DPRINTF(IDB_IOMMU, ("iommu_enter: va %lx pa %lx TSB[%lx]@%p=%lx\n", 346 va, (long)pa, (u_long)IOTSBSLOT(va,is->is_tsbsize), 347 (void *)(u_long)&is->is_tsb[IOTSBSLOT(va,is->is_tsbsize)], 348 (u_long)tte)); 349 } 350 351 352 /* 353 * Find the value of a DVMA address (debug routine). 354 */ 355 paddr_t 356 iommu_extract(is, dva) 357 struct iommu_state *is; 358 vaddr_t dva; 359 { 360 int64_t tte = 0; 361 362 if (dva >= is->is_dvmabase && dva < is->is_dvmaend) 363 tte = is->is_tsb[IOTSBSLOT(dva,is->is_tsbsize)]; 364 365 if ((tte&IOTTE_V) == 0) 366 return ((paddr_t)-1L); 367 return (tte&IOTTE_PAMASK); 368 } 369 370 /* 371 * iommu_remove: removes mappings created by iommu_enter 372 * 373 * Only demap from IOMMU if flag is set. 374 * 375 * XXX: this function needs better internal error checking. 376 */ 377 void 378 iommu_remove(is, va, len) 379 struct iommu_state *is; 380 vaddr_t va; 381 size_t len; 382 { 383 384 #ifdef DIAGNOSTIC 385 if (va < is->is_dvmabase || va > is->is_dvmaend) 386 panic("iommu_remove: va 0x%lx not in DVMA space", (u_long)va); 387 if ((long)(va + len) < (long)va) 388 panic("iommu_remove: va 0x%lx + len 0x%lx wraps", 389 (long) va, (long) len); 390 if (len & ~0xfffffff) 391 panic("iommu_remove: rediculous len 0x%lx", (u_long)len); 392 #endif 393 394 va = trunc_page(va); 395 DPRINTF(IDB_IOMMU, ("iommu_remove: va %lx TSB[%lx]@%p\n", 396 va, (u_long)IOTSBSLOT(va,is->is_tsbsize), 397 &is->is_tsb[IOTSBSLOT(va,is->is_tsbsize)])); 398 while (len > 0) { 399 DPRINTF(IDB_IOMMU, ("iommu_remove: clearing TSB slot %d for va %p size %lx\n", 400 (int)IOTSBSLOT(va,is->is_tsbsize), (void *)(u_long)va, (u_long)len)); 401 if (is->is_sb[0] || is->is_sb[0]) { 402 DPRINTF(IDB_IOMMU, ("iommu_remove: flushing va %p TSB[%lx]@%p=%lx, %lu bytes left\n", 403 (void *)(u_long)va, (long)IOTSBSLOT(va,is->is_tsbsize), 404 (void *)(u_long)&is->is_tsb[IOTSBSLOT(va,is->is_tsbsize)], 405 (long)(is->is_tsb[IOTSBSLOT(va,is->is_tsbsize)]), 406 (u_long)len)); 407 iommu_strbuf_flush(is, va); 408 if (len <= NBPG) 409 iommu_strbuf_flush_done(is); 410 DPRINTF(IDB_IOMMU, ("iommu_remove: flushed va %p TSB[%lx]@%p=%lx, %lu bytes left\n", 411 (void *)(u_long)va, (long)IOTSBSLOT(va,is->is_tsbsize), 412 (void *)(u_long)&is->is_tsb[IOTSBSLOT(va,is->is_tsbsize)], 413 (long)(is->is_tsb[IOTSBSLOT(va,is->is_tsbsize)]), 414 (u_long)len)); 415 } 416 417 if (len <= NBPG) 418 len = 0; 419 else 420 len -= NBPG; 421 422 is->is_tsb[IOTSBSLOT(va,is->is_tsbsize)] = 0; 423 bus_space_write_8(is->is_bustag, (bus_space_handle_t)(u_long) 424 &is->is_iommu->iommu_flush, 0, va); 425 va += NBPG; 426 } 427 } 428 429 static int 430 iommu_strbuf_flush_done(is) 431 struct iommu_state *is; 432 { 433 struct timeval cur, flushtimeout; 434 435 #define BUMPTIME(t, usec) { \ 436 register volatile struct timeval *tp = (t); \ 437 register long us; \ 438 \ 439 tp->tv_usec = us = tp->tv_usec + (usec); \ 440 if (us >= 1000000) { \ 441 tp->tv_usec = us - 1000000; \ 442 tp->tv_sec++; \ 443 } \ 444 } 445 446 if (!is->is_sb[0] && !is->is_sb[1]) 447 return (0); 448 449 /* 450 * Streaming buffer flushes: 451 * 452 * 1 Tell strbuf to flush by storing va to strbuf_pgflush. If 453 * we're not on a cache line boundary (64-bits): 454 * 2 Store 0 in flag 455 * 3 Store pointer to flag in flushsync 456 * 4 wait till flushsync becomes 0x1 457 * 458 * If it takes more than .5 sec, something 459 * went wrong. 460 */ 461 462 is->is_flush[0] = 1; 463 is->is_flush[1] = 1; 464 if (is->is_sb[0]) { 465 is->is_flush[0] = 0; 466 bus_space_write_8(is->is_bustag, (bus_space_handle_t)(u_long) 467 &is->is_sb[0]->strbuf_flushsync, 0, is->is_flushpa); 468 } 469 if (is->is_sb[1]) { 470 is->is_flush[0] = 1; 471 bus_space_write_8(is->is_bustag, (bus_space_handle_t)(u_long) 472 &is->is_sb[1]->strbuf_flushsync, 0, is->is_flushpa + 8); 473 } 474 475 microtime(&flushtimeout); 476 cur = flushtimeout; 477 BUMPTIME(&flushtimeout, 500000); /* 1/2 sec */ 478 479 DPRINTF(IDB_IOMMU, ("iommu_strbuf_flush_done: flush = %lx,%lx " 480 "at va = %lx pa = %lx now=%lx:%lx until = %lx:%lx\n", 481 (long)is->is_flush[0], (long)is->is_flush[1], 482 (long)&is->is_flush[0], (long)is->is_flushpa, 483 cur.tv_sec, cur.tv_usec, 484 flushtimeout.tv_sec, flushtimeout.tv_usec)); 485 486 /* Bypass non-coherent D$ */ 487 while ((!ldxa(is->is_flushpa, ASI_PHYS_CACHED) || 488 !ldxa(is->is_flushpa + 8, ASI_PHYS_CACHED)) && 489 ((cur.tv_sec <= flushtimeout.tv_sec) && 490 (cur.tv_usec <= flushtimeout.tv_usec))) 491 microtime(&cur); 492 493 #ifdef DIAGNOSTIC 494 if (!ldxa(is->is_flushpa, ASI_PHYS_CACHED) || 495 !ldxa(is->is_flushpa + 8, ASI_PHYS_CACHED)) { 496 printf("iommu_strbuf_flush_done: flush timeout %p,%p at %p\n", 497 (void *)(u_long)is->is_flush[0], 498 (void *)(u_long)is->is_flush[1], 499 (void *)(u_long)is->is_flushpa); /* panic? */ 500 #ifdef DDB 501 Debugger(); 502 #endif 503 } 504 #endif 505 DPRINTF(IDB_IOMMU, ("iommu_strbuf_flush_done: flushed\n")); 506 return (is->is_flush[0] && is->is_flush[1]); 507 } 508 509 /* 510 * IOMMU DVMA operations, common to SBUS and PCI. 511 */ 512 int 513 iommu_dvmamap_load(t, is, map, buf, buflen, p, flags) 514 bus_dma_tag_t t; 515 struct iommu_state *is; 516 bus_dmamap_t map; 517 void *buf; 518 bus_size_t buflen; 519 struct proc *p; 520 int flags; 521 { 522 int s; 523 int err; 524 bus_size_t sgsize; 525 paddr_t curaddr; 526 u_long dvmaddr, sgstart, sgend; 527 bus_size_t align, boundary; 528 vaddr_t vaddr = (vaddr_t)buf; 529 int seg; 530 pmap_t pmap; 531 532 if (map->dm_nsegs) { 533 /* Already in use?? */ 534 #ifdef DIAGNOSTIC 535 printf("iommu_dvmamap_load: map still in use\n"); 536 #endif 537 bus_dmamap_unload(t, map); 538 } 539 /* 540 * Make sure that on error condition we return "no valid mappings". 541 */ 542 map->dm_nsegs = 0; 543 544 if (buflen > map->_dm_size) { 545 DPRINTF(IDB_BUSDMA, 546 ("iommu_dvmamap_load(): error %d > %d -- " 547 "map size exceeded!\n", (int)buflen, (int)map->_dm_size)); 548 return (EINVAL); 549 } 550 551 sgsize = round_page(buflen + ((int)vaddr & PGOFSET)); 552 553 /* 554 * A boundary presented to bus_dmamem_alloc() takes precedence 555 * over boundary in the map. 556 */ 557 if ((boundary = (map->dm_segs[0]._ds_boundary)) == 0) 558 boundary = map->_dm_boundary; 559 align = max(map->dm_segs[0]._ds_align, NBPG); 560 s = splhigh(); 561 /* 562 * If our segment size is larger than the boundary we need to 563 * split the transfer up int little pieces ourselves. 564 */ 565 err = extent_alloc(is->is_dvmamap, sgsize, align, 566 (sgsize > boundary) ? 0 : boundary, 567 EX_NOWAIT|EX_BOUNDZERO, (u_long *)&dvmaddr); 568 splx(s); 569 570 #ifdef DEBUG 571 if (err || (dvmaddr == (bus_addr_t)-1)) 572 { 573 printf("iommu_dvmamap_load(): extent_alloc(%d, %x) failed!\n", 574 (int)sgsize, flags); 575 #ifdef DDB 576 Debugger(); 577 #endif 578 } 579 #endif 580 if (err != 0) 581 return (err); 582 583 if (dvmaddr == (bus_addr_t)-1) 584 return (ENOMEM); 585 586 /* Set the active DVMA map */ 587 map->_dm_dvmastart = dvmaddr; 588 map->_dm_dvmasize = sgsize; 589 590 /* 591 * Now split the DVMA range into segments, not crossing 592 * the boundary. 593 */ 594 seg = 0; 595 sgstart = dvmaddr + (vaddr & PGOFSET); 596 sgend = sgstart + buflen - 1; 597 map->dm_segs[seg].ds_addr = sgstart; 598 DPRINTF(IDB_INFO, ("iommu_dvmamap_load: boundary %lx boundary-1 %lx " 599 "~(boundary-1) %lx\n", boundary, (boundary-1), ~(boundary-1))); 600 while ((sgstart & ~(boundary - 1)) != (sgend & ~(boundary - 1))) { 601 /* Oops. We crossed a boundary. Split the xfer. */ 602 DPRINTF(IDB_INFO, ("iommu_dvmamap_load: " 603 "seg %d start %lx size %lx\n", seg, 604 map->dm_segs[seg].ds_addr, map->dm_segs[seg].ds_len)); 605 map->dm_segs[seg].ds_len = sgstart & (boundary - 1); 606 if (++seg > map->_dm_segcnt) { 607 /* Too many segments. Fail the operation. */ 608 DPRINTF(IDB_INFO, ("iommu_dvmamap_load: " 609 "too many segments %d\n", seg)); 610 s = splhigh(); 611 /* How can this fail? And if it does what can we do? */ 612 err = extent_free(is->is_dvmamap, 613 dvmaddr, sgsize, EX_NOWAIT); 614 map->_dm_dvmastart = 0; 615 map->_dm_dvmasize = 0; 616 splx(s); 617 return (E2BIG); 618 } 619 sgstart = roundup(sgstart, boundary); 620 map->dm_segs[seg].ds_addr = sgstart; 621 } 622 map->dm_segs[seg].ds_len = sgend - sgstart + 1; 623 DPRINTF(IDB_INFO, ("iommu_dvmamap_load: " 624 "seg %d start %lx size %lx\n", seg, 625 map->dm_segs[seg].ds_addr, map->dm_segs[seg].ds_len)); 626 map->dm_nsegs = seg+1; 627 map->dm_mapsize = buflen; 628 629 if (p != NULL) 630 pmap = p->p_vmspace->vm_map.pmap; 631 else 632 pmap = pmap_kernel(); 633 634 for (; buflen > 0; ) { 635 /* 636 * Get the physical address for this page. 637 */ 638 if (pmap_extract(pmap, (vaddr_t)vaddr, &curaddr) == FALSE) { 639 bus_dmamap_unload(t, map); 640 return (-1); 641 } 642 643 /* 644 * Compute the segment size, and adjust counts. 645 */ 646 sgsize = NBPG - ((u_long)vaddr & PGOFSET); 647 if (buflen < sgsize) 648 sgsize = buflen; 649 650 DPRINTF(IDB_BUSDMA, 651 ("iommu_dvmamap_load: map %p loading va %p " 652 "dva %lx at pa %lx\n", 653 map, (void *)vaddr, (long)dvmaddr, 654 (long)(curaddr&~(NBPG-1)))); 655 iommu_enter(is, trunc_page(dvmaddr), trunc_page(curaddr), 656 flags|0x4000); 657 658 dvmaddr += PAGE_SIZE; 659 vaddr += sgsize; 660 buflen -= sgsize; 661 } 662 #ifdef DIAGNOSTIC 663 for (seg = 0; seg < map->dm_nsegs; seg++) { 664 if (map->dm_segs[seg].ds_addr < is->is_dvmabase || 665 map->dm_segs[seg].ds_addr > is->is_dvmaend) { 666 printf("seg %d dvmaddr %lx out of range %x - %x\n", 667 seg, map->dm_segs[seg].ds_addr, 668 is->is_dvmabase, is->is_dvmaend); 669 Debugger(); 670 } 671 } 672 #endif 673 return (0); 674 } 675 676 677 void 678 iommu_dvmamap_unload(t, is, map) 679 bus_dma_tag_t t; 680 struct iommu_state *is; 681 bus_dmamap_t map; 682 { 683 int error, s; 684 bus_size_t sgsize; 685 686 /* Flush the iommu */ 687 #ifdef DEBUG 688 if (!map->_dm_dvmastart) { 689 printf("iommu_dvmamap_unload: No dvmastart is zero\n"); 690 #ifdef DDB 691 Debugger(); 692 #endif 693 } 694 #endif 695 iommu_remove(is, map->_dm_dvmastart, map->_dm_dvmasize); 696 697 /* Flush the caches */ 698 bus_dmamap_unload(t->_parent, map); 699 700 /* Mark the mappings as invalid. */ 701 map->dm_mapsize = 0; 702 map->dm_nsegs = 0; 703 704 s = splhigh(); 705 error = extent_free(is->is_dvmamap, map->_dm_dvmastart, 706 map->_dm_dvmasize, EX_NOWAIT); 707 map->_dm_dvmastart = 0; 708 map->_dm_dvmasize = 0; 709 splx(s); 710 if (error != 0) 711 printf("warning: %qd of DVMA space lost\n", (long long)sgsize); 712 713 /* Clear the map */ 714 } 715 716 717 int 718 iommu_dvmamap_load_raw(t, is, map, segs, nsegs, flags, size) 719 bus_dma_tag_t t; 720 struct iommu_state *is; 721 bus_dmamap_t map; 722 bus_dma_segment_t *segs; 723 int nsegs; 724 int flags; 725 bus_size_t size; 726 { 727 struct vm_page *m; 728 int i, j, s; 729 int left; 730 int err; 731 bus_size_t sgsize; 732 paddr_t pa; 733 bus_size_t boundary, align; 734 u_long dvmaddr, sgstart, sgend; 735 struct pglist *mlist; 736 int pagesz = PAGE_SIZE; 737 int npg = 0; /* DEBUG */ 738 739 if (map->dm_nsegs) { 740 /* Already in use?? */ 741 #ifdef DIAGNOSTIC 742 printf("iommu_dvmamap_load_raw: map still in use\n"); 743 #endif 744 bus_dmamap_unload(t, map); 745 } 746 747 /* 748 * A boundary presented to bus_dmamem_alloc() takes precedence 749 * over boundary in the map. 750 */ 751 if ((boundary = segs[0]._ds_boundary) == 0) 752 boundary = map->_dm_boundary; 753 754 align = max(segs[0]._ds_align, pagesz); 755 756 /* 757 * Make sure that on error condition we return "no valid mappings". 758 */ 759 map->dm_nsegs = 0; 760 /* Count up the total number of pages we need */ 761 pa = segs[0].ds_addr; 762 sgsize = 0; 763 left = size; 764 for (i=0; left && i<nsegs; i++) { 765 if (round_page(pa) != round_page(segs[i].ds_addr)) 766 sgsize = round_page(sgsize); 767 sgsize += min(left, segs[i].ds_len); 768 left -= segs[i].ds_len; 769 pa = segs[i].ds_addr + segs[i].ds_len; 770 } 771 sgsize = round_page(sgsize); 772 773 s = splhigh(); 774 /* 775 * If our segment size is larger than the boundary we need to 776 * split the transfer up into little pieces ourselves. 777 */ 778 err = extent_alloc(is->is_dvmamap, sgsize, align, 779 (sgsize > boundary) ? 0 : boundary, 780 ((flags & BUS_DMA_NOWAIT) == 0 ? EX_WAITOK : EX_NOWAIT) | 781 EX_BOUNDZERO, (u_long *)&dvmaddr); 782 splx(s); 783 784 if (err != 0) 785 return (err); 786 787 #ifdef DEBUG 788 if (dvmaddr == (bus_addr_t)-1) 789 { 790 printf("iommu_dvmamap_load_raw(): extent_alloc(%d, %x) failed!\n", 791 (int)sgsize, flags); 792 Debugger(); 793 } 794 #endif 795 if (dvmaddr == (bus_addr_t)-1) 796 return (ENOMEM); 797 798 /* Set the active DVMA map */ 799 map->_dm_dvmastart = dvmaddr; 800 map->_dm_dvmasize = sgsize; 801 802 if ((mlist = segs[0]._ds_mlist) == NULL) { 803 u_long prev_va = NULL; 804 paddr_t prev_pa = 0; 805 int end = 0, offset; 806 807 /* 808 * This segs is made up of individual physical 809 * segments, probably by _bus_dmamap_load_uio() or 810 * _bus_dmamap_load_mbuf(). Ignore the mlist and 811 * load each one individually. 812 */ 813 map->dm_mapsize = size; 814 815 j = 0; 816 for (i = 0; i < nsegs ; i++) { 817 818 pa = segs[i].ds_addr; 819 offset = (pa & PGOFSET); 820 pa = trunc_page(pa); 821 dvmaddr = trunc_page(dvmaddr); 822 left = min(size, segs[i].ds_len); 823 824 DPRINTF(IDB_INFO, ("iommu_dvmamap_load_raw: converting " 825 "physseg %d start %lx size %lx\n", i, 826 segs[i].ds_addr, segs[i].ds_len)); 827 828 if (pa == prev_pa) { 829 /* We can re-use this mapping */ 830 #ifdef DEBUG 831 if (iommudebug & 0x10) printf("reusing dva %lx prev %lx pa %lx prev %lx\n", 832 dvmaddr, prev_va, pa, prev_pa); 833 #endif 834 dvmaddr = prev_va; 835 } 836 837 sgstart = dvmaddr + offset; 838 sgend = sgstart + left - 1; 839 840 /* Are the segments virtually adjacent? */ 841 if ((end == offset) && 842 ((offset == 0) || (pa == prev_pa))) { 843 /* Just append to the previous segment. */ 844 #ifdef DEBUG 845 if (iommudebug & 0x10) { 846 printf("iommu_dvmamap_load_raw: converting " 847 "physseg %d start %lx size %lx\n", i, 848 segs[i].ds_addr, segs[i].ds_len); 849 printf("appending: offset %x pa %lx prev %lx dva %lx prev %lx\n", 850 offset, pa, prev_pa, dvmaddr, prev_va); 851 } 852 #endif 853 854 map->dm_segs[--j].ds_len += left; 855 DPRINTF(IDB_INFO, ("iommu_dvmamap_load_raw: " 856 "appending seg %d start %lx size %lx\n", j, 857 map->dm_segs[j].ds_addr, 858 map->dm_segs[j].ds_len)); 859 } else { 860 map->dm_segs[j].ds_addr = sgstart; 861 map->dm_segs[j].ds_len = left; 862 DPRINTF(IDB_INFO, ("iommu_dvmamap_load_raw: " 863 "seg %d start %lx size %lx\n", j, 864 map->dm_segs[j].ds_addr, 865 map->dm_segs[j].ds_len)); 866 } 867 end = (offset + left) & PGOFSET; 868 869 /* Check for boundary issues */ 870 while ((sgstart & ~(boundary - 1)) != 871 (sgend & ~(boundary - 1))) { 872 /* Need a new segment. */ 873 map->dm_segs[j].ds_len = 874 sgstart & (boundary - 1); 875 DPRINTF(IDB_INFO, ("iommu_dvmamap_load_raw: " 876 "seg %d start %lx size %lx\n", j, 877 map->dm_segs[j].ds_addr, 878 map->dm_segs[j].ds_len)); 879 if (++j > map->_dm_segcnt) { 880 iommu_dvmamap_unload(t, is, map); 881 return (E2BIG); 882 } 883 sgstart = roundup(sgstart, boundary); 884 map->dm_segs[j].ds_addr = sgstart; 885 map->dm_segs[j].ds_len = sgend - sgstart + 1; 886 } 887 888 if (sgsize == 0) 889 panic("iommu_dmamap_load_raw: size botch"); 890 891 /* Now map a series of pages. */ 892 while (dvmaddr < sgend) { 893 DPRINTF(IDB_BUSDMA, 894 ("iommu_dvmamap_load_raw: map %p " 895 "loading va %lx at pa %lx\n", 896 map, (long)dvmaddr, 897 (long)(pa))); 898 /* Enter it if we haven't before. */ 899 if (prev_va != dvmaddr) 900 #ifdef DEBUG 901 { if (iommudebug & 0x10) printf("seg %d:%d entering dvma %lx, prev %lx pa %lx\n", i,j, dvmaddr, prev_va, pa); 902 #endif 903 iommu_enter(is, prev_va = dvmaddr, 904 prev_pa = pa, 905 flags|(++npg<<12)); 906 #ifdef DEBUG 907 } else if (iommudebug & 0x10) printf("seg %d:%d skipping dvma %lx, prev %lx\n", i,j, dvmaddr, prev_va); 908 #endif 909 910 dvmaddr += pagesz; 911 pa += pagesz; 912 } 913 914 size -= left; 915 ++j; 916 } 917 918 map->dm_nsegs = j; 919 #ifdef DIAGNOSTIC 920 { int seg; 921 for (seg = 0; seg < map->dm_nsegs; seg++) { 922 if (map->dm_segs[seg].ds_addr < is->is_dvmabase || 923 map->dm_segs[seg].ds_addr > is->is_dvmaend) { 924 printf("seg %d dvmaddr %lx out of range %x - %x\n", 925 seg, map->dm_segs[seg].ds_addr, 926 is->is_dvmabase, is->is_dvmaend); 927 Debugger(); 928 } 929 } 930 } 931 #endif 932 return (0); 933 } 934 /* 935 * This was allocated with bus_dmamem_alloc. 936 * The pages are on an `mlist'. 937 */ 938 map->dm_mapsize = size; 939 i = 0; 940 sgstart = dvmaddr; 941 sgend = sgstart + size - 1; 942 map->dm_segs[i].ds_addr = sgstart; 943 while ((sgstart & ~(boundary - 1)) != (sgend & ~(boundary - 1))) { 944 /* Oops. We crossed a boundary. Split the xfer. */ 945 map->dm_segs[i].ds_len = sgstart & (boundary - 1); 946 DPRINTF(IDB_INFO, ("iommu_dvmamap_load_raw: " 947 "seg %d start %lx size %lx\n", i, 948 map->dm_segs[i].ds_addr, 949 map->dm_segs[i].ds_len)); 950 if (++i > map->_dm_segcnt) { 951 /* Too many segments. Fail the operation. */ 952 s = splhigh(); 953 /* How can this fail? And if it does what can we do? */ 954 err = extent_free(is->is_dvmamap, 955 dvmaddr, sgsize, EX_NOWAIT); 956 map->_dm_dvmastart = 0; 957 map->_dm_dvmasize = 0; 958 splx(s); 959 return (E2BIG); 960 } 961 sgstart = roundup(sgstart, boundary); 962 map->dm_segs[i].ds_addr = sgstart; 963 } 964 DPRINTF(IDB_INFO, ("iommu_dvmamap_load_raw: " 965 "seg %d start %lx size %lx\n", i, 966 map->dm_segs[i].ds_addr, map->dm_segs[i].ds_len)); 967 map->dm_segs[i].ds_len = sgend - sgstart + 1; 968 969 for (m = TAILQ_FIRST(mlist); m != NULL; m = TAILQ_NEXT(m,pageq)) { 970 if (sgsize == 0) 971 panic("iommu_dmamap_load_raw: size botch"); 972 pa = VM_PAGE_TO_PHYS(m); 973 974 DPRINTF(IDB_BUSDMA, 975 ("iommu_dvmamap_load_raw: map %p loading va %lx at pa %lx\n", 976 map, (long)dvmaddr, (long)(pa))); 977 iommu_enter(is, dvmaddr, pa, flags|0x8000); 978 979 dvmaddr += pagesz; 980 sgsize -= pagesz; 981 } 982 map->dm_mapsize = size; 983 map->dm_nsegs = i+1; 984 #ifdef DIAGNOSTIC 985 { int seg; 986 for (seg = 0; seg < map->dm_nsegs; seg++) { 987 if (map->dm_segs[seg].ds_addr < is->is_dvmabase || 988 map->dm_segs[seg].ds_addr > is->is_dvmaend) { 989 printf("seg %d dvmaddr %lx out of range %x - %x\n", 990 seg, map->dm_segs[seg].ds_addr, 991 is->is_dvmabase, is->is_dvmaend); 992 Debugger(); 993 } 994 } 995 } 996 #endif 997 return (0); 998 } 999 1000 void 1001 iommu_dvmamap_sync(t, is, map, offset, len, ops) 1002 bus_dma_tag_t t; 1003 struct iommu_state *is; 1004 bus_dmamap_t map; 1005 bus_addr_t offset; 1006 bus_size_t len; 1007 int ops; 1008 { 1009 vaddr_t va = map->dm_segs[0].ds_addr + offset; 1010 1011 /* 1012 * We only support one DMA segment; supporting more makes this code 1013 * too unweildy. 1014 */ 1015 1016 if (ops & BUS_DMASYNC_PREREAD) { 1017 DPRINTF(IDB_SYNC, 1018 ("iommu_dvmamap_sync: syncing va %p len %lu " 1019 "BUS_DMASYNC_PREREAD\n", (void *)(u_long)va, (u_long)len)); 1020 1021 /* Nothing to do */; 1022 } 1023 if (ops & BUS_DMASYNC_POSTREAD) { 1024 DPRINTF(IDB_SYNC, 1025 ("iommu_dvmamap_sync: syncing va %p len %lu " 1026 "BUS_DMASYNC_POSTREAD\n", (void *)(u_long)va, (u_long)len)); 1027 /* if we have a streaming buffer, flush it here first */ 1028 if (is->is_sb[0] || is->is_sb[1]) 1029 while (len > 0) { 1030 DPRINTF(IDB_BUSDMA, 1031 ("iommu_dvmamap_sync: flushing va %p, %lu " 1032 "bytes left\n", (void *)(u_long)va, (u_long)len)); 1033 iommu_strbuf_flush(is, va); 1034 if (len <= NBPG) { 1035 iommu_strbuf_flush_done(is); 1036 len = 0; 1037 } else 1038 len -= NBPG; 1039 va += NBPG; 1040 } 1041 } 1042 if (ops & BUS_DMASYNC_PREWRITE) { 1043 DPRINTF(IDB_SYNC, 1044 ("iommu_dvmamap_sync: syncing va %p len %lu " 1045 "BUS_DMASYNC_PREWRITE\n", (void *)(u_long)va, (u_long)len)); 1046 /* if we have a streaming buffer, flush it here first */ 1047 if (is->is_sb[0] || is->is_sb[1]) 1048 while (len > 0) { 1049 DPRINTF(IDB_BUSDMA, 1050 ("iommu_dvmamap_sync: flushing va %p, %lu " 1051 "bytes left\n", (void *)(u_long)va, (u_long)len)); 1052 iommu_strbuf_flush(is, va); 1053 if (len <= NBPG) { 1054 iommu_strbuf_flush_done(is); 1055 len = 0; 1056 } else 1057 len -= NBPG; 1058 va += NBPG; 1059 } 1060 } 1061 if (ops & BUS_DMASYNC_POSTWRITE) { 1062 DPRINTF(IDB_SYNC, 1063 ("iommu_dvmamap_sync: syncing va %p len %lu " 1064 "BUS_DMASYNC_POSTWRITE\n", (void *)(u_long)va, (u_long)len)); 1065 /* Nothing to do */; 1066 } 1067 } 1068 1069 int 1070 iommu_dvmamem_alloc(t, is, size, alignment, boundary, segs, nsegs, rsegs, flags) 1071 bus_dma_tag_t t; 1072 struct iommu_state *is; 1073 bus_size_t size, alignment, boundary; 1074 bus_dma_segment_t *segs; 1075 int nsegs; 1076 int *rsegs; 1077 int flags; 1078 { 1079 1080 DPRINTF(IDB_BUSDMA, ("iommu_dvmamem_alloc: sz %llx align %llx bound %llx " 1081 "segp %p flags %d\n", (unsigned long long)size, 1082 (unsigned long long)alignment, (unsigned long long)boundary, 1083 segs, flags)); 1084 return (bus_dmamem_alloc(t->_parent, size, alignment, boundary, 1085 segs, nsegs, rsegs, flags|BUS_DMA_DVMA)); 1086 } 1087 1088 void 1089 iommu_dvmamem_free(t, is, segs, nsegs) 1090 bus_dma_tag_t t; 1091 struct iommu_state *is; 1092 bus_dma_segment_t *segs; 1093 int nsegs; 1094 { 1095 1096 DPRINTF(IDB_BUSDMA, ("iommu_dvmamem_free: segp %p nsegs %d\n", 1097 segs, nsegs)); 1098 bus_dmamem_free(t->_parent, segs, nsegs); 1099 } 1100 1101 /* 1102 * Map the DVMA mappings into the kernel pmap. 1103 * Check the flags to see whether we're streaming or coherent. 1104 */ 1105 int 1106 iommu_dvmamem_map(t, is, segs, nsegs, size, kvap, flags) 1107 bus_dma_tag_t t; 1108 struct iommu_state *is; 1109 bus_dma_segment_t *segs; 1110 int nsegs; 1111 size_t size; 1112 caddr_t *kvap; 1113 int flags; 1114 { 1115 struct vm_page *m; 1116 vaddr_t va; 1117 bus_addr_t addr; 1118 struct pglist *mlist; 1119 int cbit; 1120 1121 DPRINTF(IDB_BUSDMA, ("iommu_dvmamem_map: segp %p nsegs %d size %lx\n", 1122 segs, nsegs, size)); 1123 1124 /* 1125 * Allocate some space in the kernel map, and then map these pages 1126 * into this space. 1127 */ 1128 size = round_page(size); 1129 va = uvm_km_valloc(kernel_map, size); 1130 if (va == 0) 1131 return (ENOMEM); 1132 1133 *kvap = (caddr_t)va; 1134 1135 /* 1136 * digest flags: 1137 */ 1138 cbit = 0; 1139 if (flags & BUS_DMA_COHERENT) /* Disable vcache */ 1140 cbit |= PMAP_NVC; 1141 if (flags & BUS_DMA_NOCACHE) /* sideffects */ 1142 cbit |= PMAP_NC; 1143 1144 /* 1145 * Now take this and map it into the CPU. 1146 */ 1147 mlist = segs[0]._ds_mlist; 1148 for (m = mlist->tqh_first; m != NULL; m = m->pageq.tqe_next) { 1149 #ifdef DIAGNOSTIC 1150 if (size == 0) 1151 panic("iommu_dvmamem_map: size botch"); 1152 #endif 1153 addr = VM_PAGE_TO_PHYS(m); 1154 DPRINTF(IDB_BUSDMA, ("iommu_dvmamem_map: " 1155 "mapping va %lx at %llx\n", va, (unsigned long long)addr | cbit)); 1156 pmap_enter(pmap_kernel(), va, addr | cbit, 1157 VM_PROT_READ | VM_PROT_WRITE, 1158 VM_PROT_READ | VM_PROT_WRITE | PMAP_WIRED); 1159 va += PAGE_SIZE; 1160 size -= PAGE_SIZE; 1161 } 1162 pmap_update(pmap_kernel()); 1163 1164 return (0); 1165 } 1166 1167 /* 1168 * Unmap DVMA mappings from kernel 1169 */ 1170 void 1171 iommu_dvmamem_unmap(t, is, kva, size) 1172 bus_dma_tag_t t; 1173 struct iommu_state *is; 1174 caddr_t kva; 1175 size_t size; 1176 { 1177 1178 DPRINTF(IDB_BUSDMA, ("iommu_dvmamem_unmap: kvm %p size %lx\n", 1179 kva, size)); 1180 1181 #ifdef DIAGNOSTIC 1182 if ((u_long)kva & PGOFSET) 1183 panic("iommu_dvmamem_unmap"); 1184 #endif 1185 1186 size = round_page(size); 1187 pmap_remove(pmap_kernel(), (vaddr_t)kva, size); 1188 pmap_update(pmap_kernel()); 1189 #if 0 1190 /* 1191 * XXX ? is this necessary? i think so and i think other 1192 * implementations are missing it. 1193 */ 1194 uvm_km_free(kernel_map, (vaddr_t)kva, size); 1195 #endif 1196 } 1197
Indexes created Wed Sep 24 15:09:51 GMT 2025