iommu.c revision 1.5
1 /* $NetBSD: iommu.c,v 1.5 2000/04/05 14:26:51 mrg Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Copyright (c) 1992, 1993 41 * The Regents of the University of California. All rights reserved. 42 * 43 * This software was developed by the Computer Systems Engineering group 44 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 45 * contributed to Berkeley. 46 * 47 * All advertising materials mentioning features or use of this software 48 * must display the following acknowledgement: 49 * This product includes software developed by the University of 50 * California, Lawrence Berkeley Laboratory. 51 * 52 * Redistribution and use in source and binary forms, with or without 53 * modification, are permitted provided that the following conditions 54 * are met: 55 * 1. Redistributions of source code must retain the above copyright 56 * notice, this list of conditions and the following disclaimer. 57 * 2. Redistributions in binary form must reproduce the above copyright 58 * notice, this list of conditions and the following disclaimer in the 59 * documentation and/or other materials provided with the distribution. 60 * 3. All advertising materials mentioning features or use of this software 61 * must display the following acknowledgement: 62 * This product includes software developed by the University of 63 * California, Berkeley and its contributors. 64 * 4. Neither the name of the University nor the names of its contributors 65 * may be used to endorse or promote products derived from this software 66 * without specific prior written permission. 67 * 68 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 69 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 70 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 71 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 72 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 73 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 74 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 75 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 76 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 77 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 78 * SUCH DAMAGE. 79 * 80 * from: NetBSD: sbus.c,v 1.13 1999/05/23 07:24:02 mrg Exp 81 * from: @(#)sbus.c 8.1 (Berkeley) 6/11/93 82 */ 83 84 #include "opt_ddb.h" 85 86 #include <sys/param.h> 87 #include <sys/extent.h> 88 #include <sys/malloc.h> 89 #include <sys/systm.h> 90 #include <sys/device.h> 91 #include <vm/vm.h> 92 93 #include <machine/bus.h> 94 #include <sparc64/sparc64/vaddrs.h> 95 #include <sparc64/dev/iommureg.h> 96 #include <sparc64/dev/iommuvar.h> 97 98 #include <machine/autoconf.h> 99 #include <machine/ctlreg.h> 100 #include <machine/cpu.h> 101 102 #ifdef DEBUG 103 #define IDB_DVMA 0x1 104 #define IDB_INTR 0x2 105 int iommudebug = 0; 106 #define DPRINTF(l, s) do { if (iommudebug & l) printf s; } while (0) 107 #else 108 #define DPRINTF(l, s) 109 #endif 110 111 /* 112 * initialise the UltraSPARC IOMMU (SBUS or PCI): 113 * - allocate and setup the iotsb. 114 * - enable the IOMMU 115 * - initialise the streaming buffers 116 * - create a private DVMA map. 117 * 118 */ 119 void 120 iommu_init(name, is, tsbsize) 121 char *name; 122 struct iommu_state *is; 123 int tsbsize; 124 { 125 126 /* 127 * Setup the iommu. 128 * 129 * The sun4u iommu is part of the SBUS controller so we will 130 * deal with it here. We could try to fake a device node so 131 * we can eventually share it with the PCI bus run by psycho, 132 * but I don't want to get into that sort of cruft. 133 * 134 * First we need to allocate a IOTSB. Problem is that the IOMMU 135 * can only access the IOTSB by physical address, so all the 136 * pages must be contiguous. Luckily, the smallest IOTSB size 137 * is one 8K page. 138 */ 139 if (tsbsize != 0) 140 panic("tsbsize != 0; FIX ME"); /* XXX */ 141 142 /* we want 8K pages */ 143 is->is_cr = IOMMUCR_8KPG | IOMMUCR_EN; 144 /* 145 * 146 * The IOMMU address space always ends at 0xffffe000, but the starting 147 * address depends on the size of the map. The map size is 1024 * 2 ^ 148 * is->is_tsbsize entries, where each entry is 8 bytes. The start of 149 * the map can be calculated by (0xffffe000 << (8 + is->is_tsbsize)). 150 * 151 * Note: the stupid IOMMU ignores the high bits of an address, so a 152 * NULL DMA pointer will be translated by the first page of the IOTSB. 153 * To trap bugs we'll skip the first entry in the IOTSB. 154 */ 155 is->is_dvmabase = IOTSB_VSTART(is->is_tsbsize) + NBPG; 156 is->is_tsbsize = tsbsize; 157 is->is_tsb = malloc(NBPG, M_DMAMAP, M_WAITOK); /* XXX */ 158 (void) pmap_extract(pmap_kernel(), (vaddr_t)is->is_tsb, 159 (paddr_t *)&is->is_ptsb); 160 161 #ifdef DEBUG 162 if (iommudebug & IDB_DVMA) 163 { 164 /* Probe the iommu */ 165 struct iommureg *regs = is->is_iommu; 166 int64_t cr, tsb; 167 168 printf("iommu regs at: cr=%lx tsb=%lx flush=%lx\n", ®s->iommu_cr, 169 ®s->iommu_tsb, ®s->iommu_flush); 170 cr = regs->iommu_cr; 171 tsb = regs->iommu_tsb; 172 printf("iommu cr=%lx tsb=%lx\n", (long)cr, (long)tsb); 173 printf("TSB base %p phys %p\n", (long)is->is_tsb, (long)is->is_ptsb); 174 delay(1000000); /* 1 s */ 175 } 176 #endif 177 178 /* 179 * Initialize streaming buffer. 180 */ 181 (void) pmap_extract(pmap_kernel(), (vaddr_t)&is->is_flush, 182 (paddr_t *)&is->is_flushpa); 183 184 /* 185 * now actually start up the IOMMU 186 */ 187 iommu_reset(is); 188 189 /* 190 * Now all the hardware's working we need to allocate a dvma map. 191 */ 192 is->is_dvmamap = extent_create(name, 193 is->is_dvmabase, IOTSB_VEND, 194 M_DEVBUF, 0, 0, EX_NOWAIT); 195 } 196 197 void 198 iommu_reset(is) 199 struct iommu_state *is; 200 { 201 202 /* Need to do 64-bit stores */ 203 bus_space_write_8(is->is_bustag, &is->is_iommu->iommu_cr, 0, is->is_cr); 204 bus_space_write_8(is->is_bustag, &is->is_iommu->iommu_tsb, 0, is->is_ptsb); 205 206 /* Enable diagnostics mode? */ 207 bus_space_write_8(is->is_bustag, &is->is_sb->strbuf_ctl, 0, STRBUF_EN); 208 209 /* No streaming buffers? Disable them */ 210 if (bus_space_read_8(is->is_bustag, &is->is_sb->strbuf_ctl, 0) == 0) 211 is->is_sb = 0; 212 } 213 214 /* 215 * Here are the iommu control routines. 216 */ 217 void 218 iommu_enter(is, va, pa, flags) 219 struct iommu_state *is; 220 vaddr_t va; 221 int64_t pa; 222 int flags; 223 { 224 int64_t tte; 225 226 #ifdef DIAGNOSTIC 227 if (va < is->is_dvmabase) 228 panic("iommu_enter: va 0x%lx not in DVMA space",va); 229 #endif 230 231 tte = MAKEIOTTE(pa, !(flags&BUS_DMA_NOWRITE), !(flags&BUS_DMA_NOCACHE), 232 !(flags&BUS_DMA_COHERENT)); 233 234 /* Is the streamcache flush really needed? */ 235 if (is->is_sb) { 236 bus_space_write_8(is->is_bustag, &is->is_sb->strbuf_pgflush, 0, 237 va); 238 iommu_flush(is); 239 } 240 DPRINTF(IDB_DVMA, ("Clearing TSB slot %d for va %p\n", 241 (int)IOTSBSLOT(va,is->is_tsbsize), va)); 242 is->is_tsb[IOTSBSLOT(va,is->is_tsbsize)] = tte; 243 bus_space_write_8(is->is_bustag, &is->is_iommu->iommu_flush, 244 0, va); 245 DPRINTF(IDB_DVMA, ("iommu_enter: va %lx pa %lx TSB[%lx]@%p=%lx\n", 246 va, (long)pa, IOTSBSLOT(va,is->is_tsbsize), 247 &is->is_tsb[IOTSBSLOT(va,is->is_tsbsize)], 248 (long)tte)); 249 } 250 251 /* 252 * iommu_remove: removes mappings created by iommu_enter 253 * 254 * Only demap from IOMMU if flag is set. 255 */ 256 void 257 iommu_remove(is, va, len) 258 struct iommu_state *is; 259 vaddr_t va; 260 size_t len; 261 { 262 263 #ifdef DIAGNOSTIC 264 if (va < is->is_dvmabase) 265 panic("iommu_remove: va 0x%lx not in DVMA space", (long)va); 266 if ((long)(va + len) < (long)va) 267 panic("iommu_remove: va 0x%lx + len 0x%lx wraps", 268 (long) va, (long) len); 269 if (len & ~0xfffffff) 270 panic("iommu_remove: rediculous len 0x%lx", (long)len); 271 #endif 272 273 va = trunc_page(va); 274 while (len > 0) { 275 276 /* 277 * Streaming buffer flushes: 278 * 279 * 1 Tell strbuf to flush by storing va to strbuf_pgflush 280 * If we're not on a cache line boundary (64-bits): 281 * 2 Store 0 in flag 282 * 3 Store pointer to flag in flushsync 283 * 4 wait till flushsync becomes 0x1 284 * 285 * If it takes more than .5 sec, something went wrong. 286 */ 287 if (is->is_sb) { 288 DPRINTF(IDB_DVMA, ("iommu_remove: flushing va %p TSB[%lx]@%p=%lx, %lu bytes left\n", 289 (long)va, (long)IOTSBSLOT(va,is->is_tsbsize), 290 (long)&is->is_tsb[IOTSBSLOT(va,is->is_tsbsize)], 291 (long)(is->is_tsb[IOTSBSLOT(va,is->is_tsbsize)]), 292 (u_long)len)); 293 bus_space_write_8(is->is_bustag, 294 &is->is_sb->strbuf_pgflush, 0, va); 295 if (len <= NBPG) { 296 iommu_flush(is); 297 len = 0; 298 } else len -= NBPG; 299 DPRINTF(IDB_DVMA, ("iommu_remove: flushed va %p TSB[%lx]@%p=%lx, %lu bytes left\n", 300 (long)va, (long)IOTSBSLOT(va,is->is_tsbsize), 301 (long)&is->is_tsb[IOTSBSLOT(va,is->is_tsbsize)], 302 (long)(is->is_tsb[IOTSBSLOT(va,is->is_tsbsize)]), 303 (u_long)len)); 304 } 305 is->is_tsb[IOTSBSLOT(va,is->is_tsbsize)] = 0; 306 bus_space_write_8(is->is_bustag, &is->is_iommu->iommu_flush, 0, va); 307 va += NBPG; 308 } 309 } 310 311 int 312 iommu_flush(is) 313 struct iommu_state *is; 314 { 315 struct timeval cur, flushtimeout; 316 317 #define BUMPTIME(t, usec) { \ 318 register volatile struct timeval *tp = (t); \ 319 register long us; \ 320 \ 321 tp->tv_usec = us = tp->tv_usec + (usec); \ 322 if (us >= 1000000) { \ 323 tp->tv_usec = us - 1000000; \ 324 tp->tv_sec++; \ 325 } \ 326 } 327 328 if (!is->is_sb) 329 return (0); 330 331 is->is_flush = 0; 332 membar_sync(); 333 bus_space_write_8(is->is_bustag, &is->is_sb->strbuf_flushsync, 0, is->is_flushpa); 334 membar_sync(); 335 336 microtime(&flushtimeout); 337 cur = flushtimeout; 338 BUMPTIME(&flushtimeout, 500000); /* 1/2 sec */ 339 340 DPRINTF(IDB_DVMA, ("iommu_flush: flush = %lx at va = %lx pa = %lx now=%lx:%lx until = %lx:%lx\n", 341 (long)is->is_flush, (long)&is->is_flush, 342 (long)is->is_flushpa, cur.tv_sec, cur.tv_usec, 343 flushtimeout.tv_sec, flushtimeout.tv_usec)); 344 /* Bypass non-coherent D$ */ 345 while (!ldxa(is->is_flushpa, ASI_PHYS_CACHED) && 346 ((cur.tv_sec <= flushtimeout.tv_sec) && 347 (cur.tv_usec <= flushtimeout.tv_usec))) 348 microtime(&cur); 349 350 #ifdef DIAGNOSTIC 351 if (!is->is_flush) { 352 printf("iommu_flush: flush timeout %p at %p\n", (long)is->is_flush, 353 (long)is->is_flushpa); /* panic? */ 354 #ifdef DDB 355 Debugger(); 356 #endif 357 } 358 #endif 359 DPRINTF(IDB_DVMA, ("iommu_flush: flushed\n")); 360 return (is->is_flush); 361 } 362
Indexes created Wed Sep 24 05:09:52 GMT 2025