iommu.c revision 1.7
1 /* $NetBSD: iommu.c,v 1.7 2000/04/22 17:06:03 mrg Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000 Matthew R. Green 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 23 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 24 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 25 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 /*- 32 * Copyright (c) 1998 The NetBSD Foundation, Inc. 33 * All rights reserved. 34 * 35 * This code is derived from software contributed to The NetBSD Foundation 36 * by Paul Kranenburg. 37 * 38 * Redistribution and use in source and binary forms, with or without 39 * modification, are permitted provided that the following conditions 40 * are met: 41 * 1. Redistributions of source code must retain the above copyright 42 * notice, this list of conditions and the following disclaimer. 43 * 2. Redistributions in binary form must reproduce the above copyright 44 * notice, this list of conditions and the following disclaimer in the 45 * documentation and/or other materials provided with the distribution. 46 * 3. All advertising materials mentioning features or use of this software 47 * must display the following acknowledgement: 48 * This product includes software developed by the NetBSD 49 * Foundation, Inc. and its contributors. 50 * 4. Neither the name of The NetBSD Foundation nor the names of its 51 * contributors may be used to endorse or promote products derived 52 * from this software without specific prior written permission. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 55 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 56 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 57 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 58 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 59 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 60 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 61 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 62 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 63 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 64 * POSSIBILITY OF SUCH DAMAGE. 65 */ 66 67 /* 68 * Copyright (c) 1992, 1993 69 * The Regents of the University of California. All rights reserved. 70 * 71 * This software was developed by the Computer Systems Engineering group 72 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 73 * contributed to Berkeley. 74 * 75 * All advertising materials mentioning features or use of this software 76 * must display the following acknowledgement: 77 * This product includes software developed by the University of 78 * California, Lawrence Berkeley Laboratory. 79 * 80 * Redistribution and use in source and binary forms, with or without 81 * modification, are permitted provided that the following conditions 82 * are met: 83 * 1. Redistributions of source code must retain the above copyright 84 * notice, this list of conditions and the following disclaimer. 85 * 2. Redistributions in binary form must reproduce the above copyright 86 * notice, this list of conditions and the following disclaimer in the 87 * documentation and/or other materials provided with the distribution. 88 * 3. All advertising materials mentioning features or use of this software 89 * must display the following acknowledgement: 90 * This product includes software developed by the University of 91 * California, Berkeley and its contributors. 92 * 4. Neither the name of the University nor the names of its contributors 93 * may be used to endorse or promote products derived from this software 94 * without specific prior written permission. 95 * 96 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 97 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 98 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 99 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 100 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 101 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 102 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 103 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 104 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 105 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 106 * SUCH DAMAGE. 107 * 108 * from: NetBSD: sbus.c,v 1.13 1999/05/23 07:24:02 mrg Exp 109 * from: @(#)sbus.c 8.1 (Berkeley) 6/11/93 110 */ 111 112 /* 113 * UltraSPARC IOMMU support; used by both the sbus and pci code. 114 */ 115 116 #include "opt_ddb.h" 117 118 #include <sys/param.h> 119 #include <sys/extent.h> 120 #include <sys/malloc.h> 121 #include <sys/systm.h> 122 #include <sys/device.h> 123 #include <vm/vm.h> 124 125 #include <machine/bus.h> 126 #include <sparc64/sparc64/cache.h> 127 #include <sparc64/sparc64/vaddrs.h> 128 #include <sparc64/dev/iommureg.h> 129 #include <sparc64/dev/iommuvar.h> 130 131 #include <machine/autoconf.h> 132 #include <machine/ctlreg.h> 133 #include <machine/cpu.h> 134 135 #ifdef DEBUG 136 #define IDB_DVMA 0x1 137 #define IDB_INTR 0x2 138 int iommudebug = 0x3; 139 #define DPRINTF(l, s) do { if (iommudebug & l) printf s; } while (0) 140 #else 141 #define DPRINTF(l, s) 142 #endif 143 144 /* 145 * initialise the UltraSPARC IOMMU (SBUS or PCI): 146 * - allocate and setup the iotsb. 147 * - enable the IOMMU 148 * - initialise the streaming buffers (if they exist) 149 * - create a private DVMA map. 150 */ 151 void 152 iommu_init(name, is, tsbsize) 153 char *name; 154 struct iommu_state *is; 155 int tsbsize; 156 { 157 158 /* 159 * Setup the iommu. 160 * 161 * The sun4u iommu is part of the SBUS or PCI controller so we 162 * will deal with it here.. 163 * 164 * First we need to allocate a IOTSB. Problem is that the IOMMU 165 * can only access the IOTSB by physical address, so all the 166 * pages must be contiguous. Luckily, the smallest IOTSB size 167 * is one 8K page. 168 */ 169 if (tsbsize != 0) 170 panic("tsbsize != 0; FIX ME"); /* XXX */ 171 172 /* we want 8K pages */ 173 is->is_cr = IOMMUCR_8KPG | IOMMUCR_EN; 174 /* 175 * 176 * The IOMMU address space always ends at 0xffffe000, but the starting 177 * address depends on the size of the map. The map size is 1024 * 2 ^ 178 * is->is_tsbsize entries, where each entry is 8 bytes. The start of 179 * the map can be calculated by (0xffffe000 << (8 + is->is_tsbsize)). 180 * 181 * Note: the stupid IOMMU ignores the high bits of an address, so a 182 * NULL DMA pointer will be translated by the first page of the IOTSB. 183 * To trap bugs we'll skip the first entry in the IOTSB. 184 */ 185 is->is_dvmabase = IOTSB_VSTART(is->is_tsbsize) + NBPG; 186 is->is_tsbsize = tsbsize; 187 is->is_tsb = malloc(NBPG, M_DMAMAP, M_WAITOK); /* XXX */ 188 (void) pmap_extract(pmap_kernel(), (vaddr_t)is->is_tsb, 189 (paddr_t *)&is->is_ptsb); 190 191 #ifdef DEBUG 192 if (iommudebug & IDB_DVMA) 193 { 194 /* Probe the iommu */ 195 struct iommureg *regs = is->is_iommu; 196 int64_t cr, tsb; 197 198 printf("iommu regs at: cr=%lx tsb=%lx flush=%lx\n", ®s->iommu_cr, 199 ®s->iommu_tsb, ®s->iommu_flush); 200 cr = regs->iommu_cr; 201 tsb = regs->iommu_tsb; 202 printf("iommu cr=%lx tsb=%lx\n", (long)cr, (long)tsb); 203 printf("TSB base %p phys %p\n", (long)is->is_tsb, (long)is->is_ptsb); 204 delay(1000000); /* 1 s */ 205 } 206 #endif 207 208 /* 209 * Initialize streaming buffer. 210 */ 211 (void) pmap_extract(pmap_kernel(), (vaddr_t)&is->is_flush, 212 (paddr_t *)&is->is_flushpa); 213 214 /* 215 * now actually start up the IOMMU 216 */ 217 iommu_reset(is); 218 219 /* 220 * Now all the hardware's working we need to allocate a dvma map. 221 */ 222 is->is_dvmamap = extent_create(name, 223 is->is_dvmabase, IOTSB_VEND, 224 M_DEVBUF, 0, 0, EX_NOWAIT); 225 } 226 227 void 228 iommu_reset(is) 229 struct iommu_state *is; 230 { 231 232 /* Need to do 64-bit stores */ 233 bus_space_write_8(is->is_bustag, &is->is_iommu->iommu_cr, 0, is->is_cr); 234 bus_space_write_8(is->is_bustag, &is->is_iommu->iommu_tsb, 0, is->is_ptsb); 235 236 if (!is->is_sb) 237 return; 238 239 /* Enable diagnostics mode? */ 240 bus_space_write_8(is->is_bustag, &is->is_sb->strbuf_ctl, 0, STRBUF_EN); 241 242 /* No streaming buffers? Disable them */ 243 if (bus_space_read_8(is->is_bustag, 244 (bus_space_handle_t)(u_long)&is->is_sb->strbuf_ctl, 0) == 0) 245 is->is_sb = 0; 246 } 247 248 /* 249 * Here are the iommu control routines. 250 */ 251 void 252 iommu_enter(is, va, pa, flags) 253 struct iommu_state *is; 254 vaddr_t va; 255 int64_t pa; 256 int flags; 257 { 258 int64_t tte; 259 260 #ifdef DIAGNOSTIC 261 if (va < is->is_dvmabase) 262 panic("iommu_enter: va 0x%lx not in DVMA space",va); 263 #endif 264 265 tte = MAKEIOTTE(pa, !(flags&BUS_DMA_NOWRITE), !(flags&BUS_DMA_NOCACHE), 266 !(flags&BUS_DMA_COHERENT)); 267 268 /* Is the streamcache flush really needed? */ 269 if (is->is_sb) { 270 bus_space_write_8(is->is_bustag, &is->is_sb->strbuf_pgflush, 0, 271 va); 272 iommu_flush(is); 273 } 274 DPRINTF(IDB_DVMA, ("Clearing TSB slot %d for va %p\n", 275 (int)IOTSBSLOT(va,is->is_tsbsize), va)); 276 is->is_tsb[IOTSBSLOT(va,is->is_tsbsize)] = tte; 277 bus_space_write_8(is->is_bustag, &is->is_iommu->iommu_flush, 278 0, va); 279 DPRINTF(IDB_DVMA, ("iommu_enter: va %lx pa %lx TSB[%lx]@%p=%lx\n", 280 va, (long)pa, IOTSBSLOT(va,is->is_tsbsize), 281 &is->is_tsb[IOTSBSLOT(va,is->is_tsbsize)], 282 (long)tte)); 283 } 284 285 /* 286 * iommu_remove: removes mappings created by iommu_enter 287 * 288 * Only demap from IOMMU if flag is set. 289 */ 290 void 291 iommu_remove(is, va, len) 292 struct iommu_state *is; 293 vaddr_t va; 294 size_t len; 295 { 296 297 #ifdef DIAGNOSTIC 298 if (va < is->is_dvmabase) 299 panic("iommu_remove: va 0x%lx not in DVMA space", (long)va); 300 if ((long)(va + len) < (long)va) 301 panic("iommu_remove: va 0x%lx + len 0x%lx wraps", 302 (long) va, (long) len); 303 if (len & ~0xfffffff) 304 panic("iommu_remove: rediculous len 0x%lx", (long)len); 305 #endif 306 307 va = trunc_page(va); 308 while (len > 0) { 309 if (is->is_sb) { 310 DPRINTF(IDB_DVMA, ("iommu_remove: flushing va %p TSB[%lx]@%p=%lx, %lu bytes left\n", 311 (long)va, (long)IOTSBSLOT(va,is->is_tsbsize), 312 (long)&is->is_tsb[IOTSBSLOT(va,is->is_tsbsize)], 313 (long)(is->is_tsb[IOTSBSLOT(va,is->is_tsbsize)]), 314 (u_long)len)); 315 bus_space_write_8(is->is_bustag, 316 &is->is_sb->strbuf_pgflush, 0, va); 317 if (len <= NBPG) { 318 iommu_flush(is); 319 len = 0; 320 } else len -= NBPG; 321 DPRINTF(IDB_DVMA, ("iommu_remove: flushed va %p TSB[%lx]@%p=%lx, %lu bytes left\n", 322 (long)va, (long)IOTSBSLOT(va,is->is_tsbsize), 323 (long)&is->is_tsb[IOTSBSLOT(va,is->is_tsbsize)], 324 (long)(is->is_tsb[IOTSBSLOT(va,is->is_tsbsize)]), 325 (u_long)len)); 326 } 327 is->is_tsb[IOTSBSLOT(va,is->is_tsbsize)] = 0; 328 bus_space_write_8(is->is_bustag, &is->is_iommu->iommu_flush, 0, va); 329 va += NBPG; 330 } 331 } 332 333 int 334 iommu_flush(is) 335 struct iommu_state *is; 336 { 337 struct timeval cur, flushtimeout; 338 339 #define BUMPTIME(t, usec) { \ 340 register volatile struct timeval *tp = (t); \ 341 register long us; \ 342 \ 343 tp->tv_usec = us = tp->tv_usec + (usec); \ 344 if (us >= 1000000) { \ 345 tp->tv_usec = us - 1000000; \ 346 tp->tv_sec++; \ 347 } \ 348 } 349 350 if (!is->is_sb) 351 return (0); 352 353 /* 354 * Streaming buffer flushes: 355 * 356 * 1 Tell strbuf to flush by storing va to strbuf_pgflush. If 357 * we're not on a cache line boundary (64-bits): 358 * 2 Store 0 in flag 359 * 3 Store pointer to flag in flushsync 360 * 4 wait till flushsync becomes 0x1 361 * 362 * If it takes more than .5 sec, something 363 * went wrong. 364 */ 365 366 is->is_flush = 0; 367 membar_sync(); 368 bus_space_write_8(is->is_bustag, &is->is_sb->strbuf_flushsync, 0, is->is_flushpa); 369 membar_sync(); 370 371 microtime(&flushtimeout); 372 cur = flushtimeout; 373 BUMPTIME(&flushtimeout, 500000); /* 1/2 sec */ 374 375 DPRINTF(IDB_DVMA, ("iommu_flush: flush = %lx at va = %lx pa = %lx now=%lx:%lx until = %lx:%lx\n", 376 (long)is->is_flush, (long)&is->is_flush, 377 (long)is->is_flushpa, cur.tv_sec, cur.tv_usec, 378 flushtimeout.tv_sec, flushtimeout.tv_usec)); 379 /* Bypass non-coherent D$ */ 380 while (!ldxa(is->is_flushpa, ASI_PHYS_CACHED) && 381 ((cur.tv_sec <= flushtimeout.tv_sec) && 382 (cur.tv_usec <= flushtimeout.tv_usec))) 383 microtime(&cur); 384 385 #ifdef DIAGNOSTIC 386 if (!is->is_flush) { 387 printf("iommu_flush: flush timeout %p at %p\n", (long)is->is_flush, 388 (long)is->is_flushpa); /* panic? */ 389 #ifdef DDB 390 Debugger(); 391 #endif 392 } 393 #endif 394 DPRINTF(IDB_DVMA, ("iommu_flush: flushed\n")); 395 return (is->is_flush); 396 } 397 398 /* 399 * IOMMU DVMA operations, common to SBUS and PCI. 400 */ 401 int 402 iommu_dvmamap_load(t, is, map, buf, buflen, p, flags) 403 bus_dma_tag_t t; 404 struct iommu_state *is; 405 bus_dmamap_t map; 406 void *buf; 407 bus_size_t buflen; 408 struct proc *p; 409 int flags; 410 { 411 int s; 412 int err; 413 bus_size_t sgsize; 414 paddr_t curaddr; 415 u_long dvmaddr; 416 vaddr_t vaddr = (vaddr_t)buf; 417 pmap_t pmap; 418 419 if (map->dm_nsegs) { 420 /* Already in use?? */ 421 #ifdef DIAGNOSTIC 422 printf("iommu_dvmamap_load: map still in use\n"); 423 #endif 424 bus_dmamap_unload(t, map); 425 } 426 /* 427 * Make sure that on error condition we return "no valid mappings". 428 */ 429 map->dm_nsegs = 0; 430 431 if (buflen > map->_dm_size) { 432 DPRINTF(IDB_DVMA, 433 ("iommu_dvmamap_load(): error %d > %d -- " 434 "map size exceeded!\n", buflen, map->_dm_size)); 435 return (EINVAL); 436 } 437 438 sgsize = round_page(buflen + ((int)vaddr & PGOFSET)); 439 440 /* 441 * XXX Need to implement "don't dma across this boundry". 442 */ 443 444 s = splhigh(); 445 err = extent_alloc(is->is_dvmamap, sgsize, NBPG, 446 map->_dm_boundary, EX_NOWAIT, (u_long *)&dvmaddr); 447 splx(s); 448 449 if (err != 0) 450 return (err); 451 452 #ifdef DEBUG 453 if (dvmaddr == (bus_addr_t)-1) 454 { 455 printf("iommu_dvmamap_load(): extent_alloc(%d, %x) failed!\n", 456 sgsize, flags); 457 Debugger(); 458 } 459 #endif 460 if (dvmaddr == (bus_addr_t)-1) 461 return (ENOMEM); 462 463 /* 464 * We always use just one segment. 465 */ 466 map->dm_mapsize = buflen; 467 map->dm_nsegs = 1; 468 map->dm_segs[0].ds_addr = dvmaddr + (vaddr & PGOFSET); 469 map->dm_segs[0].ds_len = sgsize; 470 471 if (p != NULL) 472 pmap = p->p_vmspace->vm_map.pmap; 473 else 474 pmap = pmap_kernel(); 475 476 dvmaddr = trunc_page(map->dm_segs[0].ds_addr); 477 sgsize = round_page(buflen + ((int)vaddr & PGOFSET)); 478 for (; buflen > 0; ) { 479 /* 480 * Get the physical address for this page. 481 */ 482 if (pmap_extract(pmap, (vaddr_t)vaddr, &curaddr) == FALSE) { 483 bus_dmamap_unload(t, map); 484 return (-1); 485 } 486 487 /* 488 * Compute the segment size, and adjust counts. 489 */ 490 sgsize = NBPG - ((u_long)vaddr & PGOFSET); 491 if (buflen < sgsize) 492 sgsize = buflen; 493 494 DPRINTF(IDB_DVMA, 495 ("iommu_dvmamap_load: map %p loading va %lx at pa %lx\n", 496 map, (long)dvmaddr, (long)(curaddr & ~(NBPG-1)))); 497 iommu_enter(is, trunc_page(dvmaddr), trunc_page(curaddr), 498 flags); 499 500 dvmaddr += PAGE_SIZE; 501 vaddr += sgsize; 502 buflen -= sgsize; 503 } 504 return (0); 505 } 506 507 508 void 509 iommu_dvmamap_unload(t, is, map) 510 bus_dma_tag_t t; 511 struct iommu_state *is; 512 bus_dmamap_t map; 513 { 514 vaddr_t addr; 515 int len; 516 int error, s; 517 bus_addr_t dvmaddr; 518 bus_size_t sgsize; 519 520 if (map->dm_nsegs != 1) 521 panic("iommu_dvmamap_unload: nsegs = %d", map->dm_nsegs); 522 523 addr = trunc_page(map->dm_segs[0].ds_addr); 524 len = map->dm_segs[0].ds_len; 525 526 DPRINTF(IDB_DVMA, 527 ("iommu_dvmamap_unload: map %p removing va %lx size %lx\n", 528 map, (long)addr, (long)len)); 529 iommu_remove(is, addr, len); 530 dvmaddr = (map->dm_segs[0].ds_addr & ~PGOFSET); 531 sgsize = map->dm_segs[0].ds_len; 532 533 /* Mark the mappings as invalid. */ 534 map->dm_mapsize = 0; 535 map->dm_nsegs = 0; 536 537 /* Unmapping is bus dependent */ 538 s = splhigh(); 539 error = extent_free(is->is_dvmamap, dvmaddr, sgsize, EX_NOWAIT); 540 splx(s); 541 if (error != 0) 542 printf("warning: %qd of DVMA space lost\n", (long long)sgsize); 543 cache_flush((caddr_t)(u_long)dvmaddr, (u_int)sgsize); 544 } 545 546 void 547 iommu_dvmamap_sync(t, is, map, offset, len, ops) 548 bus_dma_tag_t t; 549 struct iommu_state *is; 550 bus_dmamap_t map; 551 bus_addr_t offset; 552 bus_size_t len; 553 int ops; 554 { 555 vaddr_t va = map->dm_segs[0].ds_addr + offset; 556 557 /* 558 * We only support one DMA segment; supporting more makes this code 559 * too unweildy. 560 */ 561 562 if (ops & BUS_DMASYNC_PREREAD) { 563 DPRINTF(IDB_DVMA, 564 ("iommu_dvmamap_sync: syncing va %p len %lu " 565 "BUS_DMASYNC_PREREAD\n", (long)va, (u_long)len)); 566 567 /* Nothing to do */; 568 } 569 if (ops & BUS_DMASYNC_POSTREAD) { 570 DPRINTF(IDB_DVMA, 571 ("iommu_dvmamap_sync: syncing va %p len %lu " 572 "BUS_DMASYNC_POSTREAD\n", (long)va, (u_long)len)); 573 /* if we have a streaming buffer, flush it here first */ 574 if (is->is_sb) 575 while (len > 0) { 576 DPRINTF(IDB_DVMA, 577 ("iommu_dvmamap_sync: flushing va %p, %lu " 578 "bytes left\n", (long)va, (u_long)len)); 579 bus_space_write_8(is->is_bustag, 580 &is->is_sb->strbuf_pgflush, 0, va); 581 if (len <= NBPG) { 582 iommu_flush(is); 583 len = 0; 584 } else 585 len -= NBPG; 586 va += NBPG; 587 } 588 } 589 if (ops & BUS_DMASYNC_PREWRITE) { 590 DPRINTF(IDB_DVMA, 591 ("iommu_dvmamap_sync: syncing va %p len %lu " 592 "BUS_DMASYNC_PREWRITE\n", (long)va, (u_long)len)); 593 /* Nothing to do */; 594 } 595 if (ops & BUS_DMASYNC_POSTWRITE) { 596 DPRINTF(IDB_DVMA, 597 ("iommu_dvmamap_sync: syncing va %p len %lu " 598 "BUS_DMASYNC_POSTWRITE\n", (long)va, (u_long)len)); 599 /* Nothing to do */; 600 } 601 } 602 603 int 604 iommu_dvmamem_alloc(t, is, size, alignment, boundary, segs, nsegs, rsegs, flags) 605 bus_dma_tag_t t; 606 struct iommu_state *is; 607 bus_size_t size, alignment, boundary; 608 bus_dma_segment_t *segs; 609 int nsegs; 610 int *rsegs; 611 int flags; 612 { 613 614 DPRINTF(IDB_DVMA, ("iommu_dvmamem_alloc: sz %qx align %qx bound %qx " 615 "segp %p flags %d", size, alignment, boundary, segs, flags)); 616 return (bus_dmamem_alloc(t->_parent, size, alignment, boundary, 617 segs, nsegs, rsegs, flags)); 618 } 619 620 void 621 iommu_dvmamem_free(t, is, segs, nsegs) 622 bus_dma_tag_t t; 623 struct iommu_state *is; 624 bus_dma_segment_t *segs; 625 int nsegs; 626 { 627 628 DPRINTF(IDB_DVMA, ("iommu_dvmamem_free: segp %p nsegs %d\n", 629 segs, nsegs)); 630 bus_dmamem_free(t->_parent, segs, nsegs); 631 } 632 633 /* 634 * Map the DVMA mappings into the kernel pmap. 635 * Check the flags to see whether we're streaming or coherent. 636 */ 637 int 638 iommu_dvmamem_map(t, is, segs, nsegs, size, kvap, flags) 639 bus_dma_tag_t t; 640 struct iommu_state *is; 641 bus_dma_segment_t *segs; 642 int nsegs; 643 size_t size; 644 caddr_t *kvap; 645 int flags; 646 { 647 vm_page_t m; 648 vaddr_t va; 649 bus_addr_t addr; 650 struct pglist *mlist; 651 paddr_t curaddr; 652 u_long dvmaddr; 653 int cbit, s, err; 654 655 DPRINTF(IDB_DVMA, ("iommu_dvmamem_map: segp %p nsegs %d size %lx\n", 656 segs, nsegs, size)); 657 658 /* 659 * OK, now map this into the IOMMU 660 */ 661 662 s = splhigh(); 663 err = extent_alloc(is->is_dvmamap, segs[0].ds_len, NBPG, 664 segs[0]._ds_boundary, EX_NOWAIT, (u_long *)&dvmaddr); 665 splx(s); 666 667 if (err) 668 return (err); /* XXX: cleanup here? */ 669 670 segs[0].ds_addr = dvmaddr; 671 size = segs[0].ds_len; 672 mlist = segs[0]._ds_mlist; 673 674 /* Map memory into DVMA space */ 675 for (m = mlist->tqh_first; m != NULL; m = m->pageq.tqe_next) { 676 curaddr = VM_PAGE_TO_PHYS(m); 677 DPRINTF(IDB_DVMA, 678 ("iommu_dvmamem_map: map %p loading va %lx at pa %lx\n", 679 (long)m, (long)dvmaddr, (long)(curaddr & ~(NBPG-1)))); 680 iommu_enter(is, dvmaddr, curaddr, flags); 681 dvmaddr += PAGE_SIZE; 682 } 683 684 /* 685 * digest flags: 686 */ 687 cbit = 0; 688 if (flags & BUS_DMA_COHERENT) /* Disable vcache */ 689 cbit |= PMAP_NVC; 690 if (flags & BUS_DMA_NOCACHE) /* sideffects */ 691 cbit |= PMAP_NC; 692 693 /* 694 * Now take this and map it into the CPU since it should already 695 * be in the IOMMU. 696 */ 697 #ifdef DIAGNOSTIC 698 if (!segs[0].ds_addr) { 699 printf("iommu_dvmamem_map: NULL ds_addr\n"); 700 Debugger(); 701 } 702 #endif 703 *kvap = (caddr_t)va = segs[0].ds_addr; 704 mlist = segs[0]._ds_mlist; 705 for (m = mlist->tqh_first; m != NULL; m = m->pageq.tqe_next) { 706 707 if (size == 0) 708 panic("iommu_dvmamem_map: size botch"); 709 710 addr = VM_PAGE_TO_PHYS(m); 711 DPRINTF(IDB_DVMA, ("iommu_dvmamem_map: " 712 "mapping va %lx at %qx\n", va, addr | cbit)); 713 pmap_enter(pmap_kernel(), va, addr | cbit, 714 VM_PROT_READ | VM_PROT_WRITE, PMAP_WIRED); 715 va += PAGE_SIZE; 716 size -= PAGE_SIZE; 717 } 718 719 return (0); 720 } 721 722 /* 723 * Unmap DVMA mappings from kernel 724 */ 725 void 726 iommu_dvmamem_unmap(t, is, kva, size) 727 bus_dma_tag_t t; 728 struct iommu_state *is; 729 caddr_t kva; 730 size_t size; 731 { 732 733 DPRINTF(IDB_DVMA, ("iommu_dvmamem_unmap: kvm %p size %lx\n", 734 kva, size)); 735 736 #ifdef DIAGNOSTIC 737 if ((u_long)kva & PGOFSET) 738 panic("iommu_dvmamem_unmap"); 739 #endif 740 741 size = round_page(size); 742 pmap_remove(pmap_kernel(), (vaddr_t)kva, size); 743 } 744
Indexes created Wed Sep 24 15:09:51 GMT 2025