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iommureg.h revision 1.1 
      1 /*	$NetBSD: iommureg.h,v 1.1 1999/05/23 07:24:02 mrg Exp $	*/
      2 
      3 /*
      4  * Copyright (c) 1992, 1993
      5  *	The Regents of the University of California.  All rights reserved.
      6  *
      7  * This software was developed by the Computer Systems Engineering group
      8  * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
      9  * contributed to Berkeley.
     10  *
     11  * All advertising materials mentioning features or use of this software
     12  * must display the following acknowledgement:
     13  *	This product includes software developed by the University of
     14  *	California, Lawrence Berkeley Laboratory.
     15  *
     16  * Redistribution and use in source and binary forms, with or without
     17  * modification, are permitted provided that the following conditions
     18  * are met:
     19  * 1. Redistributions of source code must retain the above copyright
     20  *    notice, this list of conditions and the following disclaimer.
     21  * 2. Redistributions in binary form must reproduce the above copyright
     22  *    notice, this list of conditions and the following disclaimer in the
     23  *    documentation and/or other materials provided with the distribution.
     24  * 3. All advertising materials mentioning features or use of this software
     25  *    must display the following acknowledgement:
     26  *	This product includes software developed by the University of
     27  *	California, Berkeley and its contributors.
     28  * 4. Neither the name of the University nor the names of its contributors
     29  *    may be used to endorse or promote products derived from this software
     30  *    without specific prior written permission.
     31  *
     32  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
     33  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
     34  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
     35  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
     36  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
     37  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
     38  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     39  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     40  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     41  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     42  * SUCH DAMAGE.
     43  *
     44  *	@(#)sbusreg.h	8.1 (Berkeley) 6/11/93
     45  */
     46 
     47 /*
     48  * UltraSPARC IOMMU registers, common to both the sbus and PCI
     49  * controllers.
     50  */
     51 
     52 struct iommureg {
     53 	u_int64_t	iommu_cr;	/* IOMMU control register */
     54 	u_int64_t	iommu_tsb;	/* IOMMU TSB base register */
     55 	u_int64_t	iommu_flush;	/* IOMMU flush register */
     56 };
     57 
     58 /* control register bits */
     59 #define IOMMUCR_TSB1K		0x000000000000000000LL	/* Nummber of entries in IOTSB */
     60 #define IOMMUCR_TSB2K		0x000000000000010000LL
     61 #define IOMMUCR_TSB4K		0x000000000000020000LL
     62 #define IOMMUCR_TSB8K		0x000000000000030000LL
     63 #define IOMMUCR_TSB16K		0x000000000000040000LL
     64 #define IOMMUCR_TSB32K		0x000000000000050000LL
     65 #define IOMMUCR_TSB64K		0x000000000000060000LL
     66 #define IOMMUCR_TSB128K		0x000000000000070000LL
     67 #define IOMMUCR_8KPG		0x000000000000000000LL	/* 8K iommu page size */
     68 #define IOMMUCR_64KPG		0x000000000000000004LL	/* 64K iommu page size */
     69 #define IOMMUCR_DE		0x000000000000000002LL	/* Diag enable */
     70 #define IOMMUCR_EN		0x000000000000000001LL	/* Enable IOMMU */
     71 
     72 /*
     73  * IOMMU stuff
     74  */
     75 #define	IOTTE_V		0x8000000000000000LL	/* Entry valid */
     76 #define IOTTE_64K	0x2000000000000000LL	/* 8K or 64K page? */
     77 #define IOTTE_8K	0x0000000000000000LL
     78 #define IOTTE_STREAM	0x1000000000000000LL	/* Is page streamable? */
     79 #define	IOTTE_LOCAL	0x0800000000000000LL	/* Accesses to same bus segment? */
     80 #define IOTTE_PAMASK	0x000001ffffffe000LL	/* Let's assume this is correct */
     81 #define IOTTE_C		0x0000000000000010LL	/* Accesses to cacheable space */
     82 #define IOTTE_W		0x0000000000000002LL	/* Writeable */
     83 
     84 #define MAKEIOTTE(pa,w,c,s)	(((pa)&IOTTE_PAMASK)|((w)?IOTTE_W:0)|((c)?IOTTE_C:0)|((s)?IOTTE_STREAM:0)|(IOTTE_V|IOTTE_8K))
     85 #if 0
     86 /* This version generates a pointer to a int64_t */
     87 #define IOTSBSLOT(va,sz)	((((((vm_offset_t)(va))-(0xff800000<<(sz))))>>(13-3))&(~7))
     88 #else
     89 /* Here we just try to create an array index */
     90 #define IOTSBSLOT(va,sz)	((((((vm_offset_t)(va))-(0xff800000<<(sz))))>>(13)))
     91 #endif
     92 
     93 /*
     94  * interrupt map stuff.
     95  */
     96 
     97 #define INTMAP_V	0x080000000LL	/* Interrupt valid (enabled) */
     98 #define INTMAP_TID	0x07c000000LL	/* UPA target ID mask */
     99 #define INTMAP_IGN	0x0000007c0LL	/* Interrupt group no. */
    100 #define INTMAP_INO	0x00000003fLL	/* Interrupt number */
    101 #define INTMAP_INR	(INTMAP_IGN|INTMAP_INO)
    102 #define INTMAP_SLOT	0x000000018LL	/* SBUS slot # */
    103 #define INTMAP_OBIO	0x000000020LL	/* Onboard device */
    104 #define INTMAP_LSHIFT	11		/* Encode level in vector */
    105 #define	INTLEVENCODE(x)	(((x)&0x0f)<<INTMAP_LSHIFT)
    106 #define INTLEV(x)	(((x)>>INTMAP_LSHIFT)&0x0f)
    107 #define INTVEC(x)	((x)&INTMAP_INR)
    108 #define INTSLOT(x)	(((x)>>3)&0x7)
    109 #define	INTPRI(x)	((x)&0x7)
    110