iommureg.h revision 1.16
1 /* $NetBSD: iommureg.h,v 1.16 2011/03/16 02:41:19 mrg Exp $ */ 2 3 /* 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This software was developed by the Computer Systems Engineering group 8 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 9 * contributed to Berkeley. 10 * 11 * All advertising materials mentioning features or use of this software 12 * must display the following acknowledgement: 13 * This product includes software developed by the University of 14 * California, Lawrence Berkeley Laboratory. 15 * 16 * Redistribution and use in source and binary forms, with or without 17 * modification, are permitted provided that the following conditions 18 * are met: 19 * 1. Redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer. 21 * 2. Redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution. 24 * 3. Neither the name of the University nor the names of its contributors 25 * may be used to endorse or promote products derived from this software 26 * without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 29 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 31 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 37 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 38 * SUCH DAMAGE. 39 * 40 * @(#)sbusreg.h 8.1 (Berkeley) 6/11/93 41 */ 42 43 #ifndef _SPARC64_DEV_IOMMUREG_H_ 44 #define _SPARC64_DEV_IOMMUREG_H_ 45 46 /* 47 * UltraSPARC IOMMU registers, common to both the sbus and PCI 48 * controllers. 49 */ 50 51 /* iommmu registers */ 52 struct iommureg { 53 volatile uint64_t iommu_cr; /* IOMMU control register */ 54 volatile uint64_t iommu_tsb; /* IOMMU TSB base register */ 55 volatile uint64_t iommu_flush; /* IOMMU flush register */ 56 volatile u_int64_t iommu_ctxflush; 57 volatile u_int64_t iommu_reserved[28]; 58 volatile u_int64_t iommu_cache_flush; 59 volatile u_int64_t iommu_cache_invalidate; 60 volatile u_int64_t iommu_reserved2[30]; 61 }; 62 63 /* streaming buffer registers */ 64 struct iommu_strbuf { 65 uint64_t strbuf_ctl; /* streaming buffer control reg */ 66 uint64_t strbuf_pgflush; /* streaming buffer page flush */ 67 uint64_t strbuf_flushsync;/* streaming buffer flush sync */ 68 }; 69 70 #define IOMMUREG(x) (offsetof(struct iommureg, x)) 71 #define STRBUFREG(x) (offsetof(struct iommu_strbuf, x)) 72 73 /* streaming buffer control register */ 74 #define STRBUF_EN 0x000000000000000001LL 75 #define STRBUF_D 0x000000000000000002LL 76 77 /* control register bits */ 78 #define IOMMUCR_TSB1K 0x000000000000000000LL /* Nummber of entries in IOTSB */ 79 #define IOMMUCR_TSB2K 0x000000000000010000LL 80 #define IOMMUCR_TSB4K 0x000000000000020000LL 81 #define IOMMUCR_TSB8K 0x000000000000030000LL 82 #define IOMMUCR_TSB16K 0x000000000000040000LL 83 #define IOMMUCR_TSB32K 0x000000000000050000LL 84 #define IOMMUCR_TSB64K 0x000000000000060000LL 85 #define IOMMUCR_TSB128K 0x000000000000070000LL 86 #define IOMMUCR_TSBMASK 0xfffffffffffff8ffffLL /* Mask for above */ 87 #define IOMMUCR_8KPG 0x000000000000000000LL /* 8K iommu page size */ 88 #define IOMMUCR_64KPG 0x000000000000000004LL /* 64K iommu page size */ 89 #define IOMMUCR_DE 0x000000000000000002LL /* Diag enable */ 90 #define IOMMUCR_EN 0x000000000000000001LL /* Enable IOMMU */ 91 92 /* 93 * IOMMU stuff 94 */ 95 #define IOTTE_V 0x8000000000000000LL /* Entry valid */ 96 #define IOTTE_64K 0x2000000000000000LL /* 8K or 64K page? */ 97 #define IOTTE_8K 0x0000000000000000LL 98 #define IOTTE_STREAM 0x1000000000000000LL /* Is page streamable? */ 99 #define IOTTE_LOCAL 0x0800000000000000LL /* Accesses to same bus segment? */ 100 #define IOTTE_PAMASK 0x000001ffffffe000LL /* Let's assume this is correct */ 101 #define IOTTE_C 0x0000000000000010LL /* Accesses to cacheable space */ 102 #define IOTTE_W 0x0000000000000002LL /* Writable */ 103 104 /* 105 * On sun4u each bus controller has a separate IOMMU. The IOMMU has 106 * a TSB which must be page aligned and physically contiguous. Mappings 107 * can be of 8K IOMMU pages or 64K IOMMU pages. We use 8K for compatibility 108 * with the CPU's MMU. 109 * 110 * On sysio, psycho, and psycho+, IOMMU TSBs using 8K pages can map the 111 * following size segments: 112 * 113 * VA size VA base TSB size tsbsize 114 * -------- -------- --------- ------- 115 * 8MB ff800000 8K 0 116 * 16MB ff000000 16K 1 117 * 32MB fe000000 32K 2 118 * 64MB fc000000 64K 3 119 * 128MB f8000000 128K 4 120 * 256MB f0000000 256K 5 121 * 512MB e0000000 512K 6 122 * 1GB c0000000 1MB 7 123 * 124 * Unfortunately, sabres on UltraSPARC IIi and IIe processors does not use 125 * this scheme to determine the IOVA base address. Instead, bits 31-29 are 126 * used to check against the Target Address Space register in the IIi and 127 * the IOMMU is used if they hit. God knows what goes on in the IIe. 128 * 129 */ 130 131 132 #define IOTSB_VEND (u_int)(0xffffffffffffffffLL<<PGSHIFT) 133 #define IOTSB_VSTART(sz) (u_int)(IOTSB_VEND << ((sz)+10)) 134 #define IOTSB_VSIZE(sz) (u_int)(1 << ((sz)+10+PGSHIFT)) 135 136 #define MAKEIOTTE(pa,w,c,s) (((pa)&IOTTE_PAMASK)|((w)?IOTTE_W:0)|((c)?IOTTE_C:0)|((s)?IOTTE_STREAM:0)|(IOTTE_V|IOTTE_8K)) 137 #define IOTSBSLOT(va,sz) ((u_int)(((vaddr_t)(va))-(is->is_dvmabase))>>PGSHIFT) 138 139 /* 140 * interrupt map stuff. this belongs elsewhere. 141 */ 142 143 #define INTMAP_V 0x080000000LL /* Interrupt valid (enabled) */ 144 #define INTMAP_TID 0x07c000000LL /* UPA target ID mask */ 145 #define INTMAP_TID_SHIFT 26 146 #define INTMAP_IGN 0x0000007c0LL /* Interrupt group no (sbus only). */ 147 #define INTMAP_IGN_SHIFT 6 148 #define INTMAP_INO 0x00000003fLL /* Interrupt number */ 149 #define INTMAP_INR (INTMAP_IGN|INTMAP_INO) 150 #define INTMAP_SBUSSLOT 0x000000018LL /* SBUS slot # */ 151 #define INTMAP_PCIBUS 0x000000010LL /* PCI bus number (A or B) */ 152 #define INTMAP_PCISLOT 0x00000000cLL /* PCI slot # */ 153 #define INTMAP_PCIINT 0x000000003LL /* PCI interrupt #A,#B,#C,#D */ 154 #define INTMAP_OBIO 0x000000020LL /* Onboard device */ 155 #define INTMAP_LSHIFT 11 /* Encode level in vector */ 156 #define INTLEVENCODE(x) (((x)&0x0f)<<INTMAP_LSHIFT) 157 #define INTLEV(x) (((x)>>INTMAP_LSHIFT)&0x0f) 158 #define INTVEC(x) ((x)&INTMAP_INR) 159 #define INTSLOT(x) (((x)>>3)&0x7) 160 #define INTPRI(x) ((x)&0x7) 161 #define INTINO(x) ((x)&INTMAP_INO) 162 #define INTIGN(x) ((x)&INTMAP_IGN) 163 164 #define INTPCI_MAXOBINO 0x16 /* maximum OBIO INO value for PCI */ 165 #define INTPCIOBINOX(x) ((x)&0x1f) /* OBIO ino index (for PCI machines) */ 166 #define INTPCIINOX(x) (((x)&0x1c)>>2) /* PCI ino index */ 167 168 #endif /* _SPARC64_DEV_IOMMUREG_H_ */ 169
Indexes created Sun Oct 19 02:09:48 GMT 2025