pci_machdep.c revision 1.32 1 1.32 eeh /* $NetBSD: pci_machdep.c,v 1.32 2002/06/29 02:35:22 eeh Exp $ */
2 1.1 mrg
3 1.1 mrg /*
4 1.5 mrg * Copyright (c) 1999, 2000 Matthew R. Green
5 1.1 mrg * All rights reserved.
6 1.1 mrg *
7 1.1 mrg * Redistribution and use in source and binary forms, with or without
8 1.1 mrg * modification, are permitted provided that the following conditions
9 1.1 mrg * are met:
10 1.1 mrg * 1. Redistributions of source code must retain the above copyright
11 1.1 mrg * notice, this list of conditions and the following disclaimer.
12 1.1 mrg * 2. Redistributions in binary form must reproduce the above copyright
13 1.1 mrg * notice, this list of conditions and the following disclaimer in the
14 1.1 mrg * documentation and/or other materials provided with the distribution.
15 1.1 mrg * 3. The name of the author may not be used to endorse or promote products
16 1.1 mrg * derived from this software without specific prior written permission.
17 1.1 mrg *
18 1.1 mrg * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 1.1 mrg * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 1.1 mrg * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 1.1 mrg * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 1.1 mrg * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
23 1.1 mrg * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
24 1.1 mrg * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
25 1.1 mrg * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
26 1.1 mrg * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 1.1 mrg * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 1.1 mrg * SUCH DAMAGE.
29 1.1 mrg */
30 1.1 mrg
31 1.1 mrg /*
32 1.1 mrg * functions expected by the MI PCI code.
33 1.1 mrg */
34 1.1 mrg
35 1.1 mrg #ifdef DEBUG
36 1.1 mrg #define SPDB_CONF 0x01
37 1.1 mrg #define SPDB_INTR 0x04
38 1.1 mrg #define SPDB_INTMAP 0x08
39 1.1 mrg #define SPDB_INTFIX 0x10
40 1.22 eeh #define SPDB_PROBE 0x20
41 1.4 mrg int sparc_pci_debug = 0x0;
42 1.1 mrg #define DPRINTF(l, s) do { if (sparc_pci_debug & l) printf s; } while (0)
43 1.1 mrg #else
44 1.1 mrg #define DPRINTF(l, s)
45 1.1 mrg #endif
46 1.1 mrg
47 1.1 mrg #include <sys/types.h>
48 1.1 mrg #include <sys/param.h>
49 1.1 mrg #include <sys/time.h>
50 1.1 mrg #include <sys/systm.h>
51 1.1 mrg #include <sys/errno.h>
52 1.1 mrg #include <sys/device.h>
53 1.1 mrg #include <sys/malloc.h>
54 1.1 mrg
55 1.1 mrg #define _SPARC_BUS_DMA_PRIVATE
56 1.1 mrg #include <machine/bus.h>
57 1.1 mrg #include <machine/autoconf.h>
58 1.22 eeh #include <machine/openfirm.h>
59 1.1 mrg
60 1.1 mrg #include <dev/pci/pcivar.h>
61 1.1 mrg #include <dev/pci/pcireg.h>
62 1.1 mrg
63 1.19 mrg #include <dev/ofw/ofw_pci.h>
64 1.19 mrg
65 1.1 mrg #include <sparc64/dev/iommureg.h>
66 1.1 mrg #include <sparc64/dev/iommuvar.h>
67 1.1 mrg #include <sparc64/dev/psychoreg.h>
68 1.1 mrg #include <sparc64/dev/psychovar.h>
69 1.1 mrg
70 1.1 mrg /* this is a base to be copied */
71 1.1 mrg struct sparc_pci_chipset _sparc_pci_chipset = {
72 1.1 mrg NULL,
73 1.1 mrg };
74 1.2 mrg
75 1.30 thorpej static pcitag_t
76 1.30 thorpej ofpci_make_tag(pci_chipset_tag_t pc, int node, int b, int d, int f)
77 1.30 thorpej {
78 1.30 thorpej pcitag_t tag;
79 1.30 thorpej
80 1.30 thorpej tag = PCITAG_CREATE(node, b, d, f);
81 1.30 thorpej
82 1.30 thorpej /* Enable all the different spaces for this device */
83 1.30 thorpej pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG,
84 1.30 thorpej PCI_COMMAND_MEM_ENABLE|PCI_COMMAND_MASTER_ENABLE|
85 1.30 thorpej PCI_COMMAND_IO_ENABLE);
86 1.30 thorpej return (tag);
87 1.30 thorpej }
88 1.30 thorpej
89 1.1 mrg /*
90 1.1 mrg * functions provided to the MI code.
91 1.1 mrg */
92 1.1 mrg
93 1.1 mrg void
94 1.1 mrg pci_attach_hook(parent, self, pba)
95 1.1 mrg struct device *parent;
96 1.1 mrg struct device *self;
97 1.1 mrg struct pcibus_attach_args *pba;
98 1.1 mrg {
99 1.1 mrg }
100 1.1 mrg
101 1.1 mrg int
102 1.1 mrg pci_bus_maxdevs(pc, busno)
103 1.1 mrg pci_chipset_tag_t pc;
104 1.1 mrg int busno;
105 1.1 mrg {
106 1.1 mrg
107 1.1 mrg return 32;
108 1.1 mrg }
109 1.19 mrg
110 1.1 mrg pcitag_t
111 1.1 mrg pci_make_tag(pc, b, d, f)
112 1.1 mrg pci_chipset_tag_t pc;
113 1.1 mrg int b;
114 1.1 mrg int d;
115 1.1 mrg int f;
116 1.1 mrg {
117 1.22 eeh struct ofw_pci_register reg;
118 1.22 eeh pcitag_t tag;
119 1.22 eeh int busrange[2];
120 1.22 eeh int node, len;
121 1.22 eeh #ifdef DEBUG
122 1.22 eeh char name[80];
123 1.22 eeh bzero(name, sizeof(name));
124 1.22 eeh #endif
125 1.1 mrg
126 1.22 eeh /*
127 1.22 eeh * Hunt for the node that corresponds to this device
128 1.22 eeh *
129 1.22 eeh * We could cache this info in an array in the parent
130 1.22 eeh * device... except then we have problems with devices
131 1.22 eeh * attached below pci-pci bridges, and we would need to
132 1.22 eeh * add special code to the pci-pci bridge to cache this
133 1.22 eeh * info.
134 1.22 eeh */
135 1.1 mrg
136 1.22 eeh tag = PCITAG_CREATE(-1, b, d, f);
137 1.22 eeh node = pc->rootnode;
138 1.22 eeh /*
139 1.22 eeh * First make sure we're on the right bus. If our parent
140 1.22 eeh * has a bus-range property and we're not in the range,
141 1.22 eeh * then we're obviously on the wrong bus. So go up one
142 1.22 eeh * level.
143 1.22 eeh */
144 1.22 eeh #ifdef DEBUG
145 1.22 eeh if (sparc_pci_debug & SPDB_PROBE) {
146 1.22 eeh OF_getprop(node, "name", &name, sizeof(name));
147 1.22 eeh printf("curnode %x %s\n", node, name);
148 1.22 eeh }
149 1.22 eeh #endif
150 1.22 eeh #if 0
151 1.22 eeh while ((OF_getprop(OF_parent(node), "bus-range", (void *)&busrange,
152 1.22 eeh sizeof(busrange)) == sizeof(busrange)) &&
153 1.22 eeh (b < busrange[0] || b > busrange[1])) {
154 1.22 eeh /* Out of range, go up one */
155 1.22 eeh node = OF_parent(node);
156 1.22 eeh #ifdef DEBUG
157 1.22 eeh if (sparc_pci_debug & SPDB_PROBE) {
158 1.22 eeh OF_getprop(node, "name", &name, sizeof(name));
159 1.22 eeh printf("going up to node %x %s\n", node, name);
160 1.22 eeh }
161 1.22 eeh #endif
162 1.22 eeh }
163 1.22 eeh #endif
164 1.22 eeh /*
165 1.22 eeh * Now traverse all peers until we find the node or we find
166 1.22 eeh * the right bridge.
167 1.22 eeh *
168 1.22 eeh * XXX We go up one and down one to make sure nobody's missed.
169 1.22 eeh * but this should not be necessary.
170 1.22 eeh */
171 1.22 eeh for (node = ((node)); node; node = OF_peer(node)) {
172 1.1 mrg
173 1.22 eeh #ifdef DEBUG
174 1.22 eeh if (sparc_pci_debug & SPDB_PROBE) {
175 1.22 eeh OF_getprop(node, "name", &name, sizeof(name));
176 1.22 eeh printf("checking node %x %s\n", node, name);
177 1.22 eeh }
178 1.22 eeh #endif
179 1.1 mrg
180 1.22 eeh #if 1
181 1.1 mrg /*
182 1.22 eeh * Check for PCI-PCI bridges. If the device we want is
183 1.22 eeh * in the bus-range for that bridge, work our way down.
184 1.1 mrg */
185 1.22 eeh while ((OF_getprop(node, "bus-range", (void *)&busrange,
186 1.22 eeh sizeof(busrange)) == sizeof(busrange)) &&
187 1.22 eeh (b >= busrange[0] && b <= busrange[1])) {
188 1.22 eeh /* Go down 1 level */
189 1.22 eeh node = OF_child(node);
190 1.22 eeh #ifdef DEBUG
191 1.22 eeh if (sparc_pci_debug & SPDB_PROBE) {
192 1.22 eeh OF_getprop(node, "name", &name, sizeof(name));
193 1.22 eeh printf("going down to node %x %s\n",
194 1.22 eeh node, name);
195 1.22 eeh }
196 1.22 eeh #endif
197 1.1 mrg }
198 1.22 eeh #endif
199 1.22 eeh /*
200 1.22 eeh * We only really need the first `reg' property.
201 1.22 eeh *
202 1.22 eeh * For simplicity, we'll query the `reg' when we
203 1.22 eeh * need it. Otherwise we could malloc() it, but
204 1.22 eeh * that gets more complicated.
205 1.22 eeh */
206 1.22 eeh len = OF_getproplen(node, "reg");
207 1.22 eeh if (len < sizeof(reg))
208 1.22 eeh continue;
209 1.22 eeh if (OF_getprop(node, "reg", (void *)®, sizeof(reg)) != len)
210 1.22 eeh panic("pci_probe_bus: OF_getprop len botch");
211 1.22 eeh
212 1.22 eeh if (b != OFW_PCI_PHYS_HI_BUS(reg.phys_hi))
213 1.22 eeh continue;
214 1.22 eeh if (d != OFW_PCI_PHYS_HI_DEVICE(reg.phys_hi))
215 1.22 eeh continue;
216 1.22 eeh if (f != OFW_PCI_PHYS_HI_FUNCTION(reg.phys_hi))
217 1.22 eeh continue;
218 1.22 eeh
219 1.22 eeh /* Got a match */
220 1.27 eeh tag = ofpci_make_tag(pc, node, b, d, f);
221 1.22 eeh
222 1.22 eeh return (tag);
223 1.1 mrg }
224 1.22 eeh /* No device found -- return a dead tag */
225 1.27 eeh return (tag);
226 1.28 thorpej }
227 1.28 thorpej
228 1.28 thorpej void
229 1.28 thorpej pci_decompose_tag(pc, tag, bp, dp, fp)
230 1.28 thorpej pci_chipset_tag_t pc;
231 1.28 thorpej pcitag_t tag;
232 1.28 thorpej int *bp, *dp, *fp;
233 1.28 thorpej {
234 1.28 thorpej
235 1.28 thorpej if (bp != NULL)
236 1.28 thorpej *bp = PCITAG_BUS(tag);
237 1.28 thorpej if (dp != NULL)
238 1.28 thorpej *dp = PCITAG_DEV(tag);
239 1.28 thorpej if (fp != NULL)
240 1.28 thorpej *fp = PCITAG_FUN(tag);
241 1.27 eeh }
242 1.27 eeh
243 1.30 thorpej int
244 1.30 thorpej pci_enumerate_bus(struct pci_softc *sc,
245 1.30 thorpej int (*match)(struct pci_attach_args *), struct pci_attach_args *pap)
246 1.27 eeh {
247 1.30 thorpej struct ofw_pci_register reg;
248 1.30 thorpej pci_chipset_tag_t pc = sc->sc_pc;
249 1.27 eeh pcitag_t tag;
250 1.32 eeh pcireg_t class, csr;
251 1.30 thorpej int node, b, d, f, ret;
252 1.30 thorpej char name[30];
253 1.32 eeh extern int pci_config_dump;
254 1.30 thorpej
255 1.31 eeh if (sc->sc_bridgetag)
256 1.31 eeh node = PCITAG_NODE(*sc->sc_bridgetag);
257 1.31 eeh else
258 1.31 eeh node = pc->rootnode;
259 1.31 eeh
260 1.32 eeh /* Turn on parity for the bus. */
261 1.32 eeh tag = ofpci_make_tag(pc, node, sc->sc_bus, 0, 0);
262 1.32 eeh csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
263 1.32 eeh csr |= PCI_COMMAND_PARITY_ENABLE;
264 1.32 eeh pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr);
265 1.32 eeh
266 1.32 eeh if (pci_config_dump) pci_conf_print(pc, tag, NULL);
267 1.32 eeh
268 1.31 eeh for (node = OF_child(node); node != 0 && node != -1;
269 1.30 thorpej node = OF_peer(node)) {
270 1.30 thorpej name[0] = name[29] = 0;
271 1.30 thorpej OF_getprop(node, "name", name, sizeof(name));
272 1.27 eeh
273 1.30 thorpej if (OF_getprop(node, "class-code", &class, sizeof(class)) !=
274 1.30 thorpej sizeof(class))
275 1.30 thorpej continue;
276 1.30 thorpej if (OF_getprop(node, "reg", ®, sizeof(reg)) < sizeof(reg))
277 1.30 thorpej panic("pci_enumerate_bus: \"%s\" regs too small", name);
278 1.27 eeh
279 1.30 thorpej b = OFW_PCI_PHYS_HI_BUS(reg.phys_hi);
280 1.30 thorpej d = OFW_PCI_PHYS_HI_DEVICE(reg.phys_hi);
281 1.30 thorpej f = OFW_PCI_PHYS_HI_FUNCTION(reg.phys_hi);
282 1.30 thorpej
283 1.30 thorpej if (sc->sc_bus != b) {
284 1.30 thorpej printf("%s: WARNING: incorrect bus # for \"%s\" "
285 1.30 thorpej "(%d/%d/%d)\n", sc->sc_dev.dv_xname, name, b, d, f);
286 1.30 thorpej continue;
287 1.30 thorpej }
288 1.27 eeh
289 1.30 thorpej tag = ofpci_make_tag(pc, node, b, d, f);
290 1.32 eeh
291 1.32 eeh /*
292 1.32 eeh * Turn on parity and fast-back-to-back for the device.
293 1.32 eeh */
294 1.32 eeh csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
295 1.32 eeh if (csr & PCI_STATUS_BACKTOBACK_SUPPORT)
296 1.32 eeh csr |= PCI_COMMAND_BACKTOBACK_ENABLE;
297 1.32 eeh csr |= PCI_COMMAND_PARITY_ENABLE;
298 1.32 eeh pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr);
299 1.32 eeh
300 1.30 thorpej ret = pci_probe_device(sc, tag, match, pap);
301 1.30 thorpej if (match != NULL && ret != 0)
302 1.30 thorpej return (ret);
303 1.30 thorpej }
304 1.30 thorpej return (0);
305 1.1 mrg }
306 1.1 mrg
307 1.1 mrg /* assume we are mapped little-endian/side-effect */
308 1.1 mrg pcireg_t
309 1.1 mrg pci_conf_read(pc, tag, reg)
310 1.1 mrg pci_chipset_tag_t pc;
311 1.1 mrg pcitag_t tag;
312 1.1 mrg int reg;
313 1.1 mrg {
314 1.1 mrg struct psycho_pbm *pp = pc->cookie;
315 1.1 mrg struct psycho_softc *sc = pp->pp_sc;
316 1.22 eeh pcireg_t val = (pcireg_t)~0;
317 1.22 eeh
318 1.22 eeh DPRINTF(SPDB_CONF, ("pci_conf_read: tag %lx reg %x ",
319 1.22 eeh (long)tag, reg));
320 1.22 eeh if (PCITAG_NODE(tag) != -1) {
321 1.22 eeh DPRINTF(SPDB_CONF, ("asi=%x addr=%qx (offset=%x) ...",
322 1.26 eeh sc->sc_configaddr._asi,
323 1.26 eeh (long long)(sc->sc_configaddr._ptr +
324 1.22 eeh PCITAG_OFFSET(tag) + reg),
325 1.22 eeh (int)PCITAG_OFFSET(tag) + reg));
326 1.1 mrg
327 1.1 mrg val = bus_space_read_4(sc->sc_configtag, sc->sc_configaddr,
328 1.22 eeh PCITAG_OFFSET(tag) + reg);
329 1.1 mrg }
330 1.22 eeh #ifdef DEBUG
331 1.24 mrg else DPRINTF(SPDB_CONF, ("pci_conf_read: bogus pcitag %x\n",
332 1.24 mrg (int)PCITAG_OFFSET(tag)));
333 1.22 eeh #endif
334 1.1 mrg DPRINTF(SPDB_CONF, (" returning %08x\n", (u_int)val));
335 1.1 mrg
336 1.1 mrg return (val);
337 1.1 mrg }
338 1.1 mrg
339 1.1 mrg void
340 1.1 mrg pci_conf_write(pc, tag, reg, data)
341 1.1 mrg pci_chipset_tag_t pc;
342 1.1 mrg pcitag_t tag;
343 1.1 mrg int reg;
344 1.1 mrg pcireg_t data;
345 1.1 mrg {
346 1.1 mrg struct psycho_pbm *pp = pc->cookie;
347 1.1 mrg struct psycho_softc *sc = pp->pp_sc;
348 1.1 mrg
349 1.22 eeh DPRINTF(SPDB_CONF, ("pci_conf_write: tag %lx; reg %x; data %x; ",
350 1.22 eeh (long)PCITAG_OFFSET(tag), reg, (int)data));
351 1.1 mrg DPRINTF(SPDB_CONF, ("asi = %x; readaddr = %qx (offset = %x)\n",
352 1.26 eeh sc->sc_configaddr._asi,
353 1.26 eeh (long long)(sc->sc_configaddr._ptr + PCITAG_OFFSET(tag) + reg),
354 1.22 eeh (int)PCITAG_OFFSET(tag) + reg));
355 1.1 mrg
356 1.24 mrg /* If we don't know it, just punt it. */
357 1.24 mrg if (PCITAG_NODE(tag) == -1) {
358 1.24 mrg DPRINTF(SPDB_CONF, ("pci_conf_write: bad addr"));
359 1.24 mrg return;
360 1.24 mrg }
361 1.1 mrg
362 1.22 eeh bus_space_write_4(sc->sc_configtag, sc->sc_configaddr,
363 1.22 eeh PCITAG_OFFSET(tag) + reg, data);
364 1.1 mrg }
365 1.1 mrg
366 1.1 mrg /*
367 1.1 mrg * interrupt mapping foo.
368 1.20 mrg * XXX: how does this deal with multiple interrupts for a device?
369 1.1 mrg */
370 1.1 mrg int
371 1.16 sommerfe pci_intr_map(pa, ihp)
372 1.16 sommerfe struct pci_attach_args *pa;
373 1.1 mrg pci_intr_handle_t *ihp;
374 1.1 mrg {
375 1.22 eeh pcitag_t tag = pa->pa_tag;
376 1.22 eeh int interrupts;
377 1.22 eeh int len, node = PCITAG_NODE(tag);
378 1.22 eeh char devtype[30];
379 1.22 eeh
380 1.22 eeh len = OF_getproplen(node, "interrupts");
381 1.22 eeh if (len < sizeof(interrupts)) {
382 1.22 eeh DPRINTF(SPDB_INTMAP,
383 1.22 eeh ("pci_intr_map: interrupts len %d too small\n", len));
384 1.22 eeh return (ENODEV);
385 1.22 eeh }
386 1.22 eeh if (OF_getprop(node, "interrupts", (void *)&interrupts,
387 1.22 eeh sizeof(interrupts)) != len) {
388 1.22 eeh DPRINTF(SPDB_INTMAP,
389 1.22 eeh ("pci_intr_map: could not read interrupts\n"));
390 1.22 eeh return (ENODEV);
391 1.22 eeh }
392 1.20 mrg
393 1.22 eeh if (OF_mapintr(node, &interrupts, sizeof(interrupts),
394 1.23 eeh sizeof(interrupts)) < 0) {
395 1.22 eeh printf("OF_mapintr failed\n");
396 1.22 eeh }
397 1.22 eeh /* Try to find an IPL for this type of device. */
398 1.22 eeh if (OF_getprop(node, "device_type", &devtype, sizeof(devtype)) > 0) {
399 1.22 eeh for (len = 0; intrmap[len].in_class; len++)
400 1.22 eeh if (strcmp(intrmap[len].in_class, devtype) == 0) {
401 1.22 eeh interrupts |= INTLEVENCODE(intrmap[len].in_lev);
402 1.22 eeh break;
403 1.22 eeh }
404 1.22 eeh }
405 1.20 mrg
406 1.22 eeh /* XXXX -- we use the ino. What if there is a valid IGN? */
407 1.22 eeh *ihp = interrupts;
408 1.22 eeh return (0);
409 1.1 mrg }
410 1.1 mrg
411 1.1 mrg const char *
412 1.1 mrg pci_intr_string(pc, ih)
413 1.1 mrg pci_chipset_tag_t pc;
414 1.1 mrg pci_intr_handle_t ih;
415 1.1 mrg {
416 1.1 mrg static char str[16];
417 1.1 mrg
418 1.1 mrg DPRINTF(SPDB_INTR, ("pci_intr_string: ih %u", ih));
419 1.22 eeh sprintf(str, "ivec %x", ih);
420 1.1 mrg DPRINTF(SPDB_INTR, ("; returning %s\n", str));
421 1.1 mrg
422 1.1 mrg return (str);
423 1.8 cgd }
424 1.8 cgd
425 1.8 cgd const struct evcnt *
426 1.8 cgd pci_intr_evcnt(pc, ih)
427 1.8 cgd pci_chipset_tag_t pc;
428 1.8 cgd pci_intr_handle_t ih;
429 1.8 cgd {
430 1.8 cgd
431 1.8 cgd /* XXX for now, no evcnt parent reported */
432 1.8 cgd return NULL;
433 1.1 mrg }
434 1.1 mrg
435 1.1 mrg void *
436 1.1 mrg pci_intr_establish(pc, ih, level, func, arg)
437 1.1 mrg pci_chipset_tag_t pc;
438 1.1 mrg pci_intr_handle_t ih;
439 1.1 mrg int level;
440 1.1 mrg int (*func) __P((void *));
441 1.1 mrg void *arg;
442 1.1 mrg {
443 1.1 mrg void *cookie;
444 1.1 mrg struct psycho_pbm *pp = (struct psycho_pbm *)pc->cookie;
445 1.1 mrg
446 1.1 mrg DPRINTF(SPDB_INTR, ("pci_intr_establish: ih %lu; level %d", (u_long)ih, level));
447 1.13 pk cookie = bus_intr_establish(pp->pp_memt, ih, level, 0, func, arg);
448 1.1 mrg
449 1.1 mrg DPRINTF(SPDB_INTR, ("; returning handle %p\n", cookie));
450 1.1 mrg return (cookie);
451 1.1 mrg }
452 1.1 mrg
453 1.1 mrg void
454 1.1 mrg pci_intr_disestablish(pc, cookie)
455 1.1 mrg pci_chipset_tag_t pc;
456 1.1 mrg void *cookie;
457 1.1 mrg {
458 1.1 mrg
459 1.1 mrg DPRINTF(SPDB_INTR, ("pci_intr_disestablish: cookie %p\n", cookie));
460 1.1 mrg
461 1.1 mrg /* XXX */
462 1.1 mrg panic("can't disestablish PCI interrupts yet");
463 1.1 mrg }
464