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pci_machdep.c revision 1.36
      1  1.36    martin /*	$NetBSD: pci_machdep.c,v 1.36 2003/05/04 21:36:26 martin Exp $	*/
      2   1.1       mrg 
      3   1.1       mrg /*
      4   1.5       mrg  * Copyright (c) 1999, 2000 Matthew R. Green
      5   1.1       mrg  * All rights reserved.
      6   1.1       mrg  *
      7   1.1       mrg  * Redistribution and use in source and binary forms, with or without
      8   1.1       mrg  * modification, are permitted provided that the following conditions
      9   1.1       mrg  * are met:
     10   1.1       mrg  * 1. Redistributions of source code must retain the above copyright
     11   1.1       mrg  *    notice, this list of conditions and the following disclaimer.
     12   1.1       mrg  * 2. Redistributions in binary form must reproduce the above copyright
     13   1.1       mrg  *    notice, this list of conditions and the following disclaimer in the
     14   1.1       mrg  *    documentation and/or other materials provided with the distribution.
     15   1.1       mrg  * 3. The name of the author may not be used to endorse or promote products
     16   1.1       mrg  *    derived from this software without specific prior written permission.
     17   1.1       mrg  *
     18   1.1       mrg  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     19   1.1       mrg  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     20   1.1       mrg  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     21   1.1       mrg  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     22   1.1       mrg  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
     23   1.1       mrg  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
     24   1.1       mrg  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
     25   1.1       mrg  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
     26   1.1       mrg  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     27   1.1       mrg  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     28   1.1       mrg  * SUCH DAMAGE.
     29   1.1       mrg  */
     30   1.1       mrg 
     31   1.1       mrg /*
     32   1.1       mrg  * functions expected by the MI PCI code.
     33   1.1       mrg  */
     34   1.1       mrg 
     35   1.1       mrg #ifdef DEBUG
     36   1.1       mrg #define SPDB_CONF	0x01
     37   1.1       mrg #define SPDB_INTR	0x04
     38   1.1       mrg #define SPDB_INTMAP	0x08
     39   1.1       mrg #define SPDB_INTFIX	0x10
     40  1.22       eeh #define SPDB_PROBE	0x20
     41   1.4       mrg int sparc_pci_debug = 0x0;
     42   1.1       mrg #define DPRINTF(l, s)	do { if (sparc_pci_debug & l) printf s; } while (0)
     43   1.1       mrg #else
     44   1.1       mrg #define DPRINTF(l, s)
     45   1.1       mrg #endif
     46   1.1       mrg 
     47   1.1       mrg #include <sys/types.h>
     48   1.1       mrg #include <sys/param.h>
     49   1.1       mrg #include <sys/time.h>
     50   1.1       mrg #include <sys/systm.h>
     51   1.1       mrg #include <sys/errno.h>
     52   1.1       mrg #include <sys/device.h>
     53   1.1       mrg #include <sys/malloc.h>
     54   1.1       mrg 
     55   1.1       mrg #define _SPARC_BUS_DMA_PRIVATE
     56   1.1       mrg #include <machine/bus.h>
     57   1.1       mrg #include <machine/autoconf.h>
     58  1.22       eeh #include <machine/openfirm.h>
     59   1.1       mrg 
     60   1.1       mrg #include <dev/pci/pcivar.h>
     61   1.1       mrg #include <dev/pci/pcireg.h>
     62   1.1       mrg 
     63  1.19       mrg #include <dev/ofw/ofw_pci.h>
     64  1.19       mrg 
     65   1.1       mrg #include <sparc64/dev/iommureg.h>
     66   1.1       mrg #include <sparc64/dev/iommuvar.h>
     67   1.1       mrg #include <sparc64/dev/psychoreg.h>
     68   1.1       mrg #include <sparc64/dev/psychovar.h>
     69   1.1       mrg 
     70   1.1       mrg /* this is a base to be copied */
     71   1.1       mrg struct sparc_pci_chipset _sparc_pci_chipset = {
     72   1.1       mrg 	NULL,
     73   1.1       mrg };
     74   1.2       mrg 
     75  1.36    martin static int pci_bus_frequency(int node);
     76  1.36    martin 
     77  1.30   thorpej static pcitag_t
     78  1.30   thorpej ofpci_make_tag(pci_chipset_tag_t pc, int node, int b, int d, int f)
     79  1.30   thorpej {
     80  1.30   thorpej 	pcitag_t tag;
     81  1.30   thorpej 
     82  1.30   thorpej 	tag = PCITAG_CREATE(node, b, d, f);
     83  1.30   thorpej 
     84  1.30   thorpej 	/* Enable all the different spaces for this device */
     85  1.30   thorpej 	pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG,
     86  1.30   thorpej 		PCI_COMMAND_MEM_ENABLE|PCI_COMMAND_MASTER_ENABLE|
     87  1.30   thorpej 		PCI_COMMAND_IO_ENABLE);
     88  1.30   thorpej 	return (tag);
     89  1.30   thorpej }
     90  1.30   thorpej 
     91   1.1       mrg /*
     92   1.1       mrg  * functions provided to the MI code.
     93   1.1       mrg  */
     94   1.1       mrg 
     95   1.1       mrg void
     96   1.1       mrg pci_attach_hook(parent, self, pba)
     97   1.1       mrg 	struct device *parent;
     98   1.1       mrg 	struct device *self;
     99   1.1       mrg 	struct pcibus_attach_args *pba;
    100   1.1       mrg {
    101   1.1       mrg }
    102   1.1       mrg 
    103   1.1       mrg int
    104   1.1       mrg pci_bus_maxdevs(pc, busno)
    105   1.1       mrg 	pci_chipset_tag_t pc;
    106   1.1       mrg 	int busno;
    107   1.1       mrg {
    108   1.1       mrg 
    109   1.1       mrg 	return 32;
    110   1.1       mrg }
    111  1.19       mrg 
    112   1.1       mrg pcitag_t
    113   1.1       mrg pci_make_tag(pc, b, d, f)
    114   1.1       mrg 	pci_chipset_tag_t pc;
    115   1.1       mrg 	int b;
    116   1.1       mrg 	int d;
    117   1.1       mrg 	int f;
    118   1.1       mrg {
    119  1.35  nakayama 	struct psycho_pbm *pp = pc->cookie;
    120  1.22       eeh 	struct ofw_pci_register reg;
    121  1.22       eeh 	pcitag_t tag;
    122  1.35  nakayama 	int (*valid) __P((void *));
    123  1.22       eeh 	int busrange[2];
    124  1.22       eeh 	int node, len;
    125  1.22       eeh #ifdef DEBUG
    126  1.22       eeh 	char name[80];
    127  1.22       eeh 	bzero(name, sizeof(name));
    128  1.22       eeh #endif
    129   1.1       mrg 
    130  1.35  nakayama 	/*
    131  1.35  nakayama 	 * Refer to the PCI/CardBus bus node first.
    132  1.35  nakayama 	 * It returns a tag if node is present and bus is valid.
    133  1.35  nakayama 	 */
    134  1.35  nakayama 	if (0 <= b && b < 256) {
    135  1.35  nakayama 		node = (*pp->pp_busnode)[b].node;
    136  1.35  nakayama 		valid = (*pp->pp_busnode)[b].valid;
    137  1.35  nakayama 		if (node != 0 && d == 0 &&
    138  1.35  nakayama 		    (valid == NULL || (*valid)((*pp->pp_busnode)[b].arg)))
    139  1.35  nakayama 			return ofpci_make_tag(pc, node, b, d, f);
    140  1.35  nakayama 	}
    141  1.35  nakayama 
    142  1.22       eeh 	/*
    143  1.22       eeh 	 * Hunt for the node that corresponds to this device
    144  1.22       eeh 	 *
    145  1.22       eeh 	 * We could cache this info in an array in the parent
    146  1.22       eeh 	 * device... except then we have problems with devices
    147  1.22       eeh 	 * attached below pci-pci bridges, and we would need to
    148  1.22       eeh 	 * add special code to the pci-pci bridge to cache this
    149  1.22       eeh 	 * info.
    150  1.22       eeh 	 */
    151   1.1       mrg 
    152  1.22       eeh 	tag = PCITAG_CREATE(-1, b, d, f);
    153  1.22       eeh 	node = pc->rootnode;
    154  1.22       eeh 	/*
    155  1.22       eeh 	 * First make sure we're on the right bus.  If our parent
    156  1.22       eeh 	 * has a bus-range property and we're not in the range,
    157  1.22       eeh 	 * then we're obviously on the wrong bus.  So go up one
    158  1.22       eeh 	 * level.
    159  1.22       eeh 	 */
    160  1.22       eeh #ifdef DEBUG
    161  1.22       eeh 	if (sparc_pci_debug & SPDB_PROBE) {
    162  1.22       eeh 		OF_getprop(node, "name", &name, sizeof(name));
    163  1.22       eeh 		printf("curnode %x %s\n", node, name);
    164  1.22       eeh 	}
    165  1.22       eeh #endif
    166  1.22       eeh #if 0
    167  1.22       eeh 	while ((OF_getprop(OF_parent(node), "bus-range", (void *)&busrange,
    168  1.22       eeh 		sizeof(busrange)) == sizeof(busrange)) &&
    169  1.22       eeh 		(b < busrange[0] || b > busrange[1])) {
    170  1.22       eeh 		/* Out of range, go up one */
    171  1.22       eeh 		node = OF_parent(node);
    172  1.22       eeh #ifdef DEBUG
    173  1.22       eeh 		if (sparc_pci_debug & SPDB_PROBE) {
    174  1.22       eeh 			OF_getprop(node, "name", &name, sizeof(name));
    175  1.22       eeh 			printf("going up to node %x %s\n", node, name);
    176  1.22       eeh 		}
    177  1.22       eeh #endif
    178  1.22       eeh 	}
    179  1.22       eeh #endif
    180  1.22       eeh 	/*
    181  1.22       eeh 	 * Now traverse all peers until we find the node or we find
    182  1.22       eeh 	 * the right bridge.
    183  1.22       eeh 	 *
    184  1.22       eeh 	 * XXX We go up one and down one to make sure nobody's missed.
    185  1.22       eeh 	 * but this should not be necessary.
    186  1.22       eeh 	 */
    187  1.22       eeh 	for (node = ((node)); node; node = OF_peer(node)) {
    188   1.1       mrg 
    189  1.22       eeh #ifdef DEBUG
    190  1.22       eeh 		if (sparc_pci_debug & SPDB_PROBE) {
    191  1.22       eeh 			OF_getprop(node, "name", &name, sizeof(name));
    192  1.22       eeh 			printf("checking node %x %s\n", node, name);
    193  1.22       eeh 		}
    194  1.22       eeh #endif
    195   1.1       mrg 
    196  1.22       eeh #if 1
    197   1.1       mrg 		/*
    198  1.22       eeh 		 * Check for PCI-PCI bridges.  If the device we want is
    199  1.22       eeh 		 * in the bus-range for that bridge, work our way down.
    200   1.1       mrg 		 */
    201  1.22       eeh 		while ((OF_getprop(node, "bus-range", (void *)&busrange,
    202  1.22       eeh 			sizeof(busrange)) == sizeof(busrange)) &&
    203  1.22       eeh 			(b >= busrange[0] && b <= busrange[1])) {
    204  1.22       eeh 			/* Go down 1 level */
    205  1.22       eeh 			node = OF_child(node);
    206  1.22       eeh #ifdef DEBUG
    207  1.22       eeh 			if (sparc_pci_debug & SPDB_PROBE) {
    208  1.22       eeh 				OF_getprop(node, "name", &name, sizeof(name));
    209  1.22       eeh 				printf("going down to node %x %s\n",
    210  1.22       eeh 					node, name);
    211  1.22       eeh 			}
    212  1.22       eeh #endif
    213   1.1       mrg 		}
    214  1.22       eeh #endif
    215  1.22       eeh 		/*
    216  1.22       eeh 		 * We only really need the first `reg' property.
    217  1.22       eeh 		 *
    218  1.22       eeh 		 * For simplicity, we'll query the `reg' when we
    219  1.22       eeh 		 * need it.  Otherwise we could malloc() it, but
    220  1.22       eeh 		 * that gets more complicated.
    221  1.22       eeh 		 */
    222  1.22       eeh 		len = OF_getproplen(node, "reg");
    223  1.22       eeh 		if (len < sizeof(reg))
    224  1.22       eeh 			continue;
    225  1.22       eeh 		if (OF_getprop(node, "reg", (void *)&reg, sizeof(reg)) != len)
    226  1.22       eeh 			panic("pci_probe_bus: OF_getprop len botch");
    227  1.22       eeh 
    228  1.22       eeh 		if (b != OFW_PCI_PHYS_HI_BUS(reg.phys_hi))
    229  1.22       eeh 			continue;
    230  1.22       eeh 		if (d != OFW_PCI_PHYS_HI_DEVICE(reg.phys_hi))
    231  1.22       eeh 			continue;
    232  1.22       eeh 		if (f != OFW_PCI_PHYS_HI_FUNCTION(reg.phys_hi))
    233  1.22       eeh 			continue;
    234  1.22       eeh 
    235  1.22       eeh 		/* Got a match */
    236  1.27       eeh 		tag = ofpci_make_tag(pc, node, b, d, f);
    237  1.22       eeh 
    238  1.22       eeh 		return (tag);
    239   1.1       mrg 	}
    240  1.22       eeh 	/* No device found -- return a dead tag */
    241  1.27       eeh 	return (tag);
    242  1.28   thorpej }
    243  1.28   thorpej 
    244  1.28   thorpej void
    245  1.28   thorpej pci_decompose_tag(pc, tag, bp, dp, fp)
    246  1.28   thorpej 	pci_chipset_tag_t pc;
    247  1.28   thorpej 	pcitag_t tag;
    248  1.28   thorpej 	int *bp, *dp, *fp;
    249  1.28   thorpej {
    250  1.28   thorpej 
    251  1.28   thorpej 	if (bp != NULL)
    252  1.28   thorpej 		*bp = PCITAG_BUS(tag);
    253  1.28   thorpej 	if (dp != NULL)
    254  1.28   thorpej 		*dp = PCITAG_DEV(tag);
    255  1.28   thorpej 	if (fp != NULL)
    256  1.28   thorpej 		*fp = PCITAG_FUN(tag);
    257  1.27       eeh }
    258  1.27       eeh 
    259  1.36    martin static int
    260  1.36    martin pci_bus_frequency(int node)
    261  1.36    martin {
    262  1.36    martin 	int len, bus_frequency;
    263  1.36    martin 
    264  1.36    martin 	len = OF_getproplen(node, "clock-frequency");
    265  1.36    martin 	if (len < sizeof(bus_frequency)) {
    266  1.36    martin 		DPRINTF(SPDB_PROBE,
    267  1.36    martin 		    ("pci_bus_frequency: clock-frequency len %d too small\n",
    268  1.36    martin 		     len));
    269  1.36    martin 		return 33;
    270  1.36    martin 	}
    271  1.36    martin 	if (OF_getprop(node, "clock-frequency", &bus_frequency,
    272  1.36    martin 		       sizeof(bus_frequency)) != len) {
    273  1.36    martin 		DPRINTF(SPDB_PROBE,
    274  1.36    martin 		    ("pci_bus_frequency: could not read clock-frequency\n"));
    275  1.36    martin 		return 33;
    276  1.36    martin 	}
    277  1.36    martin 	return bus_frequency / 1000000;
    278  1.36    martin }
    279  1.36    martin 
    280  1.30   thorpej int
    281  1.30   thorpej pci_enumerate_bus(struct pci_softc *sc,
    282  1.30   thorpej     int (*match)(struct pci_attach_args *), struct pci_attach_args *pap)
    283  1.27       eeh {
    284  1.30   thorpej 	struct ofw_pci_register reg;
    285  1.30   thorpej 	pci_chipset_tag_t pc = sc->sc_pc;
    286  1.27       eeh 	pcitag_t tag;
    287  1.35  nakayama 	pcireg_t class, csr, bhlc, ic;
    288  1.30   thorpej 	int node, b, d, f, ret;
    289  1.36    martin 	int bus_frequency, lt, cl;
    290  1.30   thorpej 	char name[30];
    291  1.32       eeh 	extern int pci_config_dump;
    292  1.30   thorpej 
    293  1.31       eeh 	if (sc->sc_bridgetag)
    294  1.31       eeh 		node = PCITAG_NODE(*sc->sc_bridgetag);
    295  1.31       eeh 	else
    296  1.31       eeh 		node = pc->rootnode;
    297  1.31       eeh 
    298  1.36    martin 	bus_frequency = pci_bus_frequency(node);
    299  1.35  nakayama 
    300  1.32       eeh 	/* Turn on parity for the bus. */
    301  1.32       eeh 	tag = ofpci_make_tag(pc, node, sc->sc_bus, 0, 0);
    302  1.32       eeh 	csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
    303  1.32       eeh 	csr |= PCI_COMMAND_PARITY_ENABLE;
    304  1.32       eeh 	pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr);
    305  1.32       eeh 
    306  1.35  nakayama 	/*
    307  1.35  nakayama 	 * Initialize the latency timer register.
    308  1.35  nakayama 	 * The value 0x40 is from Solaris.
    309  1.35  nakayama 	 */
    310  1.35  nakayama 	bhlc = pci_conf_read(pc, tag, PCI_BHLC_REG);
    311  1.35  nakayama 	bhlc &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT);
    312  1.35  nakayama 	bhlc |= 0x40 << PCI_LATTIMER_SHIFT;
    313  1.35  nakayama 	pci_conf_write(pc, tag, PCI_BHLC_REG, bhlc);
    314  1.35  nakayama 
    315  1.32       eeh 	if (pci_config_dump) pci_conf_print(pc, tag, NULL);
    316  1.32       eeh 
    317  1.31       eeh 	for (node = OF_child(node); node != 0 && node != -1;
    318  1.30   thorpej 	     node = OF_peer(node)) {
    319  1.30   thorpej 		name[0] = name[29] = 0;
    320  1.30   thorpej 		OF_getprop(node, "name", name, sizeof(name));
    321  1.27       eeh 
    322  1.30   thorpej 		if (OF_getprop(node, "class-code", &class, sizeof(class)) !=
    323  1.30   thorpej 		    sizeof(class))
    324  1.30   thorpej 			continue;
    325  1.30   thorpej 		if (OF_getprop(node, "reg", &reg, sizeof(reg)) < sizeof(reg))
    326  1.30   thorpej 			panic("pci_enumerate_bus: \"%s\" regs too small", name);
    327  1.27       eeh 
    328  1.30   thorpej 		b = OFW_PCI_PHYS_HI_BUS(reg.phys_hi);
    329  1.30   thorpej 		d = OFW_PCI_PHYS_HI_DEVICE(reg.phys_hi);
    330  1.30   thorpej 		f = OFW_PCI_PHYS_HI_FUNCTION(reg.phys_hi);
    331  1.30   thorpej 
    332  1.30   thorpej 		if (sc->sc_bus != b) {
    333  1.30   thorpej 			printf("%s: WARNING: incorrect bus # for \"%s\" "
    334  1.30   thorpej 			"(%d/%d/%d)\n", sc->sc_dev.dv_xname, name, b, d, f);
    335  1.30   thorpej 			continue;
    336  1.30   thorpej 		}
    337  1.27       eeh 
    338  1.30   thorpej 		tag = ofpci_make_tag(pc, node, b, d, f);
    339  1.32       eeh 
    340  1.32       eeh 		/*
    341  1.32       eeh 		 * Turn on parity and fast-back-to-back for the device.
    342  1.32       eeh 		 */
    343  1.32       eeh 		csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
    344  1.32       eeh 		if (csr & PCI_STATUS_BACKTOBACK_SUPPORT)
    345  1.32       eeh 			csr |= PCI_COMMAND_BACKTOBACK_ENABLE;
    346  1.32       eeh 		csr |= PCI_COMMAND_PARITY_ENABLE;
    347  1.32       eeh 		pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr);
    348  1.32       eeh 
    349  1.35  nakayama 		/*
    350  1.35  nakayama 		 * Initialize the latency timer register for busmaster
    351  1.35  nakayama 		 * devices to work properly.
    352  1.35  nakayama 		 *   latency-timer = min-grant * bus-freq / 4  (from FreeBSD)
    353  1.35  nakayama 		 * Also initialize the cache line size register.
    354  1.35  nakayama 		 * Solaris anytime sets this register to the value 0x10.
    355  1.35  nakayama 		 */
    356  1.35  nakayama 		bhlc = pci_conf_read(pc, tag, PCI_BHLC_REG);
    357  1.35  nakayama 		ic = pci_conf_read(pc, tag, PCI_INTERRUPT_REG);
    358  1.35  nakayama 
    359  1.35  nakayama 		lt = min(PCI_MIN_GNT(ic) * bus_frequency / 4, 255);
    360  1.35  nakayama 		if (lt == 0 || lt < PCI_LATTIMER(bhlc))
    361  1.35  nakayama 			lt = PCI_LATTIMER(bhlc);
    362  1.35  nakayama 
    363  1.35  nakayama 		cl = PCI_CACHELINE(bhlc);
    364  1.35  nakayama 		if (cl == 0)
    365  1.35  nakayama 			cl = 0x10;
    366  1.35  nakayama 
    367  1.35  nakayama 		bhlc &= ~((PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT) |
    368  1.35  nakayama 			  (PCI_CACHELINE_MASK << PCI_CACHELINE_SHIFT));
    369  1.35  nakayama 		bhlc |= (lt << PCI_LATTIMER_SHIFT) |
    370  1.35  nakayama 			(cl << PCI_CACHELINE_SHIFT);
    371  1.35  nakayama 		pci_conf_write(pc, tag, PCI_BHLC_REG, bhlc);
    372  1.35  nakayama 
    373  1.30   thorpej 		ret = pci_probe_device(sc, tag, match, pap);
    374  1.30   thorpej 		if (match != NULL && ret != 0)
    375  1.30   thorpej 			return (ret);
    376  1.30   thorpej 	}
    377  1.30   thorpej 	return (0);
    378   1.1       mrg }
    379   1.1       mrg 
    380   1.1       mrg /* assume we are mapped little-endian/side-effect */
    381   1.1       mrg pcireg_t
    382   1.1       mrg pci_conf_read(pc, tag, reg)
    383   1.1       mrg 	pci_chipset_tag_t pc;
    384   1.1       mrg 	pcitag_t tag;
    385   1.1       mrg 	int reg;
    386   1.1       mrg {
    387   1.1       mrg 	struct psycho_pbm *pp = pc->cookie;
    388   1.1       mrg 	struct psycho_softc *sc = pp->pp_sc;
    389  1.22       eeh 	pcireg_t val = (pcireg_t)~0;
    390  1.22       eeh 
    391  1.22       eeh 	DPRINTF(SPDB_CONF, ("pci_conf_read: tag %lx reg %x ",
    392  1.22       eeh 		(long)tag, reg));
    393  1.22       eeh 	if (PCITAG_NODE(tag) != -1) {
    394  1.22       eeh 		DPRINTF(SPDB_CONF, ("asi=%x addr=%qx (offset=%x) ...",
    395  1.26       eeh 			sc->sc_configaddr._asi,
    396  1.26       eeh 			(long long)(sc->sc_configaddr._ptr +
    397  1.22       eeh 				PCITAG_OFFSET(tag) + reg),
    398  1.22       eeh 			(int)PCITAG_OFFSET(tag) + reg));
    399   1.1       mrg 
    400   1.1       mrg 		val = bus_space_read_4(sc->sc_configtag, sc->sc_configaddr,
    401  1.22       eeh 			PCITAG_OFFSET(tag) + reg);
    402   1.1       mrg 	}
    403  1.22       eeh #ifdef DEBUG
    404  1.24       mrg 	else DPRINTF(SPDB_CONF, ("pci_conf_read: bogus pcitag %x\n",
    405  1.24       mrg 		(int)PCITAG_OFFSET(tag)));
    406  1.22       eeh #endif
    407   1.1       mrg 	DPRINTF(SPDB_CONF, (" returning %08x\n", (u_int)val));
    408   1.1       mrg 
    409   1.1       mrg 	return (val);
    410   1.1       mrg }
    411   1.1       mrg 
    412   1.1       mrg void
    413   1.1       mrg pci_conf_write(pc, tag, reg, data)
    414   1.1       mrg 	pci_chipset_tag_t pc;
    415   1.1       mrg 	pcitag_t tag;
    416   1.1       mrg 	int reg;
    417   1.1       mrg 	pcireg_t data;
    418   1.1       mrg {
    419   1.1       mrg 	struct psycho_pbm *pp = pc->cookie;
    420   1.1       mrg 	struct psycho_softc *sc = pp->pp_sc;
    421   1.1       mrg 
    422  1.22       eeh 	DPRINTF(SPDB_CONF, ("pci_conf_write: tag %lx; reg %x; data %x; ",
    423  1.22       eeh 		(long)PCITAG_OFFSET(tag), reg, (int)data));
    424   1.1       mrg 	DPRINTF(SPDB_CONF, ("asi = %x; readaddr = %qx (offset = %x)\n",
    425  1.26       eeh 		sc->sc_configaddr._asi,
    426  1.26       eeh 		(long long)(sc->sc_configaddr._ptr + PCITAG_OFFSET(tag) + reg),
    427  1.22       eeh 		(int)PCITAG_OFFSET(tag) + reg));
    428   1.1       mrg 
    429  1.24       mrg 	/* If we don't know it, just punt it.  */
    430  1.24       mrg 	if (PCITAG_NODE(tag) == -1) {
    431  1.24       mrg 		DPRINTF(SPDB_CONF, ("pci_conf_write: bad addr"));
    432  1.24       mrg 		return;
    433  1.24       mrg 	}
    434   1.1       mrg 
    435  1.22       eeh 	bus_space_write_4(sc->sc_configtag, sc->sc_configaddr,
    436  1.22       eeh 		PCITAG_OFFSET(tag) + reg, data);
    437   1.1       mrg }
    438   1.1       mrg 
    439   1.1       mrg /*
    440   1.1       mrg  * interrupt mapping foo.
    441  1.20       mrg  * XXX: how does this deal with multiple interrupts for a device?
    442   1.1       mrg  */
    443   1.1       mrg int
    444  1.16  sommerfe pci_intr_map(pa, ihp)
    445  1.16  sommerfe 	struct pci_attach_args *pa;
    446   1.1       mrg 	pci_intr_handle_t *ihp;
    447   1.1       mrg {
    448  1.22       eeh 	pcitag_t tag = pa->pa_tag;
    449  1.22       eeh 	int interrupts;
    450  1.22       eeh 	int len, node = PCITAG_NODE(tag);
    451  1.22       eeh 	char devtype[30];
    452  1.22       eeh 
    453  1.22       eeh 	len = OF_getproplen(node, "interrupts");
    454  1.22       eeh 	if (len < sizeof(interrupts)) {
    455  1.22       eeh 		DPRINTF(SPDB_INTMAP,
    456  1.22       eeh 			("pci_intr_map: interrupts len %d too small\n", len));
    457  1.22       eeh 		return (ENODEV);
    458  1.22       eeh 	}
    459  1.22       eeh 	if (OF_getprop(node, "interrupts", (void *)&interrupts,
    460  1.22       eeh 		sizeof(interrupts)) != len) {
    461  1.22       eeh 		DPRINTF(SPDB_INTMAP,
    462  1.22       eeh 			("pci_intr_map: could not read interrupts\n"));
    463  1.22       eeh 		return (ENODEV);
    464  1.22       eeh 	}
    465  1.20       mrg 
    466  1.22       eeh 	if (OF_mapintr(node, &interrupts, sizeof(interrupts),
    467  1.23       eeh 		sizeof(interrupts)) < 0) {
    468  1.22       eeh 		printf("OF_mapintr failed\n");
    469  1.22       eeh 	}
    470  1.22       eeh 	/* Try to find an IPL for this type of device. */
    471  1.22       eeh 	if (OF_getprop(node, "device_type", &devtype, sizeof(devtype)) > 0) {
    472  1.22       eeh 		for (len = 0;  intrmap[len].in_class; len++)
    473  1.22       eeh 			if (strcmp(intrmap[len].in_class, devtype) == 0) {
    474  1.22       eeh 				interrupts |= INTLEVENCODE(intrmap[len].in_lev);
    475  1.22       eeh 				break;
    476  1.22       eeh 			}
    477  1.22       eeh 	}
    478  1.20       mrg 
    479  1.22       eeh 	/* XXXX -- we use the ino.  What if there is a valid IGN? */
    480  1.22       eeh 	*ihp = interrupts;
    481  1.22       eeh 	return (0);
    482   1.1       mrg }
    483   1.1       mrg 
    484   1.1       mrg const char *
    485   1.1       mrg pci_intr_string(pc, ih)
    486   1.1       mrg 	pci_chipset_tag_t pc;
    487   1.1       mrg 	pci_intr_handle_t ih;
    488   1.1       mrg {
    489   1.1       mrg 	static char str[16];
    490   1.1       mrg 
    491   1.1       mrg 	DPRINTF(SPDB_INTR, ("pci_intr_string: ih %u", ih));
    492  1.22       eeh 	sprintf(str, "ivec %x", ih);
    493   1.1       mrg 	DPRINTF(SPDB_INTR, ("; returning %s\n", str));
    494   1.1       mrg 
    495   1.1       mrg 	return (str);
    496   1.8       cgd }
    497   1.8       cgd 
    498   1.8       cgd const struct evcnt *
    499   1.8       cgd pci_intr_evcnt(pc, ih)
    500   1.8       cgd 	pci_chipset_tag_t pc;
    501   1.8       cgd 	pci_intr_handle_t ih;
    502   1.8       cgd {
    503   1.8       cgd 
    504   1.8       cgd 	/* XXX for now, no evcnt parent reported */
    505   1.8       cgd 	return NULL;
    506   1.1       mrg }
    507   1.1       mrg 
    508   1.1       mrg void *
    509   1.1       mrg pci_intr_establish(pc, ih, level, func, arg)
    510   1.1       mrg 	pci_chipset_tag_t pc;
    511   1.1       mrg 	pci_intr_handle_t ih;
    512   1.1       mrg 	int level;
    513   1.1       mrg 	int (*func) __P((void *));
    514   1.1       mrg 	void *arg;
    515   1.1       mrg {
    516   1.1       mrg 	void *cookie;
    517   1.1       mrg 	struct psycho_pbm *pp = (struct psycho_pbm *)pc->cookie;
    518   1.1       mrg 
    519   1.1       mrg 	DPRINTF(SPDB_INTR, ("pci_intr_establish: ih %lu; level %d", (u_long)ih, level));
    520  1.34        pk 	cookie = bus_intr_establish(pp->pp_memt, ih, level, func, arg);
    521   1.1       mrg 
    522   1.1       mrg 	DPRINTF(SPDB_INTR, ("; returning handle %p\n", cookie));
    523   1.1       mrg 	return (cookie);
    524   1.1       mrg }
    525   1.1       mrg 
    526   1.1       mrg void
    527   1.1       mrg pci_intr_disestablish(pc, cookie)
    528   1.1       mrg 	pci_chipset_tag_t pc;
    529   1.1       mrg 	void *cookie;
    530   1.1       mrg {
    531   1.1       mrg 
    532   1.1       mrg 	DPRINTF(SPDB_INTR, ("pci_intr_disestablish: cookie %p\n", cookie));
    533   1.1       mrg 
    534   1.1       mrg 	/* XXX */
    535   1.1       mrg 	panic("can't disestablish PCI interrupts yet");
    536   1.1       mrg }
    537