pci_machdep.c revision 1.38 1 1.38 lukem /* $NetBSD: pci_machdep.c,v 1.38 2003/07/15 03:36:05 lukem Exp $ */
2 1.1 mrg
3 1.1 mrg /*
4 1.5 mrg * Copyright (c) 1999, 2000 Matthew R. Green
5 1.1 mrg * All rights reserved.
6 1.1 mrg *
7 1.1 mrg * Redistribution and use in source and binary forms, with or without
8 1.1 mrg * modification, are permitted provided that the following conditions
9 1.1 mrg * are met:
10 1.1 mrg * 1. Redistributions of source code must retain the above copyright
11 1.1 mrg * notice, this list of conditions and the following disclaimer.
12 1.1 mrg * 2. Redistributions in binary form must reproduce the above copyright
13 1.1 mrg * notice, this list of conditions and the following disclaimer in the
14 1.1 mrg * documentation and/or other materials provided with the distribution.
15 1.1 mrg * 3. The name of the author may not be used to endorse or promote products
16 1.1 mrg * derived from this software without specific prior written permission.
17 1.1 mrg *
18 1.1 mrg * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 1.1 mrg * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 1.1 mrg * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 1.1 mrg * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 1.1 mrg * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
23 1.1 mrg * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
24 1.1 mrg * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
25 1.1 mrg * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
26 1.1 mrg * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 1.1 mrg * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 1.1 mrg * SUCH DAMAGE.
29 1.1 mrg */
30 1.1 mrg
31 1.1 mrg /*
32 1.1 mrg * functions expected by the MI PCI code.
33 1.1 mrg */
34 1.38 lukem
35 1.38 lukem #include <sys/cdefs.h>
36 1.38 lukem __KERNEL_RCSID(0, "$NetBSD: pci_machdep.c,v 1.38 2003/07/15 03:36:05 lukem Exp $");
37 1.1 mrg
38 1.1 mrg #ifdef DEBUG
39 1.1 mrg #define SPDB_CONF 0x01
40 1.1 mrg #define SPDB_INTR 0x04
41 1.1 mrg #define SPDB_INTMAP 0x08
42 1.1 mrg #define SPDB_INTFIX 0x10
43 1.22 eeh #define SPDB_PROBE 0x20
44 1.4 mrg int sparc_pci_debug = 0x0;
45 1.1 mrg #define DPRINTF(l, s) do { if (sparc_pci_debug & l) printf s; } while (0)
46 1.1 mrg #else
47 1.1 mrg #define DPRINTF(l, s)
48 1.1 mrg #endif
49 1.1 mrg
50 1.1 mrg #include <sys/types.h>
51 1.1 mrg #include <sys/param.h>
52 1.1 mrg #include <sys/time.h>
53 1.1 mrg #include <sys/systm.h>
54 1.1 mrg #include <sys/errno.h>
55 1.1 mrg #include <sys/device.h>
56 1.1 mrg #include <sys/malloc.h>
57 1.1 mrg
58 1.1 mrg #define _SPARC_BUS_DMA_PRIVATE
59 1.1 mrg #include <machine/bus.h>
60 1.1 mrg #include <machine/autoconf.h>
61 1.22 eeh #include <machine/openfirm.h>
62 1.1 mrg #include <dev/pci/pcivar.h>
63 1.1 mrg #include <dev/pci/pcireg.h>
64 1.1 mrg
65 1.19 mrg #include <dev/ofw/ofw_pci.h>
66 1.19 mrg
67 1.1 mrg #include <sparc64/dev/iommureg.h>
68 1.1 mrg #include <sparc64/dev/iommuvar.h>
69 1.1 mrg #include <sparc64/dev/psychoreg.h>
70 1.1 mrg #include <sparc64/dev/psychovar.h>
71 1.37 martin #include <sparc64/sparc64/cache.h>
72 1.1 mrg
73 1.1 mrg /* this is a base to be copied */
74 1.1 mrg struct sparc_pci_chipset _sparc_pci_chipset = {
75 1.1 mrg NULL,
76 1.1 mrg };
77 1.2 mrg
78 1.36 martin static int pci_bus_frequency(int node);
79 1.36 martin
80 1.30 thorpej static pcitag_t
81 1.30 thorpej ofpci_make_tag(pci_chipset_tag_t pc, int node, int b, int d, int f)
82 1.30 thorpej {
83 1.30 thorpej pcitag_t tag;
84 1.30 thorpej
85 1.30 thorpej tag = PCITAG_CREATE(node, b, d, f);
86 1.30 thorpej
87 1.30 thorpej /* Enable all the different spaces for this device */
88 1.30 thorpej pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG,
89 1.30 thorpej PCI_COMMAND_MEM_ENABLE|PCI_COMMAND_MASTER_ENABLE|
90 1.30 thorpej PCI_COMMAND_IO_ENABLE);
91 1.30 thorpej return (tag);
92 1.30 thorpej }
93 1.30 thorpej
94 1.1 mrg /*
95 1.1 mrg * functions provided to the MI code.
96 1.1 mrg */
97 1.1 mrg
98 1.1 mrg void
99 1.1 mrg pci_attach_hook(parent, self, pba)
100 1.1 mrg struct device *parent;
101 1.1 mrg struct device *self;
102 1.1 mrg struct pcibus_attach_args *pba;
103 1.1 mrg {
104 1.1 mrg }
105 1.1 mrg
106 1.1 mrg int
107 1.1 mrg pci_bus_maxdevs(pc, busno)
108 1.1 mrg pci_chipset_tag_t pc;
109 1.1 mrg int busno;
110 1.1 mrg {
111 1.1 mrg
112 1.1 mrg return 32;
113 1.1 mrg }
114 1.19 mrg
115 1.1 mrg pcitag_t
116 1.1 mrg pci_make_tag(pc, b, d, f)
117 1.1 mrg pci_chipset_tag_t pc;
118 1.1 mrg int b;
119 1.1 mrg int d;
120 1.1 mrg int f;
121 1.1 mrg {
122 1.35 nakayama struct psycho_pbm *pp = pc->cookie;
123 1.22 eeh struct ofw_pci_register reg;
124 1.22 eeh pcitag_t tag;
125 1.35 nakayama int (*valid) __P((void *));
126 1.22 eeh int busrange[2];
127 1.22 eeh int node, len;
128 1.22 eeh #ifdef DEBUG
129 1.22 eeh char name[80];
130 1.22 eeh bzero(name, sizeof(name));
131 1.22 eeh #endif
132 1.1 mrg
133 1.35 nakayama /*
134 1.35 nakayama * Refer to the PCI/CardBus bus node first.
135 1.35 nakayama * It returns a tag if node is present and bus is valid.
136 1.35 nakayama */
137 1.35 nakayama if (0 <= b && b < 256) {
138 1.35 nakayama node = (*pp->pp_busnode)[b].node;
139 1.35 nakayama valid = (*pp->pp_busnode)[b].valid;
140 1.35 nakayama if (node != 0 && d == 0 &&
141 1.35 nakayama (valid == NULL || (*valid)((*pp->pp_busnode)[b].arg)))
142 1.35 nakayama return ofpci_make_tag(pc, node, b, d, f);
143 1.35 nakayama }
144 1.35 nakayama
145 1.22 eeh /*
146 1.22 eeh * Hunt for the node that corresponds to this device
147 1.22 eeh *
148 1.22 eeh * We could cache this info in an array in the parent
149 1.22 eeh * device... except then we have problems with devices
150 1.22 eeh * attached below pci-pci bridges, and we would need to
151 1.22 eeh * add special code to the pci-pci bridge to cache this
152 1.22 eeh * info.
153 1.22 eeh */
154 1.1 mrg
155 1.22 eeh tag = PCITAG_CREATE(-1, b, d, f);
156 1.22 eeh node = pc->rootnode;
157 1.22 eeh /*
158 1.22 eeh * First make sure we're on the right bus. If our parent
159 1.22 eeh * has a bus-range property and we're not in the range,
160 1.22 eeh * then we're obviously on the wrong bus. So go up one
161 1.22 eeh * level.
162 1.22 eeh */
163 1.22 eeh #ifdef DEBUG
164 1.22 eeh if (sparc_pci_debug & SPDB_PROBE) {
165 1.22 eeh OF_getprop(node, "name", &name, sizeof(name));
166 1.22 eeh printf("curnode %x %s\n", node, name);
167 1.22 eeh }
168 1.22 eeh #endif
169 1.22 eeh #if 0
170 1.22 eeh while ((OF_getprop(OF_parent(node), "bus-range", (void *)&busrange,
171 1.22 eeh sizeof(busrange)) == sizeof(busrange)) &&
172 1.22 eeh (b < busrange[0] || b > busrange[1])) {
173 1.22 eeh /* Out of range, go up one */
174 1.22 eeh node = OF_parent(node);
175 1.22 eeh #ifdef DEBUG
176 1.22 eeh if (sparc_pci_debug & SPDB_PROBE) {
177 1.22 eeh OF_getprop(node, "name", &name, sizeof(name));
178 1.22 eeh printf("going up to node %x %s\n", node, name);
179 1.22 eeh }
180 1.22 eeh #endif
181 1.22 eeh }
182 1.22 eeh #endif
183 1.22 eeh /*
184 1.22 eeh * Now traverse all peers until we find the node or we find
185 1.22 eeh * the right bridge.
186 1.22 eeh *
187 1.22 eeh * XXX We go up one and down one to make sure nobody's missed.
188 1.22 eeh * but this should not be necessary.
189 1.22 eeh */
190 1.22 eeh for (node = ((node)); node; node = OF_peer(node)) {
191 1.1 mrg
192 1.22 eeh #ifdef DEBUG
193 1.22 eeh if (sparc_pci_debug & SPDB_PROBE) {
194 1.22 eeh OF_getprop(node, "name", &name, sizeof(name));
195 1.22 eeh printf("checking node %x %s\n", node, name);
196 1.22 eeh }
197 1.22 eeh #endif
198 1.1 mrg
199 1.22 eeh #if 1
200 1.1 mrg /*
201 1.22 eeh * Check for PCI-PCI bridges. If the device we want is
202 1.22 eeh * in the bus-range for that bridge, work our way down.
203 1.1 mrg */
204 1.22 eeh while ((OF_getprop(node, "bus-range", (void *)&busrange,
205 1.22 eeh sizeof(busrange)) == sizeof(busrange)) &&
206 1.22 eeh (b >= busrange[0] && b <= busrange[1])) {
207 1.22 eeh /* Go down 1 level */
208 1.22 eeh node = OF_child(node);
209 1.22 eeh #ifdef DEBUG
210 1.22 eeh if (sparc_pci_debug & SPDB_PROBE) {
211 1.22 eeh OF_getprop(node, "name", &name, sizeof(name));
212 1.22 eeh printf("going down to node %x %s\n",
213 1.22 eeh node, name);
214 1.22 eeh }
215 1.22 eeh #endif
216 1.1 mrg }
217 1.22 eeh #endif
218 1.22 eeh /*
219 1.22 eeh * We only really need the first `reg' property.
220 1.22 eeh *
221 1.22 eeh * For simplicity, we'll query the `reg' when we
222 1.22 eeh * need it. Otherwise we could malloc() it, but
223 1.22 eeh * that gets more complicated.
224 1.22 eeh */
225 1.22 eeh len = OF_getproplen(node, "reg");
226 1.22 eeh if (len < sizeof(reg))
227 1.22 eeh continue;
228 1.22 eeh if (OF_getprop(node, "reg", (void *)®, sizeof(reg)) != len)
229 1.22 eeh panic("pci_probe_bus: OF_getprop len botch");
230 1.22 eeh
231 1.22 eeh if (b != OFW_PCI_PHYS_HI_BUS(reg.phys_hi))
232 1.22 eeh continue;
233 1.22 eeh if (d != OFW_PCI_PHYS_HI_DEVICE(reg.phys_hi))
234 1.22 eeh continue;
235 1.22 eeh if (f != OFW_PCI_PHYS_HI_FUNCTION(reg.phys_hi))
236 1.22 eeh continue;
237 1.22 eeh
238 1.22 eeh /* Got a match */
239 1.27 eeh tag = ofpci_make_tag(pc, node, b, d, f);
240 1.22 eeh
241 1.22 eeh return (tag);
242 1.1 mrg }
243 1.22 eeh /* No device found -- return a dead tag */
244 1.27 eeh return (tag);
245 1.28 thorpej }
246 1.28 thorpej
247 1.28 thorpej void
248 1.28 thorpej pci_decompose_tag(pc, tag, bp, dp, fp)
249 1.28 thorpej pci_chipset_tag_t pc;
250 1.28 thorpej pcitag_t tag;
251 1.28 thorpej int *bp, *dp, *fp;
252 1.28 thorpej {
253 1.28 thorpej
254 1.28 thorpej if (bp != NULL)
255 1.28 thorpej *bp = PCITAG_BUS(tag);
256 1.28 thorpej if (dp != NULL)
257 1.28 thorpej *dp = PCITAG_DEV(tag);
258 1.28 thorpej if (fp != NULL)
259 1.28 thorpej *fp = PCITAG_FUN(tag);
260 1.27 eeh }
261 1.27 eeh
262 1.36 martin static int
263 1.36 martin pci_bus_frequency(int node)
264 1.36 martin {
265 1.36 martin int len, bus_frequency;
266 1.36 martin
267 1.36 martin len = OF_getproplen(node, "clock-frequency");
268 1.36 martin if (len < sizeof(bus_frequency)) {
269 1.36 martin DPRINTF(SPDB_PROBE,
270 1.36 martin ("pci_bus_frequency: clock-frequency len %d too small\n",
271 1.36 martin len));
272 1.36 martin return 33;
273 1.36 martin }
274 1.36 martin if (OF_getprop(node, "clock-frequency", &bus_frequency,
275 1.36 martin sizeof(bus_frequency)) != len) {
276 1.36 martin DPRINTF(SPDB_PROBE,
277 1.36 martin ("pci_bus_frequency: could not read clock-frequency\n"));
278 1.36 martin return 33;
279 1.36 martin }
280 1.36 martin return bus_frequency / 1000000;
281 1.36 martin }
282 1.36 martin
283 1.30 thorpej int
284 1.30 thorpej pci_enumerate_bus(struct pci_softc *sc,
285 1.30 thorpej int (*match)(struct pci_attach_args *), struct pci_attach_args *pap)
286 1.27 eeh {
287 1.30 thorpej struct ofw_pci_register reg;
288 1.30 thorpej pci_chipset_tag_t pc = sc->sc_pc;
289 1.27 eeh pcitag_t tag;
290 1.35 nakayama pcireg_t class, csr, bhlc, ic;
291 1.30 thorpej int node, b, d, f, ret;
292 1.37 martin int bus_frequency, lt, cl, cacheline;
293 1.30 thorpej char name[30];
294 1.32 eeh extern int pci_config_dump;
295 1.30 thorpej
296 1.31 eeh if (sc->sc_bridgetag)
297 1.31 eeh node = PCITAG_NODE(*sc->sc_bridgetag);
298 1.31 eeh else
299 1.31 eeh node = pc->rootnode;
300 1.31 eeh
301 1.36 martin bus_frequency = pci_bus_frequency(node);
302 1.35 nakayama
303 1.37 martin /*
304 1.37 martin * Make sure the cache line size is at least as big as the
305 1.37 martin * ecache line and the streaming cache (64 byte).
306 1.37 martin */
307 1.37 martin cacheline = max(cacheinfo.ec_linesize, 64);
308 1.37 martin KASSERT((cacheline/64)*64 == cacheline &&
309 1.37 martin (cacheline/cacheinfo.ec_linesize)*cacheinfo.ec_linesize == cacheline &&
310 1.37 martin (cacheline/4)*4 == cacheline);
311 1.37 martin
312 1.32 eeh /* Turn on parity for the bus. */
313 1.32 eeh tag = ofpci_make_tag(pc, node, sc->sc_bus, 0, 0);
314 1.32 eeh csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
315 1.32 eeh csr |= PCI_COMMAND_PARITY_ENABLE;
316 1.32 eeh pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr);
317 1.32 eeh
318 1.35 nakayama /*
319 1.35 nakayama * Initialize the latency timer register.
320 1.35 nakayama * The value 0x40 is from Solaris.
321 1.35 nakayama */
322 1.35 nakayama bhlc = pci_conf_read(pc, tag, PCI_BHLC_REG);
323 1.35 nakayama bhlc &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT);
324 1.35 nakayama bhlc |= 0x40 << PCI_LATTIMER_SHIFT;
325 1.35 nakayama pci_conf_write(pc, tag, PCI_BHLC_REG, bhlc);
326 1.35 nakayama
327 1.32 eeh if (pci_config_dump) pci_conf_print(pc, tag, NULL);
328 1.32 eeh
329 1.31 eeh for (node = OF_child(node); node != 0 && node != -1;
330 1.30 thorpej node = OF_peer(node)) {
331 1.30 thorpej name[0] = name[29] = 0;
332 1.30 thorpej OF_getprop(node, "name", name, sizeof(name));
333 1.27 eeh
334 1.30 thorpej if (OF_getprop(node, "class-code", &class, sizeof(class)) !=
335 1.30 thorpej sizeof(class))
336 1.30 thorpej continue;
337 1.30 thorpej if (OF_getprop(node, "reg", ®, sizeof(reg)) < sizeof(reg))
338 1.30 thorpej panic("pci_enumerate_bus: \"%s\" regs too small", name);
339 1.27 eeh
340 1.30 thorpej b = OFW_PCI_PHYS_HI_BUS(reg.phys_hi);
341 1.30 thorpej d = OFW_PCI_PHYS_HI_DEVICE(reg.phys_hi);
342 1.30 thorpej f = OFW_PCI_PHYS_HI_FUNCTION(reg.phys_hi);
343 1.30 thorpej
344 1.30 thorpej if (sc->sc_bus != b) {
345 1.30 thorpej printf("%s: WARNING: incorrect bus # for \"%s\" "
346 1.30 thorpej "(%d/%d/%d)\n", sc->sc_dev.dv_xname, name, b, d, f);
347 1.30 thorpej continue;
348 1.30 thorpej }
349 1.27 eeh
350 1.30 thorpej tag = ofpci_make_tag(pc, node, b, d, f);
351 1.32 eeh
352 1.32 eeh /*
353 1.32 eeh * Turn on parity and fast-back-to-back for the device.
354 1.32 eeh */
355 1.32 eeh csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
356 1.32 eeh if (csr & PCI_STATUS_BACKTOBACK_SUPPORT)
357 1.32 eeh csr |= PCI_COMMAND_BACKTOBACK_ENABLE;
358 1.32 eeh csr |= PCI_COMMAND_PARITY_ENABLE;
359 1.32 eeh pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr);
360 1.32 eeh
361 1.35 nakayama /*
362 1.35 nakayama * Initialize the latency timer register for busmaster
363 1.35 nakayama * devices to work properly.
364 1.35 nakayama * latency-timer = min-grant * bus-freq / 4 (from FreeBSD)
365 1.35 nakayama * Also initialize the cache line size register.
366 1.35 nakayama * Solaris anytime sets this register to the value 0x10.
367 1.35 nakayama */
368 1.35 nakayama bhlc = pci_conf_read(pc, tag, PCI_BHLC_REG);
369 1.35 nakayama ic = pci_conf_read(pc, tag, PCI_INTERRUPT_REG);
370 1.35 nakayama
371 1.35 nakayama lt = min(PCI_MIN_GNT(ic) * bus_frequency / 4, 255);
372 1.35 nakayama if (lt == 0 || lt < PCI_LATTIMER(bhlc))
373 1.35 nakayama lt = PCI_LATTIMER(bhlc);
374 1.35 nakayama
375 1.35 nakayama cl = PCI_CACHELINE(bhlc);
376 1.35 nakayama if (cl == 0)
377 1.37 martin cl = cacheline;
378 1.35 nakayama
379 1.35 nakayama bhlc &= ~((PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT) |
380 1.35 nakayama (PCI_CACHELINE_MASK << PCI_CACHELINE_SHIFT));
381 1.35 nakayama bhlc |= (lt << PCI_LATTIMER_SHIFT) |
382 1.35 nakayama (cl << PCI_CACHELINE_SHIFT);
383 1.35 nakayama pci_conf_write(pc, tag, PCI_BHLC_REG, bhlc);
384 1.35 nakayama
385 1.30 thorpej ret = pci_probe_device(sc, tag, match, pap);
386 1.30 thorpej if (match != NULL && ret != 0)
387 1.30 thorpej return (ret);
388 1.30 thorpej }
389 1.30 thorpej return (0);
390 1.1 mrg }
391 1.1 mrg
392 1.1 mrg /* assume we are mapped little-endian/side-effect */
393 1.1 mrg pcireg_t
394 1.1 mrg pci_conf_read(pc, tag, reg)
395 1.1 mrg pci_chipset_tag_t pc;
396 1.1 mrg pcitag_t tag;
397 1.1 mrg int reg;
398 1.1 mrg {
399 1.1 mrg struct psycho_pbm *pp = pc->cookie;
400 1.1 mrg struct psycho_softc *sc = pp->pp_sc;
401 1.22 eeh pcireg_t val = (pcireg_t)~0;
402 1.22 eeh
403 1.22 eeh DPRINTF(SPDB_CONF, ("pci_conf_read: tag %lx reg %x ",
404 1.22 eeh (long)tag, reg));
405 1.22 eeh if (PCITAG_NODE(tag) != -1) {
406 1.22 eeh DPRINTF(SPDB_CONF, ("asi=%x addr=%qx (offset=%x) ...",
407 1.26 eeh sc->sc_configaddr._asi,
408 1.26 eeh (long long)(sc->sc_configaddr._ptr +
409 1.22 eeh PCITAG_OFFSET(tag) + reg),
410 1.22 eeh (int)PCITAG_OFFSET(tag) + reg));
411 1.1 mrg
412 1.1 mrg val = bus_space_read_4(sc->sc_configtag, sc->sc_configaddr,
413 1.22 eeh PCITAG_OFFSET(tag) + reg);
414 1.1 mrg }
415 1.22 eeh #ifdef DEBUG
416 1.24 mrg else DPRINTF(SPDB_CONF, ("pci_conf_read: bogus pcitag %x\n",
417 1.24 mrg (int)PCITAG_OFFSET(tag)));
418 1.22 eeh #endif
419 1.1 mrg DPRINTF(SPDB_CONF, (" returning %08x\n", (u_int)val));
420 1.1 mrg
421 1.1 mrg return (val);
422 1.1 mrg }
423 1.1 mrg
424 1.1 mrg void
425 1.1 mrg pci_conf_write(pc, tag, reg, data)
426 1.1 mrg pci_chipset_tag_t pc;
427 1.1 mrg pcitag_t tag;
428 1.1 mrg int reg;
429 1.1 mrg pcireg_t data;
430 1.1 mrg {
431 1.1 mrg struct psycho_pbm *pp = pc->cookie;
432 1.1 mrg struct psycho_softc *sc = pp->pp_sc;
433 1.1 mrg
434 1.22 eeh DPRINTF(SPDB_CONF, ("pci_conf_write: tag %lx; reg %x; data %x; ",
435 1.22 eeh (long)PCITAG_OFFSET(tag), reg, (int)data));
436 1.1 mrg DPRINTF(SPDB_CONF, ("asi = %x; readaddr = %qx (offset = %x)\n",
437 1.26 eeh sc->sc_configaddr._asi,
438 1.26 eeh (long long)(sc->sc_configaddr._ptr + PCITAG_OFFSET(tag) + reg),
439 1.22 eeh (int)PCITAG_OFFSET(tag) + reg));
440 1.1 mrg
441 1.24 mrg /* If we don't know it, just punt it. */
442 1.24 mrg if (PCITAG_NODE(tag) == -1) {
443 1.24 mrg DPRINTF(SPDB_CONF, ("pci_conf_write: bad addr"));
444 1.24 mrg return;
445 1.24 mrg }
446 1.1 mrg
447 1.22 eeh bus_space_write_4(sc->sc_configtag, sc->sc_configaddr,
448 1.22 eeh PCITAG_OFFSET(tag) + reg, data);
449 1.1 mrg }
450 1.1 mrg
451 1.1 mrg /*
452 1.1 mrg * interrupt mapping foo.
453 1.20 mrg * XXX: how does this deal with multiple interrupts for a device?
454 1.1 mrg */
455 1.1 mrg int
456 1.16 sommerfe pci_intr_map(pa, ihp)
457 1.16 sommerfe struct pci_attach_args *pa;
458 1.1 mrg pci_intr_handle_t *ihp;
459 1.1 mrg {
460 1.22 eeh pcitag_t tag = pa->pa_tag;
461 1.22 eeh int interrupts;
462 1.22 eeh int len, node = PCITAG_NODE(tag);
463 1.22 eeh char devtype[30];
464 1.22 eeh
465 1.22 eeh len = OF_getproplen(node, "interrupts");
466 1.22 eeh if (len < sizeof(interrupts)) {
467 1.22 eeh DPRINTF(SPDB_INTMAP,
468 1.22 eeh ("pci_intr_map: interrupts len %d too small\n", len));
469 1.22 eeh return (ENODEV);
470 1.22 eeh }
471 1.22 eeh if (OF_getprop(node, "interrupts", (void *)&interrupts,
472 1.22 eeh sizeof(interrupts)) != len) {
473 1.22 eeh DPRINTF(SPDB_INTMAP,
474 1.22 eeh ("pci_intr_map: could not read interrupts\n"));
475 1.22 eeh return (ENODEV);
476 1.22 eeh }
477 1.20 mrg
478 1.22 eeh if (OF_mapintr(node, &interrupts, sizeof(interrupts),
479 1.23 eeh sizeof(interrupts)) < 0) {
480 1.22 eeh printf("OF_mapintr failed\n");
481 1.22 eeh }
482 1.22 eeh /* Try to find an IPL for this type of device. */
483 1.22 eeh if (OF_getprop(node, "device_type", &devtype, sizeof(devtype)) > 0) {
484 1.22 eeh for (len = 0; intrmap[len].in_class; len++)
485 1.22 eeh if (strcmp(intrmap[len].in_class, devtype) == 0) {
486 1.22 eeh interrupts |= INTLEVENCODE(intrmap[len].in_lev);
487 1.22 eeh break;
488 1.22 eeh }
489 1.22 eeh }
490 1.20 mrg
491 1.22 eeh /* XXXX -- we use the ino. What if there is a valid IGN? */
492 1.22 eeh *ihp = interrupts;
493 1.22 eeh return (0);
494 1.1 mrg }
495 1.1 mrg
496 1.1 mrg const char *
497 1.1 mrg pci_intr_string(pc, ih)
498 1.1 mrg pci_chipset_tag_t pc;
499 1.1 mrg pci_intr_handle_t ih;
500 1.1 mrg {
501 1.1 mrg static char str[16];
502 1.1 mrg
503 1.1 mrg DPRINTF(SPDB_INTR, ("pci_intr_string: ih %u", ih));
504 1.22 eeh sprintf(str, "ivec %x", ih);
505 1.1 mrg DPRINTF(SPDB_INTR, ("; returning %s\n", str));
506 1.1 mrg
507 1.1 mrg return (str);
508 1.8 cgd }
509 1.8 cgd
510 1.8 cgd const struct evcnt *
511 1.8 cgd pci_intr_evcnt(pc, ih)
512 1.8 cgd pci_chipset_tag_t pc;
513 1.8 cgd pci_intr_handle_t ih;
514 1.8 cgd {
515 1.8 cgd
516 1.8 cgd /* XXX for now, no evcnt parent reported */
517 1.8 cgd return NULL;
518 1.1 mrg }
519 1.1 mrg
520 1.1 mrg void *
521 1.1 mrg pci_intr_establish(pc, ih, level, func, arg)
522 1.1 mrg pci_chipset_tag_t pc;
523 1.1 mrg pci_intr_handle_t ih;
524 1.1 mrg int level;
525 1.1 mrg int (*func) __P((void *));
526 1.1 mrg void *arg;
527 1.1 mrg {
528 1.1 mrg void *cookie;
529 1.1 mrg struct psycho_pbm *pp = (struct psycho_pbm *)pc->cookie;
530 1.1 mrg
531 1.1 mrg DPRINTF(SPDB_INTR, ("pci_intr_establish: ih %lu; level %d", (u_long)ih, level));
532 1.34 pk cookie = bus_intr_establish(pp->pp_memt, ih, level, func, arg);
533 1.1 mrg
534 1.1 mrg DPRINTF(SPDB_INTR, ("; returning handle %p\n", cookie));
535 1.1 mrg return (cookie);
536 1.1 mrg }
537 1.1 mrg
538 1.1 mrg void
539 1.1 mrg pci_intr_disestablish(pc, cookie)
540 1.1 mrg pci_chipset_tag_t pc;
541 1.1 mrg void *cookie;
542 1.1 mrg {
543 1.1 mrg
544 1.1 mrg DPRINTF(SPDB_INTR, ("pci_intr_disestablish: cookie %p\n", cookie));
545 1.1 mrg
546 1.1 mrg /* XXX */
547 1.1 mrg panic("can't disestablish PCI interrupts yet");
548 1.1 mrg }
549