pci_machdep.c revision 1.47 1 1.47 petrov /* $NetBSD: pci_machdep.c,v 1.47 2004/06/11 03:52:00 petrov Exp $ */
2 1.1 mrg
3 1.1 mrg /*
4 1.5 mrg * Copyright (c) 1999, 2000 Matthew R. Green
5 1.1 mrg * All rights reserved.
6 1.1 mrg *
7 1.1 mrg * Redistribution and use in source and binary forms, with or without
8 1.1 mrg * modification, are permitted provided that the following conditions
9 1.1 mrg * are met:
10 1.1 mrg * 1. Redistributions of source code must retain the above copyright
11 1.1 mrg * notice, this list of conditions and the following disclaimer.
12 1.1 mrg * 2. Redistributions in binary form must reproduce the above copyright
13 1.1 mrg * notice, this list of conditions and the following disclaimer in the
14 1.1 mrg * documentation and/or other materials provided with the distribution.
15 1.1 mrg * 3. The name of the author may not be used to endorse or promote products
16 1.1 mrg * derived from this software without specific prior written permission.
17 1.1 mrg *
18 1.1 mrg * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 1.1 mrg * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 1.1 mrg * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 1.1 mrg * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 1.1 mrg * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
23 1.1 mrg * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
24 1.1 mrg * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
25 1.1 mrg * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
26 1.1 mrg * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 1.1 mrg * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 1.1 mrg * SUCH DAMAGE.
29 1.1 mrg */
30 1.1 mrg
31 1.1 mrg /*
32 1.1 mrg * functions expected by the MI PCI code.
33 1.1 mrg */
34 1.38 lukem
35 1.38 lukem #include <sys/cdefs.h>
36 1.47 petrov __KERNEL_RCSID(0, "$NetBSD: pci_machdep.c,v 1.47 2004/06/11 03:52:00 petrov Exp $");
37 1.1 mrg
38 1.1 mrg #include <sys/types.h>
39 1.1 mrg #include <sys/param.h>
40 1.1 mrg #include <sys/time.h>
41 1.1 mrg #include <sys/systm.h>
42 1.1 mrg #include <sys/errno.h>
43 1.1 mrg #include <sys/device.h>
44 1.1 mrg #include <sys/malloc.h>
45 1.1 mrg
46 1.1 mrg #define _SPARC_BUS_DMA_PRIVATE
47 1.1 mrg #include <machine/bus.h>
48 1.1 mrg #include <machine/autoconf.h>
49 1.22 eeh #include <machine/openfirm.h>
50 1.1 mrg #include <dev/pci/pcivar.h>
51 1.1 mrg #include <dev/pci/pcireg.h>
52 1.1 mrg
53 1.19 mrg #include <dev/ofw/ofw_pci.h>
54 1.19 mrg
55 1.1 mrg #include <sparc64/dev/iommureg.h>
56 1.1 mrg #include <sparc64/dev/iommuvar.h>
57 1.1 mrg #include <sparc64/dev/psychoreg.h>
58 1.1 mrg #include <sparc64/dev/psychovar.h>
59 1.37 martin #include <sparc64/sparc64/cache.h>
60 1.39 petrov
61 1.39 petrov #ifdef DEBUG
62 1.39 petrov #define SPDB_CONF 0x01
63 1.39 petrov #define SPDB_INTR 0x04
64 1.39 petrov #define SPDB_INTMAP 0x08
65 1.39 petrov #define SPDB_PROBE 0x20
66 1.39 petrov int sparc_pci_debug = 0x0;
67 1.39 petrov #define DPRINTF(l, s) do { if (sparc_pci_debug & l) printf s; } while (0)
68 1.39 petrov #else
69 1.39 petrov #define DPRINTF(l, s)
70 1.39 petrov #endif
71 1.1 mrg
72 1.1 mrg /* this is a base to be copied */
73 1.1 mrg struct sparc_pci_chipset _sparc_pci_chipset = {
74 1.1 mrg NULL,
75 1.1 mrg };
76 1.2 mrg
77 1.41 petrov static int pci_find_ino(struct pci_attach_args *, pci_intr_handle_t *);
78 1.36 martin
79 1.30 thorpej static pcitag_t
80 1.30 thorpej ofpci_make_tag(pci_chipset_tag_t pc, int node, int b, int d, int f)
81 1.30 thorpej {
82 1.30 thorpej pcitag_t tag;
83 1.30 thorpej
84 1.30 thorpej tag = PCITAG_CREATE(node, b, d, f);
85 1.30 thorpej
86 1.30 thorpej /* Enable all the different spaces for this device */
87 1.30 thorpej pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG,
88 1.30 thorpej PCI_COMMAND_MEM_ENABLE|PCI_COMMAND_MASTER_ENABLE|
89 1.30 thorpej PCI_COMMAND_IO_ENABLE);
90 1.30 thorpej return (tag);
91 1.30 thorpej }
92 1.30 thorpej
93 1.1 mrg /*
94 1.1 mrg * functions provided to the MI code.
95 1.1 mrg */
96 1.1 mrg
97 1.1 mrg void
98 1.1 mrg pci_attach_hook(parent, self, pba)
99 1.1 mrg struct device *parent;
100 1.1 mrg struct device *self;
101 1.1 mrg struct pcibus_attach_args *pba;
102 1.1 mrg {
103 1.1 mrg }
104 1.1 mrg
105 1.1 mrg int
106 1.1 mrg pci_bus_maxdevs(pc, busno)
107 1.1 mrg pci_chipset_tag_t pc;
108 1.1 mrg int busno;
109 1.1 mrg {
110 1.1 mrg
111 1.1 mrg return 32;
112 1.1 mrg }
113 1.19 mrg
114 1.1 mrg pcitag_t
115 1.1 mrg pci_make_tag(pc, b, d, f)
116 1.1 mrg pci_chipset_tag_t pc;
117 1.1 mrg int b;
118 1.1 mrg int d;
119 1.1 mrg int f;
120 1.1 mrg {
121 1.35 nakayama struct psycho_pbm *pp = pc->cookie;
122 1.46 nakayama struct ofw_pci_register reg;
123 1.22 eeh pcitag_t tag;
124 1.35 nakayama int (*valid) __P((void *));
125 1.22 eeh int node, len;
126 1.22 eeh #ifdef DEBUG
127 1.22 eeh char name[80];
128 1.40 martin memset(name, 0, sizeof(name));
129 1.22 eeh #endif
130 1.1 mrg
131 1.35 nakayama /*
132 1.35 nakayama * Refer to the PCI/CardBus bus node first.
133 1.35 nakayama * It returns a tag if node is present and bus is valid.
134 1.35 nakayama */
135 1.35 nakayama if (0 <= b && b < 256) {
136 1.35 nakayama node = (*pp->pp_busnode)[b].node;
137 1.35 nakayama valid = (*pp->pp_busnode)[b].valid;
138 1.35 nakayama if (node != 0 && d == 0 &&
139 1.35 nakayama (valid == NULL || (*valid)((*pp->pp_busnode)[b].arg)))
140 1.35 nakayama return ofpci_make_tag(pc, node, b, d, f);
141 1.35 nakayama }
142 1.35 nakayama
143 1.22 eeh /*
144 1.22 eeh * Hunt for the node that corresponds to this device
145 1.22 eeh *
146 1.22 eeh * We could cache this info in an array in the parent
147 1.22 eeh * device... except then we have problems with devices
148 1.22 eeh * attached below pci-pci bridges, and we would need to
149 1.22 eeh * add special code to the pci-pci bridge to cache this
150 1.22 eeh * info.
151 1.22 eeh */
152 1.1 mrg
153 1.22 eeh tag = PCITAG_CREATE(-1, b, d, f);
154 1.22 eeh node = pc->rootnode;
155 1.22 eeh /*
156 1.22 eeh * First make sure we're on the right bus. If our parent
157 1.22 eeh * has a bus-range property and we're not in the range,
158 1.22 eeh * then we're obviously on the wrong bus. So go up one
159 1.22 eeh * level.
160 1.22 eeh */
161 1.22 eeh #ifdef DEBUG
162 1.22 eeh if (sparc_pci_debug & SPDB_PROBE) {
163 1.42 pk printf("curnode %x %s\n", node,
164 1.42 pk prom_getpropstringA(node, "name", name, sizeof(name)));
165 1.22 eeh }
166 1.22 eeh #endif
167 1.22 eeh #if 0
168 1.22 eeh while ((OF_getprop(OF_parent(node), "bus-range", (void *)&busrange,
169 1.22 eeh sizeof(busrange)) == sizeof(busrange)) &&
170 1.22 eeh (b < busrange[0] || b > busrange[1])) {
171 1.22 eeh /* Out of range, go up one */
172 1.22 eeh node = OF_parent(node);
173 1.22 eeh #ifdef DEBUG
174 1.22 eeh if (sparc_pci_debug & SPDB_PROBE) {
175 1.42 pk printf("going up to node %x %s\n", node,
176 1.42 pk prom_getpropstringA(node, "name", name, sizeof(name)));
177 1.22 eeh }
178 1.22 eeh #endif
179 1.22 eeh }
180 1.22 eeh #endif
181 1.22 eeh /*
182 1.22 eeh * Now traverse all peers until we find the node or we find
183 1.22 eeh * the right bridge.
184 1.22 eeh *
185 1.22 eeh * XXX We go up one and down one to make sure nobody's missed.
186 1.22 eeh * but this should not be necessary.
187 1.22 eeh */
188 1.42 pk for (node = ((node)); node; node = prom_nextsibling(node)) {
189 1.1 mrg
190 1.22 eeh #ifdef DEBUG
191 1.22 eeh if (sparc_pci_debug & SPDB_PROBE) {
192 1.43 pk printf("checking node %x %s\n", node,
193 1.42 pk prom_getpropstringA(node, "name", name, sizeof(name)));
194 1.42 pk
195 1.22 eeh }
196 1.22 eeh #endif
197 1.1 mrg
198 1.22 eeh #if 1
199 1.1 mrg /*
200 1.22 eeh * Check for PCI-PCI bridges. If the device we want is
201 1.22 eeh * in the bus-range for that bridge, work our way down.
202 1.1 mrg */
203 1.44 pk while (1) {
204 1.44 pk int busrange[2], *brp;
205 1.44 pk len = 2;
206 1.44 pk brp = busrange;
207 1.45 nakayama if (prom_getprop(node, "bus-range", sizeof(*brp),
208 1.45 nakayama &len, &brp) != 0)
209 1.44 pk break;
210 1.44 pk if (len != 2 || b < busrange[0] || b > busrange[1])
211 1.44 pk break;
212 1.22 eeh /* Go down 1 level */
213 1.42 pk node = prom_firstchild(node);
214 1.22 eeh #ifdef DEBUG
215 1.22 eeh if (sparc_pci_debug & SPDB_PROBE) {
216 1.43 pk printf("going down to node %x %s\n", node,
217 1.42 pk prom_getpropstringA(node, "name",
218 1.42 pk name, sizeof(name)));
219 1.22 eeh }
220 1.22 eeh #endif
221 1.1 mrg }
222 1.44 pk #endif /*1*/
223 1.22 eeh /*
224 1.22 eeh * We only really need the first `reg' property.
225 1.22 eeh *
226 1.22 eeh * For simplicity, we'll query the `reg' when we
227 1.22 eeh * need it. Otherwise we could malloc() it, but
228 1.22 eeh * that gets more complicated.
229 1.22 eeh */
230 1.46 nakayama len = prom_getproplen(node, "reg");
231 1.46 nakayama if (len < sizeof(reg))
232 1.46 nakayama continue;
233 1.46 nakayama if (OF_getprop(node, "reg", (void *)®, sizeof(reg)) != len)
234 1.44 pk panic("pci_probe_bus: OF_getprop len botch");
235 1.22 eeh
236 1.22 eeh if (b != OFW_PCI_PHYS_HI_BUS(reg.phys_hi))
237 1.22 eeh continue;
238 1.22 eeh if (d != OFW_PCI_PHYS_HI_DEVICE(reg.phys_hi))
239 1.22 eeh continue;
240 1.22 eeh if (f != OFW_PCI_PHYS_HI_FUNCTION(reg.phys_hi))
241 1.22 eeh continue;
242 1.22 eeh
243 1.22 eeh /* Got a match */
244 1.27 eeh tag = ofpci_make_tag(pc, node, b, d, f);
245 1.22 eeh
246 1.22 eeh return (tag);
247 1.1 mrg }
248 1.22 eeh /* No device found -- return a dead tag */
249 1.27 eeh return (tag);
250 1.28 thorpej }
251 1.28 thorpej
252 1.28 thorpej void
253 1.28 thorpej pci_decompose_tag(pc, tag, bp, dp, fp)
254 1.28 thorpej pci_chipset_tag_t pc;
255 1.28 thorpej pcitag_t tag;
256 1.28 thorpej int *bp, *dp, *fp;
257 1.28 thorpej {
258 1.28 thorpej
259 1.28 thorpej if (bp != NULL)
260 1.28 thorpej *bp = PCITAG_BUS(tag);
261 1.28 thorpej if (dp != NULL)
262 1.28 thorpej *dp = PCITAG_DEV(tag);
263 1.28 thorpej if (fp != NULL)
264 1.28 thorpej *fp = PCITAG_FUN(tag);
265 1.27 eeh }
266 1.27 eeh
267 1.30 thorpej int
268 1.30 thorpej pci_enumerate_bus(struct pci_softc *sc,
269 1.30 thorpej int (*match)(struct pci_attach_args *), struct pci_attach_args *pap)
270 1.27 eeh {
271 1.30 thorpej struct ofw_pci_register reg;
272 1.30 thorpej pci_chipset_tag_t pc = sc->sc_pc;
273 1.27 eeh pcitag_t tag;
274 1.35 nakayama pcireg_t class, csr, bhlc, ic;
275 1.30 thorpej int node, b, d, f, ret;
276 1.37 martin int bus_frequency, lt, cl, cacheline;
277 1.30 thorpej char name[30];
278 1.32 eeh extern int pci_config_dump;
279 1.30 thorpej
280 1.31 eeh if (sc->sc_bridgetag)
281 1.31 eeh node = PCITAG_NODE(*sc->sc_bridgetag);
282 1.31 eeh else
283 1.31 eeh node = pc->rootnode;
284 1.31 eeh
285 1.42 pk bus_frequency =
286 1.42 pk prom_getpropint(node, "clock-frequency", 33000000) / 1000000;
287 1.35 nakayama
288 1.37 martin /*
289 1.37 martin * Make sure the cache line size is at least as big as the
290 1.37 martin * ecache line and the streaming cache (64 byte).
291 1.37 martin */
292 1.37 martin cacheline = max(cacheinfo.ec_linesize, 64);
293 1.37 martin KASSERT((cacheline/64)*64 == cacheline &&
294 1.37 martin (cacheline/cacheinfo.ec_linesize)*cacheinfo.ec_linesize == cacheline &&
295 1.37 martin (cacheline/4)*4 == cacheline);
296 1.37 martin
297 1.32 eeh /* Turn on parity for the bus. */
298 1.32 eeh tag = ofpci_make_tag(pc, node, sc->sc_bus, 0, 0);
299 1.32 eeh csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
300 1.32 eeh csr |= PCI_COMMAND_PARITY_ENABLE;
301 1.32 eeh pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr);
302 1.32 eeh
303 1.35 nakayama /*
304 1.35 nakayama * Initialize the latency timer register.
305 1.35 nakayama * The value 0x40 is from Solaris.
306 1.35 nakayama */
307 1.35 nakayama bhlc = pci_conf_read(pc, tag, PCI_BHLC_REG);
308 1.35 nakayama bhlc &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT);
309 1.35 nakayama bhlc |= 0x40 << PCI_LATTIMER_SHIFT;
310 1.35 nakayama pci_conf_write(pc, tag, PCI_BHLC_REG, bhlc);
311 1.35 nakayama
312 1.32 eeh if (pci_config_dump) pci_conf_print(pc, tag, NULL);
313 1.32 eeh
314 1.42 pk for (node = prom_firstchild(node); node != 0 && node != -1;
315 1.42 pk node = prom_nextsibling(node)) {
316 1.30 thorpej name[0] = name[29] = 0;
317 1.42 pk prom_getpropstringA(node, "name", name, sizeof(name));
318 1.27 eeh
319 1.30 thorpej if (OF_getprop(node, "class-code", &class, sizeof(class)) !=
320 1.30 thorpej sizeof(class))
321 1.30 thorpej continue;
322 1.30 thorpej if (OF_getprop(node, "reg", ®, sizeof(reg)) < sizeof(reg))
323 1.30 thorpej panic("pci_enumerate_bus: \"%s\" regs too small", name);
324 1.27 eeh
325 1.30 thorpej b = OFW_PCI_PHYS_HI_BUS(reg.phys_hi);
326 1.30 thorpej d = OFW_PCI_PHYS_HI_DEVICE(reg.phys_hi);
327 1.30 thorpej f = OFW_PCI_PHYS_HI_FUNCTION(reg.phys_hi);
328 1.30 thorpej
329 1.30 thorpej if (sc->sc_bus != b) {
330 1.30 thorpej printf("%s: WARNING: incorrect bus # for \"%s\" "
331 1.30 thorpej "(%d/%d/%d)\n", sc->sc_dev.dv_xname, name, b, d, f);
332 1.30 thorpej continue;
333 1.30 thorpej }
334 1.27 eeh
335 1.30 thorpej tag = ofpci_make_tag(pc, node, b, d, f);
336 1.32 eeh
337 1.32 eeh /*
338 1.32 eeh * Turn on parity and fast-back-to-back for the device.
339 1.32 eeh */
340 1.32 eeh csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
341 1.32 eeh if (csr & PCI_STATUS_BACKTOBACK_SUPPORT)
342 1.32 eeh csr |= PCI_COMMAND_BACKTOBACK_ENABLE;
343 1.32 eeh csr |= PCI_COMMAND_PARITY_ENABLE;
344 1.32 eeh pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr);
345 1.32 eeh
346 1.35 nakayama /*
347 1.35 nakayama * Initialize the latency timer register for busmaster
348 1.35 nakayama * devices to work properly.
349 1.35 nakayama * latency-timer = min-grant * bus-freq / 4 (from FreeBSD)
350 1.35 nakayama * Also initialize the cache line size register.
351 1.35 nakayama * Solaris anytime sets this register to the value 0x10.
352 1.35 nakayama */
353 1.35 nakayama bhlc = pci_conf_read(pc, tag, PCI_BHLC_REG);
354 1.35 nakayama ic = pci_conf_read(pc, tag, PCI_INTERRUPT_REG);
355 1.35 nakayama
356 1.35 nakayama lt = min(PCI_MIN_GNT(ic) * bus_frequency / 4, 255);
357 1.35 nakayama if (lt == 0 || lt < PCI_LATTIMER(bhlc))
358 1.35 nakayama lt = PCI_LATTIMER(bhlc);
359 1.35 nakayama
360 1.35 nakayama cl = PCI_CACHELINE(bhlc);
361 1.35 nakayama if (cl == 0)
362 1.37 martin cl = cacheline;
363 1.35 nakayama
364 1.35 nakayama bhlc &= ~((PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT) |
365 1.35 nakayama (PCI_CACHELINE_MASK << PCI_CACHELINE_SHIFT));
366 1.35 nakayama bhlc |= (lt << PCI_LATTIMER_SHIFT) |
367 1.35 nakayama (cl << PCI_CACHELINE_SHIFT);
368 1.35 nakayama pci_conf_write(pc, tag, PCI_BHLC_REG, bhlc);
369 1.35 nakayama
370 1.30 thorpej ret = pci_probe_device(sc, tag, match, pap);
371 1.30 thorpej if (match != NULL && ret != 0)
372 1.30 thorpej return (ret);
373 1.30 thorpej }
374 1.30 thorpej return (0);
375 1.1 mrg }
376 1.1 mrg
377 1.1 mrg /* assume we are mapped little-endian/side-effect */
378 1.1 mrg pcireg_t
379 1.1 mrg pci_conf_read(pc, tag, reg)
380 1.1 mrg pci_chipset_tag_t pc;
381 1.1 mrg pcitag_t tag;
382 1.1 mrg int reg;
383 1.1 mrg {
384 1.1 mrg struct psycho_pbm *pp = pc->cookie;
385 1.1 mrg struct psycho_softc *sc = pp->pp_sc;
386 1.22 eeh pcireg_t val = (pcireg_t)~0;
387 1.22 eeh
388 1.22 eeh DPRINTF(SPDB_CONF, ("pci_conf_read: tag %lx reg %x ",
389 1.22 eeh (long)tag, reg));
390 1.22 eeh if (PCITAG_NODE(tag) != -1) {
391 1.22 eeh DPRINTF(SPDB_CONF, ("asi=%x addr=%qx (offset=%x) ...",
392 1.26 eeh sc->sc_configaddr._asi,
393 1.26 eeh (long long)(sc->sc_configaddr._ptr +
394 1.22 eeh PCITAG_OFFSET(tag) + reg),
395 1.22 eeh (int)PCITAG_OFFSET(tag) + reg));
396 1.1 mrg
397 1.1 mrg val = bus_space_read_4(sc->sc_configtag, sc->sc_configaddr,
398 1.22 eeh PCITAG_OFFSET(tag) + reg);
399 1.1 mrg }
400 1.22 eeh #ifdef DEBUG
401 1.24 mrg else DPRINTF(SPDB_CONF, ("pci_conf_read: bogus pcitag %x\n",
402 1.24 mrg (int)PCITAG_OFFSET(tag)));
403 1.22 eeh #endif
404 1.1 mrg DPRINTF(SPDB_CONF, (" returning %08x\n", (u_int)val));
405 1.1 mrg
406 1.1 mrg return (val);
407 1.1 mrg }
408 1.1 mrg
409 1.1 mrg void
410 1.1 mrg pci_conf_write(pc, tag, reg, data)
411 1.1 mrg pci_chipset_tag_t pc;
412 1.1 mrg pcitag_t tag;
413 1.1 mrg int reg;
414 1.1 mrg pcireg_t data;
415 1.1 mrg {
416 1.1 mrg struct psycho_pbm *pp = pc->cookie;
417 1.1 mrg struct psycho_softc *sc = pp->pp_sc;
418 1.1 mrg
419 1.22 eeh DPRINTF(SPDB_CONF, ("pci_conf_write: tag %lx; reg %x; data %x; ",
420 1.22 eeh (long)PCITAG_OFFSET(tag), reg, (int)data));
421 1.1 mrg DPRINTF(SPDB_CONF, ("asi = %x; readaddr = %qx (offset = %x)\n",
422 1.26 eeh sc->sc_configaddr._asi,
423 1.26 eeh (long long)(sc->sc_configaddr._ptr + PCITAG_OFFSET(tag) + reg),
424 1.22 eeh (int)PCITAG_OFFSET(tag) + reg));
425 1.1 mrg
426 1.24 mrg /* If we don't know it, just punt it. */
427 1.24 mrg if (PCITAG_NODE(tag) == -1) {
428 1.24 mrg DPRINTF(SPDB_CONF, ("pci_conf_write: bad addr"));
429 1.24 mrg return;
430 1.24 mrg }
431 1.1 mrg
432 1.22 eeh bus_space_write_4(sc->sc_configtag, sc->sc_configaddr,
433 1.22 eeh PCITAG_OFFSET(tag) + reg, data);
434 1.1 mrg }
435 1.1 mrg
436 1.41 petrov static int
437 1.41 petrov pci_find_ino(pa, ihp)
438 1.41 petrov struct pci_attach_args *pa;
439 1.41 petrov pci_intr_handle_t *ihp;
440 1.41 petrov {
441 1.41 petrov struct psycho_pbm *pp = pa->pa_pc->cookie;
442 1.41 petrov struct psycho_softc *sc = pp->pp_sc;
443 1.41 petrov u_int dev;
444 1.41 petrov u_int ino;
445 1.41 petrov
446 1.47 petrov DPRINTF(SPDB_INTMAP, ("pci_find_ino: pa_tag: node %x, %d:%d:%d\n",
447 1.47 petrov PCITAG_NODE(pa->pa_tag), (int)PCITAG_BUS(pa->pa_tag),
448 1.47 petrov (int)PCITAG_DEV(pa->pa_tag),
449 1.47 petrov (int)PCITAG_FUN(pa->pa_tag)));
450 1.47 petrov DPRINTF(SPDB_INTMAP,
451 1.47 petrov ("pci_find_ino: intrswiz %d, intrpin %d, intrline %d, rawintrpin %d\n",
452 1.47 petrov pa->pa_intrswiz, pa->pa_intrpin, pa->pa_intrline, pa->pa_rawintrpin));
453 1.47 petrov DPRINTF(SPDB_INTMAP, ("pci_find_ino: pa_intrtag: node %x, %d:%d:%d\n",
454 1.47 petrov PCITAG_NODE(pa->pa_intrtag),
455 1.47 petrov (int)PCITAG_BUS(pa->pa_intrtag),
456 1.47 petrov (int)PCITAG_DEV(pa->pa_intrtag),
457 1.47 petrov (int)PCITAG_FUN(pa->pa_intrtag)));
458 1.47 petrov
459 1.41 petrov ino = *ihp;
460 1.41 petrov
461 1.41 petrov if ((ino & ~INTMAP_PCIINT) == 0) {
462 1.41 petrov
463 1.47 petrov if (pa->pa_intrswiz != 0 && PCITAG_NODE(pa->pa_intrtag) != 0)
464 1.47 petrov dev = PCITAG_DEV(pa->pa_intrtag);
465 1.47 petrov else
466 1.47 petrov dev = pa->pa_device;
467 1.47 petrov
468 1.41 petrov if (sc->sc_mode == PSYCHO_MODE_PSYCHO &&
469 1.41 petrov pp->pp_id == PSYCHO_PBM_B)
470 1.47 petrov dev -= 2;
471 1.41 petrov else
472 1.47 petrov dev--;
473 1.41 petrov
474 1.47 petrov DPRINTF(SPDB_INTMAP, ("pci_find_ino: mode %d, pbm %d, dev %d, ino %d\n",
475 1.47 petrov sc->sc_mode, pp->pp_id, dev, ino));
476 1.41 petrov
477 1.47 petrov ino = (pa->pa_intrpin - 1) & INTMAP_PCIINT;
478 1.41 petrov
479 1.41 petrov ino |= sc->sc_ign;
480 1.41 petrov ino |= ((pp->pp_id == PSYCHO_PBM_B) ? INTMAP_PCIBUS : 0);
481 1.41 petrov ino |= (dev << 2) & INTMAP_PCISLOT;
482 1.41 petrov
483 1.41 petrov *ihp = ino;
484 1.41 petrov }
485 1.41 petrov
486 1.41 petrov return (0);
487 1.41 petrov }
488 1.41 petrov
489 1.1 mrg /*
490 1.1 mrg * interrupt mapping foo.
491 1.20 mrg * XXX: how does this deal with multiple interrupts for a device?
492 1.1 mrg */
493 1.1 mrg int
494 1.16 sommerfe pci_intr_map(pa, ihp)
495 1.16 sommerfe struct pci_attach_args *pa;
496 1.1 mrg pci_intr_handle_t *ihp;
497 1.1 mrg {
498 1.22 eeh pcitag_t tag = pa->pa_tag;
499 1.44 pk int interrupts, *intp;
500 1.22 eeh int len, node = PCITAG_NODE(tag);
501 1.22 eeh char devtype[30];
502 1.22 eeh
503 1.44 pk intp = &interrupts;
504 1.44 pk len = 1;
505 1.44 pk if (prom_getprop(node, "interrupts", sizeof(interrupts),
506 1.44 pk &len, &intp) != 0 || len != 1) {
507 1.22 eeh DPRINTF(SPDB_INTMAP,
508 1.22 eeh ("pci_intr_map: could not read interrupts\n"));
509 1.22 eeh return (ENODEV);
510 1.22 eeh }
511 1.20 mrg
512 1.22 eeh if (OF_mapintr(node, &interrupts, sizeof(interrupts),
513 1.23 eeh sizeof(interrupts)) < 0) {
514 1.22 eeh printf("OF_mapintr failed\n");
515 1.41 petrov pci_find_ino(pa, &interrupts);
516 1.22 eeh }
517 1.44 pk
518 1.22 eeh /* Try to find an IPL for this type of device. */
519 1.44 pk prom_getpropstringA(node, "device_type", devtype, sizeof(devtype));
520 1.44 pk for (len = 0; intrmap[len].in_class != NULL; len++)
521 1.44 pk if (strcmp(intrmap[len].in_class, devtype) == 0) {
522 1.44 pk interrupts |= INTLEVENCODE(intrmap[len].in_lev);
523 1.44 pk break;
524 1.44 pk }
525 1.20 mrg
526 1.22 eeh /* XXXX -- we use the ino. What if there is a valid IGN? */
527 1.22 eeh *ihp = interrupts;
528 1.22 eeh return (0);
529 1.1 mrg }
530 1.1 mrg
531 1.1 mrg const char *
532 1.1 mrg pci_intr_string(pc, ih)
533 1.1 mrg pci_chipset_tag_t pc;
534 1.1 mrg pci_intr_handle_t ih;
535 1.1 mrg {
536 1.1 mrg static char str[16];
537 1.1 mrg
538 1.1 mrg DPRINTF(SPDB_INTR, ("pci_intr_string: ih %u", ih));
539 1.22 eeh sprintf(str, "ivec %x", ih);
540 1.1 mrg DPRINTF(SPDB_INTR, ("; returning %s\n", str));
541 1.1 mrg
542 1.1 mrg return (str);
543 1.8 cgd }
544 1.8 cgd
545 1.8 cgd const struct evcnt *
546 1.8 cgd pci_intr_evcnt(pc, ih)
547 1.8 cgd pci_chipset_tag_t pc;
548 1.8 cgd pci_intr_handle_t ih;
549 1.8 cgd {
550 1.8 cgd
551 1.8 cgd /* XXX for now, no evcnt parent reported */
552 1.8 cgd return NULL;
553 1.1 mrg }
554 1.1 mrg
555 1.1 mrg void *
556 1.1 mrg pci_intr_establish(pc, ih, level, func, arg)
557 1.1 mrg pci_chipset_tag_t pc;
558 1.1 mrg pci_intr_handle_t ih;
559 1.1 mrg int level;
560 1.1 mrg int (*func) __P((void *));
561 1.1 mrg void *arg;
562 1.1 mrg {
563 1.1 mrg void *cookie;
564 1.1 mrg struct psycho_pbm *pp = (struct psycho_pbm *)pc->cookie;
565 1.1 mrg
566 1.1 mrg DPRINTF(SPDB_INTR, ("pci_intr_establish: ih %lu; level %d", (u_long)ih, level));
567 1.34 pk cookie = bus_intr_establish(pp->pp_memt, ih, level, func, arg);
568 1.1 mrg
569 1.1 mrg DPRINTF(SPDB_INTR, ("; returning handle %p\n", cookie));
570 1.1 mrg return (cookie);
571 1.1 mrg }
572 1.1 mrg
573 1.1 mrg void
574 1.1 mrg pci_intr_disestablish(pc, cookie)
575 1.1 mrg pci_chipset_tag_t pc;
576 1.1 mrg void *cookie;
577 1.1 mrg {
578 1.1 mrg
579 1.1 mrg DPRINTF(SPDB_INTR, ("pci_intr_disestablish: cookie %p\n", cookie));
580 1.1 mrg
581 1.1 mrg /* XXX */
582 1.1 mrg panic("can't disestablish PCI interrupts yet");
583 1.1 mrg }
584