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pci_machdep.c revision 1.51.14.1
      1  1.51.14.1        ad /*	$NetBSD: pci_machdep.c,v 1.51.14.1 2006/11/18 21:29:32 ad Exp $	*/
      2        1.1       mrg 
      3        1.1       mrg /*
      4        1.5       mrg  * Copyright (c) 1999, 2000 Matthew R. Green
      5        1.1       mrg  * All rights reserved.
      6        1.1       mrg  *
      7        1.1       mrg  * Redistribution and use in source and binary forms, with or without
      8        1.1       mrg  * modification, are permitted provided that the following conditions
      9        1.1       mrg  * are met:
     10        1.1       mrg  * 1. Redistributions of source code must retain the above copyright
     11        1.1       mrg  *    notice, this list of conditions and the following disclaimer.
     12        1.1       mrg  * 2. Redistributions in binary form must reproduce the above copyright
     13        1.1       mrg  *    notice, this list of conditions and the following disclaimer in the
     14        1.1       mrg  *    documentation and/or other materials provided with the distribution.
     15        1.1       mrg  * 3. The name of the author may not be used to endorse or promote products
     16        1.1       mrg  *    derived from this software without specific prior written permission.
     17        1.1       mrg  *
     18        1.1       mrg  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     19        1.1       mrg  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     20        1.1       mrg  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     21        1.1       mrg  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     22        1.1       mrg  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
     23        1.1       mrg  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
     24        1.1       mrg  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
     25        1.1       mrg  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
     26        1.1       mrg  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     27        1.1       mrg  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     28        1.1       mrg  * SUCH DAMAGE.
     29        1.1       mrg  */
     30        1.1       mrg 
     31        1.1       mrg /*
     32        1.1       mrg  * functions expected by the MI PCI code.
     33        1.1       mrg  */
     34       1.38     lukem 
     35       1.38     lukem #include <sys/cdefs.h>
     36  1.51.14.1        ad __KERNEL_RCSID(0, "$NetBSD: pci_machdep.c,v 1.51.14.1 2006/11/18 21:29:32 ad Exp $");
     37        1.1       mrg 
     38        1.1       mrg #include <sys/types.h>
     39        1.1       mrg #include <sys/param.h>
     40        1.1       mrg #include <sys/time.h>
     41        1.1       mrg #include <sys/systm.h>
     42        1.1       mrg #include <sys/errno.h>
     43        1.1       mrg #include <sys/device.h>
     44        1.1       mrg #include <sys/malloc.h>
     45        1.1       mrg 
     46        1.1       mrg #define _SPARC_BUS_DMA_PRIVATE
     47        1.1       mrg #include <machine/bus.h>
     48        1.1       mrg #include <machine/autoconf.h>
     49       1.22       eeh #include <machine/openfirm.h>
     50        1.1       mrg #include <dev/pci/pcivar.h>
     51        1.1       mrg #include <dev/pci/pcireg.h>
     52        1.1       mrg 
     53       1.19       mrg #include <dev/ofw/ofw_pci.h>
     54       1.19       mrg 
     55        1.1       mrg #include <sparc64/dev/iommureg.h>
     56        1.1       mrg #include <sparc64/dev/iommuvar.h>
     57        1.1       mrg #include <sparc64/dev/psychoreg.h>
     58        1.1       mrg #include <sparc64/dev/psychovar.h>
     59       1.37    martin #include <sparc64/sparc64/cache.h>
     60       1.39    petrov 
     61       1.49  drochner #include "locators.h"
     62       1.49  drochner 
     63       1.39    petrov #ifdef DEBUG
     64       1.39    petrov #define SPDB_CONF	0x01
     65       1.39    petrov #define SPDB_INTR	0x04
     66       1.39    petrov #define SPDB_INTMAP	0x08
     67       1.39    petrov #define SPDB_PROBE	0x20
     68       1.39    petrov int sparc_pci_debug = 0x0;
     69       1.39    petrov #define DPRINTF(l, s)	do { if (sparc_pci_debug & l) printf s; } while (0)
     70       1.39    petrov #else
     71       1.39    petrov #define DPRINTF(l, s)
     72       1.39    petrov #endif
     73        1.1       mrg 
     74        1.1       mrg /* this is a base to be copied */
     75        1.1       mrg struct sparc_pci_chipset _sparc_pci_chipset = {
     76  1.51.14.1        ad 	.cookie = NULL,
     77        1.1       mrg };
     78        1.2       mrg 
     79       1.41    petrov static int pci_find_ino(struct pci_attach_args *, pci_intr_handle_t *);
     80       1.36    martin 
     81       1.30   thorpej static pcitag_t
     82       1.30   thorpej ofpci_make_tag(pci_chipset_tag_t pc, int node, int b, int d, int f)
     83       1.30   thorpej {
     84       1.30   thorpej 	pcitag_t tag;
     85       1.30   thorpej 
     86       1.30   thorpej 	tag = PCITAG_CREATE(node, b, d, f);
     87       1.30   thorpej 
     88       1.30   thorpej 	/* Enable all the different spaces for this device */
     89       1.30   thorpej 	pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG,
     90       1.30   thorpej 		PCI_COMMAND_MEM_ENABLE|PCI_COMMAND_MASTER_ENABLE|
     91       1.30   thorpej 		PCI_COMMAND_IO_ENABLE);
     92       1.30   thorpej 	return (tag);
     93       1.30   thorpej }
     94       1.30   thorpej 
     95        1.1       mrg /*
     96        1.1       mrg  * functions provided to the MI code.
     97        1.1       mrg  */
     98        1.1       mrg 
     99        1.1       mrg void
    100       1.51       cdi pci_attach_hook(struct device *parent, struct device *self,
    101       1.51       cdi 	struct pcibus_attach_args *pba)
    102        1.1       mrg {
    103        1.1       mrg }
    104        1.1       mrg 
    105        1.1       mrg int
    106       1.51       cdi pci_bus_maxdevs(pci_chipset_tag_t pc, int busno)
    107        1.1       mrg {
    108        1.1       mrg 
    109        1.1       mrg 	return 32;
    110        1.1       mrg }
    111       1.19       mrg 
    112        1.1       mrg pcitag_t
    113       1.51       cdi pci_make_tag(pci_chipset_tag_t pc, int b, int d, int f)
    114        1.1       mrg {
    115       1.35  nakayama 	struct psycho_pbm *pp = pc->cookie;
    116       1.46  nakayama 	struct ofw_pci_register reg;
    117       1.22       eeh 	pcitag_t tag;
    118       1.51       cdi 	int (*valid)(void *);
    119       1.22       eeh 	int node, len;
    120       1.22       eeh #ifdef DEBUG
    121       1.22       eeh 	char name[80];
    122       1.40    martin 	memset(name, 0, sizeof(name));
    123       1.22       eeh #endif
    124        1.1       mrg 
    125       1.35  nakayama 	/*
    126       1.35  nakayama 	 * Refer to the PCI/CardBus bus node first.
    127       1.35  nakayama 	 * It returns a tag if node is present and bus is valid.
    128       1.35  nakayama 	 */
    129       1.35  nakayama 	if (0 <= b && b < 256) {
    130       1.35  nakayama 		node = (*pp->pp_busnode)[b].node;
    131       1.35  nakayama 		valid = (*pp->pp_busnode)[b].valid;
    132       1.35  nakayama 		if (node != 0 && d == 0 &&
    133       1.35  nakayama 		    (valid == NULL || (*valid)((*pp->pp_busnode)[b].arg)))
    134       1.35  nakayama 			return ofpci_make_tag(pc, node, b, d, f);
    135       1.35  nakayama 	}
    136       1.35  nakayama 
    137       1.22       eeh 	/*
    138       1.22       eeh 	 * Hunt for the node that corresponds to this device
    139       1.22       eeh 	 *
    140       1.22       eeh 	 * We could cache this info in an array in the parent
    141       1.22       eeh 	 * device... except then we have problems with devices
    142       1.22       eeh 	 * attached below pci-pci bridges, and we would need to
    143       1.22       eeh 	 * add special code to the pci-pci bridge to cache this
    144       1.22       eeh 	 * info.
    145       1.22       eeh 	 */
    146        1.1       mrg 
    147       1.22       eeh 	tag = PCITAG_CREATE(-1, b, d, f);
    148       1.22       eeh 	node = pc->rootnode;
    149       1.22       eeh 	/*
    150       1.22       eeh 	 * First make sure we're on the right bus.  If our parent
    151       1.22       eeh 	 * has a bus-range property and we're not in the range,
    152       1.22       eeh 	 * then we're obviously on the wrong bus.  So go up one
    153       1.22       eeh 	 * level.
    154       1.22       eeh 	 */
    155       1.22       eeh #ifdef DEBUG
    156       1.22       eeh 	if (sparc_pci_debug & SPDB_PROBE) {
    157       1.42        pk 		printf("curnode %x %s\n", node,
    158       1.42        pk 			prom_getpropstringA(node, "name", name, sizeof(name)));
    159       1.22       eeh 	}
    160       1.22       eeh #endif
    161       1.22       eeh #if 0
    162       1.22       eeh 	while ((OF_getprop(OF_parent(node), "bus-range", (void *)&busrange,
    163       1.22       eeh 		sizeof(busrange)) == sizeof(busrange)) &&
    164       1.22       eeh 		(b < busrange[0] || b > busrange[1])) {
    165       1.22       eeh 		/* Out of range, go up one */
    166       1.22       eeh 		node = OF_parent(node);
    167       1.22       eeh #ifdef DEBUG
    168       1.22       eeh 		if (sparc_pci_debug & SPDB_PROBE) {
    169       1.42        pk 			printf("going up to node %x %s\n", node,
    170       1.42        pk 			prom_getpropstringA(node, "name", name, sizeof(name)));
    171       1.22       eeh 		}
    172       1.22       eeh #endif
    173       1.22       eeh 	}
    174       1.22       eeh #endif
    175       1.22       eeh 	/*
    176       1.22       eeh 	 * Now traverse all peers until we find the node or we find
    177       1.22       eeh 	 * the right bridge.
    178       1.22       eeh 	 *
    179       1.22       eeh 	 * XXX We go up one and down one to make sure nobody's missed.
    180       1.22       eeh 	 * but this should not be necessary.
    181       1.22       eeh 	 */
    182       1.42        pk 	for (node = ((node)); node; node = prom_nextsibling(node)) {
    183        1.1       mrg 
    184       1.22       eeh #ifdef DEBUG
    185       1.22       eeh 		if (sparc_pci_debug & SPDB_PROBE) {
    186       1.43        pk 			printf("checking node %x %s\n", node,
    187       1.42        pk 			prom_getpropstringA(node, "name", name, sizeof(name)));
    188       1.42        pk 
    189       1.22       eeh 		}
    190       1.22       eeh #endif
    191        1.1       mrg 
    192       1.22       eeh #if 1
    193        1.1       mrg 		/*
    194       1.22       eeh 		 * Check for PCI-PCI bridges.  If the device we want is
    195       1.22       eeh 		 * in the bus-range for that bridge, work our way down.
    196        1.1       mrg 		 */
    197       1.44        pk 		while (1) {
    198       1.44        pk 			int busrange[2], *brp;
    199       1.44        pk 			len = 2;
    200       1.44        pk 			brp = busrange;
    201       1.45  nakayama 			if (prom_getprop(node, "bus-range", sizeof(*brp),
    202       1.45  nakayama 					 &len, &brp) != 0)
    203       1.44        pk 				break;
    204       1.44        pk 			if (len != 2 || b < busrange[0] || b > busrange[1])
    205       1.44        pk 				break;
    206       1.22       eeh 			/* Go down 1 level */
    207       1.42        pk 			node = prom_firstchild(node);
    208       1.22       eeh #ifdef DEBUG
    209       1.22       eeh 			if (sparc_pci_debug & SPDB_PROBE) {
    210       1.43        pk 				printf("going down to node %x %s\n", node,
    211       1.42        pk 					prom_getpropstringA(node, "name",
    212       1.42        pk 							name, sizeof(name)));
    213       1.22       eeh 			}
    214       1.22       eeh #endif
    215        1.1       mrg 		}
    216       1.44        pk #endif /*1*/
    217       1.22       eeh 		/*
    218       1.22       eeh 		 * We only really need the first `reg' property.
    219       1.22       eeh 		 *
    220       1.22       eeh 		 * For simplicity, we'll query the `reg' when we
    221       1.22       eeh 		 * need it.  Otherwise we could malloc() it, but
    222       1.22       eeh 		 * that gets more complicated.
    223       1.22       eeh 		 */
    224       1.46  nakayama 		len = prom_getproplen(node, "reg");
    225       1.46  nakayama 		if (len < sizeof(reg))
    226       1.46  nakayama 			continue;
    227       1.46  nakayama 		if (OF_getprop(node, "reg", (void *)&reg, sizeof(reg)) != len)
    228       1.44        pk 			panic("pci_probe_bus: OF_getprop len botch");
    229       1.22       eeh 
    230       1.22       eeh 		if (b != OFW_PCI_PHYS_HI_BUS(reg.phys_hi))
    231       1.22       eeh 			continue;
    232       1.22       eeh 		if (d != OFW_PCI_PHYS_HI_DEVICE(reg.phys_hi))
    233       1.22       eeh 			continue;
    234       1.22       eeh 		if (f != OFW_PCI_PHYS_HI_FUNCTION(reg.phys_hi))
    235       1.22       eeh 			continue;
    236       1.22       eeh 
    237       1.22       eeh 		/* Got a match */
    238       1.27       eeh 		tag = ofpci_make_tag(pc, node, b, d, f);
    239       1.22       eeh 
    240       1.22       eeh 		return (tag);
    241        1.1       mrg 	}
    242       1.22       eeh 	/* No device found -- return a dead tag */
    243       1.27       eeh 	return (tag);
    244       1.28   thorpej }
    245       1.28   thorpej 
    246       1.28   thorpej void
    247       1.51       cdi pci_decompose_tag(pci_chipset_tag_t pc, pcitag_t tag, int *bp, int *dp, int *fp)
    248       1.28   thorpej {
    249       1.28   thorpej 
    250       1.28   thorpej 	if (bp != NULL)
    251       1.28   thorpej 		*bp = PCITAG_BUS(tag);
    252       1.28   thorpej 	if (dp != NULL)
    253       1.28   thorpej 		*dp = PCITAG_DEV(tag);
    254       1.28   thorpej 	if (fp != NULL)
    255       1.28   thorpej 		*fp = PCITAG_FUN(tag);
    256       1.27       eeh }
    257       1.27       eeh 
    258       1.30   thorpej int
    259       1.49  drochner sparc64_pci_enumerate_bus(struct pci_softc *sc, const int *locators,
    260       1.30   thorpej     int (*match)(struct pci_attach_args *), struct pci_attach_args *pap)
    261       1.27       eeh {
    262       1.30   thorpej 	struct ofw_pci_register reg;
    263       1.30   thorpej 	pci_chipset_tag_t pc = sc->sc_pc;
    264       1.27       eeh 	pcitag_t tag;
    265       1.35  nakayama 	pcireg_t class, csr, bhlc, ic;
    266       1.30   thorpej 	int node, b, d, f, ret;
    267       1.37    martin 	int bus_frequency, lt, cl, cacheline;
    268       1.30   thorpej 	char name[30];
    269       1.32       eeh 	extern int pci_config_dump;
    270       1.30   thorpej 
    271       1.31       eeh 	if (sc->sc_bridgetag)
    272       1.31       eeh 		node = PCITAG_NODE(*sc->sc_bridgetag);
    273       1.31       eeh 	else
    274       1.31       eeh 		node = pc->rootnode;
    275       1.31       eeh 
    276       1.42        pk 	bus_frequency =
    277       1.42        pk 		prom_getpropint(node, "clock-frequency", 33000000) / 1000000;
    278       1.35  nakayama 
    279       1.37    martin 	/*
    280       1.37    martin 	 * Make sure the cache line size is at least as big as the
    281       1.37    martin 	 * ecache line and the streaming cache (64 byte).
    282       1.37    martin 	 */
    283  1.51.14.1        ad 	cacheline = max(ecache_min_line_size, 64);
    284       1.37    martin 	KASSERT((cacheline/64)*64 == cacheline &&
    285  1.51.14.1        ad 	    (cacheline/ecache_min_line_size)*ecache_min_line_size == cacheline &&
    286       1.37    martin 	    (cacheline/4)*4 == cacheline);
    287       1.37    martin 
    288       1.32       eeh 	/* Turn on parity for the bus. */
    289       1.32       eeh 	tag = ofpci_make_tag(pc, node, sc->sc_bus, 0, 0);
    290       1.32       eeh 	csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
    291       1.32       eeh 	csr |= PCI_COMMAND_PARITY_ENABLE;
    292       1.32       eeh 	pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr);
    293       1.32       eeh 
    294       1.35  nakayama 	/*
    295       1.35  nakayama 	 * Initialize the latency timer register.
    296       1.35  nakayama 	 * The value 0x40 is from Solaris.
    297       1.35  nakayama 	 */
    298       1.35  nakayama 	bhlc = pci_conf_read(pc, tag, PCI_BHLC_REG);
    299       1.35  nakayama 	bhlc &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT);
    300       1.35  nakayama 	bhlc |= 0x40 << PCI_LATTIMER_SHIFT;
    301       1.35  nakayama 	pci_conf_write(pc, tag, PCI_BHLC_REG, bhlc);
    302       1.35  nakayama 
    303       1.32       eeh 	if (pci_config_dump) pci_conf_print(pc, tag, NULL);
    304       1.32       eeh 
    305       1.42        pk 	for (node = prom_firstchild(node); node != 0 && node != -1;
    306       1.42        pk 	     node = prom_nextsibling(node)) {
    307       1.30   thorpej 		name[0] = name[29] = 0;
    308       1.42        pk 		prom_getpropstringA(node, "name", name, sizeof(name));
    309       1.27       eeh 
    310       1.30   thorpej 		if (OF_getprop(node, "class-code", &class, sizeof(class)) !=
    311       1.30   thorpej 		    sizeof(class))
    312       1.30   thorpej 			continue;
    313       1.30   thorpej 		if (OF_getprop(node, "reg", &reg, sizeof(reg)) < sizeof(reg))
    314       1.30   thorpej 			panic("pci_enumerate_bus: \"%s\" regs too small", name);
    315       1.27       eeh 
    316       1.30   thorpej 		b = OFW_PCI_PHYS_HI_BUS(reg.phys_hi);
    317       1.30   thorpej 		d = OFW_PCI_PHYS_HI_DEVICE(reg.phys_hi);
    318       1.30   thorpej 		f = OFW_PCI_PHYS_HI_FUNCTION(reg.phys_hi);
    319       1.30   thorpej 
    320       1.30   thorpej 		if (sc->sc_bus != b) {
    321       1.30   thorpej 			printf("%s: WARNING: incorrect bus # for \"%s\" "
    322       1.30   thorpej 			"(%d/%d/%d)\n", sc->sc_dev.dv_xname, name, b, d, f);
    323       1.30   thorpej 			continue;
    324       1.30   thorpej 		}
    325       1.49  drochner                 if ((locators[PCICF_DEV] != PCICF_DEV_DEFAULT) &&
    326       1.49  drochner                     (locators[PCICF_DEV] != d))
    327       1.49  drochner                         continue;
    328       1.49  drochner 		if ((locators[PCICF_FUNCTION] != PCICF_FUNCTION_DEFAULT) &&
    329       1.49  drochner 		    (locators[PCICF_FUNCTION] != f))
    330       1.49  drochner 			continue;
    331       1.27       eeh 
    332       1.30   thorpej 		tag = ofpci_make_tag(pc, node, b, d, f);
    333       1.32       eeh 
    334       1.32       eeh 		/*
    335       1.32       eeh 		 * Turn on parity and fast-back-to-back for the device.
    336       1.32       eeh 		 */
    337       1.32       eeh 		csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
    338       1.32       eeh 		if (csr & PCI_STATUS_BACKTOBACK_SUPPORT)
    339       1.32       eeh 			csr |= PCI_COMMAND_BACKTOBACK_ENABLE;
    340       1.32       eeh 		csr |= PCI_COMMAND_PARITY_ENABLE;
    341       1.32       eeh 		pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr);
    342       1.32       eeh 
    343       1.35  nakayama 		/*
    344       1.35  nakayama 		 * Initialize the latency timer register for busmaster
    345       1.35  nakayama 		 * devices to work properly.
    346       1.35  nakayama 		 *   latency-timer = min-grant * bus-freq / 4  (from FreeBSD)
    347       1.35  nakayama 		 * Also initialize the cache line size register.
    348       1.35  nakayama 		 * Solaris anytime sets this register to the value 0x10.
    349       1.35  nakayama 		 */
    350       1.35  nakayama 		bhlc = pci_conf_read(pc, tag, PCI_BHLC_REG);
    351       1.35  nakayama 		ic = pci_conf_read(pc, tag, PCI_INTERRUPT_REG);
    352       1.35  nakayama 
    353       1.35  nakayama 		lt = min(PCI_MIN_GNT(ic) * bus_frequency / 4, 255);
    354       1.35  nakayama 		if (lt == 0 || lt < PCI_LATTIMER(bhlc))
    355       1.35  nakayama 			lt = PCI_LATTIMER(bhlc);
    356       1.35  nakayama 
    357       1.35  nakayama 		cl = PCI_CACHELINE(bhlc);
    358       1.35  nakayama 		if (cl == 0)
    359       1.37    martin 			cl = cacheline;
    360       1.35  nakayama 
    361       1.35  nakayama 		bhlc &= ~((PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT) |
    362       1.35  nakayama 			  (PCI_CACHELINE_MASK << PCI_CACHELINE_SHIFT));
    363       1.35  nakayama 		bhlc |= (lt << PCI_LATTIMER_SHIFT) |
    364       1.35  nakayama 			(cl << PCI_CACHELINE_SHIFT);
    365       1.35  nakayama 		pci_conf_write(pc, tag, PCI_BHLC_REG, bhlc);
    366       1.35  nakayama 
    367       1.30   thorpej 		ret = pci_probe_device(sc, tag, match, pap);
    368       1.30   thorpej 		if (match != NULL && ret != 0)
    369       1.30   thorpej 			return (ret);
    370       1.30   thorpej 	}
    371       1.30   thorpej 	return (0);
    372        1.1       mrg }
    373        1.1       mrg 
    374        1.1       mrg /* assume we are mapped little-endian/side-effect */
    375        1.1       mrg pcireg_t
    376       1.51       cdi pci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg)
    377        1.1       mrg {
    378        1.1       mrg 	struct psycho_pbm *pp = pc->cookie;
    379        1.1       mrg 	struct psycho_softc *sc = pp->pp_sc;
    380       1.22       eeh 	pcireg_t val = (pcireg_t)~0;
    381       1.22       eeh 
    382       1.22       eeh 	DPRINTF(SPDB_CONF, ("pci_conf_read: tag %lx reg %x ",
    383       1.22       eeh 		(long)tag, reg));
    384       1.22       eeh 	if (PCITAG_NODE(tag) != -1) {
    385       1.22       eeh 		DPRINTF(SPDB_CONF, ("asi=%x addr=%qx (offset=%x) ...",
    386       1.26       eeh 			sc->sc_configaddr._asi,
    387       1.26       eeh 			(long long)(sc->sc_configaddr._ptr +
    388       1.22       eeh 				PCITAG_OFFSET(tag) + reg),
    389       1.22       eeh 			(int)PCITAG_OFFSET(tag) + reg));
    390        1.1       mrg 
    391        1.1       mrg 		val = bus_space_read_4(sc->sc_configtag, sc->sc_configaddr,
    392       1.22       eeh 			PCITAG_OFFSET(tag) + reg);
    393        1.1       mrg 	}
    394       1.22       eeh #ifdef DEBUG
    395       1.24       mrg 	else DPRINTF(SPDB_CONF, ("pci_conf_read: bogus pcitag %x\n",
    396       1.24       mrg 		(int)PCITAG_OFFSET(tag)));
    397       1.22       eeh #endif
    398        1.1       mrg 	DPRINTF(SPDB_CONF, (" returning %08x\n", (u_int)val));
    399        1.1       mrg 
    400        1.1       mrg 	return (val);
    401        1.1       mrg }
    402        1.1       mrg 
    403        1.1       mrg void
    404       1.51       cdi pci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data)
    405        1.1       mrg {
    406        1.1       mrg 	struct psycho_pbm *pp = pc->cookie;
    407        1.1       mrg 	struct psycho_softc *sc = pp->pp_sc;
    408        1.1       mrg 
    409       1.22       eeh 	DPRINTF(SPDB_CONF, ("pci_conf_write: tag %lx; reg %x; data %x; ",
    410       1.22       eeh 		(long)PCITAG_OFFSET(tag), reg, (int)data));
    411        1.1       mrg 	DPRINTF(SPDB_CONF, ("asi = %x; readaddr = %qx (offset = %x)\n",
    412       1.26       eeh 		sc->sc_configaddr._asi,
    413       1.26       eeh 		(long long)(sc->sc_configaddr._ptr + PCITAG_OFFSET(tag) + reg),
    414       1.22       eeh 		(int)PCITAG_OFFSET(tag) + reg));
    415        1.1       mrg 
    416       1.24       mrg 	/* If we don't know it, just punt it.  */
    417       1.24       mrg 	if (PCITAG_NODE(tag) == -1) {
    418       1.24       mrg 		DPRINTF(SPDB_CONF, ("pci_conf_write: bad addr"));
    419       1.24       mrg 		return;
    420       1.24       mrg 	}
    421        1.1       mrg 
    422       1.22       eeh 	bus_space_write_4(sc->sc_configtag, sc->sc_configaddr,
    423       1.22       eeh 		PCITAG_OFFSET(tag) + reg, data);
    424        1.1       mrg }
    425        1.1       mrg 
    426       1.41    petrov static int
    427       1.51       cdi pci_find_ino(struct pci_attach_args *pa, pci_intr_handle_t *ihp)
    428       1.41    petrov {
    429       1.41    petrov 	struct psycho_pbm *pp = pa->pa_pc->cookie;
    430       1.41    petrov 	struct psycho_softc *sc = pp->pp_sc;
    431       1.41    petrov 	u_int dev;
    432       1.41    petrov 	u_int ino;
    433       1.41    petrov 
    434       1.47    petrov 	DPRINTF(SPDB_INTMAP, ("pci_find_ino: pa_tag: node %x, %d:%d:%d\n",
    435       1.47    petrov 			      PCITAG_NODE(pa->pa_tag), (int)PCITAG_BUS(pa->pa_tag),
    436       1.47    petrov 			      (int)PCITAG_DEV(pa->pa_tag),
    437       1.47    petrov 			      (int)PCITAG_FUN(pa->pa_tag)));
    438       1.47    petrov 	DPRINTF(SPDB_INTMAP,
    439       1.47    petrov 		("pci_find_ino: intrswiz %d, intrpin %d, intrline %d, rawintrpin %d\n",
    440       1.47    petrov 		 pa->pa_intrswiz, pa->pa_intrpin, pa->pa_intrline, pa->pa_rawintrpin));
    441       1.47    petrov 	DPRINTF(SPDB_INTMAP, ("pci_find_ino: pa_intrtag: node %x, %d:%d:%d\n",
    442       1.47    petrov 			      PCITAG_NODE(pa->pa_intrtag),
    443       1.47    petrov 			      (int)PCITAG_BUS(pa->pa_intrtag),
    444       1.47    petrov 			      (int)PCITAG_DEV(pa->pa_intrtag),
    445       1.47    petrov 			      (int)PCITAG_FUN(pa->pa_intrtag)));
    446       1.47    petrov 
    447       1.41    petrov 	ino = *ihp;
    448       1.41    petrov 
    449       1.41    petrov 	if ((ino & ~INTMAP_PCIINT) == 0) {
    450       1.41    petrov 
    451       1.47    petrov 		if (pa->pa_intrswiz != 0 && PCITAG_NODE(pa->pa_intrtag) != 0)
    452       1.47    petrov 			dev = PCITAG_DEV(pa->pa_intrtag);
    453       1.47    petrov 		else
    454       1.47    petrov 			dev = pa->pa_device;
    455       1.47    petrov 
    456       1.41    petrov 		if (sc->sc_mode == PSYCHO_MODE_PSYCHO &&
    457       1.41    petrov 		    pp->pp_id == PSYCHO_PBM_B)
    458       1.47    petrov 			dev -= 2;
    459       1.41    petrov 		else
    460       1.47    petrov 			dev--;
    461       1.41    petrov 
    462       1.47    petrov 		DPRINTF(SPDB_INTMAP, ("pci_find_ino: mode %d, pbm %d, dev %d, ino %d\n",
    463       1.47    petrov 		       sc->sc_mode, pp->pp_id, dev, ino));
    464       1.41    petrov 
    465       1.47    petrov 		ino = (pa->pa_intrpin - 1) & INTMAP_PCIINT;
    466       1.41    petrov 
    467       1.41    petrov 		ino |= sc->sc_ign;
    468       1.41    petrov 		ino |= ((pp->pp_id == PSYCHO_PBM_B) ? INTMAP_PCIBUS : 0);
    469       1.41    petrov 		ino |= (dev << 2) & INTMAP_PCISLOT;
    470       1.41    petrov 
    471       1.41    petrov 		*ihp = ino;
    472       1.41    petrov 	}
    473       1.41    petrov 
    474       1.41    petrov 	return (0);
    475       1.41    petrov }
    476       1.41    petrov 
    477        1.1       mrg /*
    478        1.1       mrg  * interrupt mapping foo.
    479       1.20       mrg  * XXX: how does this deal with multiple interrupts for a device?
    480        1.1       mrg  */
    481        1.1       mrg int
    482       1.51       cdi pci_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *ihp)
    483        1.1       mrg {
    484       1.22       eeh 	pcitag_t tag = pa->pa_tag;
    485       1.44        pk 	int interrupts, *intp;
    486       1.22       eeh 	int len, node = PCITAG_NODE(tag);
    487       1.22       eeh 	char devtype[30];
    488       1.22       eeh 
    489       1.44        pk 	intp = &interrupts;
    490       1.44        pk 	len = 1;
    491       1.44        pk 	if (prom_getprop(node, "interrupts", sizeof(interrupts),
    492       1.44        pk 			&len, &intp) != 0 || len != 1) {
    493       1.22       eeh 		DPRINTF(SPDB_INTMAP,
    494       1.22       eeh 			("pci_intr_map: could not read interrupts\n"));
    495       1.22       eeh 		return (ENODEV);
    496       1.22       eeh 	}
    497       1.20       mrg 
    498       1.22       eeh 	if (OF_mapintr(node, &interrupts, sizeof(interrupts),
    499       1.23       eeh 		sizeof(interrupts)) < 0) {
    500       1.22       eeh 		printf("OF_mapintr failed\n");
    501       1.41    petrov 		pci_find_ino(pa, &interrupts);
    502       1.22       eeh 	}
    503       1.44        pk 
    504       1.22       eeh 	/* Try to find an IPL for this type of device. */
    505       1.44        pk 	prom_getpropstringA(node, "device_type", devtype, sizeof(devtype));
    506       1.44        pk 	for (len = 0; intrmap[len].in_class != NULL; len++)
    507       1.44        pk 		if (strcmp(intrmap[len].in_class, devtype) == 0) {
    508       1.44        pk 			interrupts |= INTLEVENCODE(intrmap[len].in_lev);
    509       1.44        pk 			break;
    510       1.44        pk 		}
    511       1.20       mrg 
    512       1.22       eeh 	/* XXXX -- we use the ino.  What if there is a valid IGN? */
    513       1.22       eeh 	*ihp = interrupts;
    514       1.22       eeh 	return (0);
    515        1.1       mrg }
    516        1.1       mrg 
    517        1.1       mrg const char *
    518       1.51       cdi pci_intr_string(pci_chipset_tag_t pc, pci_intr_handle_t ih)
    519        1.1       mrg {
    520        1.1       mrg 	static char str[16];
    521        1.1       mrg 
    522        1.1       mrg 	DPRINTF(SPDB_INTR, ("pci_intr_string: ih %u", ih));
    523       1.22       eeh 	sprintf(str, "ivec %x", ih);
    524        1.1       mrg 	DPRINTF(SPDB_INTR, ("; returning %s\n", str));
    525        1.1       mrg 
    526        1.1       mrg 	return (str);
    527        1.8       cgd }
    528        1.8       cgd 
    529        1.8       cgd const struct evcnt *
    530       1.51       cdi pci_intr_evcnt(pci_chipset_tag_t pc, pci_intr_handle_t ih)
    531        1.8       cgd {
    532        1.8       cgd 
    533        1.8       cgd 	/* XXX for now, no evcnt parent reported */
    534        1.8       cgd 	return NULL;
    535        1.1       mrg }
    536        1.1       mrg 
    537        1.1       mrg void *
    538       1.51       cdi pci_intr_establish(pci_chipset_tag_t pc, pci_intr_handle_t ih, int level,
    539       1.51       cdi 	int (*func)(void *), void *arg)
    540        1.1       mrg {
    541        1.1       mrg 	void *cookie;
    542        1.1       mrg 	struct psycho_pbm *pp = (struct psycho_pbm *)pc->cookie;
    543        1.1       mrg 
    544        1.1       mrg 	DPRINTF(SPDB_INTR, ("pci_intr_establish: ih %lu; level %d", (u_long)ih, level));
    545       1.34        pk 	cookie = bus_intr_establish(pp->pp_memt, ih, level, func, arg);
    546        1.1       mrg 
    547        1.1       mrg 	DPRINTF(SPDB_INTR, ("; returning handle %p\n", cookie));
    548        1.1       mrg 	return (cookie);
    549        1.1       mrg }
    550        1.1       mrg 
    551        1.1       mrg void
    552       1.51       cdi pci_intr_disestablish(pci_chipset_tag_t pc, void *cookie)
    553        1.1       mrg {
    554        1.1       mrg 
    555        1.1       mrg 	DPRINTF(SPDB_INTR, ("pci_intr_disestablish: cookie %p\n", cookie));
    556        1.1       mrg 
    557        1.1       mrg 	/* XXX */
    558        1.1       mrg 	panic("can't disestablish PCI interrupts yet");
    559        1.1       mrg }
    560