pci_machdep.c revision 1.72 1 1.72 macallan /* $NetBSD: pci_machdep.c,v 1.72 2011/05/11 22:26:46 macallan Exp $ */
2 1.1 mrg
3 1.1 mrg /*
4 1.5 mrg * Copyright (c) 1999, 2000 Matthew R. Green
5 1.1 mrg * All rights reserved.
6 1.1 mrg *
7 1.1 mrg * Redistribution and use in source and binary forms, with or without
8 1.1 mrg * modification, are permitted provided that the following conditions
9 1.1 mrg * are met:
10 1.1 mrg * 1. Redistributions of source code must retain the above copyright
11 1.1 mrg * notice, this list of conditions and the following disclaimer.
12 1.1 mrg * 2. Redistributions in binary form must reproduce the above copyright
13 1.1 mrg * notice, this list of conditions and the following disclaimer in the
14 1.1 mrg * documentation and/or other materials provided with the distribution.
15 1.1 mrg *
16 1.1 mrg * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 1.1 mrg * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 1.1 mrg * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 1.1 mrg * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 1.1 mrg * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 1.1 mrg * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 1.1 mrg * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23 1.1 mrg * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 1.1 mrg * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 1.1 mrg * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 1.1 mrg * SUCH DAMAGE.
27 1.1 mrg */
28 1.1 mrg
29 1.1 mrg /*
30 1.1 mrg * functions expected by the MI PCI code.
31 1.1 mrg */
32 1.38 lukem
33 1.38 lukem #include <sys/cdefs.h>
34 1.72 macallan __KERNEL_RCSID(0, "$NetBSD: pci_machdep.c,v 1.72 2011/05/11 22:26:46 macallan Exp $");
35 1.1 mrg
36 1.1 mrg #include <sys/types.h>
37 1.1 mrg #include <sys/param.h>
38 1.1 mrg #include <sys/time.h>
39 1.1 mrg #include <sys/systm.h>
40 1.1 mrg #include <sys/errno.h>
41 1.1 mrg #include <sys/device.h>
42 1.1 mrg #include <sys/malloc.h>
43 1.1 mrg
44 1.1 mrg #define _SPARC_BUS_DMA_PRIVATE
45 1.1 mrg #include <machine/bus.h>
46 1.1 mrg #include <machine/autoconf.h>
47 1.22 eeh #include <machine/openfirm.h>
48 1.1 mrg #include <dev/pci/pcivar.h>
49 1.1 mrg #include <dev/pci/pcireg.h>
50 1.1 mrg
51 1.19 mrg #include <dev/ofw/ofw_pci.h>
52 1.19 mrg
53 1.1 mrg #include <sparc64/dev/iommureg.h>
54 1.37 martin #include <sparc64/sparc64/cache.h>
55 1.39 petrov
56 1.49 drochner #include "locators.h"
57 1.49 drochner
58 1.39 petrov #ifdef DEBUG
59 1.39 petrov #define SPDB_CONF 0x01
60 1.39 petrov #define SPDB_INTR 0x04
61 1.39 petrov #define SPDB_INTMAP 0x08
62 1.39 petrov #define SPDB_PROBE 0x20
63 1.61 mrg #define SPDB_TAG 0x40
64 1.39 petrov int sparc_pci_debug = 0x0;
65 1.39 petrov #define DPRINTF(l, s) do { if (sparc_pci_debug & l) printf s; } while (0)
66 1.39 petrov #else
67 1.39 petrov #define DPRINTF(l, s)
68 1.39 petrov #endif
69 1.1 mrg
70 1.1 mrg /* this is a base to be copied */
71 1.1 mrg struct sparc_pci_chipset _sparc_pci_chipset = {
72 1.52 martin .cookie = NULL,
73 1.1 mrg };
74 1.2 mrg
75 1.30 thorpej static pcitag_t
76 1.30 thorpej ofpci_make_tag(pci_chipset_tag_t pc, int node, int b, int d, int f)
77 1.30 thorpej {
78 1.30 thorpej pcitag_t tag;
79 1.61 mrg pcireg_t reg;
80 1.30 thorpej
81 1.30 thorpej tag = PCITAG_CREATE(node, b, d, f);
82 1.30 thorpej
83 1.61 mrg DPRINTF(SPDB_TAG,
84 1.69 mrg ("%s: creating tag for node %x bus %d dev %d fn %d\n",
85 1.61 mrg __func__, node, b, d, f));
86 1.61 mrg
87 1.30 thorpej /* Enable all the different spaces for this device */
88 1.61 mrg reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
89 1.61 mrg reg |= PCI_COMMAND_MEM_ENABLE|PCI_COMMAND_MASTER_ENABLE|
90 1.61 mrg PCI_COMMAND_IO_ENABLE;
91 1.61 mrg pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, reg);
92 1.61 mrg
93 1.30 thorpej return (tag);
94 1.30 thorpej }
95 1.30 thorpej
96 1.1 mrg /*
97 1.1 mrg * functions provided to the MI code.
98 1.1 mrg */
99 1.1 mrg
100 1.1 mrg void
101 1.51 cdi pci_attach_hook(struct device *parent, struct device *self,
102 1.51 cdi struct pcibus_attach_args *pba)
103 1.1 mrg {
104 1.1 mrg }
105 1.1 mrg
106 1.1 mrg int
107 1.51 cdi pci_bus_maxdevs(pci_chipset_tag_t pc, int busno)
108 1.1 mrg {
109 1.1 mrg
110 1.1 mrg return 32;
111 1.1 mrg }
112 1.19 mrg
113 1.1 mrg pcitag_t
114 1.51 cdi pci_make_tag(pci_chipset_tag_t pc, int b, int d, int f)
115 1.1 mrg {
116 1.46 nakayama struct ofw_pci_register reg;
117 1.22 eeh pcitag_t tag;
118 1.51 cdi int (*valid)(void *);
119 1.22 eeh int node, len;
120 1.22 eeh #ifdef DEBUG
121 1.22 eeh char name[80];
122 1.40 martin memset(name, 0, sizeof(name));
123 1.22 eeh #endif
124 1.1 mrg
125 1.35 nakayama /*
126 1.35 nakayama * Refer to the PCI/CardBus bus node first.
127 1.35 nakayama * It returns a tag if node is present and bus is valid.
128 1.35 nakayama */
129 1.35 nakayama if (0 <= b && b < 256) {
130 1.62 nakayama KASSERT(pc->spc_busnode != NULL);
131 1.60 mrg node = (*pc->spc_busnode)[b].node;
132 1.60 mrg valid = (*pc->spc_busnode)[b].valid;
133 1.35 nakayama if (node != 0 && d == 0 &&
134 1.60 mrg (valid == NULL || (*valid)((*pc->spc_busnode)[b].arg)))
135 1.35 nakayama return ofpci_make_tag(pc, node, b, d, f);
136 1.35 nakayama }
137 1.35 nakayama
138 1.22 eeh /*
139 1.22 eeh * Hunt for the node that corresponds to this device
140 1.22 eeh *
141 1.22 eeh * We could cache this info in an array in the parent
142 1.22 eeh * device... except then we have problems with devices
143 1.22 eeh * attached below pci-pci bridges, and we would need to
144 1.22 eeh * add special code to the pci-pci bridge to cache this
145 1.22 eeh * info.
146 1.22 eeh */
147 1.1 mrg
148 1.22 eeh tag = PCITAG_CREATE(-1, b, d, f);
149 1.22 eeh node = pc->rootnode;
150 1.22 eeh /*
151 1.22 eeh * First make sure we're on the right bus. If our parent
152 1.22 eeh * has a bus-range property and we're not in the range,
153 1.22 eeh * then we're obviously on the wrong bus. So go up one
154 1.22 eeh * level.
155 1.22 eeh */
156 1.22 eeh #ifdef DEBUG
157 1.22 eeh if (sparc_pci_debug & SPDB_PROBE) {
158 1.42 pk printf("curnode %x %s\n", node,
159 1.42 pk prom_getpropstringA(node, "name", name, sizeof(name)));
160 1.22 eeh }
161 1.22 eeh #endif
162 1.22 eeh #if 0
163 1.22 eeh while ((OF_getprop(OF_parent(node), "bus-range", (void *)&busrange,
164 1.22 eeh sizeof(busrange)) == sizeof(busrange)) &&
165 1.22 eeh (b < busrange[0] || b > busrange[1])) {
166 1.22 eeh /* Out of range, go up one */
167 1.22 eeh node = OF_parent(node);
168 1.22 eeh #ifdef DEBUG
169 1.22 eeh if (sparc_pci_debug & SPDB_PROBE) {
170 1.42 pk printf("going up to node %x %s\n", node,
171 1.42 pk prom_getpropstringA(node, "name", name, sizeof(name)));
172 1.22 eeh }
173 1.22 eeh #endif
174 1.22 eeh }
175 1.22 eeh #endif
176 1.72 macallan node = prom_firstchild(node);
177 1.22 eeh /*
178 1.22 eeh * Now traverse all peers until we find the node or we find
179 1.22 eeh * the right bridge.
180 1.22 eeh *
181 1.22 eeh * XXX We go up one and down one to make sure nobody's missed.
182 1.22 eeh * but this should not be necessary.
183 1.22 eeh */
184 1.42 pk for (node = ((node)); node; node = prom_nextsibling(node)) {
185 1.1 mrg
186 1.22 eeh #ifdef DEBUG
187 1.22 eeh if (sparc_pci_debug & SPDB_PROBE) {
188 1.43 pk printf("checking node %x %s\n", node,
189 1.42 pk prom_getpropstringA(node, "name", name, sizeof(name)));
190 1.42 pk
191 1.22 eeh }
192 1.22 eeh #endif
193 1.1 mrg
194 1.22 eeh #if 1
195 1.1 mrg /*
196 1.22 eeh * Check for PCI-PCI bridges. If the device we want is
197 1.22 eeh * in the bus-range for that bridge, work our way down.
198 1.1 mrg */
199 1.44 pk while (1) {
200 1.44 pk int busrange[2], *brp;
201 1.44 pk len = 2;
202 1.44 pk brp = busrange;
203 1.45 nakayama if (prom_getprop(node, "bus-range", sizeof(*brp),
204 1.45 nakayama &len, &brp) != 0)
205 1.44 pk break;
206 1.44 pk if (len != 2 || b < busrange[0] || b > busrange[1])
207 1.44 pk break;
208 1.22 eeh /* Go down 1 level */
209 1.42 pk node = prom_firstchild(node);
210 1.22 eeh #ifdef DEBUG
211 1.22 eeh if (sparc_pci_debug & SPDB_PROBE) {
212 1.43 pk printf("going down to node %x %s\n", node,
213 1.42 pk prom_getpropstringA(node, "name",
214 1.42 pk name, sizeof(name)));
215 1.22 eeh }
216 1.22 eeh #endif
217 1.1 mrg }
218 1.44 pk #endif /*1*/
219 1.22 eeh /*
220 1.22 eeh * We only really need the first `reg' property.
221 1.22 eeh *
222 1.22 eeh * For simplicity, we'll query the `reg' when we
223 1.22 eeh * need it. Otherwise we could malloc() it, but
224 1.22 eeh * that gets more complicated.
225 1.22 eeh */
226 1.46 nakayama len = prom_getproplen(node, "reg");
227 1.46 nakayama if (len < sizeof(reg))
228 1.46 nakayama continue;
229 1.46 nakayama if (OF_getprop(node, "reg", (void *)®, sizeof(reg)) != len)
230 1.44 pk panic("pci_probe_bus: OF_getprop len botch");
231 1.22 eeh
232 1.22 eeh if (b != OFW_PCI_PHYS_HI_BUS(reg.phys_hi))
233 1.22 eeh continue;
234 1.22 eeh if (d != OFW_PCI_PHYS_HI_DEVICE(reg.phys_hi))
235 1.22 eeh continue;
236 1.22 eeh if (f != OFW_PCI_PHYS_HI_FUNCTION(reg.phys_hi))
237 1.22 eeh continue;
238 1.22 eeh
239 1.22 eeh /* Got a match */
240 1.27 eeh tag = ofpci_make_tag(pc, node, b, d, f);
241 1.22 eeh
242 1.22 eeh return (tag);
243 1.1 mrg }
244 1.22 eeh /* No device found -- return a dead tag */
245 1.27 eeh return (tag);
246 1.28 thorpej }
247 1.28 thorpej
248 1.28 thorpej void
249 1.51 cdi pci_decompose_tag(pci_chipset_tag_t pc, pcitag_t tag, int *bp, int *dp, int *fp)
250 1.28 thorpej {
251 1.28 thorpej
252 1.28 thorpej if (bp != NULL)
253 1.28 thorpej *bp = PCITAG_BUS(tag);
254 1.28 thorpej if (dp != NULL)
255 1.28 thorpej *dp = PCITAG_DEV(tag);
256 1.28 thorpej if (fp != NULL)
257 1.28 thorpej *fp = PCITAG_FUN(tag);
258 1.27 eeh }
259 1.27 eeh
260 1.30 thorpej int
261 1.49 drochner sparc64_pci_enumerate_bus(struct pci_softc *sc, const int *locators,
262 1.71 dyoung int (*match)(const struct pci_attach_args *), struct pci_attach_args *pap)
263 1.27 eeh {
264 1.30 thorpej struct ofw_pci_register reg;
265 1.30 thorpej pci_chipset_tag_t pc = sc->sc_pc;
266 1.27 eeh pcitag_t tag;
267 1.35 nakayama pcireg_t class, csr, bhlc, ic;
268 1.30 thorpej int node, b, d, f, ret;
269 1.37 martin int bus_frequency, lt, cl, cacheline;
270 1.30 thorpej char name[30];
271 1.69 mrg #if 0
272 1.32 eeh extern int pci_config_dump;
273 1.69 mrg #endif
274 1.30 thorpej
275 1.31 eeh if (sc->sc_bridgetag)
276 1.31 eeh node = PCITAG_NODE(*sc->sc_bridgetag);
277 1.31 eeh else
278 1.31 eeh node = pc->rootnode;
279 1.31 eeh
280 1.42 pk bus_frequency =
281 1.42 pk prom_getpropint(node, "clock-frequency", 33000000) / 1000000;
282 1.35 nakayama
283 1.37 martin /*
284 1.37 martin * Make sure the cache line size is at least as big as the
285 1.37 martin * ecache line and the streaming cache (64 byte).
286 1.37 martin */
287 1.53 mrg cacheline = max(ecache_min_line_size, 64);
288 1.37 martin KASSERT((cacheline/64)*64 == cacheline &&
289 1.53 mrg (cacheline/ecache_min_line_size)*ecache_min_line_size == cacheline &&
290 1.37 martin (cacheline/4)*4 == cacheline);
291 1.37 martin
292 1.69 mrg #if 0
293 1.69 mrg /*
294 1.69 mrg * XXX this faults on Fire PCIe controllers.
295 1.69 mrg * XXX move into the psycho and schizo driver front ends.
296 1.69 mrg */
297 1.32 eeh /* Turn on parity for the bus. */
298 1.32 eeh tag = ofpci_make_tag(pc, node, sc->sc_bus, 0, 0);
299 1.32 eeh csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
300 1.32 eeh csr |= PCI_COMMAND_PARITY_ENABLE;
301 1.32 eeh pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr);
302 1.32 eeh
303 1.35 nakayama /*
304 1.35 nakayama * Initialize the latency timer register.
305 1.35 nakayama * The value 0x40 is from Solaris.
306 1.35 nakayama */
307 1.35 nakayama bhlc = pci_conf_read(pc, tag, PCI_BHLC_REG);
308 1.35 nakayama bhlc &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT);
309 1.35 nakayama bhlc |= 0x40 << PCI_LATTIMER_SHIFT;
310 1.35 nakayama pci_conf_write(pc, tag, PCI_BHLC_REG, bhlc);
311 1.35 nakayama
312 1.69 mrg if (pci_config_dump)
313 1.69 mrg pci_conf_print(pc, tag, NULL);
314 1.69 mrg #endif
315 1.32 eeh
316 1.42 pk for (node = prom_firstchild(node); node != 0 && node != -1;
317 1.42 pk node = prom_nextsibling(node)) {
318 1.30 thorpej name[0] = name[29] = 0;
319 1.42 pk prom_getpropstringA(node, "name", name, sizeof(name));
320 1.27 eeh
321 1.30 thorpej if (OF_getprop(node, "class-code", &class, sizeof(class)) !=
322 1.30 thorpej sizeof(class))
323 1.30 thorpej continue;
324 1.30 thorpej if (OF_getprop(node, "reg", ®, sizeof(reg)) < sizeof(reg))
325 1.30 thorpej panic("pci_enumerate_bus: \"%s\" regs too small", name);
326 1.27 eeh
327 1.30 thorpej b = OFW_PCI_PHYS_HI_BUS(reg.phys_hi);
328 1.30 thorpej d = OFW_PCI_PHYS_HI_DEVICE(reg.phys_hi);
329 1.30 thorpej f = OFW_PCI_PHYS_HI_FUNCTION(reg.phys_hi);
330 1.30 thorpej
331 1.30 thorpej if (sc->sc_bus != b) {
332 1.57 cube aprint_error_dev(sc->sc_dev, "WARNING: incorrect "
333 1.57 cube "bus # for \"%s\" (%d/%d/%d)\n", name, b, d, f);
334 1.30 thorpej continue;
335 1.30 thorpej }
336 1.49 drochner if ((locators[PCICF_DEV] != PCICF_DEV_DEFAULT) &&
337 1.49 drochner (locators[PCICF_DEV] != d))
338 1.49 drochner continue;
339 1.49 drochner if ((locators[PCICF_FUNCTION] != PCICF_FUNCTION_DEFAULT) &&
340 1.49 drochner (locators[PCICF_FUNCTION] != f))
341 1.49 drochner continue;
342 1.27 eeh
343 1.30 thorpej tag = ofpci_make_tag(pc, node, b, d, f);
344 1.32 eeh
345 1.32 eeh /*
346 1.32 eeh * Turn on parity and fast-back-to-back for the device.
347 1.32 eeh */
348 1.32 eeh csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
349 1.32 eeh if (csr & PCI_STATUS_BACKTOBACK_SUPPORT)
350 1.32 eeh csr |= PCI_COMMAND_BACKTOBACK_ENABLE;
351 1.32 eeh csr |= PCI_COMMAND_PARITY_ENABLE;
352 1.32 eeh pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr);
353 1.32 eeh
354 1.35 nakayama /*
355 1.35 nakayama * Initialize the latency timer register for busmaster
356 1.35 nakayama * devices to work properly.
357 1.35 nakayama * latency-timer = min-grant * bus-freq / 4 (from FreeBSD)
358 1.35 nakayama * Also initialize the cache line size register.
359 1.35 nakayama * Solaris anytime sets this register to the value 0x10.
360 1.35 nakayama */
361 1.35 nakayama bhlc = pci_conf_read(pc, tag, PCI_BHLC_REG);
362 1.35 nakayama ic = pci_conf_read(pc, tag, PCI_INTERRUPT_REG);
363 1.35 nakayama
364 1.35 nakayama lt = min(PCI_MIN_GNT(ic) * bus_frequency / 4, 255);
365 1.35 nakayama if (lt == 0 || lt < PCI_LATTIMER(bhlc))
366 1.35 nakayama lt = PCI_LATTIMER(bhlc);
367 1.35 nakayama
368 1.35 nakayama cl = PCI_CACHELINE(bhlc);
369 1.35 nakayama if (cl == 0)
370 1.37 martin cl = cacheline;
371 1.35 nakayama
372 1.35 nakayama bhlc &= ~((PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT) |
373 1.35 nakayama (PCI_CACHELINE_MASK << PCI_CACHELINE_SHIFT));
374 1.35 nakayama bhlc |= (lt << PCI_LATTIMER_SHIFT) |
375 1.35 nakayama (cl << PCI_CACHELINE_SHIFT);
376 1.35 nakayama pci_conf_write(pc, tag, PCI_BHLC_REG, bhlc);
377 1.35 nakayama
378 1.30 thorpej ret = pci_probe_device(sc, tag, match, pap);
379 1.30 thorpej if (match != NULL && ret != 0)
380 1.30 thorpej return (ret);
381 1.30 thorpej }
382 1.30 thorpej return (0);
383 1.1 mrg }
384 1.1 mrg
385 1.1 mrg const char *
386 1.51 cdi pci_intr_string(pci_chipset_tag_t pc, pci_intr_handle_t ih)
387 1.1 mrg {
388 1.1 mrg static char str[16];
389 1.1 mrg
390 1.22 eeh sprintf(str, "ivec %x", ih);
391 1.63 mrg DPRINTF(SPDB_INTR, ("pci_intr_string: returning %s\n", str));
392 1.1 mrg
393 1.1 mrg return (str);
394 1.8 cgd }
395 1.8 cgd
396 1.8 cgd const struct evcnt *
397 1.51 cdi pci_intr_evcnt(pci_chipset_tag_t pc, pci_intr_handle_t ih)
398 1.8 cgd {
399 1.8 cgd
400 1.8 cgd /* XXX for now, no evcnt parent reported */
401 1.8 cgd return NULL;
402 1.1 mrg }
403 1.1 mrg
404 1.59 ad int
405 1.59 ad pci_intr_setattr(pci_chipset_tag_t pc, pci_intr_handle_t *ih,
406 1.59 ad int attr, uint64_t data)
407 1.59 ad {
408 1.59 ad
409 1.59 ad switch (attr) {
410 1.59 ad case PCI_INTR_MPSAFE:
411 1.59 ad return 0;
412 1.59 ad default:
413 1.59 ad return ENODEV;
414 1.59 ad }
415 1.59 ad }
416 1.59 ad
417 1.66 mrg /*
418 1.66 mrg * interrupt mapping foo.
419 1.66 mrg * XXX: how does this deal with multiple interrupts for a device?
420 1.66 mrg */
421 1.66 mrg int
422 1.71 dyoung pci_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ihp)
423 1.66 mrg {
424 1.66 mrg pcitag_t tag = pa->pa_tag;
425 1.67 jdc int interrupts[4], *intp, int_used;
426 1.66 mrg int len, node = PCITAG_NODE(tag);
427 1.66 mrg char devtype[30];
428 1.66 mrg
429 1.67 jdc intp = &interrupts[0];
430 1.67 jdc len = prom_getproplen(node, "interrupts");
431 1.67 jdc if (len > sizeof(interrupts)) {
432 1.67 jdc DPRINTF(SPDB_INTMAP,
433 1.67 jdc ("pci_intr_map: too many available interrupts\n"));
434 1.67 jdc return (ENODEV);
435 1.67 jdc }
436 1.67 jdc if (prom_getprop(node, "interrupts", len,
437 1.66 mrg &len, &intp) != 0 || len != 1) {
438 1.66 mrg DPRINTF(SPDB_INTMAP,
439 1.66 mrg ("pci_intr_map: could not read interrupts\n"));
440 1.66 mrg return (ENODEV);
441 1.66 mrg }
442 1.66 mrg
443 1.67 jdc /* XXX We pick the first interrupt, but should do better */
444 1.67 jdc int_used = interrupts[0];
445 1.67 jdc if (OF_mapintr(node, &int_used, sizeof(int_used),
446 1.67 jdc sizeof(int_used)) < 0) {
447 1.66 mrg printf("OF_mapintr failed\n");
448 1.68 mrg if (pa->pa_pc->spc_find_ino)
449 1.68 mrg pa->pa_pc->spc_find_ino(pa, &int_used);
450 1.66 mrg }
451 1.67 jdc DPRINTF(SPDB_INTMAP, ("OF_mapintr() gave %x\n", int_used));
452 1.66 mrg
453 1.66 mrg /* Try to find an IPL for this type of device. */
454 1.66 mrg prom_getpropstringA(node, "device_type", devtype, sizeof(devtype));
455 1.66 mrg for (len = 0; intrmap[len].in_class != NULL; len++)
456 1.66 mrg if (strcmp(intrmap[len].in_class, devtype) == 0) {
457 1.67 jdc int_used |= INTLEVENCODE(intrmap[len].in_lev);
458 1.67 jdc DPRINTF(SPDB_INTMAP, ("reset to %x\n", int_used));
459 1.66 mrg break;
460 1.66 mrg }
461 1.66 mrg
462 1.67 jdc *ihp = int_used;
463 1.66 mrg
464 1.66 mrg /* Call the sub-driver is necessary */
465 1.66 mrg if (pa->pa_pc->spc_intr_map)
466 1.66 mrg (*pa->pa_pc->spc_intr_map)(pa, ihp);
467 1.66 mrg
468 1.66 mrg return (0);
469 1.66 mrg }
470 1.66 mrg
471 1.1 mrg void
472 1.51 cdi pci_intr_disestablish(pci_chipset_tag_t pc, void *cookie)
473 1.1 mrg {
474 1.1 mrg
475 1.1 mrg DPRINTF(SPDB_INTR, ("pci_intr_disestablish: cookie %p\n", cookie));
476 1.1 mrg
477 1.1 mrg /* XXX */
478 1.55 martin /* panic("can't disestablish PCI interrupts yet"); */
479 1.1 mrg }
480 1.61 mrg
481 1.61 mrg int
482 1.61 mrg sparc_pci_childspace(int type)
483 1.61 mrg {
484 1.61 mrg int ss;
485 1.61 mrg
486 1.61 mrg switch (type) {
487 1.61 mrg case PCI_CONFIG_BUS_SPACE:
488 1.61 mrg ss = 0x00;
489 1.61 mrg break;
490 1.61 mrg case PCI_IO_BUS_SPACE:
491 1.61 mrg ss = 0x01;
492 1.61 mrg break;
493 1.61 mrg case PCI_MEMORY_BUS_SPACE:
494 1.61 mrg ss = 0x02;
495 1.61 mrg break;
496 1.61 mrg #if 0
497 1.61 mrg /* we don't do 64 bit memory space */
498 1.61 mrg case PCI_MEMORY64_BUS_SPACE:
499 1.61 mrg ss = 0x03;
500 1.61 mrg break;
501 1.61 mrg #endif
502 1.61 mrg default:
503 1.69 mrg panic("get_childspace: unknown bus type: %d", type);
504 1.61 mrg }
505 1.61 mrg
506 1.61 mrg return (ss);
507 1.61 mrg }
508