pci_machdep.c revision 1.10
1 /* $NetBSD: pci_machdep.c,v 1.10 2000/06/18 07:12:39 mrg Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000 Matthew R. Green 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 23 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 24 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 25 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 /* 32 * functions expected by the MI PCI code. 33 */ 34 35 #ifdef DEBUG 36 #define SPDB_CONF 0x01 37 #define SPDB_INTR 0x04 38 #define SPDB_INTMAP 0x08 39 #define SPDB_INTFIX 0x10 40 int sparc_pci_debug = 0x0; 41 #define DPRINTF(l, s) do { if (sparc_pci_debug & l) printf s; } while (0) 42 #else 43 #define DPRINTF(l, s) 44 #endif 45 46 #include <sys/types.h> 47 #include <sys/param.h> 48 #include <sys/time.h> 49 #include <sys/systm.h> 50 #include <sys/errno.h> 51 #include <sys/device.h> 52 #include <sys/malloc.h> 53 54 #include <vm/vm.h> 55 #include <vm/vm_kern.h> 56 57 #define _SPARC_BUS_DMA_PRIVATE 58 #include <machine/bus.h> 59 #include <machine/autoconf.h> 60 61 #include <dev/pci/pcivar.h> 62 #include <dev/pci/pcireg.h> 63 64 #include <sparc64/dev/iommureg.h> 65 #include <sparc64/dev/iommuvar.h> 66 #include <sparc64/dev/psychoreg.h> 67 #include <sparc64/dev/psychovar.h> 68 69 /* this is a base to be copied */ 70 struct sparc_pci_chipset _sparc_pci_chipset = { 71 NULL, 72 }; 73 74 /* 75 * functions provided to the MI code. 76 */ 77 78 void 79 pci_attach_hook(parent, self, pba) 80 struct device *parent; 81 struct device *self; 82 struct pcibus_attach_args *pba; 83 { 84 pci_chipset_tag_t pc = pba->pba_pc; 85 struct psycho_pbm *pp = pc->cookie; 86 struct psycho_registers *pr; 87 pcitag_t tag; 88 char *name, *devtype; 89 u_int32_t hi, mid, lo, intr; 90 u_int32_t dev, fn, bus; 91 int node, i, n, *ip, *ap; 92 93 DPRINTF((SPDB_INTFIX|SPDB_INTMAP), ("\npci_attach_hook:")); 94 95 /* 96 * ok, here we look in the OFW for each PCI device and fix it's 97 * "interrupt line" register to be useful. 98 */ 99 100 for (node = firstchild(pc->node); node; node = nextsibling(node)) { 101 pr = NULL; 102 ip = ap = NULL; 103 104 /* 105 * ok, for each child we get the "interrupts" property, 106 * which contains a value to match against later. 107 * XXX deal with multiple "interrupts" values XXX. 108 * then we get the "assigned-addresses" property which 109 * contains, in the first entry, the PCI bus, device and 110 * function associated with this node, which we use to 111 * generate a pcitag_t to use pci_conf_read() and 112 * pci_conf_write(). next, we get the 'reg" property 113 * which is structured like the following: 114 * u_int32_t phys_hi; 115 * u_int32_t phys_mid; 116 * u_int32_t phys_lo; 117 * u_int32_t size_hi; 118 * u_int32_t size_lo; 119 * we mask these values with the "interrupt-map-mask" 120 * property of our parent and them compare with each 121 * entry in the "interrupt-map" property (also of our 122 * parent) which is structred like the following: 123 * u_int32_t phys_hi; 124 * u_int32_t phys_mid; 125 * u_int32_t phys_lo; 126 * u_int32_t intr; 127 * int32_t child_node; 128 * u_int32_t child_intr; 129 * if there is an exact match with phys_hi, phys_mid, 130 * phys_lo and the interrupt, we have a match and we 131 * know that this interrupt's value is really the 132 * child_intr of the interrupt map entry. we put this 133 * into the PCI interrupt line register so that when 134 * the driver for this node wants to attach, we know 135 * it's INO already. 136 */ 137 138 name = getpropstring(node, "name"); 139 DPRINTF((SPDB_INTFIX|SPDB_INTMAP), ("\n\tnode %x name `%s'", node, name)); 140 devtype = getpropstring(node, "device_type"); 141 DPRINTF((SPDB_INTFIX|SPDB_INTMAP), (" devtype `%s':", devtype)); 142 143 /* ignore PCI bridges, we'll get them later */ 144 if (strcmp(devtype, "pci") == 0) 145 continue; 146 147 /* if there isn't any "interrupts" then we don't care to fix it */ 148 ip = NULL; 149 if (getprop(node, "interrupts", sizeof(int), &n, (void **)&ip)) 150 continue; 151 DPRINTF(SPDB_INTFIX, (" got interrupts")); 152 153 /* and if there isn't an "assigned-addresses" we can't find b/d/f */ 154 if (getprop(node, "assigned-addresses", sizeof(int), &n, 155 (void **)&ap)) 156 goto clean1; 157 DPRINTF(SPDB_INTFIX, (" got assigned-addresses")); 158 159 /* ok, and now the "reg" property, so we know what we're talking about. */ 160 if (getprop(node, "reg", sizeof(*pr), &n, 161 (void **)&pr)) 162 goto clean2; 163 DPRINTF(SPDB_INTFIX, (" got reg")); 164 165 bus = TAG2BUS(ap[0]); 166 dev = TAG2DEV(ap[0]); 167 fn = TAG2FN(ap[0]); 168 169 DPRINTF(SPDB_INTFIX, ("; bus %u dev %u fn %u", bus, dev, fn)); 170 171 tag = pci_make_tag(pc, bus, dev, fn); 172 173 DPRINTF(SPDB_INTFIX, ("; tag %08x\n\t; reg: hi %x mid %x lo %x intr %x", tag, pr->phys_hi, pr->phys_mid, pr->phys_lo, *ip)); 174 DPRINTF(SPDB_INTFIX, ("\n\t; intmapmask: hi %x mid %x lo %x intr %x", pp->pp_intmapmask.phys_hi, pp->pp_intmapmask.phys_mid, 175 pp->pp_intmapmask.phys_lo, pp->pp_intmapmask.intr)); 176 177 hi = pr->phys_hi & pp->pp_intmapmask.phys_hi; 178 mid = pr->phys_mid & pp->pp_intmapmask.phys_mid; 179 lo = pr->phys_lo & pp->pp_intmapmask.phys_lo; 180 intr = *ip & pp->pp_intmapmask.intr; 181 182 DPRINTF(SPDB_INTFIX, ("\n\t; after: hi %x mid %x lo %x intr %x", hi, mid, lo, intr)); 183 184 for (i = 0; i < pp->pp_nintmap; i++) { 185 DPRINTF(SPDB_INTFIX, ("\n\t\tmatching for: hi %x mid %x lo %x intr %x", pp->pp_intmap[i].phys_hi, pp->pp_intmap[i].phys_mid, 186 pp->pp_intmap[i].phys_lo, pp->pp_intmap[i].intr)); 187 188 if (pp->pp_intmap[i].phys_hi != hi || 189 pp->pp_intmap[i].phys_mid != mid || 190 pp->pp_intmap[i].phys_lo != lo || 191 pp->pp_intmap[i].intr != intr) 192 continue; 193 DPRINTF(SPDB_INTFIX, ("... BINGO! ...")); 194 195 /* 196 * OK! we found match. pull out the old interrupt 197 * register, patch in the new value, and put it back. 198 */ 199 intr = pci_conf_read(pc, tag, PCI_INTERRUPT_REG); 200 DPRINTF(SPDB_INTFIX, ("\n\t ; read %x from intreg", intr)); 201 202 intr = (intr & ~PCI_INTERRUPT_LINE_MASK) | 203 (pp->pp_intmap[i].child_intr & PCI_INTERRUPT_LINE_MASK); 204 DPRINTF((SPDB_INTFIX|SPDB_INTMAP), ("\n\t ; gonna write %x to intreg", intr)); 205 pci_conf_write(pc, tag, PCI_INTERRUPT_REG, intr); 206 DPRINTF((SPDB_INTFIX|SPDB_INTMAP), ("\n\t ; reread %x from intreg", intr)); 207 break; 208 } 209 210 /* enable mem & dma if not already */ 211 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, 212 PCI_COMMAND_MEM_ENABLE|PCI_COMMAND_MASTER_ENABLE); 213 214 215 /* clean up */ 216 if (pr) 217 free(pr, M_DEVBUF); 218 clean2: 219 if (ap) 220 free(ap, M_DEVBUF); 221 clean1: 222 if (ip) 223 free(ip, M_DEVBUF); 224 } 225 DPRINTF(SPDB_INTFIX, ("\n")); 226 } 227 228 int 229 pci_bus_maxdevs(pc, busno) 230 pci_chipset_tag_t pc; 231 int busno; 232 { 233 234 return 32; 235 } 236 237 pcitag_t 238 pci_make_tag(pc, b, d, f) 239 pci_chipset_tag_t pc; 240 int b; 241 int d; 242 int f; 243 { 244 245 /* make me a useable offset */ 246 return (b << 16) | (d << 11) | (f << 8); 247 } 248 249 static int confaddr_ok __P((struct psycho_softc *, pcitag_t)); 250 251 /* 252 * this function is a large hack. ideally, we should also trap accesses 253 * properly, but we have to avoid letting anything read various parts 254 * of bus 0 dev 0 fn 0 space or the machine may hang. so, even if we 255 * do properly implement PCI config access trap handling, this function 256 * should remain in place Just In Case. 257 */ 258 static int 259 confaddr_ok(sc, tag) 260 struct psycho_softc *sc; 261 pcitag_t tag; 262 { 263 int bus, dev, fn; 264 265 bus = TAG2BUS(tag); 266 dev = TAG2DEV(tag); 267 fn = TAG2FN(tag); 268 269 if (sc->sc_mode == PSYCHO_MODE_SABRE) { 270 /* 271 * bus 0 is only ok for dev 0 fn 0, dev 1 fn 0 and dev fn 1. 272 */ 273 if (bus == 0 && 274 ((dev == 0 && fn > 0) || 275 (dev == 1 && fn > 1) || 276 (dev > 1))) { 277 DPRINTF(SPDB_CONF, (" confaddr_ok: rejecting bus %d dev %d fn %d -", bus, dev, fn)); 278 return (0); 279 } 280 } else if (sc->sc_mode == PSYCHO_MODE_PSYCHO_A || 281 sc->sc_mode == PSYCHO_MODE_PSYCHO_B) { 282 /* 283 * make sure we are reading our own bus 284 */ 285 /* XXX??? */ 286 panic("confaddr_ok: can't do SUNW,psycho yet"); 287 } 288 return (1); 289 } 290 291 /* assume we are mapped little-endian/side-effect */ 292 pcireg_t 293 pci_conf_read(pc, tag, reg) 294 pci_chipset_tag_t pc; 295 pcitag_t tag; 296 int reg; 297 { 298 struct psycho_pbm *pp = pc->cookie; 299 struct psycho_softc *sc = pp->pp_sc; 300 pcireg_t val; 301 302 DPRINTF(SPDB_CONF, ("pci_conf_read: tag %lx; reg %x; ", (long)tag, reg)); 303 DPRINTF(SPDB_CONF, ("asi = %x; readaddr = %qx (offset = %x) ...", 304 bus_type_asi[sc->sc_configtag->type], 305 sc->sc_configaddr + tag + reg, (int)tag + reg)); 306 307 if (confaddr_ok(sc, tag) == 0) { 308 val = (pcireg_t)~0; 309 } else { 310 membar_sync(); 311 val = bus_space_read_4(sc->sc_configtag, sc->sc_configaddr, 312 tag + reg); 313 membar_sync(); 314 } 315 DPRINTF(SPDB_CONF, (" returning %08x\n", (u_int)val)); 316 317 return (val); 318 } 319 320 void 321 pci_conf_write(pc, tag, reg, data) 322 pci_chipset_tag_t pc; 323 pcitag_t tag; 324 int reg; 325 pcireg_t data; 326 { 327 struct psycho_pbm *pp = pc->cookie; 328 struct psycho_softc *sc = pp->pp_sc; 329 330 DPRINTF(SPDB_CONF, ("pci_conf_write: tag %ld; reg %d; data %d; ", (long)tag, reg, (int)data)); 331 DPRINTF(SPDB_CONF, ("asi = %x; readaddr = %qx (offset = %x)\n", 332 bus_type_asi[sc->sc_configtag->type], 333 sc->sc_configaddr + tag + reg, (int)tag + reg)); 334 335 if (confaddr_ok(sc, tag) == 0) 336 panic("pci_conf_write: bad addr"); 337 338 membar_sync(); 339 bus_space_write_4(sc->sc_configtag, sc->sc_configaddr, tag + reg, data); 340 membar_sync(); 341 } 342 343 /* 344 * interrupt mapping foo. 345 */ 346 int 347 pci_intr_map(pc, tag, pin, line, ihp) 348 pci_chipset_tag_t pc; 349 pcitag_t tag; 350 int pin; 351 int line; 352 pci_intr_handle_t *ihp; 353 { 354 int rv; 355 356 /* 357 * XXX 358 * UltraSPARC IIi PCI does not use PCI_INTERRUPT_REG, but we have 359 * used this space for our own purposes... 360 */ 361 DPRINTF(SPDB_INTR, ("pci_intr_map: tag %lx; pin %d; line %d", 362 (long)tag, pin, line)); 363 #if 1 364 if (line == 255) { 365 *ihp = -1; 366 rv = 1; 367 goto out; 368 } 369 #endif 370 if (pin > 4) 371 panic("pci_intr_map: pin > 4"); 372 373 rv = psycho_intr_map(tag, pin, line, ihp); 374 375 out: 376 DPRINTF(SPDB_INTR, ("; handle = %d; returning %d\n", (int)*ihp, rv)); 377 return (rv); 378 } 379 380 const char * 381 pci_intr_string(pc, ih) 382 pci_chipset_tag_t pc; 383 pci_intr_handle_t ih; 384 { 385 static char str[16]; 386 387 DPRINTF(SPDB_INTR, ("pci_intr_string: ih %u", ih)); 388 if (ih < 0 || ih > 0x32) { 389 printf("\n"); /* i'm *so* beautiful */ 390 panic("pci_intr_string: bogus handle\n"); 391 } 392 sprintf(str, "vector %u", ih); 393 DPRINTF(SPDB_INTR, ("; returning %s\n", str)); 394 395 return (str); 396 } 397 398 const struct evcnt * 399 pci_intr_evcnt(pc, ih) 400 pci_chipset_tag_t pc; 401 pci_intr_handle_t ih; 402 { 403 404 /* XXX for now, no evcnt parent reported */ 405 return NULL; 406 } 407 408 void * 409 pci_intr_establish(pc, ih, level, func, arg) 410 pci_chipset_tag_t pc; 411 pci_intr_handle_t ih; 412 int level; 413 int (*func) __P((void *)); 414 void *arg; 415 { 416 void *cookie; 417 struct psycho_pbm *pp = (struct psycho_pbm *)pc->cookie; 418 419 DPRINTF(SPDB_INTR, ("pci_intr_establish: ih %lu; level %d", (u_long)ih, level)); 420 cookie = bus_intr_establish(pp->pp_memt, ih, 0, func, arg); 421 422 DPRINTF(SPDB_INTR, ("; returning handle %p\n", cookie)); 423 return (cookie); 424 } 425 426 void 427 pci_intr_disestablish(pc, cookie) 428 pci_chipset_tag_t pc; 429 void *cookie; 430 { 431 432 DPRINTF(SPDB_INTR, ("pci_intr_disestablish: cookie %p\n", cookie)); 433 434 /* XXX */ 435 panic("can't disestablish PCI interrupts yet"); 436 } 437
Indexes created Wed Oct 15 07:09:58 GMT 2025