pci_machdep.c revision 1.12
1 /* $NetBSD: pci_machdep.c,v 1.12 2000/06/29 07:37:55 mrg Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000 Matthew R. Green 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 23 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 24 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 25 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 /* 32 * functions expected by the MI PCI code. 33 */ 34 35 #ifdef DEBUG 36 #define SPDB_CONF 0x01 37 #define SPDB_INTR 0x04 38 #define SPDB_INTMAP 0x08 39 #define SPDB_INTFIX 0x10 40 int sparc_pci_debug = 0x0; 41 #define DPRINTF(l, s) do { if (sparc_pci_debug & l) printf s; } while (0) 42 #else 43 #define DPRINTF(l, s) 44 #endif 45 46 #include <sys/types.h> 47 #include <sys/param.h> 48 #include <sys/time.h> 49 #include <sys/systm.h> 50 #include <sys/errno.h> 51 #include <sys/device.h> 52 #include <sys/malloc.h> 53 54 #define _SPARC_BUS_DMA_PRIVATE 55 #include <machine/bus.h> 56 #include <machine/autoconf.h> 57 58 #include <dev/pci/pcivar.h> 59 #include <dev/pci/pcireg.h> 60 61 #include <sparc64/dev/iommureg.h> 62 #include <sparc64/dev/iommuvar.h> 63 #include <sparc64/dev/psychoreg.h> 64 #include <sparc64/dev/psychovar.h> 65 66 /* this is a base to be copied */ 67 struct sparc_pci_chipset _sparc_pci_chipset = { 68 NULL, 69 }; 70 71 /* 72 * functions provided to the MI code. 73 */ 74 75 void 76 pci_attach_hook(parent, self, pba) 77 struct device *parent; 78 struct device *self; 79 struct pcibus_attach_args *pba; 80 { 81 pci_chipset_tag_t pc = pba->pba_pc; 82 struct psycho_pbm *pp = pc->cookie; 83 struct psycho_registers *pr; 84 pcitag_t tag; 85 char *name, *devtype; 86 u_int32_t hi, mid, lo, intr; 87 u_int32_t dev, fn, bus; 88 int node, i, n, *ip, *ap; 89 90 DPRINTF((SPDB_INTFIX|SPDB_INTMAP), ("\npci_attach_hook:")); 91 92 /* 93 * ok, here we look in the OFW for each PCI device and fix it's 94 * "interrupt line" register to be useful. 95 */ 96 97 for (node = firstchild(pc->node); node; node = nextsibling(node)) { 98 pr = NULL; 99 ip = ap = NULL; 100 101 /* 102 * ok, for each child we get the "interrupts" property, 103 * which contains a value to match against later. 104 * XXX deal with multiple "interrupts" values XXX. 105 * then we get the "assigned-addresses" property which 106 * contains, in the first entry, the PCI bus, device and 107 * function associated with this node, which we use to 108 * generate a pcitag_t to use pci_conf_read() and 109 * pci_conf_write(). next, we get the 'reg" property 110 * which is structured like the following: 111 * u_int32_t phys_hi; 112 * u_int32_t phys_mid; 113 * u_int32_t phys_lo; 114 * u_int32_t size_hi; 115 * u_int32_t size_lo; 116 * we mask these values with the "interrupt-map-mask" 117 * property of our parent and them compare with each 118 * entry in the "interrupt-map" property (also of our 119 * parent) which is structred like the following: 120 * u_int32_t phys_hi; 121 * u_int32_t phys_mid; 122 * u_int32_t phys_lo; 123 * u_int32_t intr; 124 * int32_t child_node; 125 * u_int32_t child_intr; 126 * if there is an exact match with phys_hi, phys_mid, 127 * phys_lo and the interrupt, we have a match and we 128 * know that this interrupt's value is really the 129 * child_intr of the interrupt map entry. we put this 130 * into the PCI interrupt line register so that when 131 * the driver for this node wants to attach, we know 132 * it's INO already. 133 */ 134 135 name = getpropstring(node, "name"); 136 DPRINTF((SPDB_INTFIX|SPDB_INTMAP), ("\n\tnode %x name `%s'", node, name)); 137 devtype = getpropstring(node, "device_type"); 138 DPRINTF((SPDB_INTFIX|SPDB_INTMAP), (" devtype `%s':", devtype)); 139 140 /* ignore PCI bridges, we'll get them later */ 141 if (strcmp(devtype, "pci") == 0) 142 continue; 143 144 /* if there isn't any "interrupts" then we don't care to fix it */ 145 ip = NULL; 146 if (getprop(node, "interrupts", sizeof(int), &n, (void **)&ip)) 147 continue; 148 DPRINTF(SPDB_INTFIX, (" got interrupts")); 149 150 /* and if there isn't an "assigned-addresses" we can't find b/d/f */ 151 if (getprop(node, "assigned-addresses", sizeof(int), &n, 152 (void **)&ap)) 153 goto clean1; 154 DPRINTF(SPDB_INTFIX, (" got assigned-addresses")); 155 156 /* ok, and now the "reg" property, so we know what we're talking about. */ 157 if (getprop(node, "reg", sizeof(*pr), &n, 158 (void **)&pr)) 159 goto clean2; 160 DPRINTF(SPDB_INTFIX, (" got reg")); 161 162 bus = TAG2BUS(ap[0]); 163 dev = TAG2DEV(ap[0]); 164 fn = TAG2FN(ap[0]); 165 166 DPRINTF(SPDB_INTFIX, ("; bus %u dev %u fn %u", bus, dev, fn)); 167 168 tag = pci_make_tag(pc, bus, dev, fn); 169 170 DPRINTF(SPDB_INTFIX, ("; tag %08x\n\t; reg: hi %x mid %x lo %x intr %x", tag, pr->phys_hi, pr->phys_mid, pr->phys_lo, *ip)); 171 DPRINTF(SPDB_INTFIX, ("\n\t; intmapmask: hi %x mid %x lo %x intr %x", pp->pp_intmapmask.phys_hi, pp->pp_intmapmask.phys_mid, 172 pp->pp_intmapmask.phys_lo, pp->pp_intmapmask.intr)); 173 174 hi = pr->phys_hi & pp->pp_intmapmask.phys_hi; 175 mid = pr->phys_mid & pp->pp_intmapmask.phys_mid; 176 lo = pr->phys_lo & pp->pp_intmapmask.phys_lo; 177 intr = *ip & pp->pp_intmapmask.intr; 178 179 DPRINTF(SPDB_INTFIX, ("\n\t; after: hi %x mid %x lo %x intr %x", hi, mid, lo, intr)); 180 181 for (i = 0; i < pp->pp_nintmap; i++) { 182 DPRINTF(SPDB_INTFIX, ("\n\t\tmatching for: hi %x mid %x lo %x intr %x", pp->pp_intmap[i].phys_hi, pp->pp_intmap[i].phys_mid, 183 pp->pp_intmap[i].phys_lo, pp->pp_intmap[i].intr)); 184 185 if (pp->pp_intmap[i].phys_hi != hi || 186 pp->pp_intmap[i].phys_mid != mid || 187 pp->pp_intmap[i].phys_lo != lo || 188 pp->pp_intmap[i].intr != intr) 189 continue; 190 DPRINTF(SPDB_INTFIX, ("... BINGO! ...")); 191 192 /* 193 * OK! we found match. pull out the old interrupt 194 * register, patch in the new value, and put it back. 195 */ 196 intr = pci_conf_read(pc, tag, PCI_INTERRUPT_REG); 197 DPRINTF(SPDB_INTFIX, ("\n\t ; read %x from intreg", intr)); 198 199 intr = (intr & ~PCI_INTERRUPT_LINE_MASK) | 200 (pp->pp_intmap[i].child_intr & PCI_INTERRUPT_LINE_MASK); 201 DPRINTF((SPDB_INTFIX|SPDB_INTMAP), ("\n\t ; gonna write %x to intreg", intr)); 202 pci_conf_write(pc, tag, PCI_INTERRUPT_REG, intr); 203 DPRINTF((SPDB_INTFIX|SPDB_INTMAP), ("\n\t ; reread %x from intreg", intr)); 204 break; 205 } 206 207 /* enable mem & dma if not already */ 208 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, 209 PCI_COMMAND_MEM_ENABLE|PCI_COMMAND_MASTER_ENABLE); 210 211 212 /* clean up */ 213 if (pr) 214 free(pr, M_DEVBUF); 215 clean2: 216 if (ap) 217 free(ap, M_DEVBUF); 218 clean1: 219 if (ip) 220 free(ip, M_DEVBUF); 221 } 222 DPRINTF(SPDB_INTFIX, ("\n")); 223 } 224 225 int 226 pci_bus_maxdevs(pc, busno) 227 pci_chipset_tag_t pc; 228 int busno; 229 { 230 231 return 32; 232 } 233 234 pcitag_t 235 pci_make_tag(pc, b, d, f) 236 pci_chipset_tag_t pc; 237 int b; 238 int d; 239 int f; 240 { 241 242 /* make me a useable offset */ 243 return (b << 16) | (d << 11) | (f << 8); 244 } 245 246 static int confaddr_ok __P((struct psycho_softc *, pcitag_t)); 247 248 /* 249 * this function is a large hack. ideally, we should also trap accesses 250 * properly, but we have to avoid letting anything read various parts 251 * of bus 0 dev 0 fn 0 space or the machine may hang. so, even if we 252 * do properly implement PCI config access trap handling, this function 253 * should remain in place Just In Case. 254 */ 255 static int 256 confaddr_ok(sc, tag) 257 struct psycho_softc *sc; 258 pcitag_t tag; 259 { 260 int bus, dev, fn; 261 262 bus = TAG2BUS(tag); 263 dev = TAG2DEV(tag); 264 fn = TAG2FN(tag); 265 266 if (sc->sc_mode == PSYCHO_MODE_SABRE) { 267 /* 268 * bus 0 is only ok for dev 0 fn 0, dev 1 fn 0 and dev fn 1. 269 */ 270 if (bus == 0 && 271 ((dev == 0 && fn > 0) || 272 (dev == 1 && fn > 1) || 273 (dev > 1))) { 274 DPRINTF(SPDB_CONF, (" confaddr_ok: rejecting bus %d dev %d fn %d -", bus, dev, fn)); 275 return (0); 276 } 277 } else if (sc->sc_mode == PSYCHO_MODE_PSYCHO_A || 278 sc->sc_mode == PSYCHO_MODE_PSYCHO_B) { 279 /* 280 * make sure we are reading our own bus 281 */ 282 /* XXX??? */ 283 panic("confaddr_ok: can't do SUNW,psycho yet"); 284 } 285 return (1); 286 } 287 288 /* assume we are mapped little-endian/side-effect */ 289 pcireg_t 290 pci_conf_read(pc, tag, reg) 291 pci_chipset_tag_t pc; 292 pcitag_t tag; 293 int reg; 294 { 295 struct psycho_pbm *pp = pc->cookie; 296 struct psycho_softc *sc = pp->pp_sc; 297 pcireg_t val; 298 299 DPRINTF(SPDB_CONF, ("pci_conf_read: tag %lx; reg %x; ", (long)tag, reg)); 300 DPRINTF(SPDB_CONF, ("asi = %x; readaddr = %qx (offset = %x) ...", 301 bus_type_asi[sc->sc_configtag->type], 302 sc->sc_configaddr + tag + reg, (int)tag + reg)); 303 304 if (confaddr_ok(sc, tag) == 0) { 305 val = (pcireg_t)~0; 306 } else { 307 membar_sync(); 308 val = bus_space_read_4(sc->sc_configtag, sc->sc_configaddr, 309 tag + reg); 310 membar_sync(); 311 } 312 DPRINTF(SPDB_CONF, (" returning %08x\n", (u_int)val)); 313 314 return (val); 315 } 316 317 void 318 pci_conf_write(pc, tag, reg, data) 319 pci_chipset_tag_t pc; 320 pcitag_t tag; 321 int reg; 322 pcireg_t data; 323 { 324 struct psycho_pbm *pp = pc->cookie; 325 struct psycho_softc *sc = pp->pp_sc; 326 327 DPRINTF(SPDB_CONF, ("pci_conf_write: tag %ld; reg %d; data %d; ", (long)tag, reg, (int)data)); 328 DPRINTF(SPDB_CONF, ("asi = %x; readaddr = %qx (offset = %x)\n", 329 bus_type_asi[sc->sc_configtag->type], 330 sc->sc_configaddr + tag + reg, (int)tag + reg)); 331 332 if (confaddr_ok(sc, tag) == 0) 333 panic("pci_conf_write: bad addr"); 334 335 membar_sync(); 336 bus_space_write_4(sc->sc_configtag, sc->sc_configaddr, tag + reg, data); 337 membar_sync(); 338 } 339 340 /* 341 * interrupt mapping foo. 342 */ 343 int 344 pci_intr_map(pc, tag, pin, line, ihp) 345 pci_chipset_tag_t pc; 346 pcitag_t tag; 347 int pin; 348 int line; 349 pci_intr_handle_t *ihp; 350 { 351 int rv; 352 353 /* 354 * XXX 355 * UltraSPARC IIi PCI does not use PCI_INTERRUPT_REG, but we have 356 * used this space for our own purposes... 357 */ 358 DPRINTF(SPDB_INTR, ("pci_intr_map: tag %lx; pin %d; line %d", 359 (long)tag, pin, line)); 360 #if 1 361 if (line == 255) { 362 *ihp = -1; 363 rv = 1; 364 goto out; 365 } 366 #endif 367 if (pin > 4) 368 panic("pci_intr_map: pin > 4"); 369 370 rv = psycho_intr_map(tag, pin, line, ihp); 371 372 out: 373 DPRINTF(SPDB_INTR, ("; handle = %d; returning %d\n", (int)*ihp, rv)); 374 return (rv); 375 } 376 377 const char * 378 pci_intr_string(pc, ih) 379 pci_chipset_tag_t pc; 380 pci_intr_handle_t ih; 381 { 382 static char str[16]; 383 384 DPRINTF(SPDB_INTR, ("pci_intr_string: ih %u", ih)); 385 if (ih < 0 || ih > 0x32) { 386 printf("\n"); /* i'm *so* beautiful */ 387 panic("pci_intr_string: bogus handle\n"); 388 } 389 sprintf(str, "vector %u", ih); 390 DPRINTF(SPDB_INTR, ("; returning %s\n", str)); 391 392 return (str); 393 } 394 395 const struct evcnt * 396 pci_intr_evcnt(pc, ih) 397 pci_chipset_tag_t pc; 398 pci_intr_handle_t ih; 399 { 400 401 /* XXX for now, no evcnt parent reported */ 402 return NULL; 403 } 404 405 void * 406 pci_intr_establish(pc, ih, level, func, arg) 407 pci_chipset_tag_t pc; 408 pci_intr_handle_t ih; 409 int level; 410 int (*func) __P((void *)); 411 void *arg; 412 { 413 void *cookie; 414 struct psycho_pbm *pp = (struct psycho_pbm *)pc->cookie; 415 416 DPRINTF(SPDB_INTR, ("pci_intr_establish: ih %lu; level %d", (u_long)ih, level)); 417 cookie = bus_intr_establish(pp->pp_memt, ih, 0, func, arg); 418 419 DPRINTF(SPDB_INTR, ("; returning handle %p\n", cookie)); 420 return (cookie); 421 } 422 423 void 424 pci_intr_disestablish(pc, cookie) 425 pci_chipset_tag_t pc; 426 void *cookie; 427 { 428 429 DPRINTF(SPDB_INTR, ("pci_intr_disestablish: cookie %p\n", cookie)); 430 431 /* XXX */ 432 panic("can't disestablish PCI interrupts yet"); 433 } 434
Indexes created Fri Oct 17 09:09:57 GMT 2025