pci_machdep.c revision 1.21.2.6
1 /* $NetBSD: pci_machdep.c,v 1.21.2.6 2002/10/10 18:36:33 jdolecek Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000 Matthew R. Green 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 23 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 24 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 25 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 /* 32 * functions expected by the MI PCI code. 33 */ 34 35 #ifdef DEBUG 36 #define SPDB_CONF 0x01 37 #define SPDB_INTR 0x04 38 #define SPDB_INTMAP 0x08 39 #define SPDB_INTFIX 0x10 40 #define SPDB_PROBE 0x20 41 int sparc_pci_debug = 0x0; 42 #define DPRINTF(l, s) do { if (sparc_pci_debug & l) printf s; } while (0) 43 #else 44 #define DPRINTF(l, s) 45 #endif 46 47 #include <sys/types.h> 48 #include <sys/param.h> 49 #include <sys/time.h> 50 #include <sys/systm.h> 51 #include <sys/errno.h> 52 #include <sys/device.h> 53 #include <sys/malloc.h> 54 55 #define _SPARC_BUS_DMA_PRIVATE 56 #include <machine/bus.h> 57 #include <machine/autoconf.h> 58 #include <machine/openfirm.h> 59 60 #include <dev/pci/pcivar.h> 61 #include <dev/pci/pcireg.h> 62 63 #include <dev/ofw/ofw_pci.h> 64 65 #include <sparc64/dev/iommureg.h> 66 #include <sparc64/dev/iommuvar.h> 67 #include <sparc64/dev/psychoreg.h> 68 #include <sparc64/dev/psychovar.h> 69 70 /* this is a base to be copied */ 71 struct sparc_pci_chipset _sparc_pci_chipset = { 72 NULL, 73 }; 74 75 static pcitag_t 76 ofpci_make_tag(pci_chipset_tag_t pc, int node, int b, int d, int f) 77 { 78 pcitag_t tag; 79 80 tag = PCITAG_CREATE(node, b, d, f); 81 82 /* Enable all the different spaces for this device */ 83 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, 84 PCI_COMMAND_MEM_ENABLE|PCI_COMMAND_MASTER_ENABLE| 85 PCI_COMMAND_IO_ENABLE); 86 return (tag); 87 } 88 89 /* 90 * functions provided to the MI code. 91 */ 92 93 void 94 pci_attach_hook(parent, self, pba) 95 struct device *parent; 96 struct device *self; 97 struct pcibus_attach_args *pba; 98 { 99 } 100 101 int 102 pci_bus_maxdevs(pc, busno) 103 pci_chipset_tag_t pc; 104 int busno; 105 { 106 107 return 32; 108 } 109 110 pcitag_t 111 pci_make_tag(pc, b, d, f) 112 pci_chipset_tag_t pc; 113 int b; 114 int d; 115 int f; 116 { 117 struct ofw_pci_register reg; 118 pcitag_t tag; 119 int busrange[2]; 120 int node, len; 121 #ifdef DEBUG 122 char name[80]; 123 bzero(name, sizeof(name)); 124 #endif 125 126 /* 127 * Hunt for the node that corresponds to this device 128 * 129 * We could cache this info in an array in the parent 130 * device... except then we have problems with devices 131 * attached below pci-pci bridges, and we would need to 132 * add special code to the pci-pci bridge to cache this 133 * info. 134 */ 135 136 tag = PCITAG_CREATE(-1, b, d, f); 137 node = pc->rootnode; 138 /* 139 * First make sure we're on the right bus. If our parent 140 * has a bus-range property and we're not in the range, 141 * then we're obviously on the wrong bus. So go up one 142 * level. 143 */ 144 #ifdef DEBUG 145 if (sparc_pci_debug & SPDB_PROBE) { 146 OF_getprop(node, "name", &name, sizeof(name)); 147 printf("curnode %x %s\n", node, name); 148 } 149 #endif 150 #if 0 151 while ((OF_getprop(OF_parent(node), "bus-range", (void *)&busrange, 152 sizeof(busrange)) == sizeof(busrange)) && 153 (b < busrange[0] || b > busrange[1])) { 154 /* Out of range, go up one */ 155 node = OF_parent(node); 156 #ifdef DEBUG 157 if (sparc_pci_debug & SPDB_PROBE) { 158 OF_getprop(node, "name", &name, sizeof(name)); 159 printf("going up to node %x %s\n", node, name); 160 } 161 #endif 162 } 163 #endif 164 /* 165 * Now traverse all peers until we find the node or we find 166 * the right bridge. 167 * 168 * XXX We go up one and down one to make sure nobody's missed. 169 * but this should not be necessary. 170 */ 171 for (node = ((node)); node; node = OF_peer(node)) { 172 173 #ifdef DEBUG 174 if (sparc_pci_debug & SPDB_PROBE) { 175 OF_getprop(node, "name", &name, sizeof(name)); 176 printf("checking node %x %s\n", node, name); 177 } 178 #endif 179 180 #if 1 181 /* 182 * Check for PCI-PCI bridges. If the device we want is 183 * in the bus-range for that bridge, work our way down. 184 */ 185 while ((OF_getprop(node, "bus-range", (void *)&busrange, 186 sizeof(busrange)) == sizeof(busrange)) && 187 (b >= busrange[0] && b <= busrange[1])) { 188 /* Go down 1 level */ 189 node = OF_child(node); 190 #ifdef DEBUG 191 if (sparc_pci_debug & SPDB_PROBE) { 192 OF_getprop(node, "name", &name, sizeof(name)); 193 printf("going down to node %x %s\n", 194 node, name); 195 } 196 #endif 197 } 198 #endif 199 /* 200 * We only really need the first `reg' property. 201 * 202 * For simplicity, we'll query the `reg' when we 203 * need it. Otherwise we could malloc() it, but 204 * that gets more complicated. 205 */ 206 len = OF_getproplen(node, "reg"); 207 if (len < sizeof(reg)) 208 continue; 209 if (OF_getprop(node, "reg", (void *)®, sizeof(reg)) != len) 210 panic("pci_probe_bus: OF_getprop len botch"); 211 212 if (b != OFW_PCI_PHYS_HI_BUS(reg.phys_hi)) 213 continue; 214 if (d != OFW_PCI_PHYS_HI_DEVICE(reg.phys_hi)) 215 continue; 216 if (f != OFW_PCI_PHYS_HI_FUNCTION(reg.phys_hi)) 217 continue; 218 219 /* Got a match */ 220 tag = ofpci_make_tag(pc, node, b, d, f); 221 222 return (tag); 223 } 224 /* No device found -- return a dead tag */ 225 return (tag); 226 } 227 228 void 229 pci_decompose_tag(pc, tag, bp, dp, fp) 230 pci_chipset_tag_t pc; 231 pcitag_t tag; 232 int *bp, *dp, *fp; 233 { 234 235 if (bp != NULL) 236 *bp = PCITAG_BUS(tag); 237 if (dp != NULL) 238 *dp = PCITAG_DEV(tag); 239 if (fp != NULL) 240 *fp = PCITAG_FUN(tag); 241 } 242 243 int 244 pci_enumerate_bus(struct pci_softc *sc, 245 int (*match)(struct pci_attach_args *), struct pci_attach_args *pap) 246 { 247 struct ofw_pci_register reg; 248 pci_chipset_tag_t pc = sc->sc_pc; 249 pcitag_t tag; 250 pcireg_t class, csr; 251 int node, b, d, f, ret; 252 char name[30]; 253 extern int pci_config_dump; 254 255 if (sc->sc_bridgetag) 256 node = PCITAG_NODE(*sc->sc_bridgetag); 257 else 258 node = pc->rootnode; 259 260 /* Turn on parity for the bus. */ 261 tag = ofpci_make_tag(pc, node, sc->sc_bus, 0, 0); 262 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 263 csr |= PCI_COMMAND_PARITY_ENABLE; 264 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 265 266 if (pci_config_dump) pci_conf_print(pc, tag, NULL); 267 268 for (node = OF_child(node); node != 0 && node != -1; 269 node = OF_peer(node)) { 270 name[0] = name[29] = 0; 271 OF_getprop(node, "name", name, sizeof(name)); 272 273 if (OF_getprop(node, "class-code", &class, sizeof(class)) != 274 sizeof(class)) 275 continue; 276 if (OF_getprop(node, "reg", ®, sizeof(reg)) < sizeof(reg)) 277 panic("pci_enumerate_bus: \"%s\" regs too small", name); 278 279 b = OFW_PCI_PHYS_HI_BUS(reg.phys_hi); 280 d = OFW_PCI_PHYS_HI_DEVICE(reg.phys_hi); 281 f = OFW_PCI_PHYS_HI_FUNCTION(reg.phys_hi); 282 283 if (sc->sc_bus != b) { 284 printf("%s: WARNING: incorrect bus # for \"%s\" " 285 "(%d/%d/%d)\n", sc->sc_dev.dv_xname, name, b, d, f); 286 continue; 287 } 288 289 tag = ofpci_make_tag(pc, node, b, d, f); 290 291 /* 292 * Turn on parity and fast-back-to-back for the device. 293 */ 294 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 295 if (csr & PCI_STATUS_BACKTOBACK_SUPPORT) 296 csr |= PCI_COMMAND_BACKTOBACK_ENABLE; 297 csr |= PCI_COMMAND_PARITY_ENABLE; 298 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 299 300 ret = pci_probe_device(sc, tag, match, pap); 301 if (match != NULL && ret != 0) 302 return (ret); 303 } 304 return (0); 305 } 306 307 /* assume we are mapped little-endian/side-effect */ 308 pcireg_t 309 pci_conf_read(pc, tag, reg) 310 pci_chipset_tag_t pc; 311 pcitag_t tag; 312 int reg; 313 { 314 struct psycho_pbm *pp = pc->cookie; 315 struct psycho_softc *sc = pp->pp_sc; 316 pcireg_t val = (pcireg_t)~0; 317 318 DPRINTF(SPDB_CONF, ("pci_conf_read: tag %lx reg %x ", 319 (long)tag, reg)); 320 if (PCITAG_NODE(tag) != -1) { 321 DPRINTF(SPDB_CONF, ("asi=%x addr=%qx (offset=%x) ...", 322 sc->sc_configaddr._asi, 323 (long long)(sc->sc_configaddr._ptr + 324 PCITAG_OFFSET(tag) + reg), 325 (int)PCITAG_OFFSET(tag) + reg)); 326 327 val = bus_space_read_4(sc->sc_configtag, sc->sc_configaddr, 328 PCITAG_OFFSET(tag) + reg); 329 } 330 #ifdef DEBUG 331 else DPRINTF(SPDB_CONF, ("pci_conf_read: bogus pcitag %x\n", 332 (int)PCITAG_OFFSET(tag))); 333 #endif 334 DPRINTF(SPDB_CONF, (" returning %08x\n", (u_int)val)); 335 336 return (val); 337 } 338 339 void 340 pci_conf_write(pc, tag, reg, data) 341 pci_chipset_tag_t pc; 342 pcitag_t tag; 343 int reg; 344 pcireg_t data; 345 { 346 struct psycho_pbm *pp = pc->cookie; 347 struct psycho_softc *sc = pp->pp_sc; 348 349 DPRINTF(SPDB_CONF, ("pci_conf_write: tag %lx; reg %x; data %x; ", 350 (long)PCITAG_OFFSET(tag), reg, (int)data)); 351 DPRINTF(SPDB_CONF, ("asi = %x; readaddr = %qx (offset = %x)\n", 352 sc->sc_configaddr._asi, 353 (long long)(sc->sc_configaddr._ptr + PCITAG_OFFSET(tag) + reg), 354 (int)PCITAG_OFFSET(tag) + reg)); 355 356 /* If we don't know it, just punt it. */ 357 if (PCITAG_NODE(tag) == -1) { 358 DPRINTF(SPDB_CONF, ("pci_conf_write: bad addr")); 359 return; 360 } 361 362 bus_space_write_4(sc->sc_configtag, sc->sc_configaddr, 363 PCITAG_OFFSET(tag) + reg, data); 364 } 365 366 /* 367 * interrupt mapping foo. 368 * XXX: how does this deal with multiple interrupts for a device? 369 */ 370 int 371 pci_intr_map(pa, ihp) 372 struct pci_attach_args *pa; 373 pci_intr_handle_t *ihp; 374 { 375 pcitag_t tag = pa->pa_tag; 376 pcireg_t bhlc, ic; 377 int bus_frequency, val, bus_node; 378 int interrupts; 379 int len, node = PCITAG_NODE(tag); 380 char devtype[30]; 381 382 bus_node = OF_parent(node); 383 len = OF_getproplen(bus_node, "clock-frequency"); 384 if (len < sizeof(bus_frequency)) { 385 DPRINTF(SPDB_INTMAP, 386 ("pci_intr_map: clock-frequency len %d too small\n", len)); 387 return (ENODEV); 388 } 389 if (OF_getprop(bus_node, "clock-frequency", (void *)&bus_frequency, 390 sizeof(bus_frequency)) != len) { 391 DPRINTF(SPDB_INTMAP, 392 ("pci_intr_map: could not read bus_frequency\n")); 393 return (ENODEV); 394 } 395 396 len = OF_getproplen(node, "interrupts"); 397 if (len < sizeof(interrupts)) { 398 DPRINTF(SPDB_INTMAP, 399 ("pci_intr_map: interrupts len %d too small\n", len)); 400 return (ENODEV); 401 } 402 if (OF_getprop(node, "interrupts", (void *)&interrupts, 403 sizeof(interrupts)) != len) { 404 DPRINTF(SPDB_INTMAP, 405 ("pci_intr_map: could not read interrupts\n")); 406 return (ENODEV); 407 } 408 409 if (OF_mapintr(node, &interrupts, sizeof(interrupts), 410 sizeof(interrupts)) < 0) { 411 printf("OF_mapintr failed\n"); 412 } 413 /* Try to find an IPL for this type of device. */ 414 if (OF_getprop(node, "device_type", &devtype, sizeof(devtype)) > 0) { 415 for (len = 0; intrmap[len].in_class; len++) 416 if (strcmp(intrmap[len].in_class, devtype) == 0) { 417 interrupts |= INTLEVENCODE(intrmap[len].in_lev); 418 break; 419 } 420 } 421 422 /* 423 * Initialize the latency timer register for busmaster devices 424 * to work properly. 425 * latency-timer = min-grant * bus-freq / 4 (from FreeBSD) 426 */ 427 ic = pci_conf_read(pa->pa_pc, tag, PCI_INTERRUPT_REG); 428 bus_frequency /= 1000000; 429 val = min(PCI_MIN_GNT(ic) * bus_frequency / 4, 255); 430 if (val > 0) { 431 bhlc = pci_conf_read(pa->pa_pc, tag, PCI_BHLC_REG); 432 if (PCI_LATTIMER(bhlc) < val) { 433 bhlc &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 434 bhlc |= (val << PCI_LATTIMER_SHIFT); 435 pci_conf_write(pa->pa_pc, tag, PCI_BHLC_REG, bhlc); 436 } 437 } 438 439 /* XXXX -- we use the ino. What if there is a valid IGN? */ 440 *ihp = interrupts; 441 return (0); 442 } 443 444 const char * 445 pci_intr_string(pc, ih) 446 pci_chipset_tag_t pc; 447 pci_intr_handle_t ih; 448 { 449 static char str[16]; 450 451 DPRINTF(SPDB_INTR, ("pci_intr_string: ih %u", ih)); 452 sprintf(str, "ivec %x", ih); 453 DPRINTF(SPDB_INTR, ("; returning %s\n", str)); 454 455 return (str); 456 } 457 458 const struct evcnt * 459 pci_intr_evcnt(pc, ih) 460 pci_chipset_tag_t pc; 461 pci_intr_handle_t ih; 462 { 463 464 /* XXX for now, no evcnt parent reported */ 465 return NULL; 466 } 467 468 void * 469 pci_intr_establish(pc, ih, level, func, arg) 470 pci_chipset_tag_t pc; 471 pci_intr_handle_t ih; 472 int level; 473 int (*func) __P((void *)); 474 void *arg; 475 { 476 void *cookie; 477 struct psycho_pbm *pp = (struct psycho_pbm *)pc->cookie; 478 479 DPRINTF(SPDB_INTR, ("pci_intr_establish: ih %lu; level %d", (u_long)ih, level)); 480 cookie = bus_intr_establish(pp->pp_memt, ih, level, 0, func, arg); 481 482 DPRINTF(SPDB_INTR, ("; returning handle %p\n", cookie)); 483 return (cookie); 484 } 485 486 void 487 pci_intr_disestablish(pc, cookie) 488 pci_chipset_tag_t pc; 489 void *cookie; 490 { 491 492 DPRINTF(SPDB_INTR, ("pci_intr_disestablish: cookie %p\n", cookie)); 493 494 /* XXX */ 495 panic("can't disestablish PCI interrupts yet"); 496 } 497
Indexes created Wed Oct 15 07:09:58 GMT 2025