pci_machdep.c revision 1.35 1 /* $NetBSD: pci_machdep.c,v 1.35 2003/03/22 06:33:09 nakayama Exp $ */
2
3 /*
4 * Copyright (c) 1999, 2000 Matthew R. Green
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
23 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
24 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
25 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 */
30
31 /*
32 * functions expected by the MI PCI code.
33 */
34
35 #ifdef DEBUG
36 #define SPDB_CONF 0x01
37 #define SPDB_INTR 0x04
38 #define SPDB_INTMAP 0x08
39 #define SPDB_INTFIX 0x10
40 #define SPDB_PROBE 0x20
41 int sparc_pci_debug = 0x0;
42 #define DPRINTF(l, s) do { if (sparc_pci_debug & l) printf s; } while (0)
43 #else
44 #define DPRINTF(l, s)
45 #endif
46
47 #include <sys/types.h>
48 #include <sys/param.h>
49 #include <sys/time.h>
50 #include <sys/systm.h>
51 #include <sys/errno.h>
52 #include <sys/device.h>
53 #include <sys/malloc.h>
54
55 #define _SPARC_BUS_DMA_PRIVATE
56 #include <machine/bus.h>
57 #include <machine/autoconf.h>
58 #include <machine/openfirm.h>
59
60 #include <dev/pci/pcivar.h>
61 #include <dev/pci/pcireg.h>
62
63 #include <dev/ofw/ofw_pci.h>
64
65 #include <sparc64/dev/iommureg.h>
66 #include <sparc64/dev/iommuvar.h>
67 #include <sparc64/dev/psychoreg.h>
68 #include <sparc64/dev/psychovar.h>
69
70 /* this is a base to be copied */
71 struct sparc_pci_chipset _sparc_pci_chipset = {
72 NULL,
73 };
74
75 static pcitag_t
76 ofpci_make_tag(pci_chipset_tag_t pc, int node, int b, int d, int f)
77 {
78 pcitag_t tag;
79
80 tag = PCITAG_CREATE(node, b, d, f);
81
82 /* Enable all the different spaces for this device */
83 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG,
84 PCI_COMMAND_MEM_ENABLE|PCI_COMMAND_MASTER_ENABLE|
85 PCI_COMMAND_IO_ENABLE);
86 return (tag);
87 }
88
89 /*
90 * functions provided to the MI code.
91 */
92
93 void
94 pci_attach_hook(parent, self, pba)
95 struct device *parent;
96 struct device *self;
97 struct pcibus_attach_args *pba;
98 {
99 }
100
101 int
102 pci_bus_maxdevs(pc, busno)
103 pci_chipset_tag_t pc;
104 int busno;
105 {
106
107 return 32;
108 }
109
110 pcitag_t
111 pci_make_tag(pc, b, d, f)
112 pci_chipset_tag_t pc;
113 int b;
114 int d;
115 int f;
116 {
117 struct psycho_pbm *pp = pc->cookie;
118 struct ofw_pci_register reg;
119 pcitag_t tag;
120 int (*valid) __P((void *));
121 int busrange[2];
122 int node, len;
123 #ifdef DEBUG
124 char name[80];
125 bzero(name, sizeof(name));
126 #endif
127
128 /*
129 * Refer to the PCI/CardBus bus node first.
130 * It returns a tag if node is present and bus is valid.
131 */
132 if (0 <= b && b < 256) {
133 node = (*pp->pp_busnode)[b].node;
134 valid = (*pp->pp_busnode)[b].valid;
135 if (node != 0 && d == 0 &&
136 (valid == NULL || (*valid)((*pp->pp_busnode)[b].arg)))
137 return ofpci_make_tag(pc, node, b, d, f);
138 }
139
140 /*
141 * Hunt for the node that corresponds to this device
142 *
143 * We could cache this info in an array in the parent
144 * device... except then we have problems with devices
145 * attached below pci-pci bridges, and we would need to
146 * add special code to the pci-pci bridge to cache this
147 * info.
148 */
149
150 tag = PCITAG_CREATE(-1, b, d, f);
151 node = pc->rootnode;
152 /*
153 * First make sure we're on the right bus. If our parent
154 * has a bus-range property and we're not in the range,
155 * then we're obviously on the wrong bus. So go up one
156 * level.
157 */
158 #ifdef DEBUG
159 if (sparc_pci_debug & SPDB_PROBE) {
160 OF_getprop(node, "name", &name, sizeof(name));
161 printf("curnode %x %s\n", node, name);
162 }
163 #endif
164 #if 0
165 while ((OF_getprop(OF_parent(node), "bus-range", (void *)&busrange,
166 sizeof(busrange)) == sizeof(busrange)) &&
167 (b < busrange[0] || b > busrange[1])) {
168 /* Out of range, go up one */
169 node = OF_parent(node);
170 #ifdef DEBUG
171 if (sparc_pci_debug & SPDB_PROBE) {
172 OF_getprop(node, "name", &name, sizeof(name));
173 printf("going up to node %x %s\n", node, name);
174 }
175 #endif
176 }
177 #endif
178 /*
179 * Now traverse all peers until we find the node or we find
180 * the right bridge.
181 *
182 * XXX We go up one and down one to make sure nobody's missed.
183 * but this should not be necessary.
184 */
185 for (node = ((node)); node; node = OF_peer(node)) {
186
187 #ifdef DEBUG
188 if (sparc_pci_debug & SPDB_PROBE) {
189 OF_getprop(node, "name", &name, sizeof(name));
190 printf("checking node %x %s\n", node, name);
191 }
192 #endif
193
194 #if 1
195 /*
196 * Check for PCI-PCI bridges. If the device we want is
197 * in the bus-range for that bridge, work our way down.
198 */
199 while ((OF_getprop(node, "bus-range", (void *)&busrange,
200 sizeof(busrange)) == sizeof(busrange)) &&
201 (b >= busrange[0] && b <= busrange[1])) {
202 /* Go down 1 level */
203 node = OF_child(node);
204 #ifdef DEBUG
205 if (sparc_pci_debug & SPDB_PROBE) {
206 OF_getprop(node, "name", &name, sizeof(name));
207 printf("going down to node %x %s\n",
208 node, name);
209 }
210 #endif
211 }
212 #endif
213 /*
214 * We only really need the first `reg' property.
215 *
216 * For simplicity, we'll query the `reg' when we
217 * need it. Otherwise we could malloc() it, but
218 * that gets more complicated.
219 */
220 len = OF_getproplen(node, "reg");
221 if (len < sizeof(reg))
222 continue;
223 if (OF_getprop(node, "reg", (void *)®, sizeof(reg)) != len)
224 panic("pci_probe_bus: OF_getprop len botch");
225
226 if (b != OFW_PCI_PHYS_HI_BUS(reg.phys_hi))
227 continue;
228 if (d != OFW_PCI_PHYS_HI_DEVICE(reg.phys_hi))
229 continue;
230 if (f != OFW_PCI_PHYS_HI_FUNCTION(reg.phys_hi))
231 continue;
232
233 /* Got a match */
234 tag = ofpci_make_tag(pc, node, b, d, f);
235
236 return (tag);
237 }
238 /* No device found -- return a dead tag */
239 return (tag);
240 }
241
242 void
243 pci_decompose_tag(pc, tag, bp, dp, fp)
244 pci_chipset_tag_t pc;
245 pcitag_t tag;
246 int *bp, *dp, *fp;
247 {
248
249 if (bp != NULL)
250 *bp = PCITAG_BUS(tag);
251 if (dp != NULL)
252 *dp = PCITAG_DEV(tag);
253 if (fp != NULL)
254 *fp = PCITAG_FUN(tag);
255 }
256
257 int
258 pci_enumerate_bus(struct pci_softc *sc,
259 int (*match)(struct pci_attach_args *), struct pci_attach_args *pap)
260 {
261 struct ofw_pci_register reg;
262 pci_chipset_tag_t pc = sc->sc_pc;
263 pcitag_t tag;
264 pcireg_t class, csr, bhlc, ic;
265 int node, b, d, f, ret;
266 int len, bus_frequency, lt, cl;
267 char name[30];
268 extern int pci_config_dump;
269
270 if (sc->sc_bridgetag)
271 node = PCITAG_NODE(*sc->sc_bridgetag);
272 else
273 node = pc->rootnode;
274
275 len = OF_getproplen(node, "clock-frequency");
276 if (len < sizeof(bus_frequency)) {
277 DPRINTF(SPDB_PROBE,
278 ("pci_enumerate_bus: clock-frequency len %d too small\n",
279 len));
280 return 0;
281 }
282 if (OF_getprop(node, "clock-frequency", &bus_frequency,
283 sizeof(bus_frequency)) != len) {
284 DPRINTF(SPDB_PROBE,
285 ("pci_enumerate_bus: could not read clock-frequency\n"));
286 return 0;
287 }
288 bus_frequency /= 1000000;
289
290 /* Turn on parity for the bus. */
291 tag = ofpci_make_tag(pc, node, sc->sc_bus, 0, 0);
292 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
293 csr |= PCI_COMMAND_PARITY_ENABLE;
294 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr);
295
296 /*
297 * Initialize the latency timer register.
298 * The value 0x40 is from Solaris.
299 */
300 bhlc = pci_conf_read(pc, tag, PCI_BHLC_REG);
301 bhlc &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT);
302 bhlc |= 0x40 << PCI_LATTIMER_SHIFT;
303 pci_conf_write(pc, tag, PCI_BHLC_REG, bhlc);
304
305 if (pci_config_dump) pci_conf_print(pc, tag, NULL);
306
307 for (node = OF_child(node); node != 0 && node != -1;
308 node = OF_peer(node)) {
309 name[0] = name[29] = 0;
310 OF_getprop(node, "name", name, sizeof(name));
311
312 if (OF_getprop(node, "class-code", &class, sizeof(class)) !=
313 sizeof(class))
314 continue;
315 if (OF_getprop(node, "reg", ®, sizeof(reg)) < sizeof(reg))
316 panic("pci_enumerate_bus: \"%s\" regs too small", name);
317
318 b = OFW_PCI_PHYS_HI_BUS(reg.phys_hi);
319 d = OFW_PCI_PHYS_HI_DEVICE(reg.phys_hi);
320 f = OFW_PCI_PHYS_HI_FUNCTION(reg.phys_hi);
321
322 if (sc->sc_bus != b) {
323 printf("%s: WARNING: incorrect bus # for \"%s\" "
324 "(%d/%d/%d)\n", sc->sc_dev.dv_xname, name, b, d, f);
325 continue;
326 }
327
328 tag = ofpci_make_tag(pc, node, b, d, f);
329
330 /*
331 * Turn on parity and fast-back-to-back for the device.
332 */
333 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
334 if (csr & PCI_STATUS_BACKTOBACK_SUPPORT)
335 csr |= PCI_COMMAND_BACKTOBACK_ENABLE;
336 csr |= PCI_COMMAND_PARITY_ENABLE;
337 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr);
338
339 /*
340 * Initialize the latency timer register for busmaster
341 * devices to work properly.
342 * latency-timer = min-grant * bus-freq / 4 (from FreeBSD)
343 * Also initialize the cache line size register.
344 * Solaris anytime sets this register to the value 0x10.
345 */
346 bhlc = pci_conf_read(pc, tag, PCI_BHLC_REG);
347 ic = pci_conf_read(pc, tag, PCI_INTERRUPT_REG);
348
349 lt = min(PCI_MIN_GNT(ic) * bus_frequency / 4, 255);
350 if (lt == 0 || lt < PCI_LATTIMER(bhlc))
351 lt = PCI_LATTIMER(bhlc);
352
353 cl = PCI_CACHELINE(bhlc);
354 if (cl == 0)
355 cl = 0x10;
356
357 bhlc &= ~((PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT) |
358 (PCI_CACHELINE_MASK << PCI_CACHELINE_SHIFT));
359 bhlc |= (lt << PCI_LATTIMER_SHIFT) |
360 (cl << PCI_CACHELINE_SHIFT);
361 pci_conf_write(pc, tag, PCI_BHLC_REG, bhlc);
362
363 ret = pci_probe_device(sc, tag, match, pap);
364 if (match != NULL && ret != 0)
365 return (ret);
366 }
367 return (0);
368 }
369
370 /* assume we are mapped little-endian/side-effect */
371 pcireg_t
372 pci_conf_read(pc, tag, reg)
373 pci_chipset_tag_t pc;
374 pcitag_t tag;
375 int reg;
376 {
377 struct psycho_pbm *pp = pc->cookie;
378 struct psycho_softc *sc = pp->pp_sc;
379 pcireg_t val = (pcireg_t)~0;
380
381 DPRINTF(SPDB_CONF, ("pci_conf_read: tag %lx reg %x ",
382 (long)tag, reg));
383 if (PCITAG_NODE(tag) != -1) {
384 DPRINTF(SPDB_CONF, ("asi=%x addr=%qx (offset=%x) ...",
385 sc->sc_configaddr._asi,
386 (long long)(sc->sc_configaddr._ptr +
387 PCITAG_OFFSET(tag) + reg),
388 (int)PCITAG_OFFSET(tag) + reg));
389
390 val = bus_space_read_4(sc->sc_configtag, sc->sc_configaddr,
391 PCITAG_OFFSET(tag) + reg);
392 }
393 #ifdef DEBUG
394 else DPRINTF(SPDB_CONF, ("pci_conf_read: bogus pcitag %x\n",
395 (int)PCITAG_OFFSET(tag)));
396 #endif
397 DPRINTF(SPDB_CONF, (" returning %08x\n", (u_int)val));
398
399 return (val);
400 }
401
402 void
403 pci_conf_write(pc, tag, reg, data)
404 pci_chipset_tag_t pc;
405 pcitag_t tag;
406 int reg;
407 pcireg_t data;
408 {
409 struct psycho_pbm *pp = pc->cookie;
410 struct psycho_softc *sc = pp->pp_sc;
411
412 DPRINTF(SPDB_CONF, ("pci_conf_write: tag %lx; reg %x; data %x; ",
413 (long)PCITAG_OFFSET(tag), reg, (int)data));
414 DPRINTF(SPDB_CONF, ("asi = %x; readaddr = %qx (offset = %x)\n",
415 sc->sc_configaddr._asi,
416 (long long)(sc->sc_configaddr._ptr + PCITAG_OFFSET(tag) + reg),
417 (int)PCITAG_OFFSET(tag) + reg));
418
419 /* If we don't know it, just punt it. */
420 if (PCITAG_NODE(tag) == -1) {
421 DPRINTF(SPDB_CONF, ("pci_conf_write: bad addr"));
422 return;
423 }
424
425 bus_space_write_4(sc->sc_configtag, sc->sc_configaddr,
426 PCITAG_OFFSET(tag) + reg, data);
427 }
428
429 /*
430 * interrupt mapping foo.
431 * XXX: how does this deal with multiple interrupts for a device?
432 */
433 int
434 pci_intr_map(pa, ihp)
435 struct pci_attach_args *pa;
436 pci_intr_handle_t *ihp;
437 {
438 pcitag_t tag = pa->pa_tag;
439 int interrupts;
440 int len, node = PCITAG_NODE(tag);
441 char devtype[30];
442
443 len = OF_getproplen(node, "interrupts");
444 if (len < sizeof(interrupts)) {
445 DPRINTF(SPDB_INTMAP,
446 ("pci_intr_map: interrupts len %d too small\n", len));
447 return (ENODEV);
448 }
449 if (OF_getprop(node, "interrupts", (void *)&interrupts,
450 sizeof(interrupts)) != len) {
451 DPRINTF(SPDB_INTMAP,
452 ("pci_intr_map: could not read interrupts\n"));
453 return (ENODEV);
454 }
455
456 if (OF_mapintr(node, &interrupts, sizeof(interrupts),
457 sizeof(interrupts)) < 0) {
458 printf("OF_mapintr failed\n");
459 }
460 /* Try to find an IPL for this type of device. */
461 if (OF_getprop(node, "device_type", &devtype, sizeof(devtype)) > 0) {
462 for (len = 0; intrmap[len].in_class; len++)
463 if (strcmp(intrmap[len].in_class, devtype) == 0) {
464 interrupts |= INTLEVENCODE(intrmap[len].in_lev);
465 break;
466 }
467 }
468
469 /* XXXX -- we use the ino. What if there is a valid IGN? */
470 *ihp = interrupts;
471 return (0);
472 }
473
474 const char *
475 pci_intr_string(pc, ih)
476 pci_chipset_tag_t pc;
477 pci_intr_handle_t ih;
478 {
479 static char str[16];
480
481 DPRINTF(SPDB_INTR, ("pci_intr_string: ih %u", ih));
482 sprintf(str, "ivec %x", ih);
483 DPRINTF(SPDB_INTR, ("; returning %s\n", str));
484
485 return (str);
486 }
487
488 const struct evcnt *
489 pci_intr_evcnt(pc, ih)
490 pci_chipset_tag_t pc;
491 pci_intr_handle_t ih;
492 {
493
494 /* XXX for now, no evcnt parent reported */
495 return NULL;
496 }
497
498 void *
499 pci_intr_establish(pc, ih, level, func, arg)
500 pci_chipset_tag_t pc;
501 pci_intr_handle_t ih;
502 int level;
503 int (*func) __P((void *));
504 void *arg;
505 {
506 void *cookie;
507 struct psycho_pbm *pp = (struct psycho_pbm *)pc->cookie;
508
509 DPRINTF(SPDB_INTR, ("pci_intr_establish: ih %lu; level %d", (u_long)ih, level));
510 cookie = bus_intr_establish(pp->pp_memt, ih, level, func, arg);
511
512 DPRINTF(SPDB_INTR, ("; returning handle %p\n", cookie));
513 return (cookie);
514 }
515
516 void
517 pci_intr_disestablish(pc, cookie)
518 pci_chipset_tag_t pc;
519 void *cookie;
520 {
521
522 DPRINTF(SPDB_INTR, ("pci_intr_disestablish: cookie %p\n", cookie));
523
524 /* XXX */
525 panic("can't disestablish PCI interrupts yet");
526 }
527