pci_machdep.c revision 1.43
1 /* $NetBSD: pci_machdep.c,v 1.43 2004/03/21 14:28:47 pk Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000 Matthew R. Green 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 23 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 24 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 25 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 /* 32 * functions expected by the MI PCI code. 33 */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: pci_machdep.c,v 1.43 2004/03/21 14:28:47 pk Exp $"); 37 38 #include <sys/types.h> 39 #include <sys/param.h> 40 #include <sys/time.h> 41 #include <sys/systm.h> 42 #include <sys/errno.h> 43 #include <sys/device.h> 44 #include <sys/malloc.h> 45 46 #define _SPARC_BUS_DMA_PRIVATE 47 #include <machine/bus.h> 48 #include <machine/autoconf.h> 49 #include <machine/openfirm.h> 50 #include <dev/pci/pcivar.h> 51 #include <dev/pci/pcireg.h> 52 53 #include <dev/ofw/ofw_pci.h> 54 55 #include <sparc64/dev/iommureg.h> 56 #include <sparc64/dev/iommuvar.h> 57 #include <sparc64/dev/psychoreg.h> 58 #include <sparc64/dev/psychovar.h> 59 #include <sparc64/sparc64/cache.h> 60 61 #ifdef DEBUG 62 #define SPDB_CONF 0x01 63 #define SPDB_INTR 0x04 64 #define SPDB_INTMAP 0x08 65 #define SPDB_INTFIX 0x10 66 #define SPDB_PROBE 0x20 67 int sparc_pci_debug = 0x0; 68 #define DPRINTF(l, s) do { if (sparc_pci_debug & l) printf s; } while (0) 69 #else 70 #define DPRINTF(l, s) 71 #endif 72 73 /* this is a base to be copied */ 74 struct sparc_pci_chipset _sparc_pci_chipset = { 75 NULL, 76 }; 77 78 static int pci_find_ino(struct pci_attach_args *, pci_intr_handle_t *); 79 80 static pcitag_t 81 ofpci_make_tag(pci_chipset_tag_t pc, int node, int b, int d, int f) 82 { 83 pcitag_t tag; 84 85 tag = PCITAG_CREATE(node, b, d, f); 86 87 /* Enable all the different spaces for this device */ 88 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, 89 PCI_COMMAND_MEM_ENABLE|PCI_COMMAND_MASTER_ENABLE| 90 PCI_COMMAND_IO_ENABLE); 91 return (tag); 92 } 93 94 /* 95 * functions provided to the MI code. 96 */ 97 98 void 99 pci_attach_hook(parent, self, pba) 100 struct device *parent; 101 struct device *self; 102 struct pcibus_attach_args *pba; 103 { 104 } 105 106 int 107 pci_bus_maxdevs(pc, busno) 108 pci_chipset_tag_t pc; 109 int busno; 110 { 111 112 return 32; 113 } 114 115 pcitag_t 116 pci_make_tag(pc, b, d, f) 117 pci_chipset_tag_t pc; 118 int b; 119 int d; 120 int f; 121 { 122 struct psycho_pbm *pp = pc->cookie; 123 struct ofw_pci_register reg; 124 pcitag_t tag; 125 int (*valid) __P((void *)); 126 int busrange[2]; 127 int node, len; 128 #ifdef DEBUG 129 char name[80]; 130 memset(name, 0, sizeof(name)); 131 #endif 132 133 /* 134 * Refer to the PCI/CardBus bus node first. 135 * It returns a tag if node is present and bus is valid. 136 */ 137 if (0 <= b && b < 256) { 138 node = (*pp->pp_busnode)[b].node; 139 valid = (*pp->pp_busnode)[b].valid; 140 if (node != 0 && d == 0 && 141 (valid == NULL || (*valid)((*pp->pp_busnode)[b].arg))) 142 return ofpci_make_tag(pc, node, b, d, f); 143 } 144 145 /* 146 * Hunt for the node that corresponds to this device 147 * 148 * We could cache this info in an array in the parent 149 * device... except then we have problems with devices 150 * attached below pci-pci bridges, and we would need to 151 * add special code to the pci-pci bridge to cache this 152 * info. 153 */ 154 155 tag = PCITAG_CREATE(-1, b, d, f); 156 node = pc->rootnode; 157 /* 158 * First make sure we're on the right bus. If our parent 159 * has a bus-range property and we're not in the range, 160 * then we're obviously on the wrong bus. So go up one 161 * level. 162 */ 163 #ifdef DEBUG 164 if (sparc_pci_debug & SPDB_PROBE) { 165 printf("curnode %x %s\n", node, 166 prom_getpropstringA(node, "name", name, sizeof(name))); 167 } 168 #endif 169 #if 0 170 while ((OF_getprop(OF_parent(node), "bus-range", (void *)&busrange, 171 sizeof(busrange)) == sizeof(busrange)) && 172 (b < busrange[0] || b > busrange[1])) { 173 /* Out of range, go up one */ 174 node = OF_parent(node); 175 #ifdef DEBUG 176 if (sparc_pci_debug & SPDB_PROBE) { 177 printf("going up to node %x %s\n", node, 178 prom_getpropstringA(node, "name", name, sizeof(name))); 179 } 180 #endif 181 } 182 #endif 183 /* 184 * Now traverse all peers until we find the node or we find 185 * the right bridge. 186 * 187 * XXX We go up one and down one to make sure nobody's missed. 188 * but this should not be necessary. 189 */ 190 for (node = ((node)); node; node = prom_nextsibling(node)) { 191 192 #ifdef DEBUG 193 if (sparc_pci_debug & SPDB_PROBE) { 194 printf("checking node %x %s\n", node, 195 prom_getpropstringA(node, "name", name, sizeof(name))); 196 197 } 198 #endif 199 200 #if 1 201 /* 202 * Check for PCI-PCI bridges. If the device we want is 203 * in the bus-range for that bridge, work our way down. 204 */ 205 while ((OF_getprop(node, "bus-range", (void *)&busrange, 206 sizeof(busrange)) == sizeof(busrange)) && 207 (b >= busrange[0] && b <= busrange[1])) { 208 /* Go down 1 level */ 209 node = prom_firstchild(node); 210 #ifdef DEBUG 211 if (sparc_pci_debug & SPDB_PROBE) { 212 OF_getprop(node, "name", &name, sizeof(name)); 213 printf("going down to node %x %s\n", node, 214 prom_getpropstringA(node, "name", 215 name, sizeof(name))); 216 } 217 #endif 218 } 219 #endif 220 /* 221 * We only really need the first `reg' property. 222 * 223 * For simplicity, we'll query the `reg' when we 224 * need it. Otherwise we could malloc() it, but 225 * that gets more complicated. 226 */ 227 len = prom_getproplen(node, "reg"); 228 if (len < sizeof(reg)) 229 continue; 230 if (OF_getprop(node, "reg", (void *)®, sizeof(reg)) != len) 231 panic("pci_probe_bus: OF_getprop len botch"); 232 233 if (b != OFW_PCI_PHYS_HI_BUS(reg.phys_hi)) 234 continue; 235 if (d != OFW_PCI_PHYS_HI_DEVICE(reg.phys_hi)) 236 continue; 237 if (f != OFW_PCI_PHYS_HI_FUNCTION(reg.phys_hi)) 238 continue; 239 240 /* Got a match */ 241 tag = ofpci_make_tag(pc, node, b, d, f); 242 243 return (tag); 244 } 245 /* No device found -- return a dead tag */ 246 return (tag); 247 } 248 249 void 250 pci_decompose_tag(pc, tag, bp, dp, fp) 251 pci_chipset_tag_t pc; 252 pcitag_t tag; 253 int *bp, *dp, *fp; 254 { 255 256 if (bp != NULL) 257 *bp = PCITAG_BUS(tag); 258 if (dp != NULL) 259 *dp = PCITAG_DEV(tag); 260 if (fp != NULL) 261 *fp = PCITAG_FUN(tag); 262 } 263 264 int 265 pci_enumerate_bus(struct pci_softc *sc, 266 int (*match)(struct pci_attach_args *), struct pci_attach_args *pap) 267 { 268 struct ofw_pci_register reg; 269 pci_chipset_tag_t pc = sc->sc_pc; 270 pcitag_t tag; 271 pcireg_t class, csr, bhlc, ic; 272 int node, b, d, f, ret; 273 int bus_frequency, lt, cl, cacheline; 274 char name[30]; 275 extern int pci_config_dump; 276 277 if (sc->sc_bridgetag) 278 node = PCITAG_NODE(*sc->sc_bridgetag); 279 else 280 node = pc->rootnode; 281 282 bus_frequency = 283 prom_getpropint(node, "clock-frequency", 33000000) / 1000000; 284 285 /* 286 * Make sure the cache line size is at least as big as the 287 * ecache line and the streaming cache (64 byte). 288 */ 289 cacheline = max(cacheinfo.ec_linesize, 64); 290 KASSERT((cacheline/64)*64 == cacheline && 291 (cacheline/cacheinfo.ec_linesize)*cacheinfo.ec_linesize == cacheline && 292 (cacheline/4)*4 == cacheline); 293 294 /* Turn on parity for the bus. */ 295 tag = ofpci_make_tag(pc, node, sc->sc_bus, 0, 0); 296 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 297 csr |= PCI_COMMAND_PARITY_ENABLE; 298 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 299 300 /* 301 * Initialize the latency timer register. 302 * The value 0x40 is from Solaris. 303 */ 304 bhlc = pci_conf_read(pc, tag, PCI_BHLC_REG); 305 bhlc &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 306 bhlc |= 0x40 << PCI_LATTIMER_SHIFT; 307 pci_conf_write(pc, tag, PCI_BHLC_REG, bhlc); 308 309 if (pci_config_dump) pci_conf_print(pc, tag, NULL); 310 311 for (node = prom_firstchild(node); node != 0 && node != -1; 312 node = prom_nextsibling(node)) { 313 name[0] = name[29] = 0; 314 prom_getpropstringA(node, "name", name, sizeof(name)); 315 316 if (OF_getprop(node, "class-code", &class, sizeof(class)) != 317 sizeof(class)) 318 continue; 319 if (OF_getprop(node, "reg", ®, sizeof(reg)) < sizeof(reg)) 320 panic("pci_enumerate_bus: \"%s\" regs too small", name); 321 322 b = OFW_PCI_PHYS_HI_BUS(reg.phys_hi); 323 d = OFW_PCI_PHYS_HI_DEVICE(reg.phys_hi); 324 f = OFW_PCI_PHYS_HI_FUNCTION(reg.phys_hi); 325 326 if (sc->sc_bus != b) { 327 printf("%s: WARNING: incorrect bus # for \"%s\" " 328 "(%d/%d/%d)\n", sc->sc_dev.dv_xname, name, b, d, f); 329 continue; 330 } 331 332 tag = ofpci_make_tag(pc, node, b, d, f); 333 334 /* 335 * Turn on parity and fast-back-to-back for the device. 336 */ 337 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 338 if (csr & PCI_STATUS_BACKTOBACK_SUPPORT) 339 csr |= PCI_COMMAND_BACKTOBACK_ENABLE; 340 csr |= PCI_COMMAND_PARITY_ENABLE; 341 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 342 343 /* 344 * Initialize the latency timer register for busmaster 345 * devices to work properly. 346 * latency-timer = min-grant * bus-freq / 4 (from FreeBSD) 347 * Also initialize the cache line size register. 348 * Solaris anytime sets this register to the value 0x10. 349 */ 350 bhlc = pci_conf_read(pc, tag, PCI_BHLC_REG); 351 ic = pci_conf_read(pc, tag, PCI_INTERRUPT_REG); 352 353 lt = min(PCI_MIN_GNT(ic) * bus_frequency / 4, 255); 354 if (lt == 0 || lt < PCI_LATTIMER(bhlc)) 355 lt = PCI_LATTIMER(bhlc); 356 357 cl = PCI_CACHELINE(bhlc); 358 if (cl == 0) 359 cl = cacheline; 360 361 bhlc &= ~((PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT) | 362 (PCI_CACHELINE_MASK << PCI_CACHELINE_SHIFT)); 363 bhlc |= (lt << PCI_LATTIMER_SHIFT) | 364 (cl << PCI_CACHELINE_SHIFT); 365 pci_conf_write(pc, tag, PCI_BHLC_REG, bhlc); 366 367 ret = pci_probe_device(sc, tag, match, pap); 368 if (match != NULL && ret != 0) 369 return (ret); 370 } 371 return (0); 372 } 373 374 /* assume we are mapped little-endian/side-effect */ 375 pcireg_t 376 pci_conf_read(pc, tag, reg) 377 pci_chipset_tag_t pc; 378 pcitag_t tag; 379 int reg; 380 { 381 struct psycho_pbm *pp = pc->cookie; 382 struct psycho_softc *sc = pp->pp_sc; 383 pcireg_t val = (pcireg_t)~0; 384 385 DPRINTF(SPDB_CONF, ("pci_conf_read: tag %lx reg %x ", 386 (long)tag, reg)); 387 if (PCITAG_NODE(tag) != -1) { 388 DPRINTF(SPDB_CONF, ("asi=%x addr=%qx (offset=%x) ...", 389 sc->sc_configaddr._asi, 390 (long long)(sc->sc_configaddr._ptr + 391 PCITAG_OFFSET(tag) + reg), 392 (int)PCITAG_OFFSET(tag) + reg)); 393 394 val = bus_space_read_4(sc->sc_configtag, sc->sc_configaddr, 395 PCITAG_OFFSET(tag) + reg); 396 } 397 #ifdef DEBUG 398 else DPRINTF(SPDB_CONF, ("pci_conf_read: bogus pcitag %x\n", 399 (int)PCITAG_OFFSET(tag))); 400 #endif 401 DPRINTF(SPDB_CONF, (" returning %08x\n", (u_int)val)); 402 403 return (val); 404 } 405 406 void 407 pci_conf_write(pc, tag, reg, data) 408 pci_chipset_tag_t pc; 409 pcitag_t tag; 410 int reg; 411 pcireg_t data; 412 { 413 struct psycho_pbm *pp = pc->cookie; 414 struct psycho_softc *sc = pp->pp_sc; 415 416 DPRINTF(SPDB_CONF, ("pci_conf_write: tag %lx; reg %x; data %x; ", 417 (long)PCITAG_OFFSET(tag), reg, (int)data)); 418 DPRINTF(SPDB_CONF, ("asi = %x; readaddr = %qx (offset = %x)\n", 419 sc->sc_configaddr._asi, 420 (long long)(sc->sc_configaddr._ptr + PCITAG_OFFSET(tag) + reg), 421 (int)PCITAG_OFFSET(tag) + reg)); 422 423 /* If we don't know it, just punt it. */ 424 if (PCITAG_NODE(tag) == -1) { 425 DPRINTF(SPDB_CONF, ("pci_conf_write: bad addr")); 426 return; 427 } 428 429 bus_space_write_4(sc->sc_configtag, sc->sc_configaddr, 430 PCITAG_OFFSET(tag) + reg, data); 431 } 432 433 static int 434 pci_find_ino(pa, ihp) 435 struct pci_attach_args *pa; 436 pci_intr_handle_t *ihp; 437 { 438 struct psycho_pbm *pp = pa->pa_pc->cookie; 439 struct psycho_softc *sc = pp->pp_sc; 440 u_int dev; 441 u_int ino; 442 443 ino = *ihp; 444 445 if ((ino & ~INTMAP_PCIINT) == 0) { 446 447 if (sc->sc_mode == PSYCHO_MODE_PSYCHO && 448 pp->pp_id == PSYCHO_PBM_B) 449 dev = pa->pa_device - 2; 450 else 451 dev = pa->pa_device - 1; 452 453 DPRINTF(SPDB_CONF, ("pci_find_ino: mode %d, pbm %d, dev %d\n", 454 sc->sc_mode, pp->pp_id, dev)); 455 456 if (ino == 0 || ino > 4) { 457 u_int32_t intreg; 458 459 intreg = pci_conf_read(pa->pa_pc, pa->pa_tag, 460 PCI_INTERRUPT_REG); 461 462 ino = PCI_INTERRUPT_PIN(intreg) - 1; 463 } else 464 ino -= 1; 465 466 ino &= INTMAP_PCIINT; 467 468 ino |= sc->sc_ign; 469 ino |= ((pp->pp_id == PSYCHO_PBM_B) ? INTMAP_PCIBUS : 0); 470 ino |= (dev << 2) & INTMAP_PCISLOT; 471 472 *ihp = ino; 473 } 474 475 return (0); 476 } 477 478 /* 479 * interrupt mapping foo. 480 * XXX: how does this deal with multiple interrupts for a device? 481 */ 482 int 483 pci_intr_map(pa, ihp) 484 struct pci_attach_args *pa; 485 pci_intr_handle_t *ihp; 486 { 487 pcitag_t tag = pa->pa_tag; 488 int interrupts; 489 int len, node = PCITAG_NODE(tag); 490 char devtype[30]; 491 492 len = OF_getproplen(node, "interrupts"); 493 if (len < sizeof(interrupts)) { 494 DPRINTF(SPDB_INTMAP, 495 ("pci_intr_map: interrupts len %d too small\n", len)); 496 return (ENODEV); 497 } 498 if (OF_getprop(node, "interrupts", (void *)&interrupts, 499 sizeof(interrupts)) != len) { 500 DPRINTF(SPDB_INTMAP, 501 ("pci_intr_map: could not read interrupts\n")); 502 return (ENODEV); 503 } 504 505 if (OF_mapintr(node, &interrupts, sizeof(interrupts), 506 sizeof(interrupts)) < 0) { 507 printf("OF_mapintr failed\n"); 508 pci_find_ino(pa, &interrupts); 509 } 510 /* Try to find an IPL for this type of device. */ 511 if (OF_getprop(node, "device_type", &devtype, sizeof(devtype)) > 0) { 512 for (len = 0; intrmap[len].in_class; len++) 513 if (strcmp(intrmap[len].in_class, devtype) == 0) { 514 interrupts |= INTLEVENCODE(intrmap[len].in_lev); 515 break; 516 } 517 } 518 519 /* XXXX -- we use the ino. What if there is a valid IGN? */ 520 *ihp = interrupts; 521 return (0); 522 } 523 524 const char * 525 pci_intr_string(pc, ih) 526 pci_chipset_tag_t pc; 527 pci_intr_handle_t ih; 528 { 529 static char str[16]; 530 531 DPRINTF(SPDB_INTR, ("pci_intr_string: ih %u", ih)); 532 sprintf(str, "ivec %x", ih); 533 DPRINTF(SPDB_INTR, ("; returning %s\n", str)); 534 535 return (str); 536 } 537 538 const struct evcnt * 539 pci_intr_evcnt(pc, ih) 540 pci_chipset_tag_t pc; 541 pci_intr_handle_t ih; 542 { 543 544 /* XXX for now, no evcnt parent reported */ 545 return NULL; 546 } 547 548 void * 549 pci_intr_establish(pc, ih, level, func, arg) 550 pci_chipset_tag_t pc; 551 pci_intr_handle_t ih; 552 int level; 553 int (*func) __P((void *)); 554 void *arg; 555 { 556 void *cookie; 557 struct psycho_pbm *pp = (struct psycho_pbm *)pc->cookie; 558 559 DPRINTF(SPDB_INTR, ("pci_intr_establish: ih %lu; level %d", (u_long)ih, level)); 560 cookie = bus_intr_establish(pp->pp_memt, ih, level, func, arg); 561 562 DPRINTF(SPDB_INTR, ("; returning handle %p\n", cookie)); 563 return (cookie); 564 } 565 566 void 567 pci_intr_disestablish(pc, cookie) 568 pci_chipset_tag_t pc; 569 void *cookie; 570 { 571 572 DPRINTF(SPDB_INTR, ("pci_intr_disestablish: cookie %p\n", cookie)); 573 574 /* XXX */ 575 panic("can't disestablish PCI interrupts yet"); 576 } 577
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