pci_machdep.c revision 1.45.2.2
1 /* $NetBSD: pci_machdep.c,v 1.45.2.2 2004/06/14 04:14:38 jmc Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000 Matthew R. Green 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 23 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 24 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 25 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 /* 32 * functions expected by the MI PCI code. 33 */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: pci_machdep.c,v 1.45.2.2 2004/06/14 04:14:38 jmc Exp $"); 37 38 #include <sys/types.h> 39 #include <sys/param.h> 40 #include <sys/time.h> 41 #include <sys/systm.h> 42 #include <sys/errno.h> 43 #include <sys/device.h> 44 #include <sys/malloc.h> 45 46 #define _SPARC_BUS_DMA_PRIVATE 47 #include <machine/bus.h> 48 #include <machine/autoconf.h> 49 #include <machine/openfirm.h> 50 #include <dev/pci/pcivar.h> 51 #include <dev/pci/pcireg.h> 52 53 #include <dev/ofw/ofw_pci.h> 54 55 #include <sparc64/dev/iommureg.h> 56 #include <sparc64/dev/iommuvar.h> 57 #include <sparc64/dev/psychoreg.h> 58 #include <sparc64/dev/psychovar.h> 59 #include <sparc64/sparc64/cache.h> 60 61 #ifdef DEBUG 62 #define SPDB_CONF 0x01 63 #define SPDB_INTR 0x04 64 #define SPDB_INTMAP 0x08 65 #define SPDB_PROBE 0x20 66 int sparc_pci_debug = 0x0; 67 #define DPRINTF(l, s) do { if (sparc_pci_debug & l) printf s; } while (0) 68 #else 69 #define DPRINTF(l, s) 70 #endif 71 72 /* this is a base to be copied */ 73 struct sparc_pci_chipset _sparc_pci_chipset = { 74 NULL, 75 }; 76 77 static int pci_find_ino(struct pci_attach_args *, pci_intr_handle_t *); 78 79 static pcitag_t 80 ofpci_make_tag(pci_chipset_tag_t pc, int node, int b, int d, int f) 81 { 82 pcitag_t tag; 83 84 tag = PCITAG_CREATE(node, b, d, f); 85 86 /* Enable all the different spaces for this device */ 87 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, 88 PCI_COMMAND_MEM_ENABLE|PCI_COMMAND_MASTER_ENABLE| 89 PCI_COMMAND_IO_ENABLE); 90 return (tag); 91 } 92 93 /* 94 * functions provided to the MI code. 95 */ 96 97 void 98 pci_attach_hook(parent, self, pba) 99 struct device *parent; 100 struct device *self; 101 struct pcibus_attach_args *pba; 102 { 103 } 104 105 int 106 pci_bus_maxdevs(pc, busno) 107 pci_chipset_tag_t pc; 108 int busno; 109 { 110 111 return 32; 112 } 113 114 pcitag_t 115 pci_make_tag(pc, b, d, f) 116 pci_chipset_tag_t pc; 117 int b; 118 int d; 119 int f; 120 { 121 struct psycho_pbm *pp = pc->cookie; 122 struct ofw_pci_register reg; 123 pcitag_t tag; 124 int (*valid) __P((void *)); 125 int node, len; 126 #ifdef DEBUG 127 char name[80]; 128 memset(name, 0, sizeof(name)); 129 #endif 130 131 /* 132 * Refer to the PCI/CardBus bus node first. 133 * It returns a tag if node is present and bus is valid. 134 */ 135 if (0 <= b && b < 256) { 136 node = (*pp->pp_busnode)[b].node; 137 valid = (*pp->pp_busnode)[b].valid; 138 if (node != 0 && d == 0 && 139 (valid == NULL || (*valid)((*pp->pp_busnode)[b].arg))) 140 return ofpci_make_tag(pc, node, b, d, f); 141 } 142 143 /* 144 * Hunt for the node that corresponds to this device 145 * 146 * We could cache this info in an array in the parent 147 * device... except then we have problems with devices 148 * attached below pci-pci bridges, and we would need to 149 * add special code to the pci-pci bridge to cache this 150 * info. 151 */ 152 153 tag = PCITAG_CREATE(-1, b, d, f); 154 node = pc->rootnode; 155 /* 156 * First make sure we're on the right bus. If our parent 157 * has a bus-range property and we're not in the range, 158 * then we're obviously on the wrong bus. So go up one 159 * level. 160 */ 161 #ifdef DEBUG 162 if (sparc_pci_debug & SPDB_PROBE) { 163 printf("curnode %x %s\n", node, 164 prom_getpropstringA(node, "name", name, sizeof(name))); 165 } 166 #endif 167 #if 0 168 while ((OF_getprop(OF_parent(node), "bus-range", (void *)&busrange, 169 sizeof(busrange)) == sizeof(busrange)) && 170 (b < busrange[0] || b > busrange[1])) { 171 /* Out of range, go up one */ 172 node = OF_parent(node); 173 #ifdef DEBUG 174 if (sparc_pci_debug & SPDB_PROBE) { 175 printf("going up to node %x %s\n", node, 176 prom_getpropstringA(node, "name", name, sizeof(name))); 177 } 178 #endif 179 } 180 #endif 181 /* 182 * Now traverse all peers until we find the node or we find 183 * the right bridge. 184 * 185 * XXX We go up one and down one to make sure nobody's missed. 186 * but this should not be necessary. 187 */ 188 for (node = ((node)); node; node = prom_nextsibling(node)) { 189 190 #ifdef DEBUG 191 if (sparc_pci_debug & SPDB_PROBE) { 192 printf("checking node %x %s\n", node, 193 prom_getpropstringA(node, "name", name, sizeof(name))); 194 195 } 196 #endif 197 198 #if 1 199 /* 200 * Check for PCI-PCI bridges. If the device we want is 201 * in the bus-range for that bridge, work our way down. 202 */ 203 while (1) { 204 int busrange[2], *brp; 205 len = 2; 206 brp = busrange; 207 if (prom_getprop(node, "bus-range", sizeof(*brp), 208 &len, &brp) != 0) 209 break; 210 if (len != 2 || b < busrange[0] || b > busrange[1]) 211 break; 212 /* Go down 1 level */ 213 node = prom_firstchild(node); 214 #ifdef DEBUG 215 if (sparc_pci_debug & SPDB_PROBE) { 216 printf("going down to node %x %s\n", node, 217 prom_getpropstringA(node, "name", 218 name, sizeof(name))); 219 } 220 #endif 221 } 222 #endif /*1*/ 223 /* 224 * We only really need the first `reg' property. 225 * 226 * For simplicity, we'll query the `reg' when we 227 * need it. Otherwise we could malloc() it, but 228 * that gets more complicated. 229 */ 230 len = prom_getproplen(node, "reg"); 231 if (len < sizeof(reg)) 232 continue; 233 if (OF_getprop(node, "reg", (void *)®, sizeof(reg)) != len) 234 panic("pci_probe_bus: OF_getprop len botch"); 235 236 if (b != OFW_PCI_PHYS_HI_BUS(reg.phys_hi)) 237 continue; 238 if (d != OFW_PCI_PHYS_HI_DEVICE(reg.phys_hi)) 239 continue; 240 if (f != OFW_PCI_PHYS_HI_FUNCTION(reg.phys_hi)) 241 continue; 242 243 /* Got a match */ 244 tag = ofpci_make_tag(pc, node, b, d, f); 245 246 return (tag); 247 } 248 /* No device found -- return a dead tag */ 249 return (tag); 250 } 251 252 void 253 pci_decompose_tag(pc, tag, bp, dp, fp) 254 pci_chipset_tag_t pc; 255 pcitag_t tag; 256 int *bp, *dp, *fp; 257 { 258 259 if (bp != NULL) 260 *bp = PCITAG_BUS(tag); 261 if (dp != NULL) 262 *dp = PCITAG_DEV(tag); 263 if (fp != NULL) 264 *fp = PCITAG_FUN(tag); 265 } 266 267 int 268 pci_enumerate_bus(struct pci_softc *sc, 269 int (*match)(struct pci_attach_args *), struct pci_attach_args *pap) 270 { 271 struct ofw_pci_register reg; 272 pci_chipset_tag_t pc = sc->sc_pc; 273 pcitag_t tag; 274 pcireg_t class, csr, bhlc, ic; 275 int node, b, d, f, ret; 276 int bus_frequency, lt, cl, cacheline; 277 char name[30]; 278 extern int pci_config_dump; 279 280 if (sc->sc_bridgetag) 281 node = PCITAG_NODE(*sc->sc_bridgetag); 282 else 283 node = pc->rootnode; 284 285 bus_frequency = 286 prom_getpropint(node, "clock-frequency", 33000000) / 1000000; 287 288 /* 289 * Make sure the cache line size is at least as big as the 290 * ecache line and the streaming cache (64 byte). 291 */ 292 cacheline = max(cacheinfo.ec_linesize, 64); 293 KASSERT((cacheline/64)*64 == cacheline && 294 (cacheline/cacheinfo.ec_linesize)*cacheinfo.ec_linesize == cacheline && 295 (cacheline/4)*4 == cacheline); 296 297 /* Turn on parity for the bus. */ 298 tag = ofpci_make_tag(pc, node, sc->sc_bus, 0, 0); 299 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 300 csr |= PCI_COMMAND_PARITY_ENABLE; 301 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 302 303 /* 304 * Initialize the latency timer register. 305 * The value 0x40 is from Solaris. 306 */ 307 bhlc = pci_conf_read(pc, tag, PCI_BHLC_REG); 308 bhlc &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 309 bhlc |= 0x40 << PCI_LATTIMER_SHIFT; 310 pci_conf_write(pc, tag, PCI_BHLC_REG, bhlc); 311 312 if (pci_config_dump) pci_conf_print(pc, tag, NULL); 313 314 for (node = prom_firstchild(node); node != 0 && node != -1; 315 node = prom_nextsibling(node)) { 316 name[0] = name[29] = 0; 317 prom_getpropstringA(node, "name", name, sizeof(name)); 318 319 if (OF_getprop(node, "class-code", &class, sizeof(class)) != 320 sizeof(class)) 321 continue; 322 if (OF_getprop(node, "reg", ®, sizeof(reg)) < sizeof(reg)) 323 panic("pci_enumerate_bus: \"%s\" regs too small", name); 324 325 b = OFW_PCI_PHYS_HI_BUS(reg.phys_hi); 326 d = OFW_PCI_PHYS_HI_DEVICE(reg.phys_hi); 327 f = OFW_PCI_PHYS_HI_FUNCTION(reg.phys_hi); 328 329 if (sc->sc_bus != b) { 330 printf("%s: WARNING: incorrect bus # for \"%s\" " 331 "(%d/%d/%d)\n", sc->sc_dev.dv_xname, name, b, d, f); 332 continue; 333 } 334 335 tag = ofpci_make_tag(pc, node, b, d, f); 336 337 /* 338 * Turn on parity and fast-back-to-back for the device. 339 */ 340 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 341 if (csr & PCI_STATUS_BACKTOBACK_SUPPORT) 342 csr |= PCI_COMMAND_BACKTOBACK_ENABLE; 343 csr |= PCI_COMMAND_PARITY_ENABLE; 344 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 345 346 /* 347 * Initialize the latency timer register for busmaster 348 * devices to work properly. 349 * latency-timer = min-grant * bus-freq / 4 (from FreeBSD) 350 * Also initialize the cache line size register. 351 * Solaris anytime sets this register to the value 0x10. 352 */ 353 bhlc = pci_conf_read(pc, tag, PCI_BHLC_REG); 354 ic = pci_conf_read(pc, tag, PCI_INTERRUPT_REG); 355 356 lt = min(PCI_MIN_GNT(ic) * bus_frequency / 4, 255); 357 if (lt == 0 || lt < PCI_LATTIMER(bhlc)) 358 lt = PCI_LATTIMER(bhlc); 359 360 cl = PCI_CACHELINE(bhlc); 361 if (cl == 0) 362 cl = cacheline; 363 364 bhlc &= ~((PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT) | 365 (PCI_CACHELINE_MASK << PCI_CACHELINE_SHIFT)); 366 bhlc |= (lt << PCI_LATTIMER_SHIFT) | 367 (cl << PCI_CACHELINE_SHIFT); 368 pci_conf_write(pc, tag, PCI_BHLC_REG, bhlc); 369 370 ret = pci_probe_device(sc, tag, match, pap); 371 if (match != NULL && ret != 0) 372 return (ret); 373 } 374 return (0); 375 } 376 377 /* assume we are mapped little-endian/side-effect */ 378 pcireg_t 379 pci_conf_read(pc, tag, reg) 380 pci_chipset_tag_t pc; 381 pcitag_t tag; 382 int reg; 383 { 384 struct psycho_pbm *pp = pc->cookie; 385 struct psycho_softc *sc = pp->pp_sc; 386 pcireg_t val = (pcireg_t)~0; 387 388 DPRINTF(SPDB_CONF, ("pci_conf_read: tag %lx reg %x ", 389 (long)tag, reg)); 390 if (PCITAG_NODE(tag) != -1) { 391 DPRINTF(SPDB_CONF, ("asi=%x addr=%qx (offset=%x) ...", 392 sc->sc_configaddr._asi, 393 (long long)(sc->sc_configaddr._ptr + 394 PCITAG_OFFSET(tag) + reg), 395 (int)PCITAG_OFFSET(tag) + reg)); 396 397 val = bus_space_read_4(sc->sc_configtag, sc->sc_configaddr, 398 PCITAG_OFFSET(tag) + reg); 399 } 400 #ifdef DEBUG 401 else DPRINTF(SPDB_CONF, ("pci_conf_read: bogus pcitag %x\n", 402 (int)PCITAG_OFFSET(tag))); 403 #endif 404 DPRINTF(SPDB_CONF, (" returning %08x\n", (u_int)val)); 405 406 return (val); 407 } 408 409 void 410 pci_conf_write(pc, tag, reg, data) 411 pci_chipset_tag_t pc; 412 pcitag_t tag; 413 int reg; 414 pcireg_t data; 415 { 416 struct psycho_pbm *pp = pc->cookie; 417 struct psycho_softc *sc = pp->pp_sc; 418 419 DPRINTF(SPDB_CONF, ("pci_conf_write: tag %lx; reg %x; data %x; ", 420 (long)PCITAG_OFFSET(tag), reg, (int)data)); 421 DPRINTF(SPDB_CONF, ("asi = %x; readaddr = %qx (offset = %x)\n", 422 sc->sc_configaddr._asi, 423 (long long)(sc->sc_configaddr._ptr + PCITAG_OFFSET(tag) + reg), 424 (int)PCITAG_OFFSET(tag) + reg)); 425 426 /* If we don't know it, just punt it. */ 427 if (PCITAG_NODE(tag) == -1) { 428 DPRINTF(SPDB_CONF, ("pci_conf_write: bad addr")); 429 return; 430 } 431 432 bus_space_write_4(sc->sc_configtag, sc->sc_configaddr, 433 PCITAG_OFFSET(tag) + reg, data); 434 } 435 436 static int 437 pci_find_ino(pa, ihp) 438 struct pci_attach_args *pa; 439 pci_intr_handle_t *ihp; 440 { 441 struct psycho_pbm *pp = pa->pa_pc->cookie; 442 struct psycho_softc *sc = pp->pp_sc; 443 u_int dev; 444 u_int ino; 445 446 DPRINTF(SPDB_INTMAP, ("pci_find_ino: pa_tag: node %x, %d:%d:%d\n", 447 PCITAG_NODE(pa->pa_tag), (int)PCITAG_BUS(pa->pa_tag), 448 (int)PCITAG_DEV(pa->pa_tag), 449 (int)PCITAG_FUN(pa->pa_tag))); 450 DPRINTF(SPDB_INTMAP, 451 ("pci_find_ino: intrswiz %d, intrpin %d, intrline %d, rawintrpin %d\n", 452 pa->pa_intrswiz, pa->pa_intrpin, pa->pa_intrline, pa->pa_rawintrpin)); 453 DPRINTF(SPDB_INTMAP, ("pci_find_ino: pa_intrtag: node %x, %d:%d:%d\n", 454 PCITAG_NODE(pa->pa_intrtag), 455 (int)PCITAG_BUS(pa->pa_intrtag), 456 (int)PCITAG_DEV(pa->pa_intrtag), 457 (int)PCITAG_FUN(pa->pa_intrtag))); 458 459 ino = *ihp; 460 461 if ((ino & ~INTMAP_PCIINT) == 0) { 462 463 if (pa->pa_intrswiz != 0 && PCITAG_NODE(pa->pa_intrtag) != 0) 464 dev = PCITAG_DEV(pa->pa_intrtag); 465 else 466 dev = pa->pa_device; 467 468 if (sc->sc_mode == PSYCHO_MODE_PSYCHO && 469 pp->pp_id == PSYCHO_PBM_B) 470 dev -= 2; 471 else 472 dev--; 473 474 DPRINTF(SPDB_INTMAP, ("pci_find_ino: mode %d, pbm %d, dev %d, ino %d\n", 475 sc->sc_mode, pp->pp_id, dev, ino)); 476 477 ino = (pa->pa_intrpin - 1) & INTMAP_PCIINT; 478 479 ino |= sc->sc_ign; 480 ino |= ((pp->pp_id == PSYCHO_PBM_B) ? INTMAP_PCIBUS : 0); 481 ino |= (dev << 2) & INTMAP_PCISLOT; 482 483 *ihp = ino; 484 } 485 486 return (0); 487 } 488 489 /* 490 * interrupt mapping foo. 491 * XXX: how does this deal with multiple interrupts for a device? 492 */ 493 int 494 pci_intr_map(pa, ihp) 495 struct pci_attach_args *pa; 496 pci_intr_handle_t *ihp; 497 { 498 pcitag_t tag = pa->pa_tag; 499 int interrupts, *intp; 500 int len, node = PCITAG_NODE(tag); 501 char devtype[30]; 502 503 intp = &interrupts; 504 len = 1; 505 if (prom_getprop(node, "interrupts", sizeof(interrupts), 506 &len, &intp) != 0 || len != 1) { 507 DPRINTF(SPDB_INTMAP, 508 ("pci_intr_map: could not read interrupts\n")); 509 return (ENODEV); 510 } 511 512 if (OF_mapintr(node, &interrupts, sizeof(interrupts), 513 sizeof(interrupts)) < 0) { 514 printf("OF_mapintr failed\n"); 515 pci_find_ino(pa, &interrupts); 516 } 517 518 /* Try to find an IPL for this type of device. */ 519 prom_getpropstringA(node, "device_type", devtype, sizeof(devtype)); 520 for (len = 0; intrmap[len].in_class != NULL; len++) 521 if (strcmp(intrmap[len].in_class, devtype) == 0) { 522 interrupts |= INTLEVENCODE(intrmap[len].in_lev); 523 break; 524 } 525 526 /* XXXX -- we use the ino. What if there is a valid IGN? */ 527 *ihp = interrupts; 528 return (0); 529 } 530 531 const char * 532 pci_intr_string(pc, ih) 533 pci_chipset_tag_t pc; 534 pci_intr_handle_t ih; 535 { 536 static char str[16]; 537 538 DPRINTF(SPDB_INTR, ("pci_intr_string: ih %u", ih)); 539 sprintf(str, "ivec %x", ih); 540 DPRINTF(SPDB_INTR, ("; returning %s\n", str)); 541 542 return (str); 543 } 544 545 const struct evcnt * 546 pci_intr_evcnt(pc, ih) 547 pci_chipset_tag_t pc; 548 pci_intr_handle_t ih; 549 { 550 551 /* XXX for now, no evcnt parent reported */ 552 return NULL; 553 } 554 555 void * 556 pci_intr_establish(pc, ih, level, func, arg) 557 pci_chipset_tag_t pc; 558 pci_intr_handle_t ih; 559 int level; 560 int (*func) __P((void *)); 561 void *arg; 562 { 563 void *cookie; 564 struct psycho_pbm *pp = (struct psycho_pbm *)pc->cookie; 565 566 DPRINTF(SPDB_INTR, ("pci_intr_establish: ih %lu; level %d", (u_long)ih, level)); 567 cookie = bus_intr_establish(pp->pp_memt, ih, level, func, arg); 568 569 DPRINTF(SPDB_INTR, ("; returning handle %p\n", cookie)); 570 return (cookie); 571 } 572 573 void 574 pci_intr_disestablish(pc, cookie) 575 pci_chipset_tag_t pc; 576 void *cookie; 577 { 578 579 DPRINTF(SPDB_INTR, ("pci_intr_disestablish: cookie %p\n", cookie)); 580 581 /* XXX */ 582 panic("can't disestablish PCI interrupts yet"); 583 } 584
Indexes created Thu Oct 16 14:10:15 GMT 2025