pci_machdep.c revision 1.46
1 /* $NetBSD: pci_machdep.c,v 1.46 2004/04/04 11:53:40 nakayama Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000 Matthew R. Green 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 23 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 24 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 25 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 /* 32 * functions expected by the MI PCI code. 33 */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: pci_machdep.c,v 1.46 2004/04/04 11:53:40 nakayama Exp $"); 37 38 #include <sys/types.h> 39 #include <sys/param.h> 40 #include <sys/time.h> 41 #include <sys/systm.h> 42 #include <sys/errno.h> 43 #include <sys/device.h> 44 #include <sys/malloc.h> 45 46 #define _SPARC_BUS_DMA_PRIVATE 47 #include <machine/bus.h> 48 #include <machine/autoconf.h> 49 #include <machine/openfirm.h> 50 #include <dev/pci/pcivar.h> 51 #include <dev/pci/pcireg.h> 52 53 #include <dev/ofw/ofw_pci.h> 54 55 #include <sparc64/dev/iommureg.h> 56 #include <sparc64/dev/iommuvar.h> 57 #include <sparc64/dev/psychoreg.h> 58 #include <sparc64/dev/psychovar.h> 59 #include <sparc64/sparc64/cache.h> 60 61 #ifdef DEBUG 62 #define SPDB_CONF 0x01 63 #define SPDB_INTR 0x04 64 #define SPDB_INTMAP 0x08 65 #define SPDB_INTFIX 0x10 66 #define SPDB_PROBE 0x20 67 int sparc_pci_debug = 0x0; 68 #define DPRINTF(l, s) do { if (sparc_pci_debug & l) printf s; } while (0) 69 #else 70 #define DPRINTF(l, s) 71 #endif 72 73 /* this is a base to be copied */ 74 struct sparc_pci_chipset _sparc_pci_chipset = { 75 NULL, 76 }; 77 78 static int pci_find_ino(struct pci_attach_args *, pci_intr_handle_t *); 79 80 static pcitag_t 81 ofpci_make_tag(pci_chipset_tag_t pc, int node, int b, int d, int f) 82 { 83 pcitag_t tag; 84 85 tag = PCITAG_CREATE(node, b, d, f); 86 87 /* Enable all the different spaces for this device */ 88 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, 89 PCI_COMMAND_MEM_ENABLE|PCI_COMMAND_MASTER_ENABLE| 90 PCI_COMMAND_IO_ENABLE); 91 return (tag); 92 } 93 94 /* 95 * functions provided to the MI code. 96 */ 97 98 void 99 pci_attach_hook(parent, self, pba) 100 struct device *parent; 101 struct device *self; 102 struct pcibus_attach_args *pba; 103 { 104 } 105 106 int 107 pci_bus_maxdevs(pc, busno) 108 pci_chipset_tag_t pc; 109 int busno; 110 { 111 112 return 32; 113 } 114 115 pcitag_t 116 pci_make_tag(pc, b, d, f) 117 pci_chipset_tag_t pc; 118 int b; 119 int d; 120 int f; 121 { 122 struct psycho_pbm *pp = pc->cookie; 123 struct ofw_pci_register reg; 124 pcitag_t tag; 125 int (*valid) __P((void *)); 126 int node, len; 127 #ifdef DEBUG 128 char name[80]; 129 memset(name, 0, sizeof(name)); 130 #endif 131 132 /* 133 * Refer to the PCI/CardBus bus node first. 134 * It returns a tag if node is present and bus is valid. 135 */ 136 if (0 <= b && b < 256) { 137 node = (*pp->pp_busnode)[b].node; 138 valid = (*pp->pp_busnode)[b].valid; 139 if (node != 0 && d == 0 && 140 (valid == NULL || (*valid)((*pp->pp_busnode)[b].arg))) 141 return ofpci_make_tag(pc, node, b, d, f); 142 } 143 144 /* 145 * Hunt for the node that corresponds to this device 146 * 147 * We could cache this info in an array in the parent 148 * device... except then we have problems with devices 149 * attached below pci-pci bridges, and we would need to 150 * add special code to the pci-pci bridge to cache this 151 * info. 152 */ 153 154 tag = PCITAG_CREATE(-1, b, d, f); 155 node = pc->rootnode; 156 /* 157 * First make sure we're on the right bus. If our parent 158 * has a bus-range property and we're not in the range, 159 * then we're obviously on the wrong bus. So go up one 160 * level. 161 */ 162 #ifdef DEBUG 163 if (sparc_pci_debug & SPDB_PROBE) { 164 printf("curnode %x %s\n", node, 165 prom_getpropstringA(node, "name", name, sizeof(name))); 166 } 167 #endif 168 #if 0 169 while ((OF_getprop(OF_parent(node), "bus-range", (void *)&busrange, 170 sizeof(busrange)) == sizeof(busrange)) && 171 (b < busrange[0] || b > busrange[1])) { 172 /* Out of range, go up one */ 173 node = OF_parent(node); 174 #ifdef DEBUG 175 if (sparc_pci_debug & SPDB_PROBE) { 176 printf("going up to node %x %s\n", node, 177 prom_getpropstringA(node, "name", name, sizeof(name))); 178 } 179 #endif 180 } 181 #endif 182 /* 183 * Now traverse all peers until we find the node or we find 184 * the right bridge. 185 * 186 * XXX We go up one and down one to make sure nobody's missed. 187 * but this should not be necessary. 188 */ 189 for (node = ((node)); node; node = prom_nextsibling(node)) { 190 191 #ifdef DEBUG 192 if (sparc_pci_debug & SPDB_PROBE) { 193 printf("checking node %x %s\n", node, 194 prom_getpropstringA(node, "name", name, sizeof(name))); 195 196 } 197 #endif 198 199 #if 1 200 /* 201 * Check for PCI-PCI bridges. If the device we want is 202 * in the bus-range for that bridge, work our way down. 203 */ 204 while (1) { 205 int busrange[2], *brp; 206 len = 2; 207 brp = busrange; 208 if (prom_getprop(node, "bus-range", sizeof(*brp), 209 &len, &brp) != 0) 210 break; 211 if (len != 2 || b < busrange[0] || b > busrange[1]) 212 break; 213 /* Go down 1 level */ 214 node = prom_firstchild(node); 215 #ifdef DEBUG 216 if (sparc_pci_debug & SPDB_PROBE) { 217 printf("going down to node %x %s\n", node, 218 prom_getpropstringA(node, "name", 219 name, sizeof(name))); 220 } 221 #endif 222 } 223 #endif /*1*/ 224 /* 225 * We only really need the first `reg' property. 226 * 227 * For simplicity, we'll query the `reg' when we 228 * need it. Otherwise we could malloc() it, but 229 * that gets more complicated. 230 */ 231 len = prom_getproplen(node, "reg"); 232 if (len < sizeof(reg)) 233 continue; 234 if (OF_getprop(node, "reg", (void *)®, sizeof(reg)) != len) 235 panic("pci_probe_bus: OF_getprop len botch"); 236 237 if (b != OFW_PCI_PHYS_HI_BUS(reg.phys_hi)) 238 continue; 239 if (d != OFW_PCI_PHYS_HI_DEVICE(reg.phys_hi)) 240 continue; 241 if (f != OFW_PCI_PHYS_HI_FUNCTION(reg.phys_hi)) 242 continue; 243 244 /* Got a match */ 245 tag = ofpci_make_tag(pc, node, b, d, f); 246 247 return (tag); 248 } 249 /* No device found -- return a dead tag */ 250 return (tag); 251 } 252 253 void 254 pci_decompose_tag(pc, tag, bp, dp, fp) 255 pci_chipset_tag_t pc; 256 pcitag_t tag; 257 int *bp, *dp, *fp; 258 { 259 260 if (bp != NULL) 261 *bp = PCITAG_BUS(tag); 262 if (dp != NULL) 263 *dp = PCITAG_DEV(tag); 264 if (fp != NULL) 265 *fp = PCITAG_FUN(tag); 266 } 267 268 int 269 pci_enumerate_bus(struct pci_softc *sc, 270 int (*match)(struct pci_attach_args *), struct pci_attach_args *pap) 271 { 272 struct ofw_pci_register reg; 273 pci_chipset_tag_t pc = sc->sc_pc; 274 pcitag_t tag; 275 pcireg_t class, csr, bhlc, ic; 276 int node, b, d, f, ret; 277 int bus_frequency, lt, cl, cacheline; 278 char name[30]; 279 extern int pci_config_dump; 280 281 if (sc->sc_bridgetag) 282 node = PCITAG_NODE(*sc->sc_bridgetag); 283 else 284 node = pc->rootnode; 285 286 bus_frequency = 287 prom_getpropint(node, "clock-frequency", 33000000) / 1000000; 288 289 /* 290 * Make sure the cache line size is at least as big as the 291 * ecache line and the streaming cache (64 byte). 292 */ 293 cacheline = max(cacheinfo.ec_linesize, 64); 294 KASSERT((cacheline/64)*64 == cacheline && 295 (cacheline/cacheinfo.ec_linesize)*cacheinfo.ec_linesize == cacheline && 296 (cacheline/4)*4 == cacheline); 297 298 /* Turn on parity for the bus. */ 299 tag = ofpci_make_tag(pc, node, sc->sc_bus, 0, 0); 300 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 301 csr |= PCI_COMMAND_PARITY_ENABLE; 302 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 303 304 /* 305 * Initialize the latency timer register. 306 * The value 0x40 is from Solaris. 307 */ 308 bhlc = pci_conf_read(pc, tag, PCI_BHLC_REG); 309 bhlc &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 310 bhlc |= 0x40 << PCI_LATTIMER_SHIFT; 311 pci_conf_write(pc, tag, PCI_BHLC_REG, bhlc); 312 313 if (pci_config_dump) pci_conf_print(pc, tag, NULL); 314 315 for (node = prom_firstchild(node); node != 0 && node != -1; 316 node = prom_nextsibling(node)) { 317 name[0] = name[29] = 0; 318 prom_getpropstringA(node, "name", name, sizeof(name)); 319 320 if (OF_getprop(node, "class-code", &class, sizeof(class)) != 321 sizeof(class)) 322 continue; 323 if (OF_getprop(node, "reg", ®, sizeof(reg)) < sizeof(reg)) 324 panic("pci_enumerate_bus: \"%s\" regs too small", name); 325 326 b = OFW_PCI_PHYS_HI_BUS(reg.phys_hi); 327 d = OFW_PCI_PHYS_HI_DEVICE(reg.phys_hi); 328 f = OFW_PCI_PHYS_HI_FUNCTION(reg.phys_hi); 329 330 if (sc->sc_bus != b) { 331 printf("%s: WARNING: incorrect bus # for \"%s\" " 332 "(%d/%d/%d)\n", sc->sc_dev.dv_xname, name, b, d, f); 333 continue; 334 } 335 336 tag = ofpci_make_tag(pc, node, b, d, f); 337 338 /* 339 * Turn on parity and fast-back-to-back for the device. 340 */ 341 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 342 if (csr & PCI_STATUS_BACKTOBACK_SUPPORT) 343 csr |= PCI_COMMAND_BACKTOBACK_ENABLE; 344 csr |= PCI_COMMAND_PARITY_ENABLE; 345 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 346 347 /* 348 * Initialize the latency timer register for busmaster 349 * devices to work properly. 350 * latency-timer = min-grant * bus-freq / 4 (from FreeBSD) 351 * Also initialize the cache line size register. 352 * Solaris anytime sets this register to the value 0x10. 353 */ 354 bhlc = pci_conf_read(pc, tag, PCI_BHLC_REG); 355 ic = pci_conf_read(pc, tag, PCI_INTERRUPT_REG); 356 357 lt = min(PCI_MIN_GNT(ic) * bus_frequency / 4, 255); 358 if (lt == 0 || lt < PCI_LATTIMER(bhlc)) 359 lt = PCI_LATTIMER(bhlc); 360 361 cl = PCI_CACHELINE(bhlc); 362 if (cl == 0) 363 cl = cacheline; 364 365 bhlc &= ~((PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT) | 366 (PCI_CACHELINE_MASK << PCI_CACHELINE_SHIFT)); 367 bhlc |= (lt << PCI_LATTIMER_SHIFT) | 368 (cl << PCI_CACHELINE_SHIFT); 369 pci_conf_write(pc, tag, PCI_BHLC_REG, bhlc); 370 371 ret = pci_probe_device(sc, tag, match, pap); 372 if (match != NULL && ret != 0) 373 return (ret); 374 } 375 return (0); 376 } 377 378 /* assume we are mapped little-endian/side-effect */ 379 pcireg_t 380 pci_conf_read(pc, tag, reg) 381 pci_chipset_tag_t pc; 382 pcitag_t tag; 383 int reg; 384 { 385 struct psycho_pbm *pp = pc->cookie; 386 struct psycho_softc *sc = pp->pp_sc; 387 pcireg_t val = (pcireg_t)~0; 388 389 DPRINTF(SPDB_CONF, ("pci_conf_read: tag %lx reg %x ", 390 (long)tag, reg)); 391 if (PCITAG_NODE(tag) != -1) { 392 DPRINTF(SPDB_CONF, ("asi=%x addr=%qx (offset=%x) ...", 393 sc->sc_configaddr._asi, 394 (long long)(sc->sc_configaddr._ptr + 395 PCITAG_OFFSET(tag) + reg), 396 (int)PCITAG_OFFSET(tag) + reg)); 397 398 val = bus_space_read_4(sc->sc_configtag, sc->sc_configaddr, 399 PCITAG_OFFSET(tag) + reg); 400 } 401 #ifdef DEBUG 402 else DPRINTF(SPDB_CONF, ("pci_conf_read: bogus pcitag %x\n", 403 (int)PCITAG_OFFSET(tag))); 404 #endif 405 DPRINTF(SPDB_CONF, (" returning %08x\n", (u_int)val)); 406 407 return (val); 408 } 409 410 void 411 pci_conf_write(pc, tag, reg, data) 412 pci_chipset_tag_t pc; 413 pcitag_t tag; 414 int reg; 415 pcireg_t data; 416 { 417 struct psycho_pbm *pp = pc->cookie; 418 struct psycho_softc *sc = pp->pp_sc; 419 420 DPRINTF(SPDB_CONF, ("pci_conf_write: tag %lx; reg %x; data %x; ", 421 (long)PCITAG_OFFSET(tag), reg, (int)data)); 422 DPRINTF(SPDB_CONF, ("asi = %x; readaddr = %qx (offset = %x)\n", 423 sc->sc_configaddr._asi, 424 (long long)(sc->sc_configaddr._ptr + PCITAG_OFFSET(tag) + reg), 425 (int)PCITAG_OFFSET(tag) + reg)); 426 427 /* If we don't know it, just punt it. */ 428 if (PCITAG_NODE(tag) == -1) { 429 DPRINTF(SPDB_CONF, ("pci_conf_write: bad addr")); 430 return; 431 } 432 433 bus_space_write_4(sc->sc_configtag, sc->sc_configaddr, 434 PCITAG_OFFSET(tag) + reg, data); 435 } 436 437 static int 438 pci_find_ino(pa, ihp) 439 struct pci_attach_args *pa; 440 pci_intr_handle_t *ihp; 441 { 442 struct psycho_pbm *pp = pa->pa_pc->cookie; 443 struct psycho_softc *sc = pp->pp_sc; 444 u_int dev; 445 u_int ino; 446 447 ino = *ihp; 448 449 if ((ino & ~INTMAP_PCIINT) == 0) { 450 451 if (sc->sc_mode == PSYCHO_MODE_PSYCHO && 452 pp->pp_id == PSYCHO_PBM_B) 453 dev = pa->pa_device - 2; 454 else 455 dev = pa->pa_device - 1; 456 457 DPRINTF(SPDB_CONF, ("pci_find_ino: mode %d, pbm %d, dev %d\n", 458 sc->sc_mode, pp->pp_id, dev)); 459 460 if (ino == 0 || ino > 4) { 461 u_int32_t intreg; 462 463 intreg = pci_conf_read(pa->pa_pc, pa->pa_tag, 464 PCI_INTERRUPT_REG); 465 466 ino = PCI_INTERRUPT_PIN(intreg) - 1; 467 } else 468 ino -= 1; 469 470 ino &= INTMAP_PCIINT; 471 472 ino |= sc->sc_ign; 473 ino |= ((pp->pp_id == PSYCHO_PBM_B) ? INTMAP_PCIBUS : 0); 474 ino |= (dev << 2) & INTMAP_PCISLOT; 475 476 *ihp = ino; 477 } 478 479 return (0); 480 } 481 482 /* 483 * interrupt mapping foo. 484 * XXX: how does this deal with multiple interrupts for a device? 485 */ 486 int 487 pci_intr_map(pa, ihp) 488 struct pci_attach_args *pa; 489 pci_intr_handle_t *ihp; 490 { 491 pcitag_t tag = pa->pa_tag; 492 int interrupts, *intp; 493 int len, node = PCITAG_NODE(tag); 494 char devtype[30]; 495 496 intp = &interrupts; 497 len = 1; 498 if (prom_getprop(node, "interrupts", sizeof(interrupts), 499 &len, &intp) != 0 || len != 1) { 500 DPRINTF(SPDB_INTMAP, 501 ("pci_intr_map: could not read interrupts\n")); 502 return (ENODEV); 503 } 504 505 if (OF_mapintr(node, &interrupts, sizeof(interrupts), 506 sizeof(interrupts)) < 0) { 507 printf("OF_mapintr failed\n"); 508 pci_find_ino(pa, &interrupts); 509 } 510 511 /* Try to find an IPL for this type of device. */ 512 prom_getpropstringA(node, "device_type", devtype, sizeof(devtype)); 513 for (len = 0; intrmap[len].in_class != NULL; len++) 514 if (strcmp(intrmap[len].in_class, devtype) == 0) { 515 interrupts |= INTLEVENCODE(intrmap[len].in_lev); 516 break; 517 } 518 519 /* XXXX -- we use the ino. What if there is a valid IGN? */ 520 *ihp = interrupts; 521 return (0); 522 } 523 524 const char * 525 pci_intr_string(pc, ih) 526 pci_chipset_tag_t pc; 527 pci_intr_handle_t ih; 528 { 529 static char str[16]; 530 531 DPRINTF(SPDB_INTR, ("pci_intr_string: ih %u", ih)); 532 sprintf(str, "ivec %x", ih); 533 DPRINTF(SPDB_INTR, ("; returning %s\n", str)); 534 535 return (str); 536 } 537 538 const struct evcnt * 539 pci_intr_evcnt(pc, ih) 540 pci_chipset_tag_t pc; 541 pci_intr_handle_t ih; 542 { 543 544 /* XXX for now, no evcnt parent reported */ 545 return NULL; 546 } 547 548 void * 549 pci_intr_establish(pc, ih, level, func, arg) 550 pci_chipset_tag_t pc; 551 pci_intr_handle_t ih; 552 int level; 553 int (*func) __P((void *)); 554 void *arg; 555 { 556 void *cookie; 557 struct psycho_pbm *pp = (struct psycho_pbm *)pc->cookie; 558 559 DPRINTF(SPDB_INTR, ("pci_intr_establish: ih %lu; level %d", (u_long)ih, level)); 560 cookie = bus_intr_establish(pp->pp_memt, ih, level, func, arg); 561 562 DPRINTF(SPDB_INTR, ("; returning handle %p\n", cookie)); 563 return (cookie); 564 } 565 566 void 567 pci_intr_disestablish(pc, cookie) 568 pci_chipset_tag_t pc; 569 void *cookie; 570 { 571 572 DPRINTF(SPDB_INTR, ("pci_intr_disestablish: cookie %p\n", cookie)); 573 574 /* XXX */ 575 panic("can't disestablish PCI interrupts yet"); 576 } 577
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