pci_machdep.c revision 1.77.28.1
1 /* $NetBSD: pci_machdep.c,v 1.77.28.1 2018/09/06 06:55:42 pgoyette Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000 Matthew R. Green 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * functions expected by the MI PCI code. 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: pci_machdep.c,v 1.77.28.1 2018/09/06 06:55:42 pgoyette Exp $"); 35 36 #include <sys/types.h> 37 #include <sys/param.h> 38 #include <sys/time.h> 39 #include <sys/systm.h> 40 #include <sys/errno.h> 41 #include <sys/device.h> 42 #include <sys/malloc.h> 43 44 #define _SPARC_BUS_DMA_PRIVATE 45 #include <sys/bus.h> 46 #include <machine/autoconf.h> 47 #include <machine/openfirm.h> 48 #include <dev/pci/pcivar.h> 49 #include <dev/pci/pcireg.h> 50 51 #include <dev/ofw/ofw_pci.h> 52 53 #include <sparc64/dev/iommureg.h> 54 #include <sparc64/sparc64/cache.h> 55 56 #include "locators.h" 57 58 #ifdef DEBUG 59 #define SPDB_CONF 0x01 60 #define SPDB_INTR 0x04 61 #define SPDB_INTMAP 0x08 62 #define SPDB_PROBE 0x20 63 #define SPDB_TAG 0x40 64 int sparc_pci_debug = 0x0; 65 #define DPRINTF(l, s) do { if (sparc_pci_debug & l) printf s; } while (0) 66 #else 67 #define DPRINTF(l, s) 68 #endif 69 70 /* this is a base to be copied */ 71 struct sparc_pci_chipset _sparc_pci_chipset = { 72 .cookie = NULL, 73 }; 74 75 static pcitag_t 76 ofpci_make_tag(pci_chipset_tag_t pc, int node, int b, int d, int f) 77 { 78 pcitag_t tag; 79 pcireg_t reg; 80 81 tag = PCITAG_CREATE(node, b, d, f); 82 83 DPRINTF(SPDB_TAG, 84 ("%s: creating tag for node %x bus %d dev %d fn %d\n", 85 __func__, node, b, d, f)); 86 87 /* Enable all the different spaces for this device */ 88 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 89 reg |= PCI_COMMAND_MEM_ENABLE|PCI_COMMAND_MASTER_ENABLE| 90 PCI_COMMAND_IO_ENABLE; 91 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, reg); 92 93 return (tag); 94 } 95 96 /* 97 * functions provided to the MI code. 98 */ 99 100 void 101 pci_attach_hook(device_t parent, device_t self, 102 struct pcibus_attach_args *pba) 103 { 104 } 105 106 int 107 pci_bus_maxdevs(pci_chipset_tag_t pc, int busno) 108 { 109 110 return 32; 111 } 112 113 pcitag_t 114 pci_make_tag(pci_chipset_tag_t pc, int b, int d, int f) 115 { 116 struct ofw_pci_register reg; 117 pcitag_t tag; 118 int (*valid)(void *); 119 int node, len; 120 #ifdef DEBUG 121 char name[80]; 122 memset(name, 0, sizeof(name)); 123 #endif 124 125 /* 126 * Refer to the PCI/CardBus bus node first. 127 * It returns a tag if node is present and bus is valid. 128 */ 129 if (0 <= b && b < 256) { 130 KASSERT(pc->spc_busnode != NULL); 131 node = (*pc->spc_busnode)[b].node; 132 valid = (*pc->spc_busnode)[b].valid; 133 if (node != 0 && d == 0 && 134 (valid == NULL || (*valid)((*pc->spc_busnode)[b].arg))) 135 return ofpci_make_tag(pc, node, b, d, f); 136 } 137 138 /* 139 * Hunt for the node that corresponds to this device 140 * 141 * We could cache this info in an array in the parent 142 * device... except then we have problems with devices 143 * attached below pci-pci bridges, and we would need to 144 * add special code to the pci-pci bridge to cache this 145 * info. 146 */ 147 148 tag = PCITAG_CREATE(-1, b, d, f); 149 node = pc->rootnode; 150 /* 151 * First make sure we're on the right bus. If our parent 152 * has a bus-range property and we're not in the range, 153 * then we're obviously on the wrong bus. So go up one 154 * level. 155 */ 156 DPRINTF(SPDB_PROBE, ("curnode %x %s\n", node, 157 prom_getpropstringA(node, "name", name, sizeof(name)))); 158 #if 0 159 while ((OF_getprop(OF_parent(node), "bus-range", (void *)&busrange, 160 sizeof(busrange)) == sizeof(busrange)) && 161 (b < busrange[0] || b > busrange[1])) { 162 /* Out of range, go up one */ 163 node = OF_parent(node); 164 DPRINTF(SPDB_PROBE, printf("going up to node %x %s\n", 165 node, 166 prom_getpropstringA(node, "name", name, sizeof(name)))); 167 } 168 #endif 169 node = prom_firstchild(node); 170 /* 171 * Now traverse all peers until we find the node or we find 172 * the right bridge. 173 * 174 * XXX We go up one and down one to make sure nobody's missed. 175 * but this should not be necessary. 176 */ 177 for (node = ((node)); node; node = prom_nextsibling(node)) { 178 179 DPRINTF(SPDB_PROBE, ("checking node %x %s\n", node, 180 prom_getpropstringA(node, "name", name, sizeof(name)))); 181 182 #if 1 183 /* 184 * Check for PCI-PCI bridges. If the device we want is 185 * in the bus-range for that bridge, work our way down. 186 */ 187 while (1) { 188 int busrange[2], *brp; 189 len = 2; 190 brp = busrange; 191 if (prom_getprop(node, "bus-range", sizeof(*brp), 192 &len, &brp) != 0) 193 break; 194 if (len != 2 || b < busrange[0] || b > busrange[1]) 195 break; 196 /* Go down 1 level */ 197 node = prom_firstchild(node); 198 DPRINTF(SPDB_PROBE, ("going down to node %x %s\n", node, 199 prom_getpropstringA(node, "name", name, 200 sizeof(name)))); 201 } 202 #endif /*1*/ 203 /* 204 * We only really need the first `reg' property. 205 * 206 * For simplicity, we'll query the `reg' when we 207 * need it. Otherwise we could malloc() it, but 208 * that gets more complicated. 209 */ 210 len = prom_getproplen(node, "reg"); 211 if (len < sizeof(reg)) 212 continue; 213 if (OF_getprop(node, "reg", (void *)®, sizeof(reg)) != len) 214 panic("pci_probe_bus: OF_getprop len botch"); 215 216 if (b != OFW_PCI_PHYS_HI_BUS(reg.phys_hi)) 217 continue; 218 if (d != OFW_PCI_PHYS_HI_DEVICE(reg.phys_hi)) 219 continue; 220 if (f != OFW_PCI_PHYS_HI_FUNCTION(reg.phys_hi)) 221 continue; 222 223 /* Got a match */ 224 tag = ofpci_make_tag(pc, node, b, d, f); 225 226 return (tag); 227 } 228 /* No device found -- return a dead tag */ 229 return (tag); 230 } 231 232 void 233 pci_decompose_tag(pci_chipset_tag_t pc, pcitag_t tag, int *bp, int *dp, int *fp) 234 { 235 236 if (bp != NULL) 237 *bp = PCITAG_BUS(tag); 238 if (dp != NULL) 239 *dp = PCITAG_DEV(tag); 240 if (fp != NULL) 241 *fp = PCITAG_FUN(tag); 242 } 243 244 int 245 sparc64_pci_enumerate_bus(struct pci_softc *sc, const int *locators, 246 int (*match)(const struct pci_attach_args *), struct pci_attach_args *pap) 247 { 248 struct ofw_pci_register reg; 249 pci_chipset_tag_t pc = sc->sc_pc; 250 pcitag_t tag; 251 pcireg_t class, csr, bhlc, ic; 252 int node, b, d, f, ret; 253 int bus_frequency, lt, cl, cacheline; 254 char name[30]; 255 #if 0 256 extern int pci_config_dump; 257 #endif 258 259 if (sc->sc_bridgetag) 260 node = PCITAG_NODE(*sc->sc_bridgetag); 261 else 262 node = pc->rootnode; 263 264 bus_frequency = 265 prom_getpropint(node, "clock-frequency", 33000000) / 1000000; 266 267 /* 268 * Make sure the cache line size is at least as big as the 269 * ecache line and the streaming cache (64 byte). 270 */ 271 cacheline = uimax(ecache_min_line_size, 64); 272 KASSERT((cacheline/64)*64 == cacheline && 273 (cacheline/ecache_min_line_size)*ecache_min_line_size == cacheline && 274 (cacheline/4)*4 == cacheline); 275 276 #if 0 277 /* 278 * XXX this faults on Fire PCIe controllers. 279 * XXX move into the psycho and schizo driver front ends. 280 */ 281 /* Turn on parity for the bus. */ 282 tag = ofpci_make_tag(pc, node, sc->sc_bus, 0, 0); 283 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 284 csr |= PCI_COMMAND_PARITY_ENABLE; 285 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 286 287 /* 288 * Initialize the latency timer register. 289 * The value 0x40 is from Solaris. 290 */ 291 bhlc = pci_conf_read(pc, tag, PCI_BHLC_REG); 292 bhlc &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 293 bhlc |= 0x40 << PCI_LATTIMER_SHIFT; 294 pci_conf_write(pc, tag, PCI_BHLC_REG, bhlc); 295 296 if (pci_config_dump) 297 pci_conf_print(pc, tag, NULL); 298 #endif 299 300 for (node = prom_firstchild(node); node != 0 && node != -1; 301 node = prom_nextsibling(node)) { 302 name[0] = name[29] = 0; 303 prom_getpropstringA(node, "name", name, sizeof(name)); 304 305 if (OF_getprop(node, "class-code", &class, sizeof(class)) != 306 sizeof(class)) 307 continue; 308 if (OF_getprop(node, "reg", ®, sizeof(reg)) < sizeof(reg)) 309 panic("pci_enumerate_bus: \"%s\" regs too small", name); 310 311 b = OFW_PCI_PHYS_HI_BUS(reg.phys_hi); 312 d = OFW_PCI_PHYS_HI_DEVICE(reg.phys_hi); 313 f = OFW_PCI_PHYS_HI_FUNCTION(reg.phys_hi); 314 315 if (sc->sc_bus != b) { 316 aprint_error_dev(sc->sc_dev, "WARNING: incorrect " 317 "bus # for \"%s\" (%d/%d/%d)\n", name, b, d, f); 318 continue; 319 } 320 if ((locators[PCICF_DEV] != PCICF_DEV_DEFAULT) && 321 (locators[PCICF_DEV] != d)) 322 continue; 323 if ((locators[PCICF_FUNCTION] != PCICF_FUNCTION_DEFAULT) && 324 (locators[PCICF_FUNCTION] != f)) 325 continue; 326 327 tag = ofpci_make_tag(pc, node, b, d, f); 328 329 /* 330 * Turn on parity and fast-back-to-back for the device. 331 */ 332 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 333 if (csr & PCI_STATUS_BACKTOBACK_SUPPORT) 334 csr |= PCI_COMMAND_BACKTOBACK_ENABLE; 335 csr |= PCI_COMMAND_PARITY_ENABLE; 336 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 337 338 /* 339 * Initialize the latency timer register for busmaster 340 * devices to work properly. 341 * latency-timer = min-grant * bus-freq / 4 (from FreeBSD) 342 * Also initialize the cache line size register. 343 * Solaris anytime sets this register to the value 0x10. 344 */ 345 bhlc = pci_conf_read(pc, tag, PCI_BHLC_REG); 346 ic = pci_conf_read(pc, tag, PCI_INTERRUPT_REG); 347 348 lt = uimin(PCI_MIN_GNT(ic) * bus_frequency / 4, 255); 349 if (lt == 0 || lt < PCI_LATTIMER(bhlc)) 350 lt = PCI_LATTIMER(bhlc); 351 352 cl = PCI_CACHELINE(bhlc); 353 if (cl == 0) 354 cl = cacheline; 355 356 bhlc &= ~((PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT) | 357 (PCI_CACHELINE_MASK << PCI_CACHELINE_SHIFT)); 358 bhlc |= (lt << PCI_LATTIMER_SHIFT) | 359 (cl << PCI_CACHELINE_SHIFT); 360 pci_conf_write(pc, tag, PCI_BHLC_REG, bhlc); 361 362 ret = pci_probe_device(sc, tag, match, pap); 363 if (match != NULL && ret != 0) 364 return (ret); 365 } 366 return (0); 367 } 368 369 const char * 370 pci_intr_string(pci_chipset_tag_t pc, pci_intr_handle_t ih, char *buf, 371 size_t len) 372 { 373 snprintf(buf, len, "ivec %x", ih); 374 DPRINTF(SPDB_INTR, ("pci_intr_string: returning %s\n", buf)); 375 376 return buf; 377 } 378 379 const struct evcnt * 380 pci_intr_evcnt(pci_chipset_tag_t pc, pci_intr_handle_t ih) 381 { 382 383 /* XXX for now, no evcnt parent reported */ 384 return NULL; 385 } 386 387 int 388 pci_intr_setattr(pci_chipset_tag_t pc, pci_intr_handle_t *ih, 389 int attr, uint64_t data) 390 { 391 392 switch (attr) { 393 case PCI_INTR_MPSAFE: 394 return 0; 395 default: 396 return ENODEV; 397 } 398 } 399 400 /* 401 * interrupt mapping foo. 402 * XXX: how does this deal with multiple interrupts for a device? 403 */ 404 int 405 pci_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ihp) 406 { 407 pcitag_t tag = pa->pa_tag; 408 int interrupts[4], *intp, int_used; 409 int len, node = PCITAG_NODE(tag); 410 char devtype[30]; 411 412 intp = &interrupts[0]; 413 len = prom_getproplen(node, "interrupts"); 414 if (len > sizeof(interrupts)) { 415 DPRINTF(SPDB_INTMAP, 416 ("pci_intr_map: too many available interrupts\n")); 417 return (ENODEV); 418 } 419 if (prom_getprop(node, "interrupts", len, 420 &len, &intp) != 0 || len != 1) { 421 DPRINTF(SPDB_INTMAP, 422 ("pci_intr_map: could not read interrupts\n")); 423 return (ENODEV); 424 } 425 426 /* XXX We pick the first interrupt, but should do better */ 427 int_used = interrupts[0]; 428 if (OF_mapintr(node, &int_used, sizeof(int_used), 429 sizeof(int_used)) < 0) { 430 printf("OF_mapintr failed\n"); 431 if (pa->pa_pc->spc_find_ino) 432 pa->pa_pc->spc_find_ino(pa, &int_used); 433 } 434 DPRINTF(SPDB_INTMAP, ("OF_mapintr() gave %x\n", int_used)); 435 436 /* Try to find an IPL for this type of device. */ 437 prom_getpropstringA(node, "device_type", devtype, sizeof(devtype)); 438 for (len = 0; intrmap[len].in_class != NULL; len++) 439 if (strcmp(intrmap[len].in_class, devtype) == 0) { 440 int_used |= INTLEVENCODE(intrmap[len].in_lev); 441 DPRINTF(SPDB_INTMAP, ("reset to %x\n", int_used)); 442 break; 443 } 444 445 *ihp = int_used; 446 447 /* Call the sub-driver is necessary */ 448 if (pa->pa_pc->spc_intr_map) 449 (*pa->pa_pc->spc_intr_map)(pa, ihp); 450 451 return (0); 452 } 453 454 void 455 pci_intr_disestablish(pci_chipset_tag_t pc, void *cookie) 456 { 457 458 DPRINTF(SPDB_INTR, ("pci_intr_disestablish: cookie %p\n", cookie)); 459 460 /* XXX */ 461 /* panic("can't disestablish PCI interrupts yet"); */ 462 } 463 464 int 465 sparc_pci_childspace(int type) 466 { 467 int ss; 468 469 switch (type) { 470 case PCI_CONFIG_BUS_SPACE: 471 ss = 0x00; 472 break; 473 case PCI_IO_BUS_SPACE: 474 ss = 0x01; 475 break; 476 case PCI_MEMORY_BUS_SPACE: 477 ss = 0x02; 478 break; 479 #if 0 480 /* we don't do 64 bit memory space */ 481 case PCI_MEMORY64_BUS_SPACE: 482 ss = 0x03; 483 break; 484 #endif 485 default: 486 panic("get_childspace: unknown bus type: %d", type); 487 } 488 489 return (ss); 490 } 491
Indexes created Wed Oct 15 16:09:53 GMT 2025