psycho.c revision 1.39 1 1.39 eeh /* $NetBSD: psycho.c,v 1.39 2001/10/07 20:30:41 eeh Exp $ */
2 1.1 mrg
3 1.1 mrg /*
4 1.3 mrg * Copyright (c) 1999, 2000 Matthew R. Green
5 1.1 mrg * All rights reserved.
6 1.1 mrg *
7 1.1 mrg * Redistribution and use in source and binary forms, with or without
8 1.1 mrg * modification, are permitted provided that the following conditions
9 1.1 mrg * are met:
10 1.1 mrg * 1. Redistributions of source code must retain the above copyright
11 1.1 mrg * notice, this list of conditions and the following disclaimer.
12 1.1 mrg * 2. Redistributions in binary form must reproduce the above copyright
13 1.1 mrg * notice, this list of conditions and the following disclaimer in the
14 1.1 mrg * documentation and/or other materials provided with the distribution.
15 1.1 mrg * 3. The name of the author may not be used to endorse or promote products
16 1.1 mrg * derived from this software without specific prior written permission.
17 1.1 mrg *
18 1.1 mrg * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 1.1 mrg * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 1.1 mrg * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 1.1 mrg * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 1.1 mrg * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
23 1.1 mrg * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
24 1.1 mrg * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
25 1.1 mrg * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
26 1.1 mrg * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 1.1 mrg * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 1.1 mrg * SUCH DAMAGE.
29 1.1 mrg */
30 1.1 mrg
31 1.7 mrg #include "opt_ddb.h"
32 1.7 mrg
33 1.1 mrg /*
34 1.34 eeh * Support for `psycho' and `psycho+' UPA to PCI bridge and
35 1.34 eeh * UltraSPARC IIi and IIe `sabre' PCI controllers.
36 1.1 mrg */
37 1.1 mrg
38 1.1 mrg #undef DEBUG
39 1.1 mrg #define DEBUG
40 1.1 mrg
41 1.1 mrg #ifdef DEBUG
42 1.7 mrg #define PDB_PROM 0x01
43 1.34 eeh #define PDB_BUSMAP 0x02
44 1.34 eeh #define PDB_INTR 0x04
45 1.3 mrg int psycho_debug = 0x0;
46 1.1 mrg #define DPRINTF(l, s) do { if (psycho_debug & l) printf s; } while (0)
47 1.1 mrg #else
48 1.1 mrg #define DPRINTF(l, s)
49 1.1 mrg #endif
50 1.1 mrg
51 1.1 mrg #include <sys/param.h>
52 1.7 mrg #include <sys/device.h>
53 1.7 mrg #include <sys/errno.h>
54 1.1 mrg #include <sys/extent.h>
55 1.7 mrg #include <sys/malloc.h>
56 1.7 mrg #include <sys/systm.h>
57 1.1 mrg #include <sys/time.h>
58 1.34 eeh #include <sys/reboot.h>
59 1.1 mrg
60 1.1 mrg #define _SPARC_BUS_DMA_PRIVATE
61 1.1 mrg #include <machine/bus.h>
62 1.1 mrg #include <machine/autoconf.h>
63 1.18 eeh #include <machine/psl.h>
64 1.1 mrg
65 1.1 mrg #include <dev/pci/pcivar.h>
66 1.1 mrg #include <dev/pci/pcireg.h>
67 1.1 mrg
68 1.1 mrg #include <sparc64/dev/iommureg.h>
69 1.1 mrg #include <sparc64/dev/iommuvar.h>
70 1.1 mrg #include <sparc64/dev/psychoreg.h>
71 1.1 mrg #include <sparc64/dev/psychovar.h>
72 1.7 mrg #include <sparc64/sparc64/cache.h>
73 1.1 mrg
74 1.8 mrg #include "ioconf.h"
75 1.8 mrg
76 1.1 mrg static pci_chipset_tag_t psycho_alloc_chipset __P((struct psycho_pbm *, int,
77 1.1 mrg pci_chipset_tag_t));
78 1.1 mrg static void psycho_get_bus_range __P((int, int *));
79 1.1 mrg static void psycho_get_ranges __P((int, struct psycho_ranges **, int *));
80 1.34 eeh static void psycho_set_intr __P((struct psycho_softc *, int, void *,
81 1.34 eeh u_int64_t *, u_int64_t *));
82 1.34 eeh
83 1.34 eeh /* Interrupt handlers */
84 1.34 eeh static int psycho_ue __P((void *));
85 1.34 eeh static int psycho_ce __P((void *));
86 1.34 eeh static int psycho_bus_a __P((void *));
87 1.34 eeh static int psycho_bus_b __P((void *));
88 1.34 eeh static int psycho_powerfail __P((void *));
89 1.34 eeh static int psycho_wakeup __P((void *));
90 1.34 eeh
91 1.1 mrg
92 1.1 mrg /* IOMMU support */
93 1.13 eeh static void psycho_iommu_init __P((struct psycho_softc *, int));
94 1.1 mrg
95 1.7 mrg /*
96 1.7 mrg * bus space and bus dma support for UltraSPARC `psycho'. note that most
97 1.7 mrg * of the bus dma support is provided by the iommu dvma controller.
98 1.7 mrg */
99 1.37 eeh static paddr_t psycho_bus_mmap __P((bus_space_tag_t, bus_addr_t, off_t, int, int));
100 1.7 mrg static int _psycho_bus_map __P((bus_space_tag_t, bus_type_t, bus_addr_t,
101 1.7 mrg bus_size_t, int, vaddr_t,
102 1.7 mrg bus_space_handle_t *));
103 1.21 pk static void *psycho_intr_establish __P((bus_space_tag_t, int, int, int,
104 1.7 mrg int (*) __P((void *)), void *));
105 1.7 mrg
106 1.7 mrg static int psycho_dmamap_load __P((bus_dma_tag_t, bus_dmamap_t, void *,
107 1.7 mrg bus_size_t, struct proc *, int));
108 1.7 mrg static void psycho_dmamap_unload __P((bus_dma_tag_t, bus_dmamap_t));
109 1.9 eeh static int psycho_dmamap_load_raw __P((bus_dma_tag_t, bus_dmamap_t,
110 1.9 eeh bus_dma_segment_t *, int, bus_size_t, int));
111 1.7 mrg static void psycho_dmamap_sync __P((bus_dma_tag_t, bus_dmamap_t, bus_addr_t,
112 1.7 mrg bus_size_t, int));
113 1.7 mrg int psycho_dmamem_alloc __P((bus_dma_tag_t, bus_size_t, bus_size_t, bus_size_t,
114 1.7 mrg bus_dma_segment_t *, int, int *, int));
115 1.7 mrg void psycho_dmamem_free __P((bus_dma_tag_t, bus_dma_segment_t *, int));
116 1.7 mrg int psycho_dmamem_map __P((bus_dma_tag_t, bus_dma_segment_t *, int, size_t,
117 1.7 mrg caddr_t *, int));
118 1.7 mrg void psycho_dmamem_unmap __P((bus_dma_tag_t, caddr_t, size_t));
119 1.7 mrg
120 1.7 mrg /* base pci_chipset */
121 1.1 mrg extern struct sparc_pci_chipset _sparc_pci_chipset;
122 1.1 mrg
123 1.1 mrg /*
124 1.1 mrg * autoconfiguration
125 1.1 mrg */
126 1.1 mrg static int psycho_match __P((struct device *, struct cfdata *, void *));
127 1.1 mrg static void psycho_attach __P((struct device *, struct device *, void *));
128 1.1 mrg static int psycho_print __P((void *aux, const char *p));
129 1.1 mrg
130 1.1 mrg struct cfattach psycho_ca = {
131 1.1 mrg sizeof(struct psycho_softc), psycho_match, psycho_attach
132 1.1 mrg };
133 1.1 mrg
134 1.1 mrg /*
135 1.34 eeh * "sabre" is the UltraSPARC IIi onboard UPA to PCI bridge. It manages a
136 1.34 eeh * single PCI bus and does not have a streaming buffer. It often has an APB
137 1.34 eeh * (advanced PCI bridge) connected to it, which was designed specifically for
138 1.34 eeh * the IIi. The APB let's the IIi handle two independednt PCI buses, and
139 1.34 eeh * appears as two "simba"'s underneath the sabre.
140 1.34 eeh *
141 1.34 eeh * "psycho" and "psycho+" is a dual UPA to PCI bridge. It sits on the UPA bus
142 1.34 eeh * and manages two PCI buses. "psycho" has two 64-bit 33MHz buses, while
143 1.34 eeh * "psycho+" controls both a 64-bit 33Mhz and a 64-bit 66Mhz PCI bus. You
144 1.34 eeh * will usually find a "psycho+" since I don't think the original "psycho"
145 1.34 eeh * ever shipped, and if it did it would be in the U30.
146 1.34 eeh *
147 1.34 eeh * Each "psycho" PCI bus appears as a separate OFW node, but since they are
148 1.34 eeh * both part of the same IC, they only have a single register space. As such,
149 1.34 eeh * they need to be configured together, even though the autoconfiguration will
150 1.34 eeh * attach them separately.
151 1.34 eeh *
152 1.34 eeh * On UltraIIi machines, "sabre" itself usually takes pci0, with "simba" often
153 1.34 eeh * as pci1 and pci2, although they have been implemented with other PCI bus
154 1.34 eeh * numbers on some machines.
155 1.34 eeh *
156 1.34 eeh * On UltraII machines, there can be any number of "psycho+" ICs, each
157 1.34 eeh * providing two PCI buses.
158 1.34 eeh *
159 1.34 eeh *
160 1.34 eeh * XXXX The psycho/sabre node has an `interrupts' attribute. They contain
161 1.34 eeh * the values of the following interrupts in this order:
162 1.1 mrg *
163 1.34 eeh * PCI Bus Error (30)
164 1.34 eeh * DMA UE (2e)
165 1.34 eeh * DMA CE (2f)
166 1.34 eeh * Power Fail (25)
167 1.34 eeh *
168 1.34 eeh * We really should attach handlers for each.
169 1.1 mrg *
170 1.1 mrg */
171 1.35 eeh
172 1.1 mrg #define ROM_PCI_NAME "pci"
173 1.35 eeh
174 1.35 eeh struct psycho_names {
175 1.35 eeh char *p_name;
176 1.35 eeh int p_type;
177 1.35 eeh } psycho_names[] = {
178 1.35 eeh { "SUNW,psycho", PSYCHO_MODE_PSYCHO },
179 1.35 eeh { "pci108e,8000", PSYCHO_MODE_PSYCHO },
180 1.35 eeh { "SUNW,sabre", PSYCHO_MODE_SABRE },
181 1.35 eeh { "pci108e,a000", PSYCHO_MODE_SABRE },
182 1.35 eeh { "pci108e,a001", PSYCHO_MODE_SABRE },
183 1.35 eeh { NULL, 0 }
184 1.35 eeh };
185 1.1 mrg
186 1.1 mrg static int
187 1.1 mrg psycho_match(parent, match, aux)
188 1.1 mrg struct device *parent;
189 1.1 mrg struct cfdata *match;
190 1.1 mrg void *aux;
191 1.1 mrg {
192 1.1 mrg struct mainbus_attach_args *ma = aux;
193 1.38 eeh char *model = PROM_getpropstring(ma->ma_node, "model");
194 1.35 eeh int i;
195 1.1 mrg
196 1.1 mrg /* match on a name of "pci" and a sabre or a psycho */
197 1.35 eeh if (strcmp(ma->ma_name, ROM_PCI_NAME) == 0) {
198 1.35 eeh for (i=0; psycho_names[i].p_name; i++)
199 1.35 eeh if (strcmp(model, psycho_names[i].p_name) == 0)
200 1.35 eeh return (1);
201 1.35 eeh
202 1.38 eeh model = PROM_getpropstring(ma->ma_node, "compatible");
203 1.35 eeh for (i=0; psycho_names[i].p_name; i++)
204 1.35 eeh if (strcmp(model, psycho_names[i].p_name) == 0)
205 1.35 eeh return (1);
206 1.35 eeh }
207 1.1 mrg return (0);
208 1.1 mrg }
209 1.1 mrg
210 1.34 eeh /*
211 1.34 eeh * SUNW,psycho initialisation ..
212 1.34 eeh * - find the per-psycho registers
213 1.34 eeh * - figure out the IGN.
214 1.34 eeh * - find our partner psycho
215 1.34 eeh * - configure ourselves
216 1.34 eeh * - bus range, bus,
217 1.34 eeh * - get interrupt-map and interrupt-map-mask
218 1.34 eeh * - setup the chipsets.
219 1.34 eeh * - if we're the first of the pair, initialise the IOMMU, otherwise
220 1.34 eeh * just copy it's tags and addresses.
221 1.34 eeh */
222 1.1 mrg static void
223 1.1 mrg psycho_attach(parent, self, aux)
224 1.1 mrg struct device *parent, *self;
225 1.1 mrg void *aux;
226 1.1 mrg {
227 1.1 mrg struct psycho_softc *sc = (struct psycho_softc *)self;
228 1.34 eeh struct psycho_softc *osc = NULL;
229 1.34 eeh struct psycho_pbm *pp;
230 1.1 mrg struct pcibus_attach_args pba;
231 1.1 mrg struct mainbus_attach_args *ma = aux;
232 1.34 eeh bus_space_handle_t bh;
233 1.34 eeh u_int64_t csr;
234 1.35 eeh int psycho_br[2], n, i;
235 1.34 eeh struct pci_ctl *pci_ctl;
236 1.38 eeh char *model = PROM_getpropstring(ma->ma_node, "model");
237 1.1 mrg
238 1.1 mrg printf("\n");
239 1.1 mrg
240 1.1 mrg sc->sc_node = ma->ma_node;
241 1.1 mrg sc->sc_bustag = ma->ma_bustag;
242 1.1 mrg sc->sc_dmatag = ma->ma_dmatag;
243 1.1 mrg
244 1.1 mrg /*
245 1.1 mrg * call the model-specific initialisation routine.
246 1.1 mrg */
247 1.35 eeh for (i=0; psycho_names[i].p_name; i++)
248 1.35 eeh if (strcmp(model, psycho_names[i].p_name) == 0) {
249 1.35 eeh sc->sc_mode = psycho_names[i].p_type;
250 1.35 eeh goto found;
251 1.35 eeh }
252 1.35 eeh
253 1.38 eeh model = PROM_getpropstring(ma->ma_node, "compatible");
254 1.35 eeh for (i=0; psycho_names[i].p_name; i++)
255 1.35 eeh if (strcmp(model, psycho_names[i].p_name) == 0) {
256 1.35 eeh sc->sc_mode = psycho_names[i].p_type;
257 1.35 eeh goto found;
258 1.35 eeh }
259 1.34 eeh
260 1.35 eeh panic("unknown psycho model %s", model);
261 1.35 eeh found:
262 1.1 mrg
263 1.1 mrg /*
264 1.22 pk * The psycho gets three register banks:
265 1.22 pk * (0) per-PBM configuration and status registers
266 1.22 pk * (1) per-PBM PCI configuration space, containing only the
267 1.22 pk * PBM 256-byte PCI header
268 1.22 pk * (2) the shared psycho configuration registers (struct psychoreg)
269 1.22 pk *
270 1.22 pk * XXX use the prom address for the psycho registers? we do so far.
271 1.22 pk */
272 1.34 eeh
273 1.34 eeh /* Register layouts are different. stuupid. */
274 1.34 eeh if (sc->sc_mode == PSYCHO_MODE_PSYCHO) {
275 1.34 eeh sc->sc_basepaddr = (paddr_t)ma->ma_reg[2].ur_paddr;
276 1.34 eeh
277 1.34 eeh if (ma->ma_naddress > 2) {
278 1.34 eeh sc->sc_regs = (struct psychoreg *)
279 1.34 eeh (u_long)ma->ma_address[2];
280 1.34 eeh pci_ctl = (struct pci_ctl *)
281 1.34 eeh (u_long)ma->ma_address[0];
282 1.34 eeh } else if (ma->ma_nreg > 2) {
283 1.34 eeh bus_space_handle_t handle;
284 1.34 eeh
285 1.34 eeh /* We need to map this in ourselves. */
286 1.34 eeh if (bus_space_map2(sc->sc_bustag, 0,
287 1.34 eeh ma->ma_reg[2].ur_paddr,
288 1.34 eeh ma->ma_reg[2].ur_len, 0, NULL, &handle))
289 1.34 eeh panic("psycho_attach: cannot map regs");
290 1.34 eeh sc->sc_regs = (struct psychoreg *)(u_long)handle;
291 1.34 eeh
292 1.34 eeh if (bus_space_map2(sc->sc_bustag, 0,
293 1.34 eeh ma->ma_reg[0].ur_paddr,
294 1.34 eeh ma->ma_reg[0].ur_len, 0, NULL, &handle))
295 1.34 eeh panic("psycho_attach: cannot map ctl");
296 1.34 eeh /* XXX -- this is lost but never unmapped */
297 1.34 eeh pci_ctl = (struct pci_ctl *)(u_long)handle;
298 1.34 eeh
299 1.34 eeh } else
300 1.34 eeh panic("psycho_attach: %d not enough registers",
301 1.34 eeh ma->ma_nreg);
302 1.34 eeh } else {
303 1.34 eeh sc->sc_basepaddr = (paddr_t)ma->ma_reg[0].ur_paddr;
304 1.34 eeh
305 1.34 eeh if (ma->ma_naddress) {
306 1.34 eeh sc->sc_regs = (struct psychoreg *)
307 1.34 eeh (u_long)ma->ma_address[0];
308 1.34 eeh pci_ctl = (struct pci_ctl *)&sc->sc_regs->psy_pcictl[0];
309 1.34 eeh } else if (ma->ma_nreg) {
310 1.34 eeh bus_space_handle_t handle;
311 1.34 eeh
312 1.34 eeh /* We need to map this in ourselves. */
313 1.34 eeh if (bus_space_map2(sc->sc_bustag, 0,
314 1.34 eeh ma->ma_reg[0].ur_paddr,
315 1.34 eeh ma->ma_reg[0].ur_len, 0, NULL, &handle))
316 1.34 eeh panic("psycho_attach: cannot map regs");
317 1.34 eeh sc->sc_regs = (struct psychoreg *)(u_long)handle;
318 1.34 eeh pci_ctl = (struct pci_ctl *)&sc->sc_regs->psy_pcictl[0];
319 1.34 eeh } else
320 1.34 eeh panic("psycho_attach: %d not enough registers",
321 1.34 eeh ma->ma_nreg);
322 1.34 eeh }
323 1.23 pk
324 1.23 pk csr = sc->sc_regs->psy_csr;
325 1.34 eeh sc->sc_ign = 0x7c0; /* APB IGN is always 0x7c */
326 1.34 eeh if (sc->sc_mode == PSYCHO_MODE_PSYCHO)
327 1.34 eeh sc->sc_ign = PSYCHO_GCSR_IGN(csr) << 6;
328 1.24 pk
329 1.34 eeh printf("%s: impl %d, version %d: ign %x ",
330 1.34 eeh model, PSYCHO_GCSR_IMPL(csr), PSYCHO_GCSR_VERS(csr),
331 1.34 eeh sc->sc_ign);
332 1.22 pk /*
333 1.24 pk * Match other psycho's that are already configured against
334 1.24 pk * the base physical address. This will be the same for a
335 1.24 pk * pair of devices that share register space.
336 1.1 mrg */
337 1.3 mrg for (n = 0; n < psycho_cd.cd_ndevs; n++) {
338 1.8 mrg
339 1.24 pk struct psycho_softc *asc =
340 1.24 pk (struct psycho_softc *)psycho_cd.cd_devs[n];
341 1.3 mrg
342 1.24 pk if (asc == NULL || asc == sc)
343 1.24 pk /* This entry is not there or it is me */
344 1.24 pk continue;
345 1.23 pk
346 1.24 pk if (asc->sc_basepaddr != sc->sc_basepaddr)
347 1.24 pk /* This is an unrelated psycho */
348 1.3 mrg continue;
349 1.3 mrg
350 1.24 pk /* Found partner */
351 1.24 pk osc = asc;
352 1.8 mrg break;
353 1.8 mrg }
354 1.8 mrg
355 1.3 mrg
356 1.3 mrg /* Oh, dear. OK, lets get started */
357 1.3 mrg
358 1.24 pk /*
359 1.24 pk * Setup the PCI control register
360 1.24 pk */
361 1.24 pk csr = bus_space_read_8(sc->sc_bustag,
362 1.24 pk (bus_space_handle_t)(u_long)&pci_ctl->pci_csr, 0);
363 1.8 mrg csr |= PCICTL_MRLM |
364 1.8 mrg PCICTL_ARB_PARK |
365 1.8 mrg PCICTL_ERRINTEN |
366 1.8 mrg PCICTL_4ENABLE;
367 1.8 mrg csr &= ~(PCICTL_SERR |
368 1.8 mrg PCICTL_CPU_PRIO |
369 1.8 mrg PCICTL_ARB_PRIO |
370 1.8 mrg PCICTL_RTRYWAIT);
371 1.24 pk bus_space_write_8(sc->sc_bustag,
372 1.24 pk (bus_space_handle_t)(u_long)&pci_ctl->pci_csr, 0, csr);
373 1.8 mrg
374 1.24 pk
375 1.24 pk /*
376 1.24 pk * Allocate our psycho_pbm
377 1.24 pk */
378 1.22 pk pp = sc->sc_psycho_this = malloc(sizeof *pp, M_DEVBUF, M_NOWAIT);
379 1.22 pk if (pp == NULL)
380 1.8 mrg panic("could not allocate psycho pbm");
381 1.8 mrg
382 1.22 pk memset(pp, 0, sizeof *pp);
383 1.22 pk
384 1.22 pk pp->pp_sc = sc;
385 1.8 mrg
386 1.8 mrg /* grab the psycho ranges */
387 1.22 pk psycho_get_ranges(sc->sc_node, &pp->pp_range, &pp->pp_nrange);
388 1.8 mrg
389 1.8 mrg /* get the bus-range for the psycho */
390 1.8 mrg psycho_get_bus_range(sc->sc_node, psycho_br);
391 1.8 mrg
392 1.34 eeh pba.pba_bus = psycho_br[0];
393 1.8 mrg
394 1.8 mrg printf("bus range %u to %u", psycho_br[0], psycho_br[1]);
395 1.23 pk printf("; PCI bus %d", psycho_br[0]);
396 1.8 mrg
397 1.8 mrg pp->pp_pcictl = &sc->sc_regs->psy_pcictl[0];
398 1.8 mrg
399 1.8 mrg /* allocate our tags */
400 1.8 mrg pp->pp_memt = psycho_alloc_mem_tag(pp);
401 1.8 mrg pp->pp_iot = psycho_alloc_io_tag(pp);
402 1.8 mrg pp->pp_dmat = psycho_alloc_dma_tag(pp);
403 1.8 mrg pp->pp_flags = (pp->pp_memt ? PCI_FLAGS_MEM_ENABLED : 0) |
404 1.8 mrg (pp->pp_iot ? PCI_FLAGS_IO_ENABLED : 0);
405 1.8 mrg
406 1.8 mrg /* allocate a chipset for this */
407 1.8 mrg pp->pp_pc = psycho_alloc_chipset(pp, sc->sc_node, &_sparc_pci_chipset);
408 1.8 mrg
409 1.8 mrg /* setup the rest of the psycho pbm */
410 1.34 eeh pba.pba_pc = psycho_alloc_chipset(pp, sc->sc_node, pp->pp_pc);
411 1.8 mrg
412 1.8 mrg printf("\n");
413 1.8 mrg
414 1.8 mrg /*
415 1.34 eeh * And finally, if we're a sabre or the first of a pair of psycho's to
416 1.24 pk * arrive here, start up the IOMMU and get a config space tag.
417 1.8 mrg */
418 1.24 pk if (osc == NULL) {
419 1.34 eeh
420 1.34 eeh /*
421 1.34 eeh * Establish handlers for interesting interrupts....
422 1.34 eeh *
423 1.34 eeh * XXX We need to remember these and remove this to support
424 1.34 eeh * hotplug on the UPA/FHC bus.
425 1.34 eeh *
426 1.34 eeh * XXX Not all controllers have these, but installing them
427 1.34 eeh * is better than trying to sort through this mess.
428 1.34 eeh */
429 1.34 eeh psycho_set_intr(sc, 15, psycho_ue,
430 1.34 eeh &sc->sc_regs->ue_int_map,
431 1.34 eeh &sc->sc_regs->ue_clr_int);
432 1.34 eeh psycho_set_intr(sc, 1, psycho_ce,
433 1.34 eeh &sc->sc_regs->ce_int_map,
434 1.34 eeh &sc->sc_regs->ce_clr_int);
435 1.34 eeh psycho_set_intr(sc, 15, psycho_bus_a,
436 1.34 eeh &sc->sc_regs->pciaerr_int_map,
437 1.34 eeh &sc->sc_regs->pciaerr_clr_int);
438 1.34 eeh psycho_set_intr(sc, 15, psycho_bus_b,
439 1.34 eeh &sc->sc_regs->pciberr_int_map,
440 1.34 eeh &sc->sc_regs->pciberr_clr_int);
441 1.34 eeh psycho_set_intr(sc, 15, psycho_powerfail,
442 1.34 eeh &sc->sc_regs->power_int_map,
443 1.34 eeh &sc->sc_regs->power_clr_int);
444 1.34 eeh psycho_set_intr(sc, 1, psycho_wakeup,
445 1.34 eeh &sc->sc_regs->pwrmgt_int_map,
446 1.34 eeh &sc->sc_regs->pwrmgt_clr_int);
447 1.34 eeh
448 1.13 eeh /*
449 1.24 pk * Setup IOMMU and PCI configuration if we're the first
450 1.24 pk * of a pair of psycho's to arrive here.
451 1.24 pk *
452 1.13 eeh * We should calculate a TSB size based on amount of RAM
453 1.34 eeh * and number of bus controllers and number an type of
454 1.34 eeh * child devices.
455 1.13 eeh *
456 1.13 eeh * For the moment, 32KB should be more than enough.
457 1.13 eeh */
458 1.39 eeh sc->sc_is = malloc(sizeof(struct iommu_state),
459 1.39 eeh M_DEVBUF, M_NOWAIT);
460 1.39 eeh if (sc->sc_is == NULL)
461 1.39 eeh panic("psycho_attach: malloc iommu_state");
462 1.39 eeh
463 1.39 eeh
464 1.39 eeh sc->sc_is->is_sb[0] = 0;
465 1.39 eeh sc->sc_is->is_sb[1] = 0;
466 1.39 eeh if (PROM_getproplen(sc->sc_node, "no-streaming-cache") >= 0)
467 1.39 eeh sc->sc_is->is_sb[0] = &pci_ctl->pci_strbuf;
468 1.39 eeh
469 1.13 eeh psycho_iommu_init(sc, 2);
470 1.8 mrg
471 1.8 mrg sc->sc_configtag = psycho_alloc_config_tag(sc->sc_psycho_this);
472 1.8 mrg if (bus_space_map2(sc->sc_bustag,
473 1.8 mrg PCI_CONFIG_BUS_SPACE,
474 1.8 mrg sc->sc_basepaddr + 0x01000000,
475 1.8 mrg 0x0100000,
476 1.8 mrg 0,
477 1.8 mrg 0,
478 1.8 mrg &bh))
479 1.23 pk panic("could not map psycho PCI configuration space");
480 1.15 simonb sc->sc_configaddr = (off_t)bh;
481 1.8 mrg } else {
482 1.24 pk /* Just copy IOMMU state, config tag and address */
483 1.24 pk sc->sc_is = osc->sc_is;
484 1.8 mrg sc->sc_configtag = osc->sc_configtag;
485 1.8 mrg sc->sc_configaddr = osc->sc_configaddr;
486 1.39 eeh
487 1.39 eeh if (PROM_getproplen(sc->sc_node, "no-streaming-cache") >= 0)
488 1.39 eeh sc->sc_is->is_sb[1] = &pci_ctl->pci_strbuf;
489 1.39 eeh iommu_reset(sc->sc_is);
490 1.8 mrg }
491 1.34 eeh
492 1.34 eeh /*
493 1.34 eeh * attach the pci.. note we pass PCI A tags, etc., for the sabre here.
494 1.34 eeh */
495 1.34 eeh pba.pba_busname = "pci";
496 1.34 eeh pba.pba_flags = sc->sc_psycho_this->pp_flags;
497 1.34 eeh pba.pba_dmat = sc->sc_psycho_this->pp_dmat;
498 1.34 eeh pba.pba_iot = sc->sc_psycho_this->pp_iot;
499 1.34 eeh pba.pba_memt = sc->sc_psycho_this->pp_memt;
500 1.34 eeh
501 1.34 eeh config_found(self, &pba, psycho_print);
502 1.34 eeh }
503 1.34 eeh
504 1.34 eeh static int
505 1.34 eeh psycho_print(aux, p)
506 1.34 eeh void *aux;
507 1.34 eeh const char *p;
508 1.34 eeh {
509 1.34 eeh
510 1.34 eeh if (p == NULL)
511 1.34 eeh return (UNCONF);
512 1.34 eeh return (QUIET);
513 1.34 eeh }
514 1.34 eeh
515 1.34 eeh static void
516 1.34 eeh psycho_set_intr(sc, ipl, handler, mapper, clearer)
517 1.34 eeh struct psycho_softc *sc;
518 1.34 eeh int ipl;
519 1.34 eeh void *handler;
520 1.34 eeh u_int64_t *mapper;
521 1.34 eeh u_int64_t *clearer;
522 1.34 eeh {
523 1.34 eeh struct intrhand *ih;
524 1.34 eeh
525 1.34 eeh ih = (struct intrhand *)malloc(sizeof(struct intrhand),
526 1.34 eeh M_DEVBUF, M_NOWAIT);
527 1.34 eeh ih->ih_arg = sc;
528 1.34 eeh ih->ih_map = mapper;
529 1.34 eeh ih->ih_clr = clearer;
530 1.34 eeh ih->ih_fun = handler;
531 1.34 eeh ih->ih_pil = (1<<ipl);
532 1.34 eeh ih->ih_number = INTVEC(*(ih->ih_map));
533 1.34 eeh intr_establish(ipl, ih);
534 1.34 eeh *(ih->ih_map) |= INTMAP_V;
535 1.1 mrg }
536 1.1 mrg
537 1.1 mrg /*
538 1.1 mrg * PCI bus support
539 1.1 mrg */
540 1.1 mrg
541 1.1 mrg /*
542 1.1 mrg * allocate a PCI chipset tag and set it's cookie.
543 1.1 mrg */
544 1.1 mrg static pci_chipset_tag_t
545 1.1 mrg psycho_alloc_chipset(pp, node, pc)
546 1.1 mrg struct psycho_pbm *pp;
547 1.1 mrg int node;
548 1.1 mrg pci_chipset_tag_t pc;
549 1.1 mrg {
550 1.1 mrg pci_chipset_tag_t npc;
551 1.1 mrg
552 1.1 mrg npc = malloc(sizeof *npc, M_DEVBUF, M_NOWAIT);
553 1.1 mrg if (npc == NULL)
554 1.1 mrg panic("could not allocate pci_chipset_tag_t");
555 1.1 mrg memcpy(npc, pc, sizeof *pc);
556 1.1 mrg npc->cookie = pp;
557 1.34 eeh npc->rootnode = node;
558 1.34 eeh npc->curnode = node;
559 1.1 mrg
560 1.1 mrg return (npc);
561 1.1 mrg }
562 1.1 mrg
563 1.1 mrg /*
564 1.1 mrg * grovel the OBP for various psycho properties
565 1.1 mrg */
566 1.1 mrg static void
567 1.1 mrg psycho_get_bus_range(node, brp)
568 1.1 mrg int node;
569 1.1 mrg int *brp;
570 1.1 mrg {
571 1.1 mrg int n;
572 1.1 mrg
573 1.38 eeh if (PROM_getprop(node, "bus-range", sizeof(*brp), &n, (void **)&brp))
574 1.1 mrg panic("could not get psycho bus-range");
575 1.1 mrg if (n != 2)
576 1.1 mrg panic("broken psycho bus-range");
577 1.1 mrg DPRINTF(PDB_PROM, ("psycho debug: got `bus-range' for node %08x: %u - %u\n", node, brp[0], brp[1]));
578 1.1 mrg }
579 1.1 mrg
580 1.1 mrg static void
581 1.1 mrg psycho_get_ranges(node, rp, np)
582 1.1 mrg int node;
583 1.1 mrg struct psycho_ranges **rp;
584 1.1 mrg int *np;
585 1.1 mrg {
586 1.1 mrg
587 1.38 eeh if (PROM_getprop(node, "ranges", sizeof(**rp), np, (void **)rp))
588 1.1 mrg panic("could not get psycho ranges");
589 1.1 mrg DPRINTF(PDB_PROM, ("psycho debug: got `ranges' for node %08x: %d entries\n", node, *np));
590 1.1 mrg }
591 1.1 mrg
592 1.34 eeh /*
593 1.34 eeh * Interrupt handlers.
594 1.34 eeh */
595 1.34 eeh
596 1.34 eeh static int
597 1.34 eeh psycho_ue(arg)
598 1.34 eeh void *arg;
599 1.34 eeh {
600 1.34 eeh struct psycho_softc *sc = (struct psycho_softc *)arg;
601 1.34 eeh struct psychoreg *regs = sc->sc_regs;
602 1.36 eeh long long afsr = regs->psy_ue_afsr;
603 1.36 eeh long long afar = regs->psy_ue_afar;
604 1.36 eeh char bits[128];
605 1.34 eeh
606 1.34 eeh /*
607 1.34 eeh * It's uncorrectable. Dump the regs and panic.
608 1.34 eeh */
609 1.36 eeh panic("%s: uncorrectable DMA error AFAR %llx pa %llx AFSR %llx:\n%s",
610 1.36 eeh sc->sc_dev.dv_xname, afar,
611 1.36 eeh (long long)iommu_extract(sc->sc_is, (vaddr_t)afar), afsr,
612 1.36 eeh bitmask_snprintf(afsr, PSYCHO_UE_AFSR_BITS,
613 1.36 eeh bits, sizeof(bits)));
614 1.34 eeh return (1);
615 1.34 eeh }
616 1.34 eeh static int
617 1.34 eeh psycho_ce(arg)
618 1.34 eeh void *arg;
619 1.1 mrg {
620 1.34 eeh struct psycho_softc *sc = (struct psycho_softc *)arg;
621 1.34 eeh struct psychoreg *regs = sc->sc_regs;
622 1.34 eeh
623 1.34 eeh /*
624 1.34 eeh * It's correctable. Dump the regs and continue.
625 1.34 eeh */
626 1.1 mrg
627 1.34 eeh printf("%s: correctable DMA error AFAR %llx AFSR %llx\n",
628 1.34 eeh sc->sc_dev.dv_xname,
629 1.34 eeh (long long)regs->psy_ce_afar, (long long)regs->psy_ce_afsr);
630 1.34 eeh return (1);
631 1.1 mrg }
632 1.34 eeh static int
633 1.34 eeh psycho_bus_a(arg)
634 1.34 eeh void *arg;
635 1.34 eeh {
636 1.34 eeh struct psycho_softc *sc = (struct psycho_softc *)arg;
637 1.34 eeh struct psychoreg *regs = sc->sc_regs;
638 1.34 eeh
639 1.34 eeh /*
640 1.34 eeh * It's uncorrectable. Dump the regs and panic.
641 1.34 eeh */
642 1.1 mrg
643 1.34 eeh panic("%s: PCI bus A error AFAR %llx AFSR %llx\n",
644 1.34 eeh sc->sc_dev.dv_xname,
645 1.35 eeh (long long)regs->psy_pcictl[0].pci_afar,
646 1.35 eeh (long long)regs->psy_pcictl[0].pci_afsr);
647 1.34 eeh return (1);
648 1.34 eeh }
649 1.34 eeh static int
650 1.34 eeh psycho_bus_b(arg)
651 1.34 eeh void *arg;
652 1.1 mrg {
653 1.34 eeh struct psycho_softc *sc = (struct psycho_softc *)arg;
654 1.34 eeh struct psychoreg *regs = sc->sc_regs;
655 1.34 eeh
656 1.34 eeh /*
657 1.34 eeh * It's uncorrectable. Dump the regs and panic.
658 1.34 eeh */
659 1.1 mrg
660 1.34 eeh panic("%s: PCI bus B error AFAR %llx AFSR %llx\n",
661 1.34 eeh sc->sc_dev.dv_xname,
662 1.35 eeh (long long)regs->psy_pcictl[0].pci_afar,
663 1.35 eeh (long long)regs->psy_pcictl[0].pci_afsr);
664 1.34 eeh return (1);
665 1.1 mrg }
666 1.34 eeh static int
667 1.34 eeh psycho_powerfail(arg)
668 1.34 eeh void *arg;
669 1.34 eeh {
670 1.1 mrg
671 1.34 eeh /*
672 1.34 eeh * We lost power. Try to shut down NOW.
673 1.34 eeh */
674 1.34 eeh printf("Power Failure Detected: Shutting down NOW.\n");
675 1.34 eeh cpu_reboot(RB_POWERDOWN|RB_HALT, NULL);
676 1.34 eeh return (1);
677 1.34 eeh }
678 1.34 eeh static
679 1.34 eeh int psycho_wakeup(arg)
680 1.34 eeh void *arg;
681 1.1 mrg {
682 1.34 eeh struct psycho_softc *sc = (struct psycho_softc *)arg;
683 1.1 mrg
684 1.34 eeh /*
685 1.34 eeh * Gee, we don't really have a framework to deal with this
686 1.34 eeh * properly.
687 1.34 eeh */
688 1.34 eeh printf("%s: power management wakeup\n", sc->sc_dev.dv_xname);
689 1.34 eeh return (1);
690 1.1 mrg }
691 1.1 mrg
692 1.34 eeh
693 1.34 eeh
694 1.1 mrg /*
695 1.1 mrg * initialise the IOMMU..
696 1.1 mrg */
697 1.1 mrg void
698 1.13 eeh psycho_iommu_init(sc, tsbsize)
699 1.1 mrg struct psycho_softc *sc;
700 1.13 eeh int tsbsize;
701 1.1 mrg {
702 1.1 mrg char *name;
703 1.39 eeh struct iommu_state *is = sc->sc_is;
704 1.34 eeh u_int32_t iobase = -1;
705 1.34 eeh int *vdma = NULL;
706 1.34 eeh int nitem;
707 1.24 pk
708 1.1 mrg /* punch in our copies */
709 1.24 pk is->is_bustag = sc->sc_bustag;
710 1.24 pk is->is_iommu = &sc->sc_regs->psy_iommu;
711 1.1 mrg
712 1.34 eeh /*
713 1.34 eeh * Separate the men from the boys. Get the `virtual-dma'
714 1.34 eeh * property for sabre and use that to make sure the damn
715 1.34 eeh * iommu works.
716 1.34 eeh *
717 1.34 eeh * We could query the `#virtual-dma-size-cells' and
718 1.34 eeh * `#virtual-dma-addr-cells' and DTRT, but I'm lazy.
719 1.34 eeh */
720 1.38 eeh if (!PROM_getprop(sc->sc_node, "virtual-dma", sizeof(vdma), &nitem,
721 1.34 eeh (void **)&vdma)) {
722 1.34 eeh /* Damn. Gotta use these values. */
723 1.34 eeh iobase = vdma[0];
724 1.34 eeh #define TSBCASE(x) case 1<<((x)+23): tsbsize = (x); break
725 1.34 eeh switch (vdma[1]) {
726 1.34 eeh TSBCASE(1); TSBCASE(2); TSBCASE(3);
727 1.34 eeh TSBCASE(4); TSBCASE(5); TSBCASE(6);
728 1.34 eeh default:
729 1.34 eeh printf("bogus tsb size %x, using 7\n", vdma[1]);
730 1.34 eeh TSBCASE(7);
731 1.34 eeh }
732 1.34 eeh #undef TSBCASE
733 1.34 eeh }
734 1.34 eeh
735 1.1 mrg /* give us a nice name.. */
736 1.1 mrg name = (char *)malloc(32, M_DEVBUF, M_NOWAIT);
737 1.1 mrg if (name == 0)
738 1.1 mrg panic("couldn't malloc iommu name");
739 1.1 mrg snprintf(name, 32, "%s dvma", sc->sc_dev.dv_xname);
740 1.1 mrg
741 1.34 eeh iommu_init(name, is, tsbsize, iobase);
742 1.7 mrg }
743 1.7 mrg
744 1.7 mrg /*
745 1.7 mrg * below here is bus space and bus dma support
746 1.7 mrg */
747 1.7 mrg bus_space_tag_t
748 1.7 mrg psycho_alloc_bus_tag(pp, type)
749 1.7 mrg struct psycho_pbm *pp;
750 1.7 mrg int type;
751 1.7 mrg {
752 1.7 mrg struct psycho_softc *sc = pp->pp_sc;
753 1.7 mrg bus_space_tag_t bt;
754 1.7 mrg
755 1.7 mrg bt = (bus_space_tag_t)
756 1.7 mrg malloc(sizeof(struct sparc_bus_space_tag), M_DEVBUF, M_NOWAIT);
757 1.7 mrg if (bt == NULL)
758 1.7 mrg panic("could not allocate psycho bus tag");
759 1.7 mrg
760 1.7 mrg bzero(bt, sizeof *bt);
761 1.7 mrg bt->cookie = pp;
762 1.7 mrg bt->parent = sc->sc_bustag;
763 1.7 mrg bt->type = type;
764 1.7 mrg bt->sparc_bus_map = _psycho_bus_map;
765 1.7 mrg bt->sparc_bus_mmap = psycho_bus_mmap;
766 1.7 mrg bt->sparc_intr_establish = psycho_intr_establish;
767 1.7 mrg return (bt);
768 1.7 mrg }
769 1.7 mrg
770 1.7 mrg bus_dma_tag_t
771 1.7 mrg psycho_alloc_dma_tag(pp)
772 1.7 mrg struct psycho_pbm *pp;
773 1.7 mrg {
774 1.7 mrg struct psycho_softc *sc = pp->pp_sc;
775 1.7 mrg bus_dma_tag_t dt, pdt = sc->sc_dmatag;
776 1.7 mrg
777 1.7 mrg dt = (bus_dma_tag_t)
778 1.7 mrg malloc(sizeof(struct sparc_bus_dma_tag), M_DEVBUF, M_NOWAIT);
779 1.7 mrg if (dt == NULL)
780 1.7 mrg panic("could not allocate psycho dma tag");
781 1.7 mrg
782 1.7 mrg bzero(dt, sizeof *dt);
783 1.7 mrg dt->_cookie = pp;
784 1.7 mrg dt->_parent = pdt;
785 1.7 mrg #define PCOPY(x) dt->x = pdt->x
786 1.7 mrg PCOPY(_dmamap_create);
787 1.7 mrg PCOPY(_dmamap_destroy);
788 1.7 mrg dt->_dmamap_load = psycho_dmamap_load;
789 1.7 mrg PCOPY(_dmamap_load_mbuf);
790 1.7 mrg PCOPY(_dmamap_load_uio);
791 1.9 eeh dt->_dmamap_load_raw = psycho_dmamap_load_raw;
792 1.7 mrg dt->_dmamap_unload = psycho_dmamap_unload;
793 1.7 mrg dt->_dmamap_sync = psycho_dmamap_sync;
794 1.7 mrg dt->_dmamem_alloc = psycho_dmamem_alloc;
795 1.7 mrg dt->_dmamem_free = psycho_dmamem_free;
796 1.7 mrg dt->_dmamem_map = psycho_dmamem_map;
797 1.7 mrg dt->_dmamem_unmap = psycho_dmamem_unmap;
798 1.7 mrg PCOPY(_dmamem_mmap);
799 1.7 mrg #undef PCOPY
800 1.7 mrg return (dt);
801 1.7 mrg }
802 1.7 mrg
803 1.7 mrg /*
804 1.7 mrg * bus space support. <sparc64/dev/psychoreg.h> has a discussion about
805 1.7 mrg * PCI physical addresses.
806 1.7 mrg */
807 1.7 mrg
808 1.7 mrg static int get_childspace __P((int));
809 1.7 mrg
810 1.7 mrg static int
811 1.7 mrg get_childspace(type)
812 1.7 mrg int type;
813 1.7 mrg {
814 1.7 mrg int ss;
815 1.7 mrg
816 1.7 mrg switch (type) {
817 1.7 mrg case PCI_CONFIG_BUS_SPACE:
818 1.7 mrg ss = 0x00;
819 1.7 mrg break;
820 1.7 mrg case PCI_IO_BUS_SPACE:
821 1.7 mrg ss = 0x01;
822 1.7 mrg break;
823 1.7 mrg case PCI_MEMORY_BUS_SPACE:
824 1.7 mrg ss = 0x02;
825 1.7 mrg break;
826 1.7 mrg #if 0
827 1.7 mrg /* we don't do 64 bit memory space */
828 1.7 mrg case PCI_MEMORY64_BUS_SPACE:
829 1.7 mrg ss = 0x03;
830 1.7 mrg break;
831 1.7 mrg #endif
832 1.7 mrg default:
833 1.7 mrg panic("get_childspace: unknown bus type");
834 1.7 mrg }
835 1.7 mrg
836 1.7 mrg return (ss);
837 1.7 mrg }
838 1.7 mrg
839 1.7 mrg static int
840 1.7 mrg _psycho_bus_map(t, btype, offset, size, flags, vaddr, hp)
841 1.7 mrg bus_space_tag_t t;
842 1.7 mrg bus_type_t btype;
843 1.7 mrg bus_addr_t offset;
844 1.7 mrg bus_size_t size;
845 1.7 mrg int flags;
846 1.7 mrg vaddr_t vaddr;
847 1.7 mrg bus_space_handle_t *hp;
848 1.7 mrg {
849 1.7 mrg struct psycho_pbm *pp = t->cookie;
850 1.7 mrg struct psycho_softc *sc = pp->pp_sc;
851 1.7 mrg int i, ss;
852 1.7 mrg
853 1.27 fvdl DPRINTF(PDB_BUSMAP, ("_psycho_bus_map: type %d off %qx sz %qx flags %d va %p", t->type, (unsigned long long)offset, (unsigned long long)size, flags,
854 1.27 fvdl (void *)vaddr));
855 1.7 mrg
856 1.7 mrg ss = get_childspace(t->type);
857 1.7 mrg DPRINTF(PDB_BUSMAP, (" cspace %d", ss));
858 1.7 mrg
859 1.7 mrg for (i = 0; i < pp->pp_nrange; i++) {
860 1.7 mrg bus_addr_t paddr;
861 1.7 mrg
862 1.7 mrg if (((pp->pp_range[i].cspace >> 24) & 0x03) != ss)
863 1.7 mrg continue;
864 1.7 mrg
865 1.7 mrg paddr = pp->pp_range[i].phys_lo + offset;
866 1.7 mrg paddr |= ((bus_addr_t)pp->pp_range[i].phys_hi<<32);
867 1.7 mrg DPRINTF(PDB_BUSMAP, ("\n_psycho_bus_map: mapping paddr space %lx offset %lx paddr %qx\n",
868 1.27 fvdl (long)ss, (long)offset,
869 1.27 fvdl (unsigned long long)paddr));
870 1.7 mrg return (bus_space_map2(sc->sc_bustag, t->type, paddr,
871 1.7 mrg size, flags, vaddr, hp));
872 1.7 mrg }
873 1.7 mrg DPRINTF(PDB_BUSMAP, (" FAILED\n"));
874 1.7 mrg return (EINVAL);
875 1.7 mrg }
876 1.7 mrg
877 1.37 eeh static paddr_t
878 1.37 eeh psycho_bus_mmap(t, paddr, off, prot, flags)
879 1.7 mrg bus_space_tag_t t;
880 1.7 mrg bus_addr_t paddr;
881 1.37 eeh off_t off;
882 1.37 eeh int prot;
883 1.7 mrg int flags;
884 1.7 mrg {
885 1.7 mrg bus_addr_t offset = paddr;
886 1.7 mrg struct psycho_pbm *pp = t->cookie;
887 1.7 mrg struct psycho_softc *sc = pp->pp_sc;
888 1.7 mrg int i, ss;
889 1.7 mrg
890 1.7 mrg ss = get_childspace(t->type);
891 1.7 mrg
892 1.37 eeh DPRINTF(PDB_BUSMAP, ("_psycho_bus_mmap: prot %x flags %d pa %qx\n",
893 1.37 eeh prot, flags, (unsigned long long)paddr));
894 1.7 mrg
895 1.7 mrg for (i = 0; i < pp->pp_nrange; i++) {
896 1.7 mrg bus_addr_t paddr;
897 1.7 mrg
898 1.7 mrg if (((pp->pp_range[i].cspace >> 24) & 0x03) != ss)
899 1.7 mrg continue;
900 1.7 mrg
901 1.7 mrg paddr = pp->pp_range[i].phys_lo + offset;
902 1.7 mrg paddr |= ((bus_addr_t)pp->pp_range[i].phys_hi<<32);
903 1.37 eeh DPRINTF(PDB_BUSMAP, ("\n_psycho_bus_mmap: mapping paddr "
904 1.37 eeh "space %lx offset %lx paddr %qx\n",
905 1.27 fvdl (long)ss, (long)offset,
906 1.27 fvdl (unsigned long long)paddr));
907 1.37 eeh return (bus_space_mmap(sc->sc_bustag, paddr, off,
908 1.37 eeh prot, flags));
909 1.7 mrg }
910 1.7 mrg
911 1.7 mrg return (-1);
912 1.7 mrg }
913 1.7 mrg
914 1.7 mrg
915 1.7 mrg /*
916 1.7 mrg * install an interrupt handler for a PCI device
917 1.7 mrg */
918 1.7 mrg void *
919 1.21 pk psycho_intr_establish(t, ihandle, level, flags, handler, arg)
920 1.7 mrg bus_space_tag_t t;
921 1.21 pk int ihandle;
922 1.7 mrg int level;
923 1.7 mrg int flags;
924 1.7 mrg int (*handler) __P((void *));
925 1.7 mrg void *arg;
926 1.7 mrg {
927 1.7 mrg struct psycho_pbm *pp = t->cookie;
928 1.7 mrg struct psycho_softc *sc = pp->pp_sc;
929 1.7 mrg struct intrhand *ih;
930 1.34 eeh volatile u_int64_t *intrmapptr = NULL, *intrclrptr = NULL;
931 1.34 eeh int64_t intrmap = 0;
932 1.7 mrg int ino;
933 1.34 eeh long vec = INTVEC(ihandle);
934 1.7 mrg
935 1.7 mrg ih = (struct intrhand *)
936 1.7 mrg malloc(sizeof(struct intrhand), M_DEVBUF, M_NOWAIT);
937 1.7 mrg if (ih == NULL)
938 1.7 mrg return (NULL);
939 1.7 mrg
940 1.34 eeh /*
941 1.34 eeh * Hunt through all the interrupt mapping regs to look for our
942 1.34 eeh * interrupt vector.
943 1.34 eeh *
944 1.34 eeh * XXX We only compare INOs rather than IGNs since the firmware may
945 1.34 eeh * not provide the IGN and the IGN is constant for all device on that
946 1.34 eeh * PCI controller. This could cause problems for the FFB/external
947 1.34 eeh * interrupt which has a full vector that can be set arbitrarily.
948 1.34 eeh */
949 1.34 eeh
950 1.34 eeh
951 1.31 mrg DPRINTF(PDB_INTR, ("\npsycho_intr_establish: ihandle %x vec %lx", ihandle, vec));
952 1.7 mrg ino = INTINO(vec);
953 1.7 mrg DPRINTF(PDB_INTR, (" ino %x", ino));
954 1.34 eeh
955 1.34 eeh /* If the device didn't ask for an IPL, use the one encoded. */
956 1.34 eeh if (level == IPL_NONE) level = INTLEV(vec);
957 1.34 eeh /* If it still has no level, print a warning and assign IPL 2 */
958 1.34 eeh if (level == IPL_NONE) {
959 1.34 eeh printf("ERROR: no IPL, setting IPL 2.\n");
960 1.34 eeh level = 2;
961 1.34 eeh }
962 1.34 eeh
963 1.7 mrg if ((flags & BUS_INTR_ESTABLISH_SOFTINTR) == 0) {
964 1.7 mrg
965 1.27 fvdl DPRINTF(PDB_INTR, ("\npsycho: intr %lx: %p\nHunting for IRQ...\n",
966 1.7 mrg (long)ino, intrlev[ino]));
967 1.7 mrg
968 1.34 eeh /* Hunt thru obio first */
969 1.34 eeh for (intrmapptr = &sc->sc_regs->scsi_int_map,
970 1.34 eeh intrclrptr = &sc->sc_regs->scsi_clr_int;
971 1.34 eeh intrmapptr <= &sc->sc_regs->ffb1_int_map;
972 1.34 eeh intrmapptr++, intrclrptr++) {
973 1.34 eeh if (INTINO(*intrmapptr) == ino)
974 1.34 eeh goto found;
975 1.34 eeh }
976 1.7 mrg
977 1.34 eeh /* Now do PCI interrupts */
978 1.34 eeh for (intrmapptr = &sc->sc_regs->pcia_slot0_int,
979 1.34 eeh intrclrptr = &sc->sc_regs->pcia0_clr_int[0];
980 1.34 eeh intrmapptr <= &sc->sc_regs->pcib_slot3_int;
981 1.34 eeh intrmapptr++, intrclrptr += 4) {
982 1.34 eeh if (((*intrmapptr ^ vec) & 0x3c) == 0) {
983 1.34 eeh intrclrptr += vec & 0x3;
984 1.34 eeh goto found;
985 1.34 eeh }
986 1.7 mrg }
987 1.34 eeh printf("Cannot find interrupt vector %lx\n", vec);
988 1.34 eeh return (NULL);
989 1.7 mrg
990 1.34 eeh found:
991 1.7 mrg /* Register the map and clear intr registers */
992 1.7 mrg ih->ih_map = intrmapptr;
993 1.7 mrg ih->ih_clr = intrclrptr;
994 1.7 mrg }
995 1.10 mrg #ifdef NOT_DEBUG
996 1.7 mrg if (psycho_debug & PDB_INTR) {
997 1.7 mrg long i;
998 1.7 mrg
999 1.7 mrg for (i = 0; i < 500000000; i++)
1000 1.7 mrg continue;
1001 1.7 mrg }
1002 1.7 mrg #endif
1003 1.7 mrg
1004 1.7 mrg ih->ih_fun = handler;
1005 1.7 mrg ih->ih_arg = arg;
1006 1.34 eeh ih->ih_pil = level;
1007 1.24 pk ih->ih_number = ino | sc->sc_ign;
1008 1.19 pk
1009 1.19 pk DPRINTF(PDB_INTR, (
1010 1.19 pk "; installing handler %p arg %p with ino %u pil %u\n",
1011 1.19 pk handler, arg, (u_int)ino, (u_int)ih->ih_pil));
1012 1.19 pk
1013 1.7 mrg intr_establish(ih->ih_pil, ih);
1014 1.34 eeh
1015 1.34 eeh /*
1016 1.34 eeh * Enable the interrupt now we have the handler installed.
1017 1.34 eeh * Read the current value as we can't change it besides the
1018 1.34 eeh * valid bit so so make sure only this bit is changed.
1019 1.34 eeh *
1020 1.34 eeh * XXXX --- we really should use bus_space for this.
1021 1.34 eeh */
1022 1.34 eeh if (intrmapptr) {
1023 1.34 eeh intrmap = *intrmapptr;
1024 1.34 eeh DPRINTF(PDB_INTR, ("; read intrmap = %016qx",
1025 1.34 eeh (unsigned long long)intrmap));
1026 1.34 eeh
1027 1.34 eeh /* Enable the interrupt */
1028 1.34 eeh intrmap |= INTMAP_V;
1029 1.34 eeh DPRINTF(PDB_INTR, ("; addr of intrmapptr = %p", intrmapptr));
1030 1.34 eeh DPRINTF(PDB_INTR, ("; writing intrmap = %016qx\n",
1031 1.34 eeh (unsigned long long)intrmap));
1032 1.34 eeh *intrmapptr = intrmap;
1033 1.34 eeh DPRINTF(PDB_INTR, ("; reread intrmap = %016qx",
1034 1.34 eeh (unsigned long long)(intrmap = *intrmapptr)));
1035 1.34 eeh }
1036 1.7 mrg return (ih);
1037 1.7 mrg }
1038 1.7 mrg
1039 1.7 mrg /*
1040 1.7 mrg * hooks into the iommu dvma calls.
1041 1.7 mrg */
1042 1.7 mrg int
1043 1.7 mrg psycho_dmamap_load(t, map, buf, buflen, p, flags)
1044 1.7 mrg bus_dma_tag_t t;
1045 1.7 mrg bus_dmamap_t map;
1046 1.7 mrg void *buf;
1047 1.7 mrg bus_size_t buflen;
1048 1.7 mrg struct proc *p;
1049 1.7 mrg int flags;
1050 1.7 mrg {
1051 1.7 mrg struct psycho_pbm *pp = (struct psycho_pbm *)t->_cookie;
1052 1.7 mrg struct psycho_softc *sc = pp->pp_sc;
1053 1.7 mrg
1054 1.24 pk return (iommu_dvmamap_load(t, sc->sc_is, map, buf, buflen, p, flags));
1055 1.7 mrg }
1056 1.7 mrg
1057 1.7 mrg void
1058 1.7 mrg psycho_dmamap_unload(t, map)
1059 1.7 mrg bus_dma_tag_t t;
1060 1.7 mrg bus_dmamap_t map;
1061 1.7 mrg {
1062 1.7 mrg struct psycho_pbm *pp = (struct psycho_pbm *)t->_cookie;
1063 1.7 mrg struct psycho_softc *sc = pp->pp_sc;
1064 1.7 mrg
1065 1.24 pk iommu_dvmamap_unload(t, sc->sc_is, map);
1066 1.9 eeh }
1067 1.9 eeh
1068 1.9 eeh int
1069 1.10 mrg psycho_dmamap_load_raw(t, map, segs, nsegs, size, flags)
1070 1.10 mrg bus_dma_tag_t t;
1071 1.9 eeh bus_dmamap_t map;
1072 1.9 eeh bus_dma_segment_t *segs;
1073 1.9 eeh int nsegs;
1074 1.9 eeh bus_size_t size;
1075 1.9 eeh int flags;
1076 1.9 eeh {
1077 1.9 eeh struct psycho_pbm *pp = (struct psycho_pbm *)t->_cookie;
1078 1.9 eeh struct psycho_softc *sc = pp->pp_sc;
1079 1.9 eeh
1080 1.24 pk return (iommu_dvmamap_load_raw(t, sc->sc_is, map, segs, nsegs, flags, size));
1081 1.7 mrg }
1082 1.7 mrg
1083 1.7 mrg void
1084 1.7 mrg psycho_dmamap_sync(t, map, offset, len, ops)
1085 1.7 mrg bus_dma_tag_t t;
1086 1.7 mrg bus_dmamap_t map;
1087 1.7 mrg bus_addr_t offset;
1088 1.7 mrg bus_size_t len;
1089 1.7 mrg int ops;
1090 1.7 mrg {
1091 1.7 mrg struct psycho_pbm *pp = (struct psycho_pbm *)t->_cookie;
1092 1.7 mrg struct psycho_softc *sc = pp->pp_sc;
1093 1.7 mrg
1094 1.13 eeh if (ops & (BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE)) {
1095 1.13 eeh /* Flush the CPU then the IOMMU */
1096 1.13 eeh bus_dmamap_sync(t->_parent, map, offset, len, ops);
1097 1.24 pk iommu_dvmamap_sync(t, sc->sc_is, map, offset, len, ops);
1098 1.13 eeh }
1099 1.13 eeh if (ops & (BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE)) {
1100 1.13 eeh /* Flush the IOMMU then the CPU */
1101 1.24 pk iommu_dvmamap_sync(t, sc->sc_is, map, offset, len, ops);
1102 1.13 eeh bus_dmamap_sync(t->_parent, map, offset, len, ops);
1103 1.13 eeh }
1104 1.13 eeh
1105 1.7 mrg }
1106 1.7 mrg
1107 1.7 mrg int
1108 1.7 mrg psycho_dmamem_alloc(t, size, alignment, boundary, segs, nsegs, rsegs, flags)
1109 1.7 mrg bus_dma_tag_t t;
1110 1.7 mrg bus_size_t size;
1111 1.7 mrg bus_size_t alignment;
1112 1.7 mrg bus_size_t boundary;
1113 1.7 mrg bus_dma_segment_t *segs;
1114 1.7 mrg int nsegs;
1115 1.7 mrg int *rsegs;
1116 1.7 mrg int flags;
1117 1.7 mrg {
1118 1.7 mrg struct psycho_pbm *pp = (struct psycho_pbm *)t->_cookie;
1119 1.7 mrg struct psycho_softc *sc = pp->pp_sc;
1120 1.7 mrg
1121 1.24 pk return (iommu_dvmamem_alloc(t, sc->sc_is, size, alignment, boundary,
1122 1.7 mrg segs, nsegs, rsegs, flags));
1123 1.7 mrg }
1124 1.7 mrg
1125 1.7 mrg void
1126 1.7 mrg psycho_dmamem_free(t, segs, nsegs)
1127 1.7 mrg bus_dma_tag_t t;
1128 1.7 mrg bus_dma_segment_t *segs;
1129 1.7 mrg int nsegs;
1130 1.7 mrg {
1131 1.7 mrg struct psycho_pbm *pp = (struct psycho_pbm *)t->_cookie;
1132 1.7 mrg struct psycho_softc *sc = pp->pp_sc;
1133 1.7 mrg
1134 1.24 pk iommu_dvmamem_free(t, sc->sc_is, segs, nsegs);
1135 1.7 mrg }
1136 1.7 mrg
1137 1.7 mrg int
1138 1.7 mrg psycho_dmamem_map(t, segs, nsegs, size, kvap, flags)
1139 1.7 mrg bus_dma_tag_t t;
1140 1.7 mrg bus_dma_segment_t *segs;
1141 1.7 mrg int nsegs;
1142 1.7 mrg size_t size;
1143 1.7 mrg caddr_t *kvap;
1144 1.7 mrg int flags;
1145 1.7 mrg {
1146 1.7 mrg struct psycho_pbm *pp = (struct psycho_pbm *)t->_cookie;
1147 1.7 mrg struct psycho_softc *sc = pp->pp_sc;
1148 1.7 mrg
1149 1.24 pk return (iommu_dvmamem_map(t, sc->sc_is, segs, nsegs, size, kvap, flags));
1150 1.7 mrg }
1151 1.7 mrg
1152 1.7 mrg void
1153 1.7 mrg psycho_dmamem_unmap(t, kva, size)
1154 1.7 mrg bus_dma_tag_t t;
1155 1.7 mrg caddr_t kva;
1156 1.7 mrg size_t size;
1157 1.7 mrg {
1158 1.7 mrg struct psycho_pbm *pp = (struct psycho_pbm *)t->_cookie;
1159 1.7 mrg struct psycho_softc *sc = pp->pp_sc;
1160 1.7 mrg
1161 1.24 pk iommu_dvmamem_unmap(t, sc->sc_is, kva, size);
1162 1.1 mrg }
1163