psycho.c revision 1.101
1 /* $NetBSD: psycho.c,v 1.101 2010/07/10 10:07:40 nakayama Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000 Matthew R. Green 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * Copyright (c) 2001, 2002 Eduardo E. Horvath 31 * All rights reserved. 32 * 33 * Redistribution and use in source and binary forms, with or without 34 * modification, are permitted provided that the following conditions 35 * are met: 36 * 1. Redistributions of source code must retain the above copyright 37 * notice, this list of conditions and the following disclaimer. 38 * 2. Redistributions in binary form must reproduce the above copyright 39 * notice, this list of conditions and the following disclaimer in the 40 * documentation and/or other materials provided with the distribution. 41 * 3. The name of the author may not be used to endorse or promote products 42 * derived from this software without specific prior written permission. 43 * 44 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 45 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 46 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 47 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 48 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 49 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 50 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 51 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 52 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 53 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 54 * SUCH DAMAGE. 55 */ 56 57 #include <sys/cdefs.h> 58 __KERNEL_RCSID(0, "$NetBSD: psycho.c,v 1.101 2010/07/10 10:07:40 nakayama Exp $"); 59 60 #include "opt_ddb.h" 61 62 /* 63 * Support for `psycho' and `psycho+' UPA to PCI bridge and 64 * UltraSPARC IIi and IIe `sabre' PCI controllers. 65 */ 66 67 #ifdef DEBUG 68 #define PDB_PROM 0x01 69 #define PDB_BUSMAP 0x02 70 #define PDB_INTR 0x04 71 #define PDB_INTMAP 0x08 72 #define PDB_CONF 0x10 73 int psycho_debug = 0x0; 74 #define DPRINTF(l, s) do { if (psycho_debug & l) printf s; } while (0) 75 #else 76 #define DPRINTF(l, s) 77 #endif 78 79 #include <sys/param.h> 80 #include <sys/device.h> 81 #include <sys/errno.h> 82 #include <sys/extent.h> 83 #include <sys/malloc.h> 84 #include <sys/systm.h> 85 #include <sys/time.h> 86 #include <sys/reboot.h> 87 88 #include <uvm/uvm.h> 89 90 #define _SPARC_BUS_DMA_PRIVATE 91 #include <machine/bus.h> 92 #include <machine/autoconf.h> 93 #include <machine/psl.h> 94 95 #include <dev/pci/pcivar.h> 96 #include <dev/pci/pcireg.h> 97 #include <dev/sysmon/sysmon_taskq.h> 98 99 #include <sparc64/dev/iommureg.h> 100 #include <sparc64/dev/iommuvar.h> 101 #include <sparc64/dev/psychoreg.h> 102 #include <sparc64/dev/psychovar.h> 103 104 #include "ioconf.h" 105 106 static pci_chipset_tag_t psycho_alloc_chipset(struct psycho_pbm *, int, 107 pci_chipset_tag_t); 108 static struct extent *psycho_alloc_extent(struct psycho_pbm *, int, int, 109 const char *); 110 static void psycho_get_bus_range(int, int *); 111 static void psycho_get_ranges(int, struct psycho_ranges **, int *); 112 static void psycho_set_intr(struct psycho_softc *, int, void *, uint64_t *, 113 uint64_t *); 114 115 /* chipset handlers */ 116 static pcireg_t psycho_pci_conf_read(pci_chipset_tag_t, pcitag_t, int); 117 static void psycho_pci_conf_write(pci_chipset_tag_t, pcitag_t, int, 118 pcireg_t); 119 static void *psycho_pci_intr_establish(pci_chipset_tag_t, 120 pci_intr_handle_t, 121 int, int (*)(void *), void *); 122 static int psycho_pci_find_ino(struct pci_attach_args *, 123 pci_intr_handle_t *); 124 125 /* Interrupt handlers */ 126 static int psycho_ue(void *); 127 static int psycho_ce(void *); 128 static int psycho_bus_a(void *); 129 static int psycho_bus_b(void *); 130 static int psycho_powerfail(void *); 131 static int psycho_wakeup(void *); 132 133 134 /* IOMMU support */ 135 static void psycho_iommu_init(struct psycho_softc *, int); 136 137 /* 138 * bus space and bus DMA support for UltraSPARC `psycho'. note that most 139 * of the bus DMA support is provided by the iommu dvma controller. 140 */ 141 static struct psycho_ranges *get_psychorange(struct psycho_pbm *, int); 142 143 static paddr_t psycho_bus_mmap(bus_space_tag_t, bus_addr_t, off_t, int, int); 144 static int _psycho_bus_map(bus_space_tag_t, bus_addr_t, bus_size_t, int, 145 vaddr_t, bus_space_handle_t *); 146 static void *psycho_intr_establish(bus_space_tag_t, int, int, int (*)(void *), 147 void *, void(*)(void)); 148 149 static int psycho_dmamap_create(bus_dma_tag_t, bus_size_t, int, bus_size_t, 150 bus_size_t, int, bus_dmamap_t *); 151 static void psycho_sabre_dmamap_sync(bus_dma_tag_t, bus_dmamap_t, bus_addr_t, 152 bus_size_t, int); 153 154 /* base pci_chipset */ 155 extern struct sparc_pci_chipset _sparc_pci_chipset; 156 157 /* power button handlers */ 158 static void psycho_register_power_button(struct psycho_softc *sc); 159 static void psycho_power_button_pressed(void *arg); 160 161 /* 162 * autoconfiguration 163 */ 164 static int psycho_match(struct device *, struct cfdata *, void *); 165 static void psycho_attach(struct device *, struct device *, void *); 166 static int psycho_print(void *aux, const char *p); 167 168 CFATTACH_DECL(psycho, sizeof(struct psycho_softc), 169 psycho_match, psycho_attach, NULL, NULL); 170 171 /* 172 * "sabre" is the UltraSPARC IIi onboard UPA to PCI bridge. It manages a 173 * single PCI bus and does not have a streaming buffer. It often has an APB 174 * (advanced PCI bridge) connected to it, which was designed specifically for 175 * the IIi. The APB let's the IIi handle two independednt PCI buses, and 176 * appears as two "simba"'s underneath the sabre. 177 * 178 * "psycho" and "psycho+" is a dual UPA to PCI bridge. It sits on the UPA bus 179 * and manages two PCI buses. "psycho" has two 64-bit 33 MHz buses, while 180 * "psycho+" controls both a 64-bit 33 MHz and a 64-bit 66 MHz PCI bus. You 181 * will usually find a "psycho+" since I don't think the original "psycho" 182 * ever shipped, and if it did it would be in the U30. 183 * 184 * Each "psycho" PCI bus appears as a separate OFW node, but since they are 185 * both part of the same IC, they only have a single register space. As such, 186 * they need to be configured together, even though the autoconfiguration will 187 * attach them separately. 188 * 189 * On UltraIIi machines, "sabre" itself usually takes pci0, with "simba" often 190 * as pci1 and pci2, although they have been implemented with other PCI bus 191 * numbers on some machines. 192 * 193 * On UltraII machines, there can be any number of "psycho+" ICs, each 194 * providing two PCI buses. 195 * 196 * 197 * XXXX The psycho/sabre node has an `interrupts' attribute. They contain 198 * the values of the following interrupts in this order: 199 * 200 * PCI Bus Error (30) 201 * DMA UE (2e) 202 * DMA CE (2f) 203 * Power Fail (25) 204 * 205 * We really should attach handlers for each. 206 * 207 */ 208 209 #define ROM_PCI_NAME "pci" 210 211 struct psycho_names { 212 const char *p_name; 213 int p_type; 214 } psycho_names[] = { 215 { "SUNW,psycho", PSYCHO_MODE_PSYCHO }, 216 { "pci108e,8000", PSYCHO_MODE_PSYCHO }, 217 { "SUNW,sabre", PSYCHO_MODE_SABRE }, 218 { "pci108e,a000", PSYCHO_MODE_SABRE }, 219 { "pci108e,a001", PSYCHO_MODE_SABRE }, 220 { NULL, 0 } 221 }; 222 223 static int 224 psycho_match(struct device *parent, struct cfdata *match, void *aux) 225 { 226 struct mainbus_attach_args *ma = aux; 227 char *model = prom_getpropstring(ma->ma_node, "model"); 228 int i; 229 230 /* match on a name of "pci" and a sabre or a psycho */ 231 if (strcmp(ma->ma_name, ROM_PCI_NAME) == 0) { 232 for (i=0; psycho_names[i].p_name; i++) 233 if (strcmp(model, psycho_names[i].p_name) == 0) 234 return (1); 235 236 model = prom_getpropstring(ma->ma_node, "compatible"); 237 for (i=0; psycho_names[i].p_name; i++) 238 if (strcmp(model, psycho_names[i].p_name) == 0) 239 return (1); 240 } 241 return (0); 242 } 243 244 #ifdef DEBUG 245 static void psycho_dump_intmap(struct psycho_softc *sc); 246 static void 247 psycho_dump_intmap(struct psycho_softc *sc) 248 { 249 volatile uint64_t *intrmapptr = NULL; 250 251 printf("psycho_dump_intmap: OBIO\n"); 252 253 for (intrmapptr = &sc->sc_regs->scsi_int_map; 254 intrmapptr < &sc->sc_regs->ue_int_map; 255 intrmapptr++) 256 printf("%p: %llx\n", intrmapptr, 257 (unsigned long long)*intrmapptr); 258 259 printf("\tintmap:pci\n"); 260 for (intrmapptr = &sc->sc_regs->pcia_slot0_int; 261 intrmapptr <= &sc->sc_regs->pcib_slot3_int; 262 intrmapptr++) 263 printf("%p: %llx\n", intrmapptr, 264 (unsigned long long)*intrmapptr); 265 266 printf("\tintmap:ffb\n"); 267 for (intrmapptr = &sc->sc_regs->ffb0_int_map; 268 intrmapptr <= &sc->sc_regs->ffb1_int_map; 269 intrmapptr++) 270 printf("%p: %llx\n", intrmapptr, 271 (unsigned long long)*intrmapptr); 272 } 273 #endif 274 275 /* 276 * SUNW,psycho initialisation .. 277 * - find the per-psycho registers 278 * - figure out the IGN. 279 * - find our partner psycho 280 * - configure ourselves 281 * - bus range, bus, 282 * - get interrupt-map and interrupt-map-mask 283 * - setup the chipsets. 284 * - if we're the first of the pair, initialise the IOMMU, otherwise 285 * just copy it's tags and addresses. 286 */ 287 static void 288 psycho_attach(struct device *parent, struct device *self, void *aux) 289 { 290 struct psycho_softc *sc = (struct psycho_softc *)self; 291 struct psycho_softc *osc = NULL; 292 struct psycho_pbm *pp; 293 struct pcibus_attach_args pba; 294 struct mainbus_attach_args *ma = aux; 295 struct psycho_ranges *pr; 296 prop_dictionary_t dict; 297 bus_space_handle_t bh; 298 uint64_t csr, mem_base; 299 int psycho_br[2], n, i; 300 bus_space_handle_t pci_ctl; 301 char *model = prom_getpropstring(ma->ma_node, "model"); 302 303 aprint_normal("\n"); 304 305 sc->sc_node = ma->ma_node; 306 sc->sc_bustag = ma->ma_bustag; 307 sc->sc_dmatag = ma->ma_dmatag; 308 309 /* 310 * Identify the device. 311 */ 312 for (i=0; psycho_names[i].p_name; i++) 313 if (strcmp(model, psycho_names[i].p_name) == 0) { 314 sc->sc_mode = psycho_names[i].p_type; 315 goto found; 316 } 317 318 model = prom_getpropstring(ma->ma_node, "compatible"); 319 for (i=0; psycho_names[i].p_name; i++) 320 if (strcmp(model, psycho_names[i].p_name) == 0) { 321 sc->sc_mode = psycho_names[i].p_type; 322 goto found; 323 } 324 325 panic("unknown psycho model %s", model); 326 found: 327 328 /* 329 * The psycho gets three register banks: 330 * (0) per-PBM configuration and status registers 331 * (1) per-PBM PCI configuration space, containing only the 332 * PBM 256-byte PCI header 333 * (2) the shared psycho configuration registers (struct psychoreg) 334 */ 335 336 /* Register layouts are different. stuupid. */ 337 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) { 338 sc->sc_basepaddr = (paddr_t)ma->ma_reg[2].ur_paddr; 339 340 if (ma->ma_naddress > 2) { 341 sparc_promaddr_to_handle(sc->sc_bustag, 342 ma->ma_address[2], &sc->sc_bh); 343 sparc_promaddr_to_handle(sc->sc_bustag, 344 ma->ma_address[0], &pci_ctl); 345 346 sc->sc_regs = (struct psychoreg *) 347 bus_space_vaddr(sc->sc_bustag, sc->sc_bh); 348 } else if (ma->ma_nreg > 2) { 349 350 /* We need to map this in ourselves. */ 351 if (bus_space_map(sc->sc_bustag, 352 ma->ma_reg[2].ur_paddr, 353 ma->ma_reg[2].ur_len, BUS_SPACE_MAP_LINEAR, 354 &sc->sc_bh)) 355 panic("psycho_attach: cannot map regs"); 356 sc->sc_regs = (struct psychoreg *) 357 bus_space_vaddr(sc->sc_bustag, sc->sc_bh); 358 359 if (bus_space_map(sc->sc_bustag, 360 ma->ma_reg[0].ur_paddr, 361 ma->ma_reg[0].ur_len, BUS_SPACE_MAP_LINEAR, 362 &pci_ctl)) 363 panic("psycho_attach: cannot map ctl"); 364 } else 365 panic("psycho_attach: %d not enough registers", 366 ma->ma_nreg); 367 368 } else { 369 sc->sc_basepaddr = (paddr_t)ma->ma_reg[0].ur_paddr; 370 371 if (ma->ma_naddress) { 372 sparc_promaddr_to_handle(sc->sc_bustag, 373 ma->ma_address[0], &sc->sc_bh); 374 sc->sc_regs = (struct psychoreg *) 375 bus_space_vaddr(sc->sc_bustag, sc->sc_bh); 376 bus_space_subregion(sc->sc_bustag, sc->sc_bh, 377 offsetof(struct psychoreg, psy_pcictl), 378 sizeof(struct pci_ctl), &pci_ctl); 379 } else if (ma->ma_nreg) { 380 381 /* We need to map this in ourselves. */ 382 if (bus_space_map(sc->sc_bustag, 383 ma->ma_reg[0].ur_paddr, 384 ma->ma_reg[0].ur_len, BUS_SPACE_MAP_LINEAR, 385 &sc->sc_bh)) 386 panic("psycho_attach: cannot map regs"); 387 sc->sc_regs = (struct psychoreg *) 388 bus_space_vaddr(sc->sc_bustag, sc->sc_bh); 389 390 bus_space_subregion(sc->sc_bustag, sc->sc_bh, 391 offsetof(struct psychoreg, psy_pcictl), 392 sizeof(struct pci_ctl), &pci_ctl); 393 } else 394 panic("psycho_attach: %d not enough registers", 395 ma->ma_nreg); 396 } 397 398 399 csr = bus_space_read_8(sc->sc_bustag, sc->sc_bh, 400 offsetof(struct psychoreg, psy_csr)); 401 sc->sc_ign = 0x7c0; /* APB IGN is always 0x7c */ 402 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) 403 sc->sc_ign = PSYCHO_GCSR_IGN(csr) << 6; 404 405 aprint_normal_dev(self, "%s: impl %d, version %d: ign %x ", 406 model, PSYCHO_GCSR_IMPL(csr), PSYCHO_GCSR_VERS(csr), 407 sc->sc_ign); 408 /* 409 * Match other psycho's that are already configured against 410 * the base physical address. This will be the same for a 411 * pair of devices that share register space. 412 */ 413 for (n = 0; n < psycho_cd.cd_ndevs; n++) { 414 415 struct psycho_softc *asc = device_lookup_private(&psycho_cd, n); 416 417 if (asc == NULL || asc == sc) 418 /* This entry is not there or it is me */ 419 continue; 420 421 if (asc->sc_basepaddr != sc->sc_basepaddr) 422 /* This is an unrelated psycho */ 423 continue; 424 425 /* Found partner */ 426 osc = asc; 427 break; 428 } 429 430 431 /* Oh, dear. OK, lets get started */ 432 433 /* 434 * Setup the PCI control register 435 */ 436 csr = bus_space_read_8(sc->sc_bustag, pci_ctl, 437 offsetof(struct pci_ctl, pci_csr)); 438 csr |= PCICTL_MRLM | 439 PCICTL_ARB_PARK | 440 PCICTL_ERRINTEN | 441 PCICTL_4ENABLE; 442 csr &= ~(PCICTL_SERR | 443 PCICTL_CPU_PRIO | 444 PCICTL_ARB_PRIO | 445 PCICTL_RTRYWAIT); 446 bus_space_write_8(sc->sc_bustag, pci_ctl, 447 offsetof(struct pci_ctl, pci_csr), csr); 448 449 450 /* 451 * Allocate our psycho_pbm 452 */ 453 pp = sc->sc_psycho_this = malloc(sizeof *pp, M_DEVBUF, 454 M_NOWAIT | M_ZERO); 455 if (pp == NULL) 456 panic("could not allocate psycho pbm"); 457 458 pp->pp_sc = sc; 459 460 /* grab the psycho ranges */ 461 psycho_get_ranges(sc->sc_node, &pp->pp_range, &pp->pp_nrange); 462 463 /* get the bus-range for the psycho */ 464 psycho_get_bus_range(sc->sc_node, psycho_br); 465 466 pba.pba_bus = psycho_br[0]; 467 pba.pba_bridgetag = NULL; 468 469 aprint_normal("bus range %u to %u", psycho_br[0], psycho_br[1]); 470 aprint_normal("; PCI bus %d", psycho_br[0]); 471 472 pp->pp_pcictl = pci_ctl; 473 474 /* allocate our tags */ 475 pp->pp_memt = psycho_alloc_mem_tag(pp); 476 pp->pp_iot = psycho_alloc_io_tag(pp); 477 pp->pp_dmat = psycho_alloc_dma_tag(pp); 478 pp->pp_flags = (pp->pp_memt ? PCI_FLAGS_MEM_ENABLED : 0) | 479 (pp->pp_iot ? PCI_FLAGS_IO_ENABLED : 0); 480 481 /* allocate a chipset for this */ 482 pp->pp_pc = psycho_alloc_chipset(pp, sc->sc_node, &_sparc_pci_chipset); 483 pp->pp_pc->spc_busmax = psycho_br[1]; 484 485 switch((ma->ma_reg[0].ur_paddr) & 0xf000) { 486 case 0x2000: 487 pp->pp_id = PSYCHO_PBM_A; 488 break; 489 case 0x4000: 490 pp->pp_id = PSYCHO_PBM_B; 491 break; 492 } 493 494 aprint_normal("\n"); 495 496 /* allocate extents for free bus space */ 497 pp->pp_exmem = psycho_alloc_extent(pp, sc->sc_node, 0x02, "psycho mem"); 498 pp->pp_exio = psycho_alloc_extent(pp, sc->sc_node, 0x01, "psycho io"); 499 500 #ifdef DEBUG 501 if (psycho_debug & PDB_INTR) 502 psycho_dump_intmap(sc); 503 #endif 504 505 /* 506 * And finally, if we're a sabre or the first of a pair of psycho's to 507 * arrive here, start up the IOMMU and get a config space tag. 508 */ 509 if (osc == NULL) { 510 uint64_t timeo; 511 512 /* 513 * Establish handlers for interesting interrupts.... 514 * 515 * XXX We need to remember these and remove this to support 516 * hotplug on the UPA/FHC bus. 517 * 518 * XXX Not all controllers have these, but installing them 519 * is better than trying to sort through this mess. 520 */ 521 psycho_set_intr(sc, 15, psycho_ue, 522 &sc->sc_regs->ue_int_map, 523 &sc->sc_regs->ue_clr_int); 524 psycho_set_intr(sc, 1, psycho_ce, 525 &sc->sc_regs->ce_int_map, 526 &sc->sc_regs->ce_clr_int); 527 psycho_set_intr(sc, 15, psycho_bus_a, 528 &sc->sc_regs->pciaerr_int_map, 529 &sc->sc_regs->pciaerr_clr_int); 530 psycho_set_intr(sc, 15, psycho_powerfail, 531 &sc->sc_regs->power_int_map, 532 &sc->sc_regs->power_clr_int); 533 psycho_register_power_button(sc); 534 if (sc->sc_mode != PSYCHO_MODE_SABRE) { 535 /* sabre doesn't have these interrupts */ 536 psycho_set_intr(sc, 15, psycho_bus_b, 537 &sc->sc_regs->pciberr_int_map, 538 &sc->sc_regs->pciberr_clr_int); 539 psycho_set_intr(sc, 1, psycho_wakeup, 540 &sc->sc_regs->pwrmgt_int_map, 541 &sc->sc_regs->pwrmgt_clr_int); 542 } 543 544 /* 545 * Apparently a number of machines with psycho and psycho+ 546 * controllers have interrupt latency issues. We'll try 547 * setting the interrupt retry timeout to 0xff which gives us 548 * a retry of 3-6 usec (which is what sysio is set to) for the 549 * moment, which seems to help alleviate this problem. 550 */ 551 timeo = sc->sc_regs->intr_retry_timer; 552 if (timeo > 0xfff) { 553 #ifdef DEBUG 554 printf("decreasing interrupt retry timeout " 555 "from %lx to 0xff\n", (long)timeo); 556 #endif 557 sc->sc_regs->intr_retry_timer = 0xff; 558 } 559 560 /* 561 * Allocate bus node, this contains a prom node per bus. 562 */ 563 pp->pp_pc->spc_busnode = 564 malloc(sizeof(*pp->pp_pc->spc_busnode), M_DEVBUF, 565 M_NOWAIT | M_ZERO); 566 if (pp->pp_pc->spc_busnode == NULL) 567 panic("psycho_attach: malloc busnode"); 568 569 /* 570 * Setup IOMMU and PCI configuration if we're the first 571 * of a pair of psycho's to arrive here. 572 * 573 * We should calculate a TSB size based on amount of RAM 574 * and number of bus controllers and number an type of 575 * child devices. 576 * 577 * For the moment, 32KB should be more than enough. 578 */ 579 sc->sc_is = malloc(sizeof(struct iommu_state), 580 M_DEVBUF, M_NOWAIT); 581 if (sc->sc_is == NULL) 582 panic("psycho_attach: malloc iommu_state"); 583 584 /* Point the strbuf_ctl at the iommu_state */ 585 pp->pp_sb.sb_is = sc->sc_is; 586 587 sc->sc_is->is_sb[0] = sc->sc_is->is_sb[1] = NULL; 588 if (prom_getproplen(sc->sc_node, "no-streaming-cache") < 0) { 589 struct strbuf_ctl *sb = &pp->pp_sb; 590 vaddr_t va = (vaddr_t)&pp->pp_flush[0x40]; 591 592 /* 593 * Initialize the strbuf_ctl. 594 * 595 * The flush sync buffer must be 64-byte aligned. 596 */ 597 sb->sb_flush = (void *)(va & ~0x3f); 598 599 bus_space_subregion(sc->sc_bustag, pci_ctl, 600 offsetof(struct pci_ctl, pci_strbuf), 601 sizeof (struct iommu_strbuf), &sb->sb_sb); 602 603 /* Point our iommu at the strbuf_ctl */ 604 sc->sc_is->is_sb[0] = sb; 605 } 606 607 psycho_iommu_init(sc, 2); 608 609 sc->sc_configtag = psycho_alloc_config_tag(sc->sc_psycho_this); 610 611 /* 612 * XXX This is a really ugly hack because PCI config space 613 * is explicitly handled with unmapped accesses. 614 */ 615 i = sc->sc_bustag->type; 616 sc->sc_bustag->type = PCI_CONFIG_BUS_SPACE; 617 if (bus_space_map(sc->sc_bustag, sc->sc_basepaddr + 0x01000000, 618 0x01000000, 0, &bh)) 619 panic("could not map psycho PCI configuration space"); 620 sc->sc_bustag->type = i; 621 sc->sc_configaddr = bh; 622 } else { 623 /* Share bus numbers with the pair of mine */ 624 pp->pp_pc->spc_busnode = 625 osc->sc_psycho_this->pp_pc->spc_busnode; 626 627 /* Just copy IOMMU state, config tag and address */ 628 sc->sc_is = osc->sc_is; 629 sc->sc_configtag = osc->sc_configtag; 630 sc->sc_configaddr = osc->sc_configaddr; 631 632 /* Point the strbuf_ctl at the iommu_state */ 633 pp->pp_sb.sb_is = sc->sc_is; 634 635 if (prom_getproplen(sc->sc_node, "no-streaming-cache") < 0) { 636 struct strbuf_ctl *sb = &pp->pp_sb; 637 vaddr_t va = (vaddr_t)&pp->pp_flush[0x40]; 638 639 /* 640 * Initialize the strbuf_ctl. 641 * 642 * The flush sync buffer must be 64-byte aligned. 643 */ 644 sb->sb_flush = (void *)(va & ~0x3f); 645 646 bus_space_subregion(sc->sc_bustag, pci_ctl, 647 offsetof(struct pci_ctl, pci_strbuf), 648 sizeof (struct iommu_strbuf), &sb->sb_sb); 649 650 /* Point our iommu at the strbuf_ctl */ 651 sc->sc_is->is_sb[1] = sb; 652 } 653 iommu_reset(sc->sc_is); 654 } 655 656 dict = device_properties(self); 657 pr = get_psychorange(pp, 2); /* memory range */ 658 #ifdef DEBUG 659 printf("memory range: %08x %08x\n", pr->phys_hi, pr->phys_lo); 660 #endif 661 mem_base = ((uint64_t)pr->phys_hi) << 32 | pr->phys_lo; 662 prop_dictionary_set_uint64(dict, "mem_base", mem_base); 663 664 /* 665 * attach the pci.. note we pass PCI A tags, etc., for the sabre here. 666 */ 667 pba.pba_flags = sc->sc_psycho_this->pp_flags; 668 pba.pba_dmat = sc->sc_psycho_this->pp_dmat; 669 pba.pba_dmat64 = NULL; 670 pba.pba_iot = sc->sc_psycho_this->pp_iot; 671 pba.pba_memt = sc->sc_psycho_this->pp_memt; 672 pba.pba_pc = pp->pp_pc; 673 674 config_found_ia(self, "pcibus", &pba, psycho_print); 675 } 676 677 static int 678 psycho_print(void *aux, const char *p) 679 { 680 681 if (p == NULL) 682 return (UNCONF); 683 return (QUIET); 684 } 685 686 static void 687 psycho_set_intr(struct psycho_softc *sc, int ipl, void *handler, 688 uint64_t *mapper, uint64_t *clearer) 689 { 690 struct intrhand *ih; 691 692 ih = (struct intrhand *)malloc(sizeof(struct intrhand), 693 M_DEVBUF, M_NOWAIT); 694 ih->ih_arg = sc; 695 ih->ih_map = mapper; 696 ih->ih_clr = clearer; 697 ih->ih_fun = handler; 698 ih->ih_pil = (1<<ipl); 699 ih->ih_number = INTVEC(*(ih->ih_map)); 700 intr_establish(ipl, ipl != IPL_VM, ih); 701 *(ih->ih_map) |= INTMAP_V|(CPU_UPAID << INTMAP_TID_SHIFT); 702 } 703 704 /* 705 * power button handlers 706 */ 707 static void 708 psycho_register_power_button(struct psycho_softc *sc) 709 { 710 sysmon_task_queue_init(); 711 712 sc->sc_powerpressed = 0; 713 sc->sc_smcontext = malloc(sizeof(struct sysmon_pswitch), M_DEVBUF, 0); 714 if (!sc->sc_smcontext) { 715 aprint_error_dev(&sc->sc_dev, "could not allocate power button context\n"); 716 return; 717 } 718 memset(sc->sc_smcontext, 0, sizeof(struct sysmon_pswitch)); 719 sc->sc_smcontext->smpsw_name = device_xname(&sc->sc_dev); 720 sc->sc_smcontext->smpsw_type = PSWITCH_TYPE_POWER; 721 if (sysmon_pswitch_register(sc->sc_smcontext) != 0) 722 aprint_error_dev(&sc->sc_dev, "unable to register power button with sysmon\n"); 723 } 724 725 static void 726 psycho_power_button_pressed(void *arg) 727 { 728 struct psycho_softc *sc = arg; 729 730 sysmon_pswitch_event(sc->sc_smcontext, PSWITCH_EVENT_PRESSED); 731 sc->sc_powerpressed = 0; 732 } 733 734 /* 735 * PCI bus support 736 */ 737 738 /* 739 * allocate a PCI chipset tag and set it's cookie. 740 */ 741 static pci_chipset_tag_t 742 psycho_alloc_chipset(struct psycho_pbm *pp, int node, pci_chipset_tag_t pc) 743 { 744 pci_chipset_tag_t npc; 745 746 npc = malloc(sizeof *npc, M_DEVBUF, M_NOWAIT); 747 if (npc == NULL) 748 panic("could not allocate pci_chipset_tag_t"); 749 memcpy(npc, pc, sizeof *pc); 750 npc->cookie = pp; 751 npc->rootnode = node; 752 npc->spc_conf_read = psycho_pci_conf_read; 753 npc->spc_conf_write = psycho_pci_conf_write; 754 npc->spc_intr_map = NULL; 755 npc->spc_intr_establish = psycho_pci_intr_establish; 756 npc->spc_find_ino = psycho_pci_find_ino; 757 758 return (npc); 759 } 760 761 /* 762 * create extent for free bus space, then allocate assigned regions. 763 */ 764 static struct extent * 765 psycho_alloc_extent(struct psycho_pbm *pp, int node, int ss, const char *name) 766 { 767 struct psycho_registers *pa = NULL; 768 struct psycho_ranges *pr; 769 struct extent *ex; 770 bus_addr_t baddr, addr; 771 bus_size_t bsize, size; 772 int i, num; 773 774 /* get bus space size */ 775 pr = get_psychorange(pp, ss); 776 if (pr == NULL) { 777 printf("psycho_alloc_extent: get_psychorange failed\n"); 778 return NULL; 779 } 780 baddr = 0x00000000; 781 bsize = BUS_ADDR(pr->size_hi, pr->size_lo); 782 783 /* get available lists */ 784 num = 0; 785 if (prom_getprop(node, "available", sizeof(*pa), &num, &pa)) { 786 printf("psycho_alloc_extent: no \"available\" property\n"); 787 return NULL; 788 } 789 790 /* create extent */ 791 ex = extent_create(name, baddr, bsize - baddr - 1, M_DEVBUF, 0, 0, 792 EX_NOWAIT); 793 if (ex == NULL) { 794 printf("psycho_alloc_extent: extent_create failed\n"); 795 goto ret; 796 } 797 798 /* allocate assigned regions */ 799 for (i = 0; i < num; i++) 800 if (((pa[i].phys_hi >> 24) & 0x03) == ss) { 801 /* allocate bus space */ 802 addr = BUS_ADDR(pa[i].phys_mid, pa[i].phys_lo); 803 size = BUS_ADDR(pa[i].size_hi, pa[i].size_lo); 804 if (extent_alloc_region(ex, baddr, addr - baddr, 805 EX_NOWAIT)) { 806 printf("psycho_alloc_extent: " 807 "extent_alloc_region %" PRIx64 "-%" 808 PRIx64 " failed\n", baddr, addr); 809 extent_destroy(ex); 810 ex = NULL; 811 goto ret; 812 } 813 baddr = addr + size; 814 } 815 /* allocate left region if available */ 816 if (baddr < bsize) 817 if (extent_alloc_region(ex, baddr, bsize - baddr, EX_NOWAIT)) { 818 printf("psycho_alloc_extent: extent_alloc_region %" 819 PRIx64 "-%" PRIx64 " failed\n", baddr, bsize); 820 extent_destroy(ex); 821 ex = NULL; 822 goto ret; 823 } 824 825 #ifdef DEBUG 826 /* print extent */ 827 extent_print(ex); 828 #endif 829 830 ret: 831 /* return extent */ 832 free(pa, M_DEVBUF); 833 return ex; 834 } 835 836 /* 837 * grovel the OBP for various psycho properties 838 */ 839 static void 840 psycho_get_bus_range(int node, int *brp) 841 { 842 int n, error; 843 844 n = 2; 845 error = prom_getprop(node, "bus-range", sizeof(*brp), &n, &brp); 846 if (error) 847 panic("could not get psycho bus-range, error %d", error); 848 if (n != 2) 849 panic("broken psycho bus-range"); 850 DPRINTF(PDB_PROM, ("psycho debug: got `bus-range' for node %08x: %u - %u\n", 851 node, brp[0], brp[1])); 852 } 853 854 static void 855 psycho_get_ranges(int node, struct psycho_ranges **rp, int *np) 856 { 857 858 if (prom_getprop(node, "ranges", sizeof(**rp), np, rp)) 859 panic("could not get psycho ranges"); 860 DPRINTF(PDB_PROM, ("psycho debug: got `ranges' for node %08x: %d entries\n", node, *np)); 861 } 862 863 /* 864 * Interrupt handlers. 865 */ 866 867 static int 868 psycho_ue(void *arg) 869 { 870 struct psycho_softc *sc = (struct psycho_softc *)arg; 871 struct psychoreg *regs = sc->sc_regs; 872 struct iommu_state *is = sc->sc_is; 873 uint64_t afsr = regs->psy_ue_afsr; 874 uint64_t afar = regs->psy_ue_afar; 875 psize_t size = PAGE_SIZE << is->is_tsbsize; 876 char bits[128]; 877 878 /* 879 * It's uncorrectable. Dump the regs and panic. 880 */ 881 snprintb(bits, sizeof(bits), PSYCHO_UE_AFSR_BITS, afsr); 882 aprint_error_dev(&sc->sc_dev, 883 "uncorrectable DMA error AFAR %" PRIx64 " AFSR %s\n", afar, bits); 884 885 /* Sometimes the AFAR points to an IOTSB entry */ 886 if (afar >= is->is_ptsb && afar < is->is_ptsb + size) { 887 aprint_error_dev(&sc->sc_dev, 888 "IOVA %" PRIx64 " IOTTE %" PRIx64 "\n", 889 (afar - is->is_ptsb) / sizeof(is->is_tsb[0]) * PAGE_SIZE 890 + is->is_dvmabase, ldxa(afar, ASI_PHYS_CACHED)); 891 } 892 #ifdef DDB 893 Debugger(); 894 #endif 895 regs->psy_ue_afar = 0; 896 regs->psy_ue_afsr = 0; 897 return (1); 898 } 899 900 static int 901 psycho_ce(void *arg) 902 { 903 struct psycho_softc *sc = (struct psycho_softc *)arg; 904 struct psychoreg *regs = sc->sc_regs; 905 906 /* 907 * It's correctable. Dump the regs and continue. 908 */ 909 aprint_error_dev(&sc->sc_dev, 910 "correctable DMA error AFAR %" PRIx64 " AFSR %" PRIx64 "\n", 911 regs->psy_ce_afar, regs->psy_ce_afsr); 912 return (1); 913 } 914 915 static int 916 psycho_bus_a(void *arg) 917 { 918 struct psycho_softc *sc = (struct psycho_softc *)arg; 919 struct psychoreg *regs = sc->sc_regs; 920 921 /* 922 * It's uncorrectable. Dump the regs and panic. 923 */ 924 925 panic("%s: PCI bus A error AFAR %" PRIx64 " AFSR %" PRIx64, 926 device_xname(&sc->sc_dev), 927 regs->psy_pcictl[0].pci_afar, regs->psy_pcictl[0].pci_afsr); 928 return (1); 929 } 930 931 static int 932 psycho_bus_b(void *arg) 933 { 934 struct psycho_softc *sc = (struct psycho_softc *)arg; 935 struct psychoreg *regs = sc->sc_regs; 936 937 /* 938 * It's uncorrectable. Dump the regs and panic. 939 */ 940 941 panic("%s: PCI bus B error AFAR %" PRIx64 " AFSR %" PRIx64, 942 device_xname(&sc->sc_dev), 943 regs->psy_pcictl[0].pci_afar, regs->psy_pcictl[0].pci_afsr); 944 return (1); 945 } 946 947 static int 948 psycho_powerfail(void *arg) 949 { 950 struct psycho_softc *sc = (struct psycho_softc *)arg; 951 952 /* 953 * We lost power. Queue a callback with thread context to 954 * handle all the real work. 955 */ 956 if (sc->sc_powerpressed == 0 && sc->sc_smcontext != NULL) { 957 sc->sc_powerpressed = 1; 958 sysmon_task_queue_sched(0, psycho_power_button_pressed, sc); 959 } 960 return (1); 961 } 962 963 static 964 int psycho_wakeup(void *arg) 965 { 966 struct psycho_softc *sc = (struct psycho_softc *)arg; 967 968 /* 969 * Gee, we don't really have a framework to deal with this 970 * properly. 971 */ 972 aprint_error_dev(&sc->sc_dev, "power management wakeup\n"); 973 return (1); 974 } 975 976 977 /* 978 * initialise the IOMMU.. 979 */ 980 void 981 psycho_iommu_init(struct psycho_softc *sc, int tsbsize) 982 { 983 char *name; 984 struct iommu_state *is = sc->sc_is; 985 uint32_t iobase = -1; 986 int *vdma = NULL; 987 int nitem; 988 989 /* punch in our copies */ 990 is->is_bustag = sc->sc_bustag; 991 bus_space_subregion(sc->sc_bustag, sc->sc_bh, 992 offsetof(struct psychoreg, psy_iommu), 993 sizeof (struct iommureg), 994 &is->is_iommu); 995 996 /* 997 * Separate the men from the boys. Get the `virtual-dma' 998 * property for sabre and use that to make sure the damn 999 * iommu works. 1000 * 1001 * We could query the `#virtual-dma-size-cells' and 1002 * `#virtual-dma-addr-cells' and DTRT, but I'm lazy. 1003 */ 1004 nitem = 0; 1005 if (!prom_getprop(sc->sc_node, "virtual-dma", sizeof(vdma), &nitem, 1006 &vdma)) { 1007 /* Damn. Gotta use these values. */ 1008 iobase = vdma[0]; 1009 #define TSBCASE(x) case 1<<((x)+23): tsbsize = (x); break 1010 switch (vdma[1]) { 1011 TSBCASE(1); TSBCASE(2); TSBCASE(3); 1012 TSBCASE(4); TSBCASE(5); TSBCASE(6); 1013 default: 1014 printf("bogus tsb size %x, using 7\n", vdma[1]); 1015 TSBCASE(7); 1016 } 1017 #undef TSBCASE 1018 } 1019 1020 /* give us a nice name.. */ 1021 name = (char *)malloc(32, M_DEVBUF, M_NOWAIT); 1022 if (name == 0) 1023 panic("couldn't malloc iommu name"); 1024 snprintf(name, 32, "%s dvma", device_xname(&sc->sc_dev)); 1025 1026 iommu_init(name, is, tsbsize, iobase); 1027 } 1028 1029 /* 1030 * below here is bus space and bus DMA support 1031 */ 1032 bus_space_tag_t 1033 psycho_alloc_bus_tag(struct psycho_pbm *pp, int type) 1034 { 1035 struct psycho_softc *sc = pp->pp_sc; 1036 bus_space_tag_t bt; 1037 1038 bt = (bus_space_tag_t) malloc(sizeof(struct sparc_bus_space_tag), 1039 M_DEVBUF, M_NOWAIT | M_ZERO); 1040 if (bt == NULL) 1041 panic("could not allocate psycho bus tag"); 1042 1043 bt->cookie = pp; 1044 bt->parent = sc->sc_bustag; 1045 bt->type = type; 1046 bt->sparc_bus_map = _psycho_bus_map; 1047 bt->sparc_bus_mmap = psycho_bus_mmap; 1048 bt->sparc_intr_establish = psycho_intr_establish; 1049 return (bt); 1050 } 1051 1052 bus_dma_tag_t 1053 psycho_alloc_dma_tag(struct psycho_pbm *pp) 1054 { 1055 struct psycho_softc *sc = pp->pp_sc; 1056 bus_dma_tag_t dt, pdt = sc->sc_dmatag; 1057 1058 dt = (bus_dma_tag_t) 1059 malloc(sizeof(struct sparc_bus_dma_tag), M_DEVBUF, M_NOWAIT); 1060 if (dt == NULL) 1061 panic("could not allocate psycho DMA tag"); 1062 1063 memset(dt, 0, sizeof *dt); 1064 dt->_cookie = pp; 1065 dt->_parent = pdt; 1066 #define PCOPY(x) dt->x = pdt->x 1067 dt->_dmamap_create = psycho_dmamap_create; 1068 PCOPY(_dmamap_destroy); 1069 dt->_dmamap_load = iommu_dvmamap_load; 1070 PCOPY(_dmamap_load_mbuf); 1071 PCOPY(_dmamap_load_uio); 1072 dt->_dmamap_load_raw = iommu_dvmamap_load_raw; 1073 dt->_dmamap_unload = iommu_dvmamap_unload; 1074 if (sc->sc_mode == PSYCHO_MODE_SABRE) 1075 dt->_dmamap_sync = psycho_sabre_dmamap_sync; 1076 else 1077 dt->_dmamap_sync = iommu_dvmamap_sync; 1078 dt->_dmamem_alloc = iommu_dvmamem_alloc; 1079 dt->_dmamem_free = iommu_dvmamem_free; 1080 dt->_dmamem_map = iommu_dvmamem_map; 1081 dt->_dmamem_unmap = iommu_dvmamem_unmap; 1082 PCOPY(_dmamem_mmap); 1083 #undef PCOPY 1084 return (dt); 1085 } 1086 1087 /* 1088 * bus space support. <sparc64/dev/psychoreg.h> has a discussion about 1089 * PCI physical addresses. 1090 */ 1091 1092 static struct psycho_ranges * 1093 get_psychorange(struct psycho_pbm *pp, int ss) 1094 { 1095 int i; 1096 1097 for (i = 0; i < pp->pp_nrange; i++) { 1098 if (((pp->pp_range[i].cspace >> 24) & 0x03) == ss) 1099 return (&pp->pp_range[i]); 1100 } 1101 /* not found */ 1102 return (NULL); 1103 } 1104 1105 static int 1106 _psycho_bus_map(bus_space_tag_t t, bus_addr_t offset, bus_size_t size, 1107 int flags, vaddr_t unused, bus_space_handle_t *hp) 1108 { 1109 struct psycho_pbm *pp = t->cookie; 1110 struct psycho_softc *sc = pp->pp_sc; 1111 struct psycho_ranges *pr; 1112 bus_addr_t paddr; 1113 int ss; 1114 1115 DPRINTF(PDB_BUSMAP, 1116 ("_psycho_bus_map: type %d off %qx sz %qx flags %d", 1117 t->type, (unsigned long long)offset, 1118 (unsigned long long)size, flags)); 1119 1120 ss = sparc_pci_childspace(t->type); 1121 DPRINTF(PDB_BUSMAP, (" cspace %d", ss)); 1122 1123 pr = get_psychorange(pp, ss); 1124 if (pr != NULL) { 1125 paddr = BUS_ADDR(pr->phys_hi, pr->phys_lo + offset); 1126 DPRINTF(PDB_BUSMAP, ("\n_psycho_bus_map: mapping paddr " 1127 "space %lx offset %lx paddr %qx\n", 1128 (long)ss, (long)offset, 1129 (unsigned long long)paddr)); 1130 return ((*sc->sc_bustag->sparc_bus_map)(t, paddr, size, 1131 flags, 0, hp)); 1132 } 1133 DPRINTF(PDB_BUSMAP, (" FAILED\n")); 1134 return (EINVAL); 1135 } 1136 1137 static paddr_t 1138 psycho_bus_mmap(bus_space_tag_t t, bus_addr_t paddr, off_t off, int prot, 1139 int flags) 1140 { 1141 bus_addr_t offset = paddr; 1142 struct psycho_pbm *pp = t->cookie; 1143 struct psycho_softc *sc = pp->pp_sc; 1144 struct psycho_ranges *pr; 1145 int ss; 1146 1147 ss = sparc_pci_childspace(t->type); 1148 1149 DPRINTF(PDB_BUSMAP, ("_psycho_bus_mmap: prot %x flags %d pa %qx\n", 1150 prot, flags, (unsigned long long)paddr)); 1151 1152 pr = get_psychorange(pp, ss); 1153 if (pr != NULL) { 1154 paddr = BUS_ADDR(pr->phys_hi, pr->phys_lo + offset); 1155 DPRINTF(PDB_BUSMAP, ("\n_psycho_bus_mmap: mapping paddr " 1156 "space %lx offset %lx paddr %qx\n", 1157 (long)ss, (long)offset, 1158 (unsigned long long)paddr)); 1159 return (bus_space_mmap(sc->sc_bustag, paddr, off, 1160 prot, flags)); 1161 } 1162 1163 return (-1); 1164 } 1165 1166 /* 1167 * Get a PCI offset address from bus_space_handle_t. 1168 */ 1169 bus_addr_t 1170 psycho_bus_offset(bus_space_tag_t t, bus_space_handle_t *hp) 1171 { 1172 struct psycho_pbm *pp = t->cookie; 1173 struct psycho_ranges *pr; 1174 bus_addr_t addr, offset; 1175 vaddr_t va; 1176 int ss; 1177 1178 addr = hp->_ptr; 1179 ss = sparc_pci_childspace(t->type); 1180 DPRINTF(PDB_BUSMAP, ("psycho_bus_offset: type %d addr %" PRIx64 1181 " cspace %d", t->type, addr, ss)); 1182 1183 pr = get_psychorange(pp, ss); 1184 if (pr != NULL) { 1185 if (!PHYS_ASI(hp->_asi)) { 1186 va = trunc_page((vaddr_t)addr); 1187 if (pmap_extract(pmap_kernel(), va, &addr) == FALSE) { 1188 DPRINTF(PDB_BUSMAP, 1189 ("\n pmap_extract FAILED\n")); 1190 return (-1); 1191 } 1192 addr += hp->_ptr & PGOFSET; 1193 } 1194 offset = BUS_ADDR_PADDR(addr) - pr->phys_lo; 1195 DPRINTF(PDB_BUSMAP, ("\npsycho_bus_offset: paddr %" PRIx64 1196 " offset %" PRIx64 "\n", addr, offset)); 1197 return (offset); 1198 } 1199 DPRINTF(PDB_BUSMAP, ("\n FAILED\n")); 1200 return (-1); 1201 } 1202 1203 1204 /* 1205 * install an interrupt handler for a PCI device 1206 */ 1207 void * 1208 psycho_intr_establish(bus_space_tag_t t, int ihandle, int level, 1209 int (*handler)(void *), void *arg, void (*fastvec)(void) /* ignored */) 1210 { 1211 struct psycho_pbm *pp = t->cookie; 1212 struct psycho_softc *sc = pp->pp_sc; 1213 struct intrhand *ih; 1214 volatile uint64_t *intrmapptr = NULL, *intrclrptr = NULL; 1215 int64_t imap = 0; 1216 int ino; 1217 long vec = INTVEC(ihandle); 1218 1219 ih = (struct intrhand *) 1220 malloc(sizeof(struct intrhand), M_DEVBUF, M_NOWAIT); 1221 if (ih == NULL) 1222 return (NULL); 1223 1224 /* 1225 * Hunt through all the interrupt mapping regs to look for our 1226 * interrupt vector. 1227 * 1228 * XXX We only compare INOs rather than IGNs since the firmware may 1229 * not provide the IGN and the IGN is constant for all device on that 1230 * PCI controller. This could cause problems for the FFB/external 1231 * interrupt which has a full vector that can be set arbitrarily. 1232 */ 1233 1234 DPRINTF(PDB_INTR, ("\npsycho_intr_establish: ihandle %x vec %lx", ihandle, vec)); 1235 ino = INTINO(vec); 1236 DPRINTF(PDB_INTR, (" ino %x", ino)); 1237 1238 /* If the device didn't ask for an IPL, use the one encoded. */ 1239 if (level == IPL_NONE) level = INTLEV(vec); 1240 /* If it still has no level, print a warning and assign IPL 2 */ 1241 if (level == IPL_NONE) { 1242 printf("ERROR: no IPL, setting IPL 2.\n"); 1243 level = 2; 1244 } 1245 1246 DPRINTF(PDB_INTR, ("\npsycho: intr %lx: %p\nHunting for IRQ...\n", 1247 (long)ino, intrlev[ino])); 1248 1249 /* 1250 * First look for PCI interrupts, otherwise the PCI A slot 0 1251 * INTA# interrupt might match an unused non-PCI (obio) 1252 * interrupt. 1253 */ 1254 for (intrmapptr = &sc->sc_regs->pcia_slot0_int, 1255 intrclrptr = &sc->sc_regs->pcia0_clr_int[0]; 1256 intrmapptr <= &sc->sc_regs->pcib_slot3_int; 1257 intrmapptr++, intrclrptr += 4) { 1258 if (sc->sc_mode == PSYCHO_MODE_PSYCHO && 1259 (intrmapptr == &sc->sc_regs->pcia_slot2_int || 1260 intrmapptr == &sc->sc_regs->pcia_slot3_int)) 1261 continue; 1262 if (((*intrmapptr ^ vec) & 0x3c) == 0) { 1263 intrclrptr += vec & 0x3; 1264 goto found; 1265 } 1266 } 1267 1268 /* Now hunt thru obio. */ 1269 for (intrmapptr = &sc->sc_regs->scsi_int_map, 1270 intrclrptr = &sc->sc_regs->scsi_clr_int; 1271 intrmapptr < &sc->sc_regs->ue_int_map; 1272 intrmapptr++, intrclrptr++) { 1273 if (INTINO(*intrmapptr) == ino) 1274 goto found; 1275 } 1276 1277 /* Finally check the two FFB slots */ 1278 intrclrptr = NULL; /* XXX? */ 1279 for (intrmapptr = &sc->sc_regs->ffb0_int_map; 1280 intrmapptr <= &sc->sc_regs->ffb1_int_map; 1281 intrmapptr++) { 1282 if (INTVEC(*intrmapptr) == ino) 1283 goto found; 1284 } 1285 1286 printf("Cannot find interrupt vector %lx\n", vec); 1287 return (NULL); 1288 1289 found: 1290 /* Register the map and clear intr registers */ 1291 ih->ih_map = intrmapptr; 1292 ih->ih_clr = intrclrptr; 1293 1294 ih->ih_fun = handler; 1295 ih->ih_arg = arg; 1296 ih->ih_pil = level; 1297 ih->ih_number = ino | sc->sc_ign; 1298 1299 DPRINTF(PDB_INTR, ( 1300 "; installing handler %p arg %p with ino %u pil %u\n", 1301 handler, arg, (u_int)ino, (u_int)ih->ih_pil)); 1302 1303 intr_establish(ih->ih_pil, level != IPL_VM, ih); 1304 1305 /* 1306 * Enable the interrupt now we have the handler installed. 1307 * Read the current value as we can't change it besides the 1308 * valid bit so so make sure only this bit is changed. 1309 * 1310 * XXXX --- we really should use bus_space for this. 1311 */ 1312 if (intrmapptr) { 1313 imap = *intrmapptr; 1314 DPRINTF(PDB_INTR, ("; read intrmap = %016qx", 1315 (unsigned long long)imap)); 1316 1317 /* Enable the interrupt */ 1318 imap |= INTMAP_V|(CPU_UPAID << INTMAP_TID_SHIFT); 1319 DPRINTF(PDB_INTR, ("; addr of intrmapptr = %p", intrmapptr)); 1320 DPRINTF(PDB_INTR, ("; writing intrmap = %016qx\n", 1321 (unsigned long long)imap)); 1322 *intrmapptr = imap; 1323 DPRINTF(PDB_INTR, ("; reread intrmap = %016qx", 1324 (unsigned long long)(imap = *intrmapptr))); 1325 } 1326 if (intrclrptr) { 1327 /* set state to IDLE */ 1328 *intrclrptr = 0; 1329 } 1330 return (ih); 1331 } 1332 1333 /* 1334 * per-controller driver calls 1335 */ 1336 1337 /* assume we are mapped little-endian/side-effect */ 1338 static pcireg_t 1339 psycho_pci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg) 1340 { 1341 struct psycho_pbm *pp = pc->cookie; 1342 struct psycho_softc *sc = pp->pp_sc; 1343 pcireg_t val = (pcireg_t)~0; 1344 1345 DPRINTF(PDB_CONF, ("%s: tag %lx reg %x ", __func__, 1346 (long)tag, reg)); 1347 if (PCITAG_NODE(tag) != -1) { 1348 1349 DPRINTF(PDB_CONF, ("asi=%x addr=%qx (offset=%x) ...", 1350 sc->sc_configaddr._asi, 1351 (long long)(sc->sc_configaddr._ptr + 1352 PCITAG_OFFSET(tag) + reg), 1353 (int)PCITAG_OFFSET(tag) + reg)); 1354 1355 val = bus_space_read_4(sc->sc_configtag, sc->sc_configaddr, 1356 PCITAG_OFFSET(tag) + reg); 1357 } 1358 #ifdef DEBUG 1359 else DPRINTF(PDB_CONF, ("%s: bogus pcitag %x\n", __func__, 1360 (int)PCITAG_OFFSET(tag))); 1361 #endif 1362 DPRINTF(PDB_CONF, (" returning %08x\n", (u_int)val)); 1363 1364 return (val); 1365 } 1366 1367 static void 1368 psycho_pci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data) 1369 { 1370 struct psycho_pbm *pp = pc->cookie; 1371 struct psycho_softc *sc = pp->pp_sc; 1372 1373 DPRINTF(PDB_CONF, ("%s: tag %lx; reg %x; data %x; ", __func__, 1374 (long)PCITAG_OFFSET(tag), reg, (int)data)); 1375 DPRINTF(PDB_CONF, ("asi = %x; readaddr = %qx (offset = %x)\n", 1376 sc->sc_configaddr._asi, 1377 (long long)(sc->sc_configaddr._ptr + PCITAG_OFFSET(tag) + reg), 1378 (int)PCITAG_OFFSET(tag) + reg)); 1379 1380 /* If we don't know it, just punt it. */ 1381 if (PCITAG_NODE(tag) == -1) { 1382 DPRINTF(PDB_CONF, ("%s: bad addr", __func__)); 1383 return; 1384 } 1385 1386 bus_space_write_4(sc->sc_configtag, sc->sc_configaddr, 1387 PCITAG_OFFSET(tag) + reg, data); 1388 } 1389 1390 static void * 1391 psycho_pci_intr_establish(pci_chipset_tag_t pc, pci_intr_handle_t ih, int level, 1392 int (*func)(void *), void *arg) 1393 { 1394 void *cookie; 1395 struct psycho_pbm *pp = (struct psycho_pbm *)pc->cookie; 1396 1397 DPRINTF(PDB_INTR, ("%s: ih %lx; level %d", __func__, (u_long)ih, level)); 1398 cookie = bus_intr_establish(pp->pp_memt, ih, level, func, arg); 1399 1400 DPRINTF(PDB_INTR, ("; returning handle %p\n", cookie)); 1401 return (cookie); 1402 } 1403 1404 static int 1405 psycho_pci_find_ino(struct pci_attach_args *pa, pci_intr_handle_t *ihp) 1406 { 1407 struct psycho_pbm *pp = pa->pa_pc->cookie; 1408 struct psycho_softc *sc = pp->pp_sc; 1409 u_int bus; 1410 u_int dev; 1411 u_int pin; 1412 1413 DPRINTF(PDB_INTMAP, ("%s: pa_tag: node %x, %d:%d:%d\n", __func__, 1414 PCITAG_NODE(pa->pa_tag), (int)PCITAG_BUS(pa->pa_tag), 1415 (int)PCITAG_DEV(pa->pa_tag), 1416 (int)PCITAG_FUN(pa->pa_tag))); 1417 DPRINTF(PDB_INTMAP, 1418 ("%s: intrswiz %d, intrpin %d, intrline %d, rawintrpin %d\n", __func__, 1419 pa->pa_intrswiz, pa->pa_intrpin, pa->pa_intrline, pa->pa_rawintrpin)); 1420 DPRINTF(PDB_INTMAP, ("%s: pa_intrtag: node %x, %d:%d:%d\n", __func__, 1421 PCITAG_NODE(pa->pa_intrtag), 1422 (int)PCITAG_BUS(pa->pa_intrtag), 1423 (int)PCITAG_DEV(pa->pa_intrtag), 1424 (int)PCITAG_FUN(pa->pa_intrtag))); 1425 1426 bus = (pp->pp_id == PSYCHO_PBM_B); 1427 /* 1428 * If we are on a ppb, use the devno on the underlying bus when forming 1429 * the ivec. 1430 */ 1431 if (pa->pa_intrswiz != 0 && PCITAG_NODE(pa->pa_intrtag) != 0) 1432 dev = PCITAG_DEV(pa->pa_intrtag); 1433 else 1434 dev = pa->pa_device; 1435 dev--; 1436 1437 if (sc->sc_mode == PSYCHO_MODE_PSYCHO && 1438 pp->pp_id == PSYCHO_PBM_B) 1439 dev--; 1440 1441 pin = pa->pa_intrpin - 1; 1442 DPRINTF(PDB_INTMAP, ("%s: mode %d, pbm %d, dev %d, pin %d\n", __func__, 1443 sc->sc_mode, pp->pp_id, dev, pin)); 1444 1445 *ihp = sc->sc_ign | ((bus << 4) & INTMAP_PCIBUS) | 1446 ((dev << 2) & INTMAP_PCISLOT) | (pin & INTMAP_PCIINT); 1447 1448 return (0); 1449 } 1450 1451 /* 1452 * hooks into the iommu dvma calls. 1453 */ 1454 static int 1455 psycho_dmamap_create(bus_dma_tag_t t, bus_size_t size, int nsegments, 1456 bus_size_t maxsegsz, bus_size_t boundary, int flags, 1457 bus_dmamap_t *dmamp) 1458 { 1459 struct psycho_pbm *pp = (struct psycho_pbm *)t->_cookie; 1460 int error; 1461 1462 error = bus_dmamap_create(t->_parent, size, nsegments, maxsegsz, 1463 boundary, flags, dmamp); 1464 if (error == 0) 1465 (*dmamp)->_dm_cookie = &pp->pp_sb; 1466 return error; 1467 } 1468 1469 /* 1470 * UltraSPARC IIi and IIe have no streaming buffers, but have PCI DMA 1471 * Write Synchronization Register (see UltraSPARC-IIi User's Manual 1472 * section 19.3.0.5). So use it to synchronize with the DMA writes. 1473 */ 1474 static void 1475 psycho_sabre_dmamap_sync(bus_dma_tag_t t, bus_dmamap_t map, bus_addr_t offset, 1476 bus_size_t len, int ops) 1477 { 1478 struct psycho_pbm *pp; 1479 struct psycho_softc *sc; 1480 1481 /* If len is 0, then there is nothing to do. */ 1482 if (len == 0) 1483 return; 1484 1485 if (ops & BUS_DMASYNC_POSTREAD) { 1486 pp = (struct psycho_pbm *)t->_cookie; 1487 sc = pp->pp_sc; 1488 bus_space_read_8(sc->sc_bustag, sc->sc_bh, 1489 offsetof(struct psychoreg, pci_dma_write_sync)); 1490 } 1491 bus_dmamap_sync(t->_parent, map, offset, len, ops); 1492 } 1493
Indexes created Fri Sep 26 20:09:58 GMT 2025