psycho.c revision 1.106
1 /* $NetBSD: psycho.c,v 1.106 2011/05/17 17:34:53 dyoung Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000 Matthew R. Green 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * Copyright (c) 2001, 2002 Eduardo E. Horvath 31 * All rights reserved. 32 * 33 * Redistribution and use in source and binary forms, with or without 34 * modification, are permitted provided that the following conditions 35 * are met: 36 * 1. Redistributions of source code must retain the above copyright 37 * notice, this list of conditions and the following disclaimer. 38 * 2. Redistributions in binary form must reproduce the above copyright 39 * notice, this list of conditions and the following disclaimer in the 40 * documentation and/or other materials provided with the distribution. 41 * 3. The name of the author may not be used to endorse or promote products 42 * derived from this software without specific prior written permission. 43 * 44 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 45 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 46 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 47 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 48 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 49 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 50 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 51 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 52 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 53 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 54 * SUCH DAMAGE. 55 */ 56 57 #include <sys/cdefs.h> 58 __KERNEL_RCSID(0, "$NetBSD: psycho.c,v 1.106 2011/05/17 17:34:53 dyoung Exp $"); 59 60 #include "opt_ddb.h" 61 62 /* 63 * Support for `psycho' and `psycho+' UPA to PCI bridge and 64 * UltraSPARC IIi and IIe `sabre' PCI controllers. 65 */ 66 67 #ifdef DEBUG 68 #define PDB_PROM 0x01 69 #define PDB_BUSMAP 0x02 70 #define PDB_INTR 0x04 71 #define PDB_INTMAP 0x08 72 #define PDB_CONF 0x10 73 int psycho_debug = 0x0; 74 #define DPRINTF(l, s) do { if (psycho_debug & l) printf s; } while (0) 75 #else 76 #define DPRINTF(l, s) 77 #endif 78 79 #include <sys/param.h> 80 #include <sys/device.h> 81 #include <sys/errno.h> 82 #include <sys/extent.h> 83 #include <sys/malloc.h> 84 #include <sys/systm.h> 85 #include <sys/time.h> 86 #include <sys/reboot.h> 87 88 #include <uvm/uvm.h> 89 90 #define _SPARC_BUS_DMA_PRIVATE 91 #include <machine/bus.h> 92 #include <machine/autoconf.h> 93 #include <machine/psl.h> 94 95 #include <dev/pci/pcivar.h> 96 #include <dev/pci/pcireg.h> 97 #include <dev/sysmon/sysmon_taskq.h> 98 99 #include <sparc64/dev/iommureg.h> 100 #include <sparc64/dev/iommuvar.h> 101 #include <sparc64/dev/psychoreg.h> 102 #include <sparc64/dev/psychovar.h> 103 104 #include "ioconf.h" 105 106 static pci_chipset_tag_t psycho_alloc_chipset(struct psycho_pbm *, int, 107 pci_chipset_tag_t); 108 static struct extent *psycho_alloc_extent(struct psycho_pbm *, int, int, 109 const char *); 110 static void psycho_get_bus_range(int, int *); 111 static void psycho_get_ranges(int, struct psycho_ranges **, int *); 112 static void psycho_set_intr(struct psycho_softc *, int, void *, uint64_t *, 113 uint64_t *); 114 115 /* chipset handlers */ 116 static pcireg_t psycho_pci_conf_read(pci_chipset_tag_t, pcitag_t, int); 117 static void psycho_pci_conf_write(pci_chipset_tag_t, pcitag_t, int, 118 pcireg_t); 119 static void *psycho_pci_intr_establish(pci_chipset_tag_t, 120 pci_intr_handle_t, 121 int, int (*)(void *), void *); 122 static int psycho_pci_find_ino(const struct pci_attach_args *, 123 pci_intr_handle_t *); 124 125 /* Interrupt handlers */ 126 static int psycho_ue(void *); 127 static int psycho_ce(void *); 128 static int psycho_bus_a(void *); 129 static int psycho_bus_b(void *); 130 static int psycho_powerfail(void *); 131 static int psycho_wakeup(void *); 132 133 134 /* IOMMU support */ 135 static void psycho_iommu_init(struct psycho_softc *, int); 136 137 /* 138 * bus space and bus DMA support for UltraSPARC `psycho'. note that most 139 * of the bus DMA support is provided by the iommu dvma controller. 140 */ 141 static struct psycho_ranges *get_psychorange(struct psycho_pbm *, int); 142 143 static paddr_t psycho_bus_mmap(bus_space_tag_t, bus_addr_t, off_t, int, int); 144 static int _psycho_bus_map(bus_space_tag_t, bus_addr_t, bus_size_t, int, 145 vaddr_t, bus_space_handle_t *); 146 static void *psycho_intr_establish(bus_space_tag_t, int, int, int (*)(void *), 147 void *, void(*)(void)); 148 149 static int psycho_dmamap_create(bus_dma_tag_t, bus_size_t, int, bus_size_t, 150 bus_size_t, int, bus_dmamap_t *); 151 static void psycho_sabre_dmamap_sync(bus_dma_tag_t, bus_dmamap_t, bus_addr_t, 152 bus_size_t, int); 153 154 /* base pci_chipset */ 155 extern struct sparc_pci_chipset _sparc_pci_chipset; 156 157 /* power button handlers */ 158 static void psycho_register_power_button(struct psycho_softc *sc); 159 static void psycho_power_button_pressed(void *arg); 160 161 /* 162 * autoconfiguration 163 */ 164 static int psycho_match(struct device *, struct cfdata *, void *); 165 static void psycho_attach(struct device *, struct device *, void *); 166 static int psycho_print(void *aux, const char *p); 167 168 CFATTACH_DECL(psycho, sizeof(struct psycho_softc), 169 psycho_match, psycho_attach, NULL, NULL); 170 171 /* 172 * "sabre" is the UltraSPARC IIi onboard UPA to PCI bridge. It manages a 173 * single PCI bus and does not have a streaming buffer. It often has an APB 174 * (advanced PCI bridge) connected to it, which was designed specifically for 175 * the IIi. The APB let's the IIi handle two independednt PCI buses, and 176 * appears as two "simba"'s underneath the sabre. 177 * 178 * "psycho" and "psycho+" is a dual UPA to PCI bridge. It sits on the UPA bus 179 * and manages two PCI buses. "psycho" has two 64-bit 33 MHz buses, while 180 * "psycho+" controls both a 64-bit 33 MHz and a 64-bit 66 MHz PCI bus. You 181 * will usually find a "psycho+" since I don't think the original "psycho" 182 * ever shipped, and if it did it would be in the U30. 183 * 184 * Each "psycho" PCI bus appears as a separate OFW node, but since they are 185 * both part of the same IC, they only have a single register space. As such, 186 * they need to be configured together, even though the autoconfiguration will 187 * attach them separately. 188 * 189 * On UltraIIi machines, "sabre" itself usually takes pci0, with "simba" often 190 * as pci1 and pci2, although they have been implemented with other PCI bus 191 * numbers on some machines. 192 * 193 * On UltraII machines, there can be any number of "psycho+" ICs, each 194 * providing two PCI buses. 195 * 196 * 197 * XXXX The psycho/sabre node has an `interrupts' attribute. They contain 198 * the values of the following interrupts in this order: 199 * 200 * PCI Bus Error (30) 201 * DMA UE (2e) 202 * DMA CE (2f) 203 * Power Fail (25) 204 * 205 * We really should attach handlers for each. 206 * 207 */ 208 209 #define ROM_PCI_NAME "pci" 210 211 struct psycho_names { 212 const char *p_name; 213 int p_type; 214 } psycho_names[] = { 215 { "SUNW,psycho", PSYCHO_MODE_PSYCHO }, 216 { "pci108e,8000", PSYCHO_MODE_PSYCHO }, 217 { "SUNW,sabre", PSYCHO_MODE_SABRE }, 218 { "pci108e,a000", PSYCHO_MODE_SABRE }, 219 { "pci108e,a001", PSYCHO_MODE_SABRE }, 220 { NULL, 0 } 221 }; 222 223 static int 224 psycho_match(struct device *parent, struct cfdata *match, void *aux) 225 { 226 struct mainbus_attach_args *ma = aux; 227 char *model = prom_getpropstring(ma->ma_node, "model"); 228 int i; 229 230 /* match on a name of "pci" and a sabre or a psycho */ 231 if (strcmp(ma->ma_name, ROM_PCI_NAME) == 0) { 232 for (i=0; psycho_names[i].p_name; i++) 233 if (strcmp(model, psycho_names[i].p_name) == 0) 234 return (1); 235 236 model = prom_getpropstring(ma->ma_node, "compatible"); 237 for (i=0; psycho_names[i].p_name; i++) 238 if (strcmp(model, psycho_names[i].p_name) == 0) 239 return (1); 240 } 241 return (0); 242 } 243 244 #ifdef DEBUG 245 static void psycho_dump_intmap(struct psycho_softc *sc); 246 static void 247 psycho_dump_intmap(struct psycho_softc *sc) 248 { 249 volatile uint64_t *intrmapptr = NULL; 250 251 printf("psycho_dump_intmap: OBIO\n"); 252 253 for (intrmapptr = &sc->sc_regs->scsi_int_map; 254 intrmapptr < &sc->sc_regs->ue_int_map; 255 intrmapptr++) 256 printf("%p: %llx\n", intrmapptr, 257 (unsigned long long)*intrmapptr); 258 259 printf("\tintmap:pci\n"); 260 for (intrmapptr = &sc->sc_regs->pcia_slot0_int; 261 intrmapptr <= &sc->sc_regs->pcib_slot3_int; 262 intrmapptr++) 263 printf("%p: %llx\n", intrmapptr, 264 (unsigned long long)*intrmapptr); 265 266 printf("\tintmap:ffb\n"); 267 for (intrmapptr = &sc->sc_regs->ffb0_int_map; 268 intrmapptr <= &sc->sc_regs->ffb1_int_map; 269 intrmapptr++) 270 printf("%p: %llx\n", intrmapptr, 271 (unsigned long long)*intrmapptr); 272 } 273 #endif 274 275 /* 276 * SUNW,psycho initialisation .. 277 * - find the per-psycho registers 278 * - figure out the IGN. 279 * - find our partner psycho 280 * - configure ourselves 281 * - bus range, bus, 282 * - get interrupt-map and interrupt-map-mask 283 * - setup the chipsets. 284 * - if we're the first of the pair, initialise the IOMMU, otherwise 285 * just copy it's tags and addresses. 286 */ 287 static void 288 psycho_attach(struct device *parent, struct device *self, void *aux) 289 { 290 struct psycho_softc *sc = (struct psycho_softc *)self; 291 struct psycho_softc *osc = NULL; 292 struct psycho_pbm *pp; 293 struct pcibus_attach_args pba; 294 struct mainbus_attach_args *ma = aux; 295 struct psycho_ranges *pr; 296 prop_dictionary_t dict; 297 bus_space_handle_t bh; 298 uint64_t csr, mem_base; 299 int psycho_br[2], n, i; 300 bus_space_handle_t pci_ctl; 301 char *model = prom_getpropstring(ma->ma_node, "model"); 302 extern char machine_model[]; 303 304 aprint_normal("\n"); 305 306 sc->sc_node = ma->ma_node; 307 sc->sc_bustag = ma->ma_bustag; 308 sc->sc_dmatag = ma->ma_dmatag; 309 310 /* 311 * Identify the device. 312 */ 313 for (i=0; psycho_names[i].p_name; i++) 314 if (strcmp(model, psycho_names[i].p_name) == 0) { 315 sc->sc_mode = psycho_names[i].p_type; 316 goto found; 317 } 318 319 model = prom_getpropstring(ma->ma_node, "compatible"); 320 for (i=0; psycho_names[i].p_name; i++) 321 if (strcmp(model, psycho_names[i].p_name) == 0) { 322 sc->sc_mode = psycho_names[i].p_type; 323 goto found; 324 } 325 326 panic("unknown psycho model %s", model); 327 found: 328 329 /* 330 * The psycho gets three register banks: 331 * (0) per-PBM configuration and status registers 332 * (1) per-PBM PCI configuration space, containing only the 333 * PBM 256-byte PCI header 334 * (2) the shared psycho configuration registers (struct psychoreg) 335 */ 336 337 /* Register layouts are different. stuupid. */ 338 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) { 339 sc->sc_basepaddr = (paddr_t)ma->ma_reg[2].ur_paddr; 340 341 if (ma->ma_naddress > 2) { 342 sparc_promaddr_to_handle(sc->sc_bustag, 343 ma->ma_address[2], &sc->sc_bh); 344 sparc_promaddr_to_handle(sc->sc_bustag, 345 ma->ma_address[0], &pci_ctl); 346 347 sc->sc_regs = (struct psychoreg *) 348 bus_space_vaddr(sc->sc_bustag, sc->sc_bh); 349 } else if (ma->ma_nreg > 2) { 350 351 /* We need to map this in ourselves. */ 352 if (bus_space_map(sc->sc_bustag, 353 ma->ma_reg[2].ur_paddr, 354 ma->ma_reg[2].ur_len, BUS_SPACE_MAP_LINEAR, 355 &sc->sc_bh)) 356 panic("psycho_attach: cannot map regs"); 357 sc->sc_regs = (struct psychoreg *) 358 bus_space_vaddr(sc->sc_bustag, sc->sc_bh); 359 360 if (bus_space_map(sc->sc_bustag, 361 ma->ma_reg[0].ur_paddr, 362 ma->ma_reg[0].ur_len, BUS_SPACE_MAP_LINEAR, 363 &pci_ctl)) 364 panic("psycho_attach: cannot map ctl"); 365 } else 366 panic("psycho_attach: %d not enough registers", 367 ma->ma_nreg); 368 369 } else { 370 sc->sc_basepaddr = (paddr_t)ma->ma_reg[0].ur_paddr; 371 372 if (ma->ma_naddress) { 373 sparc_promaddr_to_handle(sc->sc_bustag, 374 ma->ma_address[0], &sc->sc_bh); 375 sc->sc_regs = (struct psychoreg *) 376 bus_space_vaddr(sc->sc_bustag, sc->sc_bh); 377 bus_space_subregion(sc->sc_bustag, sc->sc_bh, 378 offsetof(struct psychoreg, psy_pcictl), 379 sizeof(struct pci_ctl), &pci_ctl); 380 } else if (ma->ma_nreg) { 381 382 /* We need to map this in ourselves. */ 383 if (bus_space_map(sc->sc_bustag, 384 ma->ma_reg[0].ur_paddr, 385 ma->ma_reg[0].ur_len, BUS_SPACE_MAP_LINEAR, 386 &sc->sc_bh)) 387 panic("psycho_attach: cannot map regs"); 388 sc->sc_regs = (struct psychoreg *) 389 bus_space_vaddr(sc->sc_bustag, sc->sc_bh); 390 391 bus_space_subregion(sc->sc_bustag, sc->sc_bh, 392 offsetof(struct psychoreg, psy_pcictl), 393 sizeof(struct pci_ctl), &pci_ctl); 394 } else 395 panic("psycho_attach: %d not enough registers", 396 ma->ma_nreg); 397 } 398 399 400 csr = bus_space_read_8(sc->sc_bustag, sc->sc_bh, 401 offsetof(struct psychoreg, psy_csr)); 402 sc->sc_ign = 0x7c0; /* APB IGN is always 0x7c */ 403 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) 404 sc->sc_ign = PSYCHO_GCSR_IGN(csr) << 6; 405 406 aprint_normal_dev(self, "%s: impl %d, version %d: ign %x ", 407 model, PSYCHO_GCSR_IMPL(csr), PSYCHO_GCSR_VERS(csr), 408 sc->sc_ign); 409 /* 410 * Match other psycho's that are already configured against 411 * the base physical address. This will be the same for a 412 * pair of devices that share register space. 413 */ 414 for (n = 0; n < psycho_cd.cd_ndevs; n++) { 415 416 struct psycho_softc *asc = device_lookup_private(&psycho_cd, n); 417 418 if (asc == NULL || asc == sc) 419 /* This entry is not there or it is me */ 420 continue; 421 422 if (asc->sc_basepaddr != sc->sc_basepaddr) 423 /* This is an unrelated psycho */ 424 continue; 425 426 /* Found partner */ 427 osc = asc; 428 break; 429 } 430 431 432 /* Oh, dear. OK, lets get started */ 433 434 /* 435 * Setup the PCI control register 436 */ 437 csr = bus_space_read_8(sc->sc_bustag, pci_ctl, 438 offsetof(struct pci_ctl, pci_csr)); 439 csr |= PCICTL_MRLM | 440 PCICTL_ARB_PARK | 441 PCICTL_ERRINTEN | 442 PCICTL_4ENABLE; 443 csr &= ~(PCICTL_SERR | 444 PCICTL_CPU_PRIO | 445 PCICTL_ARB_PRIO | 446 PCICTL_RTRYWAIT); 447 bus_space_write_8(sc->sc_bustag, pci_ctl, 448 offsetof(struct pci_ctl, pci_csr), csr); 449 450 451 /* 452 * Allocate our psycho_pbm 453 */ 454 pp = sc->sc_psycho_this = malloc(sizeof *pp, M_DEVBUF, 455 M_NOWAIT | M_ZERO); 456 if (pp == NULL) 457 panic("could not allocate psycho pbm"); 458 459 pp->pp_sc = sc; 460 461 /* grab the psycho ranges */ 462 psycho_get_ranges(sc->sc_node, &pp->pp_range, &pp->pp_nrange); 463 464 /* get the bus-range for the psycho */ 465 psycho_get_bus_range(sc->sc_node, psycho_br); 466 467 pba.pba_bus = psycho_br[0]; 468 pba.pba_bridgetag = NULL; 469 470 aprint_normal("bus range %u to %u", psycho_br[0], psycho_br[1]); 471 aprint_normal("; PCI bus %d", psycho_br[0]); 472 473 pp->pp_pcictl = pci_ctl; 474 475 /* allocate our tags */ 476 pp->pp_memt = psycho_alloc_mem_tag(pp); 477 pp->pp_iot = psycho_alloc_io_tag(pp); 478 pp->pp_dmat = psycho_alloc_dma_tag(pp); 479 pp->pp_flags = (pp->pp_memt ? PCI_FLAGS_MEM_OKAY : 0) | 480 (pp->pp_iot ? PCI_FLAGS_IO_OKAY : 0); 481 482 /* allocate a chipset for this */ 483 pp->pp_pc = psycho_alloc_chipset(pp, sc->sc_node, &_sparc_pci_chipset); 484 pp->pp_pc->spc_busmax = psycho_br[1]; 485 486 switch((ma->ma_reg[0].ur_paddr) & 0xf000) { 487 case 0x2000: 488 pp->pp_id = PSYCHO_PBM_A; 489 break; 490 case 0x4000: 491 pp->pp_id = PSYCHO_PBM_B; 492 break; 493 } 494 495 aprint_normal("\n"); 496 497 /* allocate extents for free bus space */ 498 pp->pp_exmem = psycho_alloc_extent(pp, sc->sc_node, 0x02, "psycho mem"); 499 pp->pp_exio = psycho_alloc_extent(pp, sc->sc_node, 0x01, "psycho io"); 500 501 #ifdef DEBUG 502 if (psycho_debug & PDB_INTR) 503 psycho_dump_intmap(sc); 504 #endif 505 506 /* 507 * And finally, if we're a sabre or the first of a pair of psycho's to 508 * arrive here, start up the IOMMU and get a config space tag. 509 */ 510 if (osc == NULL) { 511 uint64_t timeo; 512 513 /* 514 * Establish handlers for interesting interrupts.... 515 * 516 * XXX We need to remember these and remove this to support 517 * hotplug on the UPA/FHC bus. 518 * 519 * XXX Not all controllers have these, but installing them 520 * is better than trying to sort through this mess. 521 */ 522 psycho_set_intr(sc, 15, psycho_ue, 523 &sc->sc_regs->ue_int_map, 524 &sc->sc_regs->ue_clr_int); 525 psycho_set_intr(sc, 1, psycho_ce, 526 &sc->sc_regs->ce_int_map, 527 &sc->sc_regs->ce_clr_int); 528 psycho_set_intr(sc, 15, psycho_bus_a, 529 &sc->sc_regs->pciaerr_int_map, 530 &sc->sc_regs->pciaerr_clr_int); 531 /* 532 * Netra X1 may hang when the powerfail interrupt is enabled. 533 */ 534 if (strcmp(machine_model, "SUNW,UltraAX-i2") != 0) { 535 psycho_set_intr(sc, 15, psycho_powerfail, 536 &sc->sc_regs->power_int_map, 537 &sc->sc_regs->power_clr_int); 538 psycho_register_power_button(sc); 539 } 540 if (sc->sc_mode != PSYCHO_MODE_SABRE) { 541 /* sabre doesn't have these interrupts */ 542 psycho_set_intr(sc, 15, psycho_bus_b, 543 &sc->sc_regs->pciberr_int_map, 544 &sc->sc_regs->pciberr_clr_int); 545 psycho_set_intr(sc, 1, psycho_wakeup, 546 &sc->sc_regs->pwrmgt_int_map, 547 &sc->sc_regs->pwrmgt_clr_int); 548 } 549 550 /* 551 * Apparently a number of machines with psycho and psycho+ 552 * controllers have interrupt latency issues. We'll try 553 * setting the interrupt retry timeout to 0xff which gives us 554 * a retry of 3-6 usec (which is what sysio is set to) for the 555 * moment, which seems to help alleviate this problem. 556 */ 557 timeo = sc->sc_regs->intr_retry_timer; 558 if (timeo > 0xfff) { 559 #ifdef DEBUG 560 printf("decreasing interrupt retry timeout " 561 "from %lx to 0xff\n", (long)timeo); 562 #endif 563 sc->sc_regs->intr_retry_timer = 0xff; 564 } 565 566 /* 567 * Allocate bus node, this contains a prom node per bus. 568 */ 569 pp->pp_pc->spc_busnode = 570 malloc(sizeof(*pp->pp_pc->spc_busnode), M_DEVBUF, 571 M_NOWAIT | M_ZERO); 572 if (pp->pp_pc->spc_busnode == NULL) 573 panic("psycho_attach: malloc busnode"); 574 575 /* 576 * Setup IOMMU and PCI configuration if we're the first 577 * of a pair of psycho's to arrive here. 578 * 579 * We should calculate a TSB size based on amount of RAM 580 * and number of bus controllers and number an type of 581 * child devices. 582 * 583 * For the moment, 32KB should be more than enough. 584 */ 585 sc->sc_is = malloc(sizeof(struct iommu_state), 586 M_DEVBUF, M_NOWAIT); 587 if (sc->sc_is == NULL) 588 panic("psycho_attach: malloc iommu_state"); 589 590 /* Point the strbuf_ctl at the iommu_state */ 591 pp->pp_sb.sb_is = sc->sc_is; 592 593 sc->sc_is->is_sb[0] = sc->sc_is->is_sb[1] = NULL; 594 if (prom_getproplen(sc->sc_node, "no-streaming-cache") < 0) { 595 struct strbuf_ctl *sb = &pp->pp_sb; 596 vaddr_t va = (vaddr_t)&pp->pp_flush[0x40]; 597 598 /* 599 * Initialize the strbuf_ctl. 600 * 601 * The flush sync buffer must be 64-byte aligned. 602 */ 603 sb->sb_flush = (void *)(va & ~0x3f); 604 605 bus_space_subregion(sc->sc_bustag, pci_ctl, 606 offsetof(struct pci_ctl, pci_strbuf), 607 sizeof (struct iommu_strbuf), &sb->sb_sb); 608 609 /* Point our iommu at the strbuf_ctl */ 610 sc->sc_is->is_sb[0] = sb; 611 } 612 613 psycho_iommu_init(sc, 2); 614 615 sc->sc_configtag = psycho_alloc_config_tag(sc->sc_psycho_this); 616 617 /* 618 * XXX This is a really ugly hack because PCI config space 619 * is explicitly handled with unmapped accesses. 620 */ 621 i = sc->sc_bustag->type; 622 sc->sc_bustag->type = PCI_CONFIG_BUS_SPACE; 623 if (bus_space_map(sc->sc_bustag, sc->sc_basepaddr + 0x01000000, 624 0x01000000, 0, &bh)) 625 panic("could not map psycho PCI configuration space"); 626 sc->sc_bustag->type = i; 627 sc->sc_configaddr = bh; 628 } else { 629 /* Share bus numbers with the pair of mine */ 630 pp->pp_pc->spc_busnode = 631 osc->sc_psycho_this->pp_pc->spc_busnode; 632 633 /* Just copy IOMMU state, config tag and address */ 634 sc->sc_is = osc->sc_is; 635 sc->sc_configtag = osc->sc_configtag; 636 sc->sc_configaddr = osc->sc_configaddr; 637 638 /* Point the strbuf_ctl at the iommu_state */ 639 pp->pp_sb.sb_is = sc->sc_is; 640 641 if (prom_getproplen(sc->sc_node, "no-streaming-cache") < 0) { 642 struct strbuf_ctl *sb = &pp->pp_sb; 643 vaddr_t va = (vaddr_t)&pp->pp_flush[0x40]; 644 645 /* 646 * Initialize the strbuf_ctl. 647 * 648 * The flush sync buffer must be 64-byte aligned. 649 */ 650 sb->sb_flush = (void *)(va & ~0x3f); 651 652 bus_space_subregion(sc->sc_bustag, pci_ctl, 653 offsetof(struct pci_ctl, pci_strbuf), 654 sizeof (struct iommu_strbuf), &sb->sb_sb); 655 656 /* Point our iommu at the strbuf_ctl */ 657 sc->sc_is->is_sb[1] = sb; 658 } 659 iommu_reset(sc->sc_is); 660 } 661 662 dict = device_properties(self); 663 pr = get_psychorange(pp, 2); /* memory range */ 664 #ifdef DEBUG 665 printf("memory range: %08x %08x\n", pr->phys_hi, pr->phys_lo); 666 #endif 667 mem_base = ((uint64_t)pr->phys_hi) << 32 | pr->phys_lo; 668 prop_dictionary_set_uint64(dict, "mem_base", mem_base); 669 670 /* 671 * attach the pci.. note we pass PCI A tags, etc., for the sabre here. 672 */ 673 pba.pba_flags = sc->sc_psycho_this->pp_flags; 674 pba.pba_dmat = sc->sc_psycho_this->pp_dmat; 675 pba.pba_dmat64 = NULL; 676 pba.pba_iot = sc->sc_psycho_this->pp_iot; 677 pba.pba_memt = sc->sc_psycho_this->pp_memt; 678 pba.pba_pc = pp->pp_pc; 679 680 config_found_ia(self, "pcibus", &pba, psycho_print); 681 } 682 683 static int 684 psycho_print(void *aux, const char *p) 685 { 686 687 if (p == NULL) 688 return (UNCONF); 689 return (QUIET); 690 } 691 692 static void 693 psycho_set_intr(struct psycho_softc *sc, int ipl, void *handler, 694 uint64_t *mapper, uint64_t *clearer) 695 { 696 struct intrhand *ih; 697 698 ih = (struct intrhand *)malloc(sizeof(struct intrhand), 699 M_DEVBUF, M_NOWAIT); 700 ih->ih_arg = sc; 701 ih->ih_map = mapper; 702 ih->ih_clr = clearer; 703 ih->ih_fun = handler; 704 ih->ih_pil = (1<<ipl); 705 ih->ih_number = INTVEC(*(ih->ih_map)); 706 intr_establish(ipl, ipl != IPL_VM, ih); 707 *(ih->ih_map) |= INTMAP_V|(CPU_UPAID << INTMAP_TID_SHIFT); 708 } 709 710 /* 711 * power button handlers 712 */ 713 static void 714 psycho_register_power_button(struct psycho_softc *sc) 715 { 716 sysmon_task_queue_init(); 717 718 sc->sc_powerpressed = 0; 719 sc->sc_smcontext = malloc(sizeof(struct sysmon_pswitch), M_DEVBUF, 0); 720 if (!sc->sc_smcontext) { 721 aprint_error_dev(&sc->sc_dev, "could not allocate power button context\n"); 722 return; 723 } 724 memset(sc->sc_smcontext, 0, sizeof(struct sysmon_pswitch)); 725 sc->sc_smcontext->smpsw_name = device_xname(&sc->sc_dev); 726 sc->sc_smcontext->smpsw_type = PSWITCH_TYPE_POWER; 727 if (sysmon_pswitch_register(sc->sc_smcontext) != 0) 728 aprint_error_dev(&sc->sc_dev, "unable to register power button with sysmon\n"); 729 } 730 731 static void 732 psycho_power_button_pressed(void *arg) 733 { 734 struct psycho_softc *sc = arg; 735 736 sysmon_pswitch_event(sc->sc_smcontext, PSWITCH_EVENT_PRESSED); 737 sc->sc_powerpressed = 0; 738 } 739 740 /* 741 * PCI bus support 742 */ 743 744 /* 745 * allocate a PCI chipset tag and set it's cookie. 746 */ 747 static pci_chipset_tag_t 748 psycho_alloc_chipset(struct psycho_pbm *pp, int node, pci_chipset_tag_t pc) 749 { 750 pci_chipset_tag_t npc; 751 752 npc = malloc(sizeof *npc, M_DEVBUF, M_NOWAIT); 753 if (npc == NULL) 754 panic("could not allocate pci_chipset_tag_t"); 755 memcpy(npc, pc, sizeof *pc); 756 npc->cookie = pp; 757 npc->rootnode = node; 758 npc->spc_conf_read = psycho_pci_conf_read; 759 npc->spc_conf_write = psycho_pci_conf_write; 760 npc->spc_intr_map = NULL; 761 npc->spc_intr_establish = psycho_pci_intr_establish; 762 npc->spc_find_ino = psycho_pci_find_ino; 763 764 return (npc); 765 } 766 767 /* 768 * create extent for free bus space, then allocate assigned regions. 769 */ 770 static struct extent * 771 psycho_alloc_extent(struct psycho_pbm *pp, int node, int ss, const char *name) 772 { 773 struct psycho_registers *pa = NULL; 774 struct psycho_ranges *pr; 775 struct extent *ex; 776 bus_addr_t baddr, addr; 777 bus_size_t bsize, size; 778 int i, num; 779 780 /* get bus space size */ 781 pr = get_psychorange(pp, ss); 782 if (pr == NULL) { 783 printf("psycho_alloc_extent: get_psychorange failed\n"); 784 return NULL; 785 } 786 baddr = 0x00000000; 787 bsize = BUS_ADDR(pr->size_hi, pr->size_lo); 788 789 /* get available lists */ 790 num = 0; 791 if (prom_getprop(node, "available", sizeof(*pa), &num, &pa)) { 792 printf("psycho_alloc_extent: no \"available\" property\n"); 793 return NULL; 794 } 795 796 /* create extent */ 797 ex = extent_create(name, baddr, bsize - baddr - 1, M_DEVBUF, 0, 0, 798 EX_NOWAIT); 799 if (ex == NULL) { 800 printf("psycho_alloc_extent: extent_create failed\n"); 801 goto ret; 802 } 803 804 /* allocate assigned regions */ 805 for (i = 0; i < num; i++) 806 if (((pa[i].phys_hi >> 24) & 0x03) == ss) { 807 /* allocate bus space */ 808 addr = BUS_ADDR(pa[i].phys_mid, pa[i].phys_lo); 809 size = BUS_ADDR(pa[i].size_hi, pa[i].size_lo); 810 if (extent_alloc_region(ex, baddr, addr - baddr, 811 EX_NOWAIT)) { 812 printf("psycho_alloc_extent: " 813 "extent_alloc_region %" PRIx64 "-%" 814 PRIx64 " failed\n", baddr, addr); 815 extent_destroy(ex); 816 ex = NULL; 817 goto ret; 818 } 819 baddr = addr + size; 820 } 821 /* allocate left region if available */ 822 if (baddr < bsize) 823 if (extent_alloc_region(ex, baddr, bsize - baddr, EX_NOWAIT)) { 824 printf("psycho_alloc_extent: extent_alloc_region %" 825 PRIx64 "-%" PRIx64 " failed\n", baddr, bsize); 826 extent_destroy(ex); 827 ex = NULL; 828 goto ret; 829 } 830 831 #ifdef DEBUG 832 /* print extent */ 833 extent_print(ex); 834 #endif 835 836 ret: 837 /* return extent */ 838 free(pa, M_DEVBUF); 839 return ex; 840 } 841 842 /* 843 * grovel the OBP for various psycho properties 844 */ 845 static void 846 psycho_get_bus_range(int node, int *brp) 847 { 848 int n, error; 849 850 n = 2; 851 error = prom_getprop(node, "bus-range", sizeof(*brp), &n, &brp); 852 if (error) 853 panic("could not get psycho bus-range, error %d", error); 854 if (n != 2) 855 panic("broken psycho bus-range"); 856 DPRINTF(PDB_PROM, ("psycho debug: got `bus-range' for node %08x: %u - %u\n", 857 node, brp[0], brp[1])); 858 } 859 860 static void 861 psycho_get_ranges(int node, struct psycho_ranges **rp, int *np) 862 { 863 864 if (prom_getprop(node, "ranges", sizeof(**rp), np, rp)) 865 panic("could not get psycho ranges"); 866 DPRINTF(PDB_PROM, ("psycho debug: got `ranges' for node %08x: %d entries\n", node, *np)); 867 } 868 869 /* 870 * Interrupt handlers. 871 */ 872 873 static int 874 psycho_ue(void *arg) 875 { 876 struct psycho_softc *sc = (struct psycho_softc *)arg; 877 struct psychoreg *regs = sc->sc_regs; 878 struct iommu_state *is = sc->sc_is; 879 uint64_t afsr = regs->psy_ue_afsr; 880 uint64_t afar = regs->psy_ue_afar; 881 psize_t size = PAGE_SIZE << is->is_tsbsize; 882 char bits[128]; 883 884 /* 885 * It's uncorrectable. Dump the regs and panic. 886 */ 887 snprintb(bits, sizeof(bits), PSYCHO_UE_AFSR_BITS, afsr); 888 aprint_error_dev(&sc->sc_dev, 889 "uncorrectable DMA error AFAR %" PRIx64 " AFSR %s\n", afar, bits); 890 891 /* Sometimes the AFAR points to an IOTSB entry */ 892 if (afar >= is->is_ptsb && afar < is->is_ptsb + size) { 893 aprint_error_dev(&sc->sc_dev, 894 "IOVA %" PRIx64 " IOTTE %" PRIx64 "\n", 895 (afar - is->is_ptsb) / sizeof(is->is_tsb[0]) * PAGE_SIZE 896 + is->is_dvmabase, ldxa(afar, ASI_PHYS_CACHED)); 897 } 898 #ifdef DDB 899 Debugger(); 900 #endif 901 regs->psy_ue_afar = 0; 902 regs->psy_ue_afsr = 0; 903 return (1); 904 } 905 906 static int 907 psycho_ce(void *arg) 908 { 909 struct psycho_softc *sc = (struct psycho_softc *)arg; 910 struct psychoreg *regs = sc->sc_regs; 911 912 /* 913 * It's correctable. Dump the regs and continue. 914 */ 915 aprint_error_dev(&sc->sc_dev, 916 "correctable DMA error AFAR %" PRIx64 " AFSR %" PRIx64 "\n", 917 regs->psy_ce_afar, regs->psy_ce_afsr); 918 return (1); 919 } 920 921 static int 922 psycho_bus_a(void *arg) 923 { 924 struct psycho_softc *sc = (struct psycho_softc *)arg; 925 struct psychoreg *regs = sc->sc_regs; 926 927 /* 928 * It's uncorrectable. Dump the regs and panic. 929 */ 930 931 panic("%s: PCI bus A error AFAR %" PRIx64 " AFSR %" PRIx64, 932 device_xname(&sc->sc_dev), 933 regs->psy_pcictl[0].pci_afar, regs->psy_pcictl[0].pci_afsr); 934 return (1); 935 } 936 937 static int 938 psycho_bus_b(void *arg) 939 { 940 struct psycho_softc *sc = (struct psycho_softc *)arg; 941 struct psychoreg *regs = sc->sc_regs; 942 943 /* 944 * It's uncorrectable. Dump the regs and panic. 945 */ 946 947 panic("%s: PCI bus B error AFAR %" PRIx64 " AFSR %" PRIx64, 948 device_xname(&sc->sc_dev), 949 regs->psy_pcictl[0].pci_afar, regs->psy_pcictl[0].pci_afsr); 950 return (1); 951 } 952 953 static int 954 psycho_powerfail(void *arg) 955 { 956 struct psycho_softc *sc = (struct psycho_softc *)arg; 957 958 /* 959 * We lost power. Queue a callback with thread context to 960 * handle all the real work. 961 */ 962 if (sc->sc_powerpressed == 0 && sc->sc_smcontext != NULL) { 963 sc->sc_powerpressed = 1; 964 sysmon_task_queue_sched(0, psycho_power_button_pressed, sc); 965 } 966 return (1); 967 } 968 969 static 970 int psycho_wakeup(void *arg) 971 { 972 struct psycho_softc *sc = (struct psycho_softc *)arg; 973 974 /* 975 * Gee, we don't really have a framework to deal with this 976 * properly. 977 */ 978 aprint_error_dev(&sc->sc_dev, "power management wakeup\n"); 979 return (1); 980 } 981 982 983 /* 984 * initialise the IOMMU.. 985 */ 986 void 987 psycho_iommu_init(struct psycho_softc *sc, int tsbsize) 988 { 989 char *name; 990 struct iommu_state *is = sc->sc_is; 991 uint32_t iobase = -1; 992 int *vdma = NULL; 993 int nitem; 994 995 /* punch in our copies */ 996 is->is_bustag = sc->sc_bustag; 997 bus_space_subregion(sc->sc_bustag, sc->sc_bh, 998 offsetof(struct psychoreg, psy_iommu), 999 sizeof (struct iommureg), 1000 &is->is_iommu); 1001 1002 /* 1003 * Separate the men from the boys. Get the `virtual-dma' 1004 * property for sabre and use that to make sure the damn 1005 * iommu works. 1006 * 1007 * We could query the `#virtual-dma-size-cells' and 1008 * `#virtual-dma-addr-cells' and DTRT, but I'm lazy. 1009 */ 1010 nitem = 0; 1011 if (!prom_getprop(sc->sc_node, "virtual-dma", sizeof(vdma), &nitem, 1012 &vdma)) { 1013 /* Damn. Gotta use these values. */ 1014 iobase = vdma[0]; 1015 #define TSBCASE(x) case 1<<((x)+23): tsbsize = (x); break 1016 switch (vdma[1]) { 1017 TSBCASE(1); TSBCASE(2); TSBCASE(3); 1018 TSBCASE(4); TSBCASE(5); TSBCASE(6); 1019 default: 1020 printf("bogus tsb size %x, using 7\n", vdma[1]); 1021 TSBCASE(7); 1022 } 1023 #undef TSBCASE 1024 } 1025 1026 /* give us a nice name.. */ 1027 name = (char *)malloc(32, M_DEVBUF, M_NOWAIT); 1028 if (name == 0) 1029 panic("couldn't malloc iommu name"); 1030 snprintf(name, 32, "%s dvma", device_xname(&sc->sc_dev)); 1031 1032 iommu_init(name, is, tsbsize, iobase); 1033 } 1034 1035 /* 1036 * below here is bus space and bus DMA support 1037 */ 1038 bus_space_tag_t 1039 psycho_alloc_bus_tag(struct psycho_pbm *pp, int type) 1040 { 1041 struct psycho_softc *sc = pp->pp_sc; 1042 bus_space_tag_t bt; 1043 1044 bt = (bus_space_tag_t) malloc(sizeof(struct sparc_bus_space_tag), 1045 M_DEVBUF, M_NOWAIT | M_ZERO); 1046 if (bt == NULL) 1047 panic("could not allocate psycho bus tag"); 1048 1049 bt->cookie = pp; 1050 bt->parent = sc->sc_bustag; 1051 bt->type = type; 1052 bt->sparc_bus_map = _psycho_bus_map; 1053 bt->sparc_bus_mmap = psycho_bus_mmap; 1054 bt->sparc_intr_establish = psycho_intr_establish; 1055 return (bt); 1056 } 1057 1058 bus_dma_tag_t 1059 psycho_alloc_dma_tag(struct psycho_pbm *pp) 1060 { 1061 struct psycho_softc *sc = pp->pp_sc; 1062 bus_dma_tag_t dt, pdt = sc->sc_dmatag; 1063 1064 dt = (bus_dma_tag_t) 1065 malloc(sizeof(struct sparc_bus_dma_tag), M_DEVBUF, M_NOWAIT); 1066 if (dt == NULL) 1067 panic("could not allocate psycho DMA tag"); 1068 1069 memset(dt, 0, sizeof *dt); 1070 dt->_cookie = pp; 1071 dt->_parent = pdt; 1072 #define PCOPY(x) dt->x = pdt->x 1073 dt->_dmamap_create = psycho_dmamap_create; 1074 PCOPY(_dmamap_destroy); 1075 dt->_dmamap_load = iommu_dvmamap_load; 1076 PCOPY(_dmamap_load_mbuf); 1077 PCOPY(_dmamap_load_uio); 1078 dt->_dmamap_load_raw = iommu_dvmamap_load_raw; 1079 dt->_dmamap_unload = iommu_dvmamap_unload; 1080 if (sc->sc_mode == PSYCHO_MODE_SABRE) 1081 dt->_dmamap_sync = psycho_sabre_dmamap_sync; 1082 else 1083 dt->_dmamap_sync = iommu_dvmamap_sync; 1084 dt->_dmamem_alloc = iommu_dvmamem_alloc; 1085 dt->_dmamem_free = iommu_dvmamem_free; 1086 dt->_dmamem_map = iommu_dvmamem_map; 1087 dt->_dmamem_unmap = iommu_dvmamem_unmap; 1088 PCOPY(_dmamem_mmap); 1089 #undef PCOPY 1090 return (dt); 1091 } 1092 1093 /* 1094 * bus space support. <sparc64/dev/psychoreg.h> has a discussion about 1095 * PCI physical addresses. 1096 */ 1097 1098 static struct psycho_ranges * 1099 get_psychorange(struct psycho_pbm *pp, int ss) 1100 { 1101 int i; 1102 1103 for (i = 0; i < pp->pp_nrange; i++) { 1104 if (((pp->pp_range[i].cspace >> 24) & 0x03) == ss) 1105 return (&pp->pp_range[i]); 1106 } 1107 /* not found */ 1108 return (NULL); 1109 } 1110 1111 static int 1112 _psycho_bus_map(bus_space_tag_t t, bus_addr_t offset, bus_size_t size, 1113 int flags, vaddr_t unused, bus_space_handle_t *hp) 1114 { 1115 struct psycho_pbm *pp = t->cookie; 1116 struct psycho_softc *sc = pp->pp_sc; 1117 struct psycho_ranges *pr; 1118 bus_addr_t paddr; 1119 int ss; 1120 1121 DPRINTF(PDB_BUSMAP, 1122 ("_psycho_bus_map: type %d off %qx sz %qx flags %d", 1123 t->type, (unsigned long long)offset, 1124 (unsigned long long)size, flags)); 1125 1126 ss = sparc_pci_childspace(t->type); 1127 DPRINTF(PDB_BUSMAP, (" cspace %d", ss)); 1128 1129 pr = get_psychorange(pp, ss); 1130 if (pr != NULL) { 1131 paddr = BUS_ADDR(pr->phys_hi, pr->phys_lo + offset); 1132 DPRINTF(PDB_BUSMAP, ("\n_psycho_bus_map: mapping paddr " 1133 "space %lx offset %lx paddr %qx\n", 1134 (long)ss, (long)offset, 1135 (unsigned long long)paddr)); 1136 return ((*sc->sc_bustag->sparc_bus_map)(t, paddr, size, 1137 flags, 0, hp)); 1138 } 1139 DPRINTF(PDB_BUSMAP, (" FAILED\n")); 1140 return (EINVAL); 1141 } 1142 1143 static paddr_t 1144 psycho_bus_mmap(bus_space_tag_t t, bus_addr_t paddr, off_t off, int prot, 1145 int flags) 1146 { 1147 bus_addr_t offset = paddr; 1148 struct psycho_pbm *pp = t->cookie; 1149 struct psycho_softc *sc = pp->pp_sc; 1150 struct psycho_ranges *pr; 1151 int ss; 1152 1153 ss = sparc_pci_childspace(t->type); 1154 1155 DPRINTF(PDB_BUSMAP, ("_psycho_bus_mmap: prot %x flags %d pa %qx\n", 1156 prot, flags, (unsigned long long)paddr)); 1157 1158 pr = get_psychorange(pp, ss); 1159 if (pr != NULL) { 1160 paddr = BUS_ADDR(pr->phys_hi, pr->phys_lo + offset); 1161 DPRINTF(PDB_BUSMAP, ("\n_psycho_bus_mmap: mapping paddr " 1162 "space %lx offset %lx paddr %qx\n", 1163 (long)ss, (long)offset, 1164 (unsigned long long)paddr)); 1165 return (bus_space_mmap(sc->sc_bustag, paddr, off, 1166 prot, flags)); 1167 } 1168 1169 return (-1); 1170 } 1171 1172 /* 1173 * Get a PCI offset address from bus_space_handle_t. 1174 */ 1175 bus_addr_t 1176 psycho_bus_offset(bus_space_tag_t t, bus_space_handle_t *hp) 1177 { 1178 struct psycho_pbm *pp = t->cookie; 1179 struct psycho_ranges *pr; 1180 bus_addr_t addr, offset; 1181 vaddr_t va; 1182 int ss; 1183 1184 addr = hp->_ptr; 1185 ss = sparc_pci_childspace(t->type); 1186 DPRINTF(PDB_BUSMAP, ("psycho_bus_offset: type %d addr %" PRIx64 1187 " cspace %d", t->type, addr, ss)); 1188 1189 pr = get_psychorange(pp, ss); 1190 if (pr != NULL) { 1191 if (!PHYS_ASI(hp->_asi)) { 1192 va = trunc_page((vaddr_t)addr); 1193 if (pmap_extract(pmap_kernel(), va, &addr) == FALSE) { 1194 DPRINTF(PDB_BUSMAP, 1195 ("\n pmap_extract FAILED\n")); 1196 return (-1); 1197 } 1198 addr += hp->_ptr & PGOFSET; 1199 } 1200 offset = BUS_ADDR_PADDR(addr) - pr->phys_lo; 1201 DPRINTF(PDB_BUSMAP, ("\npsycho_bus_offset: paddr %" PRIx64 1202 " offset %" PRIx64 "\n", addr, offset)); 1203 return (offset); 1204 } 1205 DPRINTF(PDB_BUSMAP, ("\n FAILED\n")); 1206 return (-1); 1207 } 1208 1209 1210 /* 1211 * install an interrupt handler for a PCI device 1212 */ 1213 void * 1214 psycho_intr_establish(bus_space_tag_t t, int ihandle, int level, 1215 int (*handler)(void *), void *arg, void (*fastvec)(void) /* ignored */) 1216 { 1217 struct psycho_pbm *pp = t->cookie; 1218 struct psycho_softc *sc = pp->pp_sc; 1219 struct intrhand *ih; 1220 volatile uint64_t *intrmapptr = NULL, *intrclrptr = NULL; 1221 int64_t imap = 0; 1222 int ino; 1223 long vec = INTVEC(ihandle); 1224 1225 ih = (struct intrhand *) 1226 malloc(sizeof(struct intrhand), M_DEVBUF, M_NOWAIT); 1227 if (ih == NULL) 1228 return (NULL); 1229 1230 /* 1231 * Hunt through all the interrupt mapping regs to look for our 1232 * interrupt vector. 1233 * 1234 * XXX We only compare INOs rather than IGNs since the firmware may 1235 * not provide the IGN and the IGN is constant for all device on that 1236 * PCI controller. This could cause problems for the FFB/external 1237 * interrupt which has a full vector that can be set arbitrarily. 1238 */ 1239 1240 DPRINTF(PDB_INTR, ("\npsycho_intr_establish: ihandle %x vec %lx", ihandle, vec)); 1241 ino = INTINO(vec); 1242 DPRINTF(PDB_INTR, (" ino %x", ino)); 1243 1244 /* If the device didn't ask for an IPL, use the one encoded. */ 1245 if (level == IPL_NONE) level = INTLEV(vec); 1246 /* If it still has no level, print a warning and assign IPL 2 */ 1247 if (level == IPL_NONE) { 1248 printf("ERROR: no IPL, setting IPL 2.\n"); 1249 level = 2; 1250 } 1251 1252 DPRINTF(PDB_INTR, ("\npsycho: intr %lx: %p\nHunting for IRQ...\n", 1253 (long)ino, intrlev[ino])); 1254 1255 /* 1256 * First look for PCI interrupts, otherwise the PCI A slot 0 1257 * INTA# interrupt might match an unused non-PCI (obio) 1258 * interrupt. 1259 */ 1260 for (intrmapptr = &sc->sc_regs->pcia_slot0_int, 1261 intrclrptr = &sc->sc_regs->pcia0_clr_int[0]; 1262 intrmapptr <= &sc->sc_regs->pcib_slot3_int; 1263 intrmapptr++, intrclrptr += 4) { 1264 if (sc->sc_mode == PSYCHO_MODE_PSYCHO && 1265 (intrmapptr == &sc->sc_regs->pcia_slot2_int || 1266 intrmapptr == &sc->sc_regs->pcia_slot3_int)) 1267 continue; 1268 if (((*intrmapptr ^ vec) & 0x3c) == 0) { 1269 intrclrptr += vec & 0x3; 1270 goto found; 1271 } 1272 } 1273 1274 /* Now hunt thru obio. */ 1275 for (intrmapptr = &sc->sc_regs->scsi_int_map, 1276 intrclrptr = &sc->sc_regs->scsi_clr_int; 1277 intrmapptr < &sc->sc_regs->ue_int_map; 1278 intrmapptr++, intrclrptr++) { 1279 if (INTINO(*intrmapptr) == ino) 1280 goto found; 1281 } 1282 1283 /* Finally check the two FFB slots */ 1284 intrclrptr = NULL; /* XXX? */ 1285 for (intrmapptr = &sc->sc_regs->ffb0_int_map; 1286 intrmapptr <= &sc->sc_regs->ffb1_int_map; 1287 intrmapptr++) { 1288 if (INTVEC(*intrmapptr) == ino) 1289 goto found; 1290 } 1291 1292 printf("Cannot find interrupt vector %lx\n", vec); 1293 return (NULL); 1294 1295 found: 1296 /* Register the map and clear intr registers */ 1297 ih->ih_map = intrmapptr; 1298 ih->ih_clr = intrclrptr; 1299 1300 ih->ih_fun = handler; 1301 ih->ih_arg = arg; 1302 ih->ih_pil = level; 1303 ih->ih_number = ino | sc->sc_ign; 1304 1305 DPRINTF(PDB_INTR, ( 1306 "; installing handler %p arg %p with ino %u pil %u\n", 1307 handler, arg, (u_int)ino, (u_int)ih->ih_pil)); 1308 1309 intr_establish(ih->ih_pil, level != IPL_VM, ih); 1310 1311 /* 1312 * Enable the interrupt now we have the handler installed. 1313 * Read the current value as we can't change it besides the 1314 * valid bit so so make sure only this bit is changed. 1315 * 1316 * XXXX --- we really should use bus_space for this. 1317 */ 1318 if (intrmapptr) { 1319 imap = *intrmapptr; 1320 DPRINTF(PDB_INTR, ("; read intrmap = %016qx", 1321 (unsigned long long)imap)); 1322 1323 /* Enable the interrupt */ 1324 imap |= INTMAP_V|(CPU_UPAID << INTMAP_TID_SHIFT); 1325 DPRINTF(PDB_INTR, ("; addr of intrmapptr = %p", intrmapptr)); 1326 DPRINTF(PDB_INTR, ("; writing intrmap = %016qx\n", 1327 (unsigned long long)imap)); 1328 *intrmapptr = imap; 1329 DPRINTF(PDB_INTR, ("; reread intrmap = %016qx", 1330 (unsigned long long)(imap = *intrmapptr))); 1331 } 1332 if (intrclrptr) { 1333 /* set state to IDLE */ 1334 *intrclrptr = 0; 1335 } 1336 return (ih); 1337 } 1338 1339 /* 1340 * per-controller driver calls 1341 */ 1342 1343 /* assume we are mapped little-endian/side-effect */ 1344 static pcireg_t 1345 psycho_pci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg) 1346 { 1347 struct psycho_pbm *pp = pc->cookie; 1348 struct psycho_softc *sc = pp->pp_sc; 1349 pcireg_t val = (pcireg_t)~0; 1350 1351 DPRINTF(PDB_CONF, ("%s: tag %lx reg %x ", __func__, 1352 (long)tag, reg)); 1353 if (PCITAG_NODE(tag) != -1) { 1354 1355 DPRINTF(PDB_CONF, ("asi=%x addr=%qx (offset=%x) ...", 1356 sc->sc_configaddr._asi, 1357 (long long)(sc->sc_configaddr._ptr + 1358 PCITAG_OFFSET(tag) + reg), 1359 (int)PCITAG_OFFSET(tag) + reg)); 1360 1361 val = bus_space_read_4(sc->sc_configtag, sc->sc_configaddr, 1362 PCITAG_OFFSET(tag) + reg); 1363 } 1364 #ifdef DEBUG 1365 else DPRINTF(PDB_CONF, ("%s: bogus pcitag %x\n", __func__, 1366 (int)PCITAG_OFFSET(tag))); 1367 #endif 1368 DPRINTF(PDB_CONF, (" returning %08x\n", (u_int)val)); 1369 1370 return (val); 1371 } 1372 1373 static void 1374 psycho_pci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data) 1375 { 1376 struct psycho_pbm *pp = pc->cookie; 1377 struct psycho_softc *sc = pp->pp_sc; 1378 1379 DPRINTF(PDB_CONF, ("%s: tag %lx; reg %x; data %x; ", __func__, 1380 (long)PCITAG_OFFSET(tag), reg, (int)data)); 1381 DPRINTF(PDB_CONF, ("asi = %x; readaddr = %qx (offset = %x)\n", 1382 sc->sc_configaddr._asi, 1383 (long long)(sc->sc_configaddr._ptr + PCITAG_OFFSET(tag) + reg), 1384 (int)PCITAG_OFFSET(tag) + reg)); 1385 1386 /* If we don't know it, just punt it. */ 1387 if (PCITAG_NODE(tag) == -1) { 1388 DPRINTF(PDB_CONF, ("%s: bad addr", __func__)); 1389 return; 1390 } 1391 1392 bus_space_write_4(sc->sc_configtag, sc->sc_configaddr, 1393 PCITAG_OFFSET(tag) + reg, data); 1394 } 1395 1396 static void * 1397 psycho_pci_intr_establish(pci_chipset_tag_t pc, pci_intr_handle_t ih, int level, 1398 int (*func)(void *), void *arg) 1399 { 1400 void *cookie; 1401 struct psycho_pbm *pp = (struct psycho_pbm *)pc->cookie; 1402 1403 DPRINTF(PDB_INTR, ("%s: ih %lx; level %d", __func__, (u_long)ih, level)); 1404 cookie = bus_intr_establish(pp->pp_memt, ih, level, func, arg); 1405 1406 DPRINTF(PDB_INTR, ("; returning handle %p\n", cookie)); 1407 return (cookie); 1408 } 1409 1410 static int 1411 psycho_pci_find_ino(const struct pci_attach_args *pa, pci_intr_handle_t *ihp) 1412 { 1413 struct psycho_pbm *pp = pa->pa_pc->cookie; 1414 struct psycho_softc *sc = pp->pp_sc; 1415 u_int bus; 1416 u_int dev; 1417 u_int pin; 1418 1419 DPRINTF(PDB_INTMAP, ("%s: pa_tag: node %x, %d:%d:%d\n", __func__, 1420 PCITAG_NODE(pa->pa_tag), (int)PCITAG_BUS(pa->pa_tag), 1421 (int)PCITAG_DEV(pa->pa_tag), 1422 (int)PCITAG_FUN(pa->pa_tag))); 1423 DPRINTF(PDB_INTMAP, 1424 ("%s: intrswiz %d, intrpin %d, intrline %d, rawintrpin %d\n", __func__, 1425 pa->pa_intrswiz, pa->pa_intrpin, pa->pa_intrline, pa->pa_rawintrpin)); 1426 DPRINTF(PDB_INTMAP, ("%s: pa_intrtag: node %x, %d:%d:%d\n", __func__, 1427 PCITAG_NODE(pa->pa_intrtag), 1428 (int)PCITAG_BUS(pa->pa_intrtag), 1429 (int)PCITAG_DEV(pa->pa_intrtag), 1430 (int)PCITAG_FUN(pa->pa_intrtag))); 1431 1432 bus = (pp->pp_id == PSYCHO_PBM_B); 1433 /* 1434 * If we are on a ppb, use the devno on the underlying bus when forming 1435 * the ivec. 1436 */ 1437 if (pa->pa_intrswiz != 0 && PCITAG_NODE(pa->pa_intrtag) != 0) 1438 dev = PCITAG_DEV(pa->pa_intrtag); 1439 else 1440 dev = pa->pa_device; 1441 dev--; 1442 1443 if (sc->sc_mode == PSYCHO_MODE_PSYCHO && 1444 pp->pp_id == PSYCHO_PBM_B) 1445 dev--; 1446 1447 pin = pa->pa_intrpin - 1; 1448 DPRINTF(PDB_INTMAP, ("%s: mode %d, pbm %d, dev %d, pin %d\n", __func__, 1449 sc->sc_mode, pp->pp_id, dev, pin)); 1450 1451 *ihp = sc->sc_ign | ((bus << 4) & INTMAP_PCIBUS) | 1452 ((dev << 2) & INTMAP_PCISLOT) | (pin & INTMAP_PCIINT); 1453 1454 return (0); 1455 } 1456 1457 /* 1458 * hooks into the iommu dvma calls. 1459 */ 1460 static int 1461 psycho_dmamap_create(bus_dma_tag_t t, bus_size_t size, int nsegments, 1462 bus_size_t maxsegsz, bus_size_t boundary, int flags, 1463 bus_dmamap_t *dmamp) 1464 { 1465 struct psycho_pbm *pp = (struct psycho_pbm *)t->_cookie; 1466 int error; 1467 1468 error = bus_dmamap_create(t->_parent, size, nsegments, maxsegsz, 1469 boundary, flags, dmamp); 1470 if (error == 0) 1471 (*dmamp)->_dm_cookie = &pp->pp_sb; 1472 return error; 1473 } 1474 1475 /* 1476 * UltraSPARC IIi and IIe have no streaming buffers, but have PCI DMA 1477 * Write Synchronization Register (see UltraSPARC-IIi User's Manual 1478 * section 19.3.0.5). So use it to synchronize with the DMA writes. 1479 */ 1480 static void 1481 psycho_sabre_dmamap_sync(bus_dma_tag_t t, bus_dmamap_t map, bus_addr_t offset, 1482 bus_size_t len, int ops) 1483 { 1484 struct psycho_pbm *pp; 1485 struct psycho_softc *sc; 1486 1487 /* If len is 0, then there is nothing to do. */ 1488 if (len == 0) 1489 return; 1490 1491 if (ops & BUS_DMASYNC_POSTREAD) { 1492 pp = (struct psycho_pbm *)t->_cookie; 1493 sc = pp->pp_sc; 1494 bus_space_read_8(sc->sc_bustag, sc->sc_bh, 1495 offsetof(struct psychoreg, pci_dma_write_sync)); 1496 } 1497 bus_dmamap_sync(t->_parent, map, offset, len, ops); 1498 } 1499
Indexes created Thu Sep 25 16:09:42 GMT 2025