psycho.c revision 1.111
1 /* $NetBSD: psycho.c,v 1.111 2011/09/04 12:17:14 nakayama Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000 Matthew R. Green 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * Copyright (c) 2001, 2002 Eduardo E. Horvath 31 * All rights reserved. 32 * 33 * Redistribution and use in source and binary forms, with or without 34 * modification, are permitted provided that the following conditions 35 * are met: 36 * 1. Redistributions of source code must retain the above copyright 37 * notice, this list of conditions and the following disclaimer. 38 * 2. Redistributions in binary form must reproduce the above copyright 39 * notice, this list of conditions and the following disclaimer in the 40 * documentation and/or other materials provided with the distribution. 41 * 3. The name of the author may not be used to endorse or promote products 42 * derived from this software without specific prior written permission. 43 * 44 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 45 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 46 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 47 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 48 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 49 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 50 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 51 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 52 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 53 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 54 * SUCH DAMAGE. 55 */ 56 57 #include <sys/cdefs.h> 58 __KERNEL_RCSID(0, "$NetBSD: psycho.c,v 1.111 2011/09/04 12:17:14 nakayama Exp $"); 59 60 #include "opt_ddb.h" 61 62 /* 63 * Support for `psycho' and `psycho+' UPA to PCI bridge and 64 * UltraSPARC IIi and IIe `sabre' PCI controllers. 65 */ 66 67 #ifdef DEBUG 68 #define PDB_PROM 0x01 69 #define PDB_BUSMAP 0x02 70 #define PDB_INTR 0x04 71 #define PDB_INTMAP 0x08 72 #define PDB_CONF 0x10 73 int psycho_debug = 0x0; 74 #define DPRINTF(l, s) do { if (psycho_debug & l) printf s; } while (0) 75 #else 76 #define DPRINTF(l, s) 77 #endif 78 79 #include <sys/param.h> 80 #include <sys/device.h> 81 #include <sys/errno.h> 82 #include <sys/extent.h> 83 #include <sys/malloc.h> 84 #include <sys/systm.h> 85 #include <sys/time.h> 86 #include <sys/reboot.h> 87 88 #include <uvm/uvm.h> 89 90 #define _SPARC_BUS_DMA_PRIVATE 91 #include <sys/bus.h> 92 #include <machine/autoconf.h> 93 #include <machine/psl.h> 94 95 #include <dev/pci/pcivar.h> 96 #include <dev/pci/pcireg.h> 97 #include <dev/sysmon/sysmon_taskq.h> 98 99 #include <sparc64/dev/iommureg.h> 100 #include <sparc64/dev/iommuvar.h> 101 #include <sparc64/dev/psychoreg.h> 102 #include <sparc64/dev/psychovar.h> 103 104 #include "ioconf.h" 105 106 static pci_chipset_tag_t psycho_alloc_chipset(struct psycho_pbm *, int, 107 pci_chipset_tag_t); 108 static struct extent *psycho_alloc_extent(struct psycho_pbm *, int, int, 109 const char *); 110 static void psycho_get_bus_range(int, int *); 111 static void psycho_get_ranges(int, struct psycho_ranges **, int *); 112 static void psycho_set_intr(struct psycho_softc *, int, void *, uint64_t *, 113 uint64_t *); 114 115 /* chipset handlers */ 116 static pcireg_t psycho_pci_conf_read(pci_chipset_tag_t, pcitag_t, int); 117 static void psycho_pci_conf_write(pci_chipset_tag_t, pcitag_t, int, 118 pcireg_t); 119 static void *psycho_pci_intr_establish(pci_chipset_tag_t, 120 pci_intr_handle_t, 121 int, int (*)(void *), void *); 122 static int psycho_pci_find_ino(const struct pci_attach_args *, 123 pci_intr_handle_t *); 124 125 /* Interrupt handlers */ 126 static int psycho_ue(void *); 127 static int psycho_ce(void *); 128 static int psycho_bus_a(void *); 129 static int psycho_bus_b(void *); 130 static int psycho_powerfail(void *); 131 static int psycho_wakeup(void *); 132 133 134 /* IOMMU support */ 135 static void psycho_iommu_init(struct psycho_softc *, int); 136 137 /* 138 * bus space and bus DMA support for UltraSPARC `psycho'. note that most 139 * of the bus DMA support is provided by the iommu dvma controller. 140 */ 141 static struct psycho_ranges *get_psychorange(struct psycho_pbm *, int); 142 143 static paddr_t psycho_bus_mmap(bus_space_tag_t, bus_addr_t, off_t, int, int); 144 static int _psycho_bus_map(bus_space_tag_t, bus_addr_t, bus_size_t, int, 145 vaddr_t, bus_space_handle_t *); 146 static void *psycho_intr_establish(bus_space_tag_t, int, int, int (*)(void *), 147 void *, void(*)(void)); 148 149 static int psycho_dmamap_create(bus_dma_tag_t, bus_size_t, int, bus_size_t, 150 bus_size_t, int, bus_dmamap_t *); 151 static void psycho_sabre_dmamap_sync(bus_dma_tag_t, bus_dmamap_t, bus_addr_t, 152 bus_size_t, int); 153 154 /* base pci_chipset */ 155 extern struct sparc_pci_chipset _sparc_pci_chipset; 156 157 /* power button handlers */ 158 static void psycho_register_power_button(struct psycho_softc *sc); 159 static void psycho_power_button_pressed(void *arg); 160 161 /* 162 * autoconfiguration 163 */ 164 static int psycho_match(device_t, cfdata_t, void *); 165 static void psycho_attach(device_t, device_t, void *); 166 static int psycho_print(void *aux, const char *p); 167 168 CFATTACH_DECL_NEW(psycho, sizeof(struct psycho_softc), 169 psycho_match, psycho_attach, NULL, NULL); 170 171 /* 172 * "sabre" is the UltraSPARC IIi onboard UPA to PCI bridge. It manages a 173 * single PCI bus and does not have a streaming buffer. It often has an APB 174 * (advanced PCI bridge) connected to it, which was designed specifically for 175 * the IIi. The APB let's the IIi handle two independednt PCI buses, and 176 * appears as two "simba"'s underneath the sabre. 177 * 178 * "psycho" and "psycho+" is a dual UPA to PCI bridge. It sits on the UPA bus 179 * and manages two PCI buses. "psycho" has two 64-bit 33 MHz buses, while 180 * "psycho+" controls both a 64-bit 33 MHz and a 64-bit 66 MHz PCI bus. You 181 * will usually find a "psycho+" since I don't think the original "psycho" 182 * ever shipped, and if it did it would be in the U30. 183 * 184 * Each "psycho" PCI bus appears as a separate OFW node, but since they are 185 * both part of the same IC, they only have a single register space. As such, 186 * they need to be configured together, even though the autoconfiguration will 187 * attach them separately. 188 * 189 * On UltraIIi machines, "sabre" itself usually takes pci0, with "simba" often 190 * as pci1 and pci2, although they have been implemented with other PCI bus 191 * numbers on some machines. 192 * 193 * On UltraII machines, there can be any number of "psycho+" ICs, each 194 * providing two PCI buses. 195 * 196 * 197 * XXXX The psycho/sabre node has an `interrupts' attribute. They contain 198 * the values of the following interrupts in this order: 199 * 200 * PCI Bus Error (30) 201 * DMA UE (2e) 202 * DMA CE (2f) 203 * Power Fail (25) 204 * 205 * We really should attach handlers for each. 206 * 207 */ 208 209 #define ROM_PCI_NAME "pci" 210 211 struct psycho_names { 212 const char *p_name; 213 int p_type; 214 } psycho_names[] = { 215 { "SUNW,psycho", PSYCHO_MODE_PSYCHO }, 216 { "pci108e,8000", PSYCHO_MODE_PSYCHO }, 217 { "SUNW,sabre", PSYCHO_MODE_SABRE }, 218 { "pci108e,a000", PSYCHO_MODE_SABRE }, 219 { "pci108e,a001", PSYCHO_MODE_SABRE }, 220 { NULL, 0 } 221 }; 222 223 static int 224 psycho_match(device_t parent, cfdata_t match, void *aux) 225 { 226 struct mainbus_attach_args *ma = aux; 227 char *model = prom_getpropstring(ma->ma_node, "model"); 228 int i; 229 230 /* match on a name of "pci" and a sabre or a psycho */ 231 if (strcmp(ma->ma_name, ROM_PCI_NAME) == 0) { 232 for (i=0; psycho_names[i].p_name; i++) 233 if (strcmp(model, psycho_names[i].p_name) == 0) 234 return (1); 235 236 model = prom_getpropstring(ma->ma_node, "compatible"); 237 for (i=0; psycho_names[i].p_name; i++) 238 if (strcmp(model, psycho_names[i].p_name) == 0) 239 return (1); 240 } 241 return (0); 242 } 243 244 #ifdef DEBUG 245 static void psycho_dump_intmap(struct psycho_softc *sc); 246 static void 247 psycho_dump_intmap(struct psycho_softc *sc) 248 { 249 volatile uint64_t *intrmapptr = NULL; 250 251 printf("psycho_dump_intmap: OBIO\n"); 252 253 for (intrmapptr = &sc->sc_regs->scsi_int_map; 254 intrmapptr < &sc->sc_regs->ue_int_map; 255 intrmapptr++) 256 printf("%p: %llx\n", intrmapptr, 257 (unsigned long long)*intrmapptr); 258 259 printf("\tintmap:pci\n"); 260 for (intrmapptr = &sc->sc_regs->pcia_slot0_int; 261 intrmapptr <= &sc->sc_regs->pcib_slot3_int; 262 intrmapptr++) 263 printf("%p: %llx\n", intrmapptr, 264 (unsigned long long)*intrmapptr); 265 266 printf("\tintmap:ffb\n"); 267 for (intrmapptr = &sc->sc_regs->ffb0_int_map; 268 intrmapptr <= &sc->sc_regs->ffb1_int_map; 269 intrmapptr++) 270 printf("%p: %llx\n", intrmapptr, 271 (unsigned long long)*intrmapptr); 272 } 273 #endif 274 275 /* 276 * SUNW,psycho initialisation .. 277 * - find the per-psycho registers 278 * - figure out the IGN. 279 * - find our partner psycho 280 * - configure ourselves 281 * - bus range, bus, 282 * - get interrupt-map and interrupt-map-mask 283 * - setup the chipsets. 284 * - if we're the first of the pair, initialise the IOMMU, otherwise 285 * just copy it's tags and addresses. 286 */ 287 static void 288 psycho_attach(device_t parent, device_t self, void *aux) 289 { 290 struct psycho_softc *sc = device_private(self); 291 struct psycho_softc *osc = NULL; 292 struct psycho_pbm *pp; 293 struct pcibus_attach_args pba; 294 struct mainbus_attach_args *ma = aux; 295 struct psycho_ranges *pr; 296 prop_dictionary_t dict; 297 bus_space_handle_t bh; 298 uint64_t csr, mem_base; 299 int psycho_br[2], n, i; 300 bus_space_handle_t pci_ctl; 301 char *model = prom_getpropstring(ma->ma_node, "model"); 302 extern char machine_model[]; 303 304 aprint_normal("\n"); 305 306 sc->sc_dev = self; 307 sc->sc_node = ma->ma_node; 308 sc->sc_bustag = ma->ma_bustag; 309 sc->sc_dmatag = ma->ma_dmatag; 310 311 /* 312 * Identify the device. 313 */ 314 for (i=0; psycho_names[i].p_name; i++) 315 if (strcmp(model, psycho_names[i].p_name) == 0) { 316 sc->sc_mode = psycho_names[i].p_type; 317 goto found; 318 } 319 320 model = prom_getpropstring(ma->ma_node, "compatible"); 321 for (i=0; psycho_names[i].p_name; i++) 322 if (strcmp(model, psycho_names[i].p_name) == 0) { 323 sc->sc_mode = psycho_names[i].p_type; 324 goto found; 325 } 326 327 panic("unknown psycho model %s", model); 328 found: 329 330 /* 331 * The psycho gets three register banks: 332 * (0) per-PBM configuration and status registers 333 * (1) per-PBM PCI configuration space, containing only the 334 * PBM 256-byte PCI header 335 * (2) the shared psycho configuration registers (struct psychoreg) 336 */ 337 338 /* Register layouts are different. stuupid. */ 339 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) { 340 sc->sc_basepaddr = (paddr_t)ma->ma_reg[2].ur_paddr; 341 342 if (ma->ma_naddress > 2) { 343 sparc_promaddr_to_handle(sc->sc_bustag, 344 ma->ma_address[2], &sc->sc_bh); 345 sparc_promaddr_to_handle(sc->sc_bustag, 346 ma->ma_address[0], &pci_ctl); 347 348 sc->sc_regs = (struct psychoreg *) 349 bus_space_vaddr(sc->sc_bustag, sc->sc_bh); 350 } else if (ma->ma_nreg > 2) { 351 352 /* We need to map this in ourselves. */ 353 if (bus_space_map(sc->sc_bustag, 354 ma->ma_reg[2].ur_paddr, 355 ma->ma_reg[2].ur_len, BUS_SPACE_MAP_LINEAR, 356 &sc->sc_bh)) 357 panic("psycho_attach: cannot map regs"); 358 sc->sc_regs = (struct psychoreg *) 359 bus_space_vaddr(sc->sc_bustag, sc->sc_bh); 360 361 if (bus_space_map(sc->sc_bustag, 362 ma->ma_reg[0].ur_paddr, 363 ma->ma_reg[0].ur_len, BUS_SPACE_MAP_LINEAR, 364 &pci_ctl)) 365 panic("psycho_attach: cannot map ctl"); 366 } else 367 panic("psycho_attach: %d not enough registers", 368 ma->ma_nreg); 369 370 } else { 371 sc->sc_basepaddr = (paddr_t)ma->ma_reg[0].ur_paddr; 372 373 if (ma->ma_naddress) { 374 sparc_promaddr_to_handle(sc->sc_bustag, 375 ma->ma_address[0], &sc->sc_bh); 376 sc->sc_regs = (struct psychoreg *) 377 bus_space_vaddr(sc->sc_bustag, sc->sc_bh); 378 bus_space_subregion(sc->sc_bustag, sc->sc_bh, 379 offsetof(struct psychoreg, psy_pcictl), 380 sizeof(struct pci_ctl), &pci_ctl); 381 } else if (ma->ma_nreg) { 382 383 /* We need to map this in ourselves. */ 384 if (bus_space_map(sc->sc_bustag, 385 ma->ma_reg[0].ur_paddr, 386 ma->ma_reg[0].ur_len, BUS_SPACE_MAP_LINEAR, 387 &sc->sc_bh)) 388 panic("psycho_attach: cannot map regs"); 389 sc->sc_regs = (struct psychoreg *) 390 bus_space_vaddr(sc->sc_bustag, sc->sc_bh); 391 392 bus_space_subregion(sc->sc_bustag, sc->sc_bh, 393 offsetof(struct psychoreg, psy_pcictl), 394 sizeof(struct pci_ctl), &pci_ctl); 395 } else 396 panic("psycho_attach: %d not enough registers", 397 ma->ma_nreg); 398 } 399 400 401 csr = bus_space_read_8(sc->sc_bustag, sc->sc_bh, 402 offsetof(struct psychoreg, psy_csr)); 403 sc->sc_ign = 0x7c0; /* APB IGN is always 0x7c */ 404 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) 405 sc->sc_ign = PSYCHO_GCSR_IGN(csr) << 6; 406 407 aprint_normal_dev(self, "%s: impl %d, version %d: ign %x ", 408 model, PSYCHO_GCSR_IMPL(csr), PSYCHO_GCSR_VERS(csr), 409 sc->sc_ign); 410 /* 411 * Match other psycho's that are already configured against 412 * the base physical address. This will be the same for a 413 * pair of devices that share register space. 414 */ 415 for (n = 0; n < psycho_cd.cd_ndevs; n++) { 416 417 struct psycho_softc *asc = device_lookup_private(&psycho_cd, n); 418 419 if (asc == NULL || asc == sc) 420 /* This entry is not there or it is me */ 421 continue; 422 423 if (asc->sc_basepaddr != sc->sc_basepaddr) 424 /* This is an unrelated psycho */ 425 continue; 426 427 /* Found partner */ 428 osc = asc; 429 break; 430 } 431 432 433 /* Oh, dear. OK, lets get started */ 434 435 /* 436 * Setup the PCI control register 437 */ 438 csr = bus_space_read_8(sc->sc_bustag, pci_ctl, 439 offsetof(struct pci_ctl, pci_csr)); 440 csr |= PCICTL_MRLM | 441 PCICTL_ARB_PARK | 442 PCICTL_ERRINTEN | 443 PCICTL_4ENABLE; 444 csr &= ~(PCICTL_SERR | 445 PCICTL_CPU_PRIO | 446 PCICTL_ARB_PRIO | 447 PCICTL_RTRYWAIT); 448 bus_space_write_8(sc->sc_bustag, pci_ctl, 449 offsetof(struct pci_ctl, pci_csr), csr); 450 451 452 /* 453 * Allocate our psycho_pbm 454 */ 455 pp = sc->sc_psycho_this = malloc(sizeof *pp, M_DEVBUF, 456 M_NOWAIT | M_ZERO); 457 if (pp == NULL) 458 panic("could not allocate psycho pbm"); 459 460 pp->pp_sc = sc; 461 462 /* grab the psycho ranges */ 463 psycho_get_ranges(sc->sc_node, &pp->pp_range, &pp->pp_nrange); 464 465 /* get the bus-range for the psycho */ 466 psycho_get_bus_range(sc->sc_node, psycho_br); 467 468 pba.pba_bus = psycho_br[0]; 469 pba.pba_bridgetag = NULL; 470 471 aprint_normal("bus range %u to %u", psycho_br[0], psycho_br[1]); 472 aprint_normal("; PCI bus %d", psycho_br[0]); 473 474 pp->pp_pcictl = pci_ctl; 475 476 /* allocate our tags */ 477 pp->pp_memt = psycho_alloc_mem_tag(pp); 478 pp->pp_iot = psycho_alloc_io_tag(pp); 479 pp->pp_dmat = psycho_alloc_dma_tag(pp); 480 pp->pp_flags = (pp->pp_memt ? PCI_FLAGS_MEM_OKAY : 0) | 481 (pp->pp_iot ? PCI_FLAGS_IO_OKAY : 0); 482 483 /* allocate a chipset for this */ 484 pp->pp_pc = psycho_alloc_chipset(pp, sc->sc_node, &_sparc_pci_chipset); 485 pp->pp_pc->spc_busmax = psycho_br[1]; 486 487 switch((ma->ma_reg[0].ur_paddr) & 0xf000) { 488 case 0x2000: 489 pp->pp_id = PSYCHO_PBM_A; 490 break; 491 case 0x4000: 492 pp->pp_id = PSYCHO_PBM_B; 493 break; 494 } 495 496 aprint_normal("\n"); 497 498 /* allocate extents for free bus space */ 499 pp->pp_exmem = psycho_alloc_extent(pp, sc->sc_node, 0x02, "psycho mem"); 500 pp->pp_exio = psycho_alloc_extent(pp, sc->sc_node, 0x01, "psycho io"); 501 502 #ifdef DEBUG 503 if (psycho_debug & PDB_INTR) 504 psycho_dump_intmap(sc); 505 #endif 506 507 /* 508 * And finally, if we're a sabre or the first of a pair of psycho's to 509 * arrive here, start up the IOMMU and get a config space tag. 510 */ 511 if (osc == NULL) { 512 uint64_t timeo; 513 514 /* 515 * Establish handlers for interesting interrupts.... 516 * 517 * XXX We need to remember these and remove this to support 518 * hotplug on the UPA/FHC bus. 519 * 520 * XXX Not all controllers have these, but installing them 521 * is better than trying to sort through this mess. 522 */ 523 psycho_set_intr(sc, 15, psycho_ue, 524 &sc->sc_regs->ue_int_map, 525 &sc->sc_regs->ue_clr_int); 526 psycho_set_intr(sc, 1, psycho_ce, 527 &sc->sc_regs->ce_int_map, 528 &sc->sc_regs->ce_clr_int); 529 psycho_set_intr(sc, 15, psycho_bus_a, 530 &sc->sc_regs->pciaerr_int_map, 531 &sc->sc_regs->pciaerr_clr_int); 532 /* 533 * Netra X1 may hang when the powerfail interrupt is enabled. 534 */ 535 if (strcmp(machine_model, "SUNW,UltraAX-i2") != 0) { 536 psycho_set_intr(sc, 15, psycho_powerfail, 537 &sc->sc_regs->power_int_map, 538 &sc->sc_regs->power_clr_int); 539 psycho_register_power_button(sc); 540 } 541 if (sc->sc_mode != PSYCHO_MODE_SABRE) { 542 /* sabre doesn't have these interrupts */ 543 psycho_set_intr(sc, 15, psycho_bus_b, 544 &sc->sc_regs->pciberr_int_map, 545 &sc->sc_regs->pciberr_clr_int); 546 psycho_set_intr(sc, 1, psycho_wakeup, 547 &sc->sc_regs->pwrmgt_int_map, 548 &sc->sc_regs->pwrmgt_clr_int); 549 } 550 551 /* 552 * Apparently a number of machines with psycho and psycho+ 553 * controllers have interrupt latency issues. We'll try 554 * setting the interrupt retry timeout to 0xff which gives us 555 * a retry of 3-6 usec (which is what sysio is set to) for the 556 * moment, which seems to help alleviate this problem. 557 */ 558 timeo = sc->sc_regs->intr_retry_timer; 559 if (timeo > 0xfff) { 560 #ifdef DEBUG 561 printf("decreasing interrupt retry timeout " 562 "from %lx to 0xff\n", (long)timeo); 563 #endif 564 sc->sc_regs->intr_retry_timer = 0xff; 565 } 566 567 /* 568 * Allocate bus node, this contains a prom node per bus. 569 */ 570 pp->pp_pc->spc_busnode = 571 malloc(sizeof(*pp->pp_pc->spc_busnode), M_DEVBUF, 572 M_NOWAIT | M_ZERO); 573 if (pp->pp_pc->spc_busnode == NULL) 574 panic("psycho_attach: malloc busnode"); 575 576 /* 577 * Setup IOMMU and PCI configuration if we're the first 578 * of a pair of psycho's to arrive here. 579 * 580 * We should calculate a TSB size based on amount of RAM 581 * and number of bus controllers and number an type of 582 * child devices. 583 * 584 * For the moment, 32KB should be more than enough. 585 */ 586 sc->sc_is = malloc(sizeof(struct iommu_state), 587 M_DEVBUF, M_NOWAIT); 588 if (sc->sc_is == NULL) 589 panic("psycho_attach: malloc iommu_state"); 590 591 /* Point the strbuf_ctl at the iommu_state */ 592 pp->pp_sb.sb_is = sc->sc_is; 593 594 sc->sc_is->is_sb[0] = sc->sc_is->is_sb[1] = NULL; 595 if (prom_getproplen(sc->sc_node, "no-streaming-cache") < 0) { 596 struct strbuf_ctl *sb = &pp->pp_sb; 597 vaddr_t va = (vaddr_t)&pp->pp_flush[0x40]; 598 599 /* 600 * Initialize the strbuf_ctl. 601 * 602 * The flush sync buffer must be 64-byte aligned. 603 */ 604 sb->sb_flush = (void *)(va & ~0x3f); 605 606 bus_space_subregion(sc->sc_bustag, pci_ctl, 607 offsetof(struct pci_ctl, pci_strbuf), 608 sizeof (struct iommu_strbuf), &sb->sb_sb); 609 610 /* Point our iommu at the strbuf_ctl */ 611 sc->sc_is->is_sb[0] = sb; 612 } 613 614 psycho_iommu_init(sc, 2); 615 616 sc->sc_configtag = psycho_alloc_config_tag(sc->sc_psycho_this); 617 618 /* 619 * XXX This is a really ugly hack because PCI config space 620 * is explicitly handled with unmapped accesses. 621 */ 622 i = sc->sc_bustag->type; 623 sc->sc_bustag->type = PCI_CONFIG_BUS_SPACE; 624 if (bus_space_map(sc->sc_bustag, sc->sc_basepaddr + 0x01000000, 625 0x01000000, 0, &bh)) 626 panic("could not map psycho PCI configuration space"); 627 sc->sc_bustag->type = i; 628 sc->sc_configaddr = bh; 629 } else { 630 /* Share bus numbers with the pair of mine */ 631 pp->pp_pc->spc_busnode = 632 osc->sc_psycho_this->pp_pc->spc_busnode; 633 634 /* Just copy IOMMU state, config tag and address */ 635 sc->sc_is = osc->sc_is; 636 sc->sc_configtag = osc->sc_configtag; 637 sc->sc_configaddr = osc->sc_configaddr; 638 639 /* Point the strbuf_ctl at the iommu_state */ 640 pp->pp_sb.sb_is = sc->sc_is; 641 642 if (prom_getproplen(sc->sc_node, "no-streaming-cache") < 0) { 643 struct strbuf_ctl *sb = &pp->pp_sb; 644 vaddr_t va = (vaddr_t)&pp->pp_flush[0x40]; 645 646 /* 647 * Initialize the strbuf_ctl. 648 * 649 * The flush sync buffer must be 64-byte aligned. 650 */ 651 sb->sb_flush = (void *)(va & ~0x3f); 652 653 bus_space_subregion(sc->sc_bustag, pci_ctl, 654 offsetof(struct pci_ctl, pci_strbuf), 655 sizeof (struct iommu_strbuf), &sb->sb_sb); 656 657 /* Point our iommu at the strbuf_ctl */ 658 sc->sc_is->is_sb[1] = sb; 659 } 660 iommu_reset(sc->sc_is); 661 } 662 663 dict = device_properties(self); 664 pr = get_psychorange(pp, 2); /* memory range */ 665 #ifdef DEBUG 666 printf("memory range: %08x %08x\n", pr->phys_hi, pr->phys_lo); 667 #endif 668 mem_base = ((uint64_t)pr->phys_hi) << 32 | pr->phys_lo; 669 prop_dictionary_set_uint64(dict, "mem_base", mem_base); 670 671 /* 672 * attach the pci.. note we pass PCI A tags, etc., for the sabre here. 673 */ 674 pba.pba_flags = sc->sc_psycho_this->pp_flags; 675 pba.pba_dmat = sc->sc_psycho_this->pp_dmat; 676 pba.pba_dmat64 = NULL; 677 pba.pba_iot = sc->sc_psycho_this->pp_iot; 678 pba.pba_memt = sc->sc_psycho_this->pp_memt; 679 pba.pba_pc = pp->pp_pc; 680 681 config_found_ia(self, "pcibus", &pba, psycho_print); 682 } 683 684 static int 685 psycho_print(void *aux, const char *p) 686 { 687 688 if (p == NULL) 689 return (UNCONF); 690 return (QUIET); 691 } 692 693 static void 694 psycho_set_intr(struct psycho_softc *sc, int ipl, void *handler, 695 uint64_t *mapper, uint64_t *clearer) 696 { 697 struct intrhand *ih; 698 699 ih = (struct intrhand *)malloc(sizeof(struct intrhand), 700 M_DEVBUF, M_NOWAIT); 701 ih->ih_arg = sc; 702 ih->ih_map = mapper; 703 ih->ih_clr = clearer; 704 ih->ih_fun = handler; 705 ih->ih_pil = ipl; 706 ih->ih_number = INTVEC(*(ih->ih_map)); 707 ih->ih_pending = 0; 708 intr_establish(ipl, ipl != IPL_VM, ih); 709 *(ih->ih_map) |= INTMAP_V|(CPU_UPAID << INTMAP_TID_SHIFT); 710 } 711 712 /* 713 * power button handlers 714 */ 715 static void 716 psycho_register_power_button(struct psycho_softc *sc) 717 { 718 sysmon_task_queue_init(); 719 720 sc->sc_powerpressed = 0; 721 sc->sc_smcontext = malloc(sizeof(struct sysmon_pswitch), M_DEVBUF, 0); 722 if (!sc->sc_smcontext) { 723 aprint_error_dev(sc->sc_dev, "could not allocate power button context\n"); 724 return; 725 } 726 memset(sc->sc_smcontext, 0, sizeof(struct sysmon_pswitch)); 727 sc->sc_smcontext->smpsw_name = device_xname(sc->sc_dev); 728 sc->sc_smcontext->smpsw_type = PSWITCH_TYPE_POWER; 729 if (sysmon_pswitch_register(sc->sc_smcontext) != 0) 730 aprint_error_dev(sc->sc_dev, "unable to register power button with sysmon\n"); 731 } 732 733 static void 734 psycho_power_button_pressed(void *arg) 735 { 736 struct psycho_softc *sc = arg; 737 738 sysmon_pswitch_event(sc->sc_smcontext, PSWITCH_EVENT_PRESSED); 739 sc->sc_powerpressed = 0; 740 } 741 742 /* 743 * PCI bus support 744 */ 745 746 /* 747 * allocate a PCI chipset tag and set it's cookie. 748 */ 749 static pci_chipset_tag_t 750 psycho_alloc_chipset(struct psycho_pbm *pp, int node, pci_chipset_tag_t pc) 751 { 752 pci_chipset_tag_t npc; 753 754 npc = malloc(sizeof *npc, M_DEVBUF, M_NOWAIT); 755 if (npc == NULL) 756 panic("could not allocate pci_chipset_tag_t"); 757 memcpy(npc, pc, sizeof *pc); 758 npc->cookie = pp; 759 npc->rootnode = node; 760 npc->spc_conf_read = psycho_pci_conf_read; 761 npc->spc_conf_write = psycho_pci_conf_write; 762 npc->spc_intr_map = NULL; 763 npc->spc_intr_establish = psycho_pci_intr_establish; 764 npc->spc_find_ino = psycho_pci_find_ino; 765 766 return (npc); 767 } 768 769 /* 770 * create extent for free bus space, then allocate assigned regions. 771 */ 772 static struct extent * 773 psycho_alloc_extent(struct psycho_pbm *pp, int node, int ss, const char *name) 774 { 775 struct psycho_registers *pa = NULL; 776 struct psycho_ranges *pr; 777 struct extent *ex; 778 bus_addr_t baddr, addr; 779 bus_size_t bsize, size; 780 int i, num; 781 782 /* get bus space size */ 783 pr = get_psychorange(pp, ss); 784 if (pr == NULL) { 785 printf("psycho_alloc_extent: get_psychorange failed\n"); 786 return NULL; 787 } 788 baddr = 0x00000000; 789 bsize = BUS_ADDR(pr->size_hi, pr->size_lo); 790 791 /* get available lists */ 792 num = 0; 793 if (prom_getprop(node, "available", sizeof(*pa), &num, &pa)) { 794 printf("psycho_alloc_extent: no \"available\" property\n"); 795 return NULL; 796 } 797 798 /* create extent */ 799 ex = extent_create(name, baddr, bsize - baddr - 1, M_DEVBUF, 0, 0, 800 EX_NOWAIT); 801 if (ex == NULL) { 802 printf("psycho_alloc_extent: extent_create failed\n"); 803 goto ret; 804 } 805 806 /* allocate assigned regions */ 807 for (i = 0; i < num; i++) 808 if (((pa[i].phys_hi >> 24) & 0x03) == ss) { 809 /* allocate bus space */ 810 addr = BUS_ADDR(pa[i].phys_mid, pa[i].phys_lo); 811 size = BUS_ADDR(pa[i].size_hi, pa[i].size_lo); 812 if (extent_alloc_region(ex, baddr, addr - baddr, 813 EX_NOWAIT)) { 814 printf("psycho_alloc_extent: " 815 "extent_alloc_region %" PRIx64 "-%" 816 PRIx64 " failed\n", baddr, addr); 817 extent_destroy(ex); 818 ex = NULL; 819 goto ret; 820 } 821 baddr = addr + size; 822 } 823 /* allocate left region if available */ 824 if (baddr < bsize) 825 if (extent_alloc_region(ex, baddr, bsize - baddr, EX_NOWAIT)) { 826 printf("psycho_alloc_extent: extent_alloc_region %" 827 PRIx64 "-%" PRIx64 " failed\n", baddr, bsize); 828 extent_destroy(ex); 829 ex = NULL; 830 goto ret; 831 } 832 833 #ifdef DEBUG 834 /* print extent */ 835 extent_print(ex); 836 #endif 837 838 ret: 839 /* return extent */ 840 free(pa, M_DEVBUF); 841 return ex; 842 } 843 844 /* 845 * grovel the OBP for various psycho properties 846 */ 847 static void 848 psycho_get_bus_range(int node, int *brp) 849 { 850 int n, error; 851 852 n = 2; 853 error = prom_getprop(node, "bus-range", sizeof(*brp), &n, &brp); 854 if (error) 855 panic("could not get psycho bus-range, error %d", error); 856 if (n != 2) 857 panic("broken psycho bus-range"); 858 DPRINTF(PDB_PROM, ("psycho debug: got `bus-range' for node %08x: %u - %u\n", 859 node, brp[0], brp[1])); 860 } 861 862 static void 863 psycho_get_ranges(int node, struct psycho_ranges **rp, int *np) 864 { 865 866 if (prom_getprop(node, "ranges", sizeof(**rp), np, rp)) 867 panic("could not get psycho ranges"); 868 DPRINTF(PDB_PROM, ("psycho debug: got `ranges' for node %08x: %d entries\n", node, *np)); 869 } 870 871 /* 872 * Interrupt handlers. 873 */ 874 875 static int 876 psycho_ue(void *arg) 877 { 878 struct psycho_softc *sc = (struct psycho_softc *)arg; 879 struct psychoreg *regs = sc->sc_regs; 880 struct iommu_state *is = sc->sc_is; 881 uint64_t afsr = regs->psy_ue_afsr; 882 uint64_t afar = regs->psy_ue_afar; 883 psize_t size = PAGE_SIZE << is->is_tsbsize; 884 char bits[128]; 885 886 /* 887 * It's uncorrectable. Dump the regs and panic. 888 */ 889 snprintb(bits, sizeof(bits), PSYCHO_UE_AFSR_BITS, afsr); 890 aprint_error_dev(sc->sc_dev, 891 "uncorrectable DMA error AFAR %" PRIx64 " AFSR %s\n", afar, bits); 892 893 /* Sometimes the AFAR points to an IOTSB entry */ 894 if (afar >= is->is_ptsb && afar < is->is_ptsb + size) { 895 aprint_error_dev(sc->sc_dev, 896 "IOVA %" PRIx64 " IOTTE %" PRIx64 "\n", 897 (afar - is->is_ptsb) / sizeof(is->is_tsb[0]) * PAGE_SIZE 898 + is->is_dvmabase, ldxa(afar, ASI_PHYS_CACHED)); 899 } 900 #ifdef DDB 901 Debugger(); 902 #endif 903 regs->psy_ue_afar = 0; 904 regs->psy_ue_afsr = 0; 905 return (1); 906 } 907 908 static int 909 psycho_ce(void *arg) 910 { 911 struct psycho_softc *sc = (struct psycho_softc *)arg; 912 struct psychoreg *regs = sc->sc_regs; 913 914 /* 915 * It's correctable. Dump the regs and continue. 916 */ 917 aprint_error_dev(sc->sc_dev, 918 "correctable DMA error AFAR %" PRIx64 " AFSR %" PRIx64 "\n", 919 regs->psy_ce_afar, regs->psy_ce_afsr); 920 return (1); 921 } 922 923 static int 924 psycho_bus_a(void *arg) 925 { 926 struct psycho_softc *sc = (struct psycho_softc *)arg; 927 struct psychoreg *regs = sc->sc_regs; 928 929 /* 930 * It's uncorrectable. Dump the regs and panic. 931 */ 932 933 panic("%s: PCI bus A error AFAR %" PRIx64 " AFSR %" PRIx64, 934 device_xname(sc->sc_dev), 935 regs->psy_pcictl[0].pci_afar, regs->psy_pcictl[0].pci_afsr); 936 return (1); 937 } 938 939 static int 940 psycho_bus_b(void *arg) 941 { 942 struct psycho_softc *sc = (struct psycho_softc *)arg; 943 struct psychoreg *regs = sc->sc_regs; 944 945 /* 946 * It's uncorrectable. Dump the regs and panic. 947 */ 948 949 panic("%s: PCI bus B error AFAR %" PRIx64 " AFSR %" PRIx64, 950 device_xname(sc->sc_dev), 951 regs->psy_pcictl[0].pci_afar, regs->psy_pcictl[0].pci_afsr); 952 return (1); 953 } 954 955 static int 956 psycho_powerfail(void *arg) 957 { 958 struct psycho_softc *sc = (struct psycho_softc *)arg; 959 960 /* 961 * We lost power. Queue a callback with thread context to 962 * handle all the real work. 963 */ 964 if (sc->sc_powerpressed == 0 && sc->sc_smcontext != NULL) { 965 sc->sc_powerpressed = 1; 966 sysmon_task_queue_sched(0, psycho_power_button_pressed, sc); 967 } 968 return (1); 969 } 970 971 static 972 int psycho_wakeup(void *arg) 973 { 974 struct psycho_softc *sc = (struct psycho_softc *)arg; 975 976 /* 977 * Gee, we don't really have a framework to deal with this 978 * properly. 979 */ 980 aprint_error_dev(sc->sc_dev, "power management wakeup\n"); 981 return (1); 982 } 983 984 985 /* 986 * initialise the IOMMU.. 987 */ 988 void 989 psycho_iommu_init(struct psycho_softc *sc, int tsbsize) 990 { 991 char *name; 992 struct iommu_state *is = sc->sc_is; 993 uint32_t iobase = -1; 994 int *vdma = NULL; 995 int nitem; 996 997 /* punch in our copies */ 998 is->is_bustag = sc->sc_bustag; 999 bus_space_subregion(sc->sc_bustag, sc->sc_bh, 1000 offsetof(struct psychoreg, psy_iommu), 1001 sizeof (struct iommureg), 1002 &is->is_iommu); 1003 1004 /* 1005 * Separate the men from the boys. Get the `virtual-dma' 1006 * property for sabre and use that to make sure the damn 1007 * iommu works. 1008 * 1009 * We could query the `#virtual-dma-size-cells' and 1010 * `#virtual-dma-addr-cells' and DTRT, but I'm lazy. 1011 */ 1012 nitem = 0; 1013 if (!prom_getprop(sc->sc_node, "virtual-dma", sizeof(vdma), &nitem, 1014 &vdma)) { 1015 /* Damn. Gotta use these values. */ 1016 iobase = vdma[0]; 1017 #define TSBCASE(x) case 1<<((x)+23): tsbsize = (x); break 1018 switch (vdma[1]) { 1019 TSBCASE(1); TSBCASE(2); TSBCASE(3); 1020 TSBCASE(4); TSBCASE(5); TSBCASE(6); 1021 default: 1022 printf("bogus tsb size %x, using 7\n", vdma[1]); 1023 TSBCASE(7); 1024 } 1025 #undef TSBCASE 1026 } 1027 1028 /* give us a nice name.. */ 1029 name = (char *)malloc(32, M_DEVBUF, M_NOWAIT); 1030 if (name == 0) 1031 panic("couldn't malloc iommu name"); 1032 snprintf(name, 32, "%s dvma", device_xname(sc->sc_dev)); 1033 1034 iommu_init(name, is, tsbsize, iobase); 1035 } 1036 1037 /* 1038 * below here is bus space and bus DMA support 1039 */ 1040 bus_space_tag_t 1041 psycho_alloc_bus_tag(struct psycho_pbm *pp, int type) 1042 { 1043 struct psycho_softc *sc = pp->pp_sc; 1044 bus_space_tag_t bt; 1045 1046 bt = (bus_space_tag_t) malloc(sizeof(struct sparc_bus_space_tag), 1047 M_DEVBUF, M_NOWAIT | M_ZERO); 1048 if (bt == NULL) 1049 panic("could not allocate psycho bus tag"); 1050 1051 bt->cookie = pp; 1052 bt->parent = sc->sc_bustag; 1053 bt->type = type; 1054 bt->sparc_bus_map = _psycho_bus_map; 1055 bt->sparc_bus_mmap = psycho_bus_mmap; 1056 bt->sparc_intr_establish = psycho_intr_establish; 1057 return (bt); 1058 } 1059 1060 bus_dma_tag_t 1061 psycho_alloc_dma_tag(struct psycho_pbm *pp) 1062 { 1063 struct psycho_softc *sc = pp->pp_sc; 1064 bus_dma_tag_t dt, pdt = sc->sc_dmatag; 1065 1066 dt = (bus_dma_tag_t) 1067 malloc(sizeof(struct sparc_bus_dma_tag), M_DEVBUF, M_NOWAIT); 1068 if (dt == NULL) 1069 panic("could not allocate psycho DMA tag"); 1070 1071 memset(dt, 0, sizeof *dt); 1072 dt->_cookie = pp; 1073 dt->_parent = pdt; 1074 #define PCOPY(x) dt->x = pdt->x 1075 dt->_dmamap_create = psycho_dmamap_create; 1076 PCOPY(_dmamap_destroy); 1077 dt->_dmamap_load = iommu_dvmamap_load; 1078 PCOPY(_dmamap_load_mbuf); 1079 PCOPY(_dmamap_load_uio); 1080 dt->_dmamap_load_raw = iommu_dvmamap_load_raw; 1081 dt->_dmamap_unload = iommu_dvmamap_unload; 1082 if (sc->sc_mode == PSYCHO_MODE_SABRE) 1083 dt->_dmamap_sync = psycho_sabre_dmamap_sync; 1084 else 1085 dt->_dmamap_sync = iommu_dvmamap_sync; 1086 dt->_dmamem_alloc = iommu_dvmamem_alloc; 1087 dt->_dmamem_free = iommu_dvmamem_free; 1088 dt->_dmamem_map = iommu_dvmamem_map; 1089 dt->_dmamem_unmap = iommu_dvmamem_unmap; 1090 PCOPY(_dmamem_mmap); 1091 #undef PCOPY 1092 return (dt); 1093 } 1094 1095 /* 1096 * bus space support. <sparc64/dev/psychoreg.h> has a discussion about 1097 * PCI physical addresses. 1098 */ 1099 1100 static struct psycho_ranges * 1101 get_psychorange(struct psycho_pbm *pp, int ss) 1102 { 1103 int i; 1104 1105 for (i = 0; i < pp->pp_nrange; i++) { 1106 if (((pp->pp_range[i].cspace >> 24) & 0x03) == ss) 1107 return (&pp->pp_range[i]); 1108 } 1109 /* not found */ 1110 return (NULL); 1111 } 1112 1113 static int 1114 _psycho_bus_map(bus_space_tag_t t, bus_addr_t offset, bus_size_t size, 1115 int flags, vaddr_t unused, bus_space_handle_t *hp) 1116 { 1117 struct psycho_pbm *pp = t->cookie; 1118 struct psycho_softc *sc = pp->pp_sc; 1119 struct psycho_ranges *pr; 1120 bus_addr_t paddr; 1121 int ss; 1122 1123 DPRINTF(PDB_BUSMAP, 1124 ("_psycho_bus_map: type %d off %qx sz %qx flags %d", 1125 t->type, (unsigned long long)offset, 1126 (unsigned long long)size, flags)); 1127 1128 ss = sparc_pci_childspace(t->type); 1129 DPRINTF(PDB_BUSMAP, (" cspace %d", ss)); 1130 1131 pr = get_psychorange(pp, ss); 1132 if (pr != NULL) { 1133 paddr = BUS_ADDR(pr->phys_hi, pr->phys_lo + offset); 1134 DPRINTF(PDB_BUSMAP, ("\n_psycho_bus_map: mapping paddr " 1135 "space %lx offset %lx paddr %qx\n", 1136 (long)ss, (long)offset, 1137 (unsigned long long)paddr)); 1138 return ((*sc->sc_bustag->sparc_bus_map)(t, paddr, size, 1139 flags, 0, hp)); 1140 } 1141 DPRINTF(PDB_BUSMAP, (" FAILED\n")); 1142 return (EINVAL); 1143 } 1144 1145 static paddr_t 1146 psycho_bus_mmap(bus_space_tag_t t, bus_addr_t paddr, off_t off, int prot, 1147 int flags) 1148 { 1149 bus_addr_t offset = paddr; 1150 struct psycho_pbm *pp = t->cookie; 1151 struct psycho_softc *sc = pp->pp_sc; 1152 struct psycho_ranges *pr; 1153 int ss; 1154 1155 ss = sparc_pci_childspace(t->type); 1156 1157 DPRINTF(PDB_BUSMAP, ("_psycho_bus_mmap: prot %x flags %d pa %qx\n", 1158 prot, flags, (unsigned long long)paddr)); 1159 1160 pr = get_psychorange(pp, ss); 1161 if (pr != NULL) { 1162 paddr = BUS_ADDR(pr->phys_hi, pr->phys_lo + offset); 1163 DPRINTF(PDB_BUSMAP, ("\n_psycho_bus_mmap: mapping paddr " 1164 "space %lx offset %lx paddr %qx\n", 1165 (long)ss, (long)offset, 1166 (unsigned long long)paddr)); 1167 return (bus_space_mmap(sc->sc_bustag, paddr, off, 1168 prot, flags)); 1169 } 1170 1171 return (-1); 1172 } 1173 1174 /* 1175 * Get a PCI offset address from bus_space_handle_t. 1176 */ 1177 bus_addr_t 1178 psycho_bus_offset(bus_space_tag_t t, bus_space_handle_t *hp) 1179 { 1180 struct psycho_pbm *pp = t->cookie; 1181 struct psycho_ranges *pr; 1182 bus_addr_t addr, offset; 1183 vaddr_t va; 1184 int ss; 1185 1186 addr = hp->_ptr; 1187 ss = sparc_pci_childspace(t->type); 1188 DPRINTF(PDB_BUSMAP, ("psycho_bus_offset: type %d addr %" PRIx64 1189 " cspace %d", t->type, addr, ss)); 1190 1191 pr = get_psychorange(pp, ss); 1192 if (pr != NULL) { 1193 if (!PHYS_ASI(hp->_asi)) { 1194 va = trunc_page((vaddr_t)addr); 1195 if (pmap_extract(pmap_kernel(), va, &addr) == FALSE) { 1196 DPRINTF(PDB_BUSMAP, 1197 ("\n pmap_extract FAILED\n")); 1198 return (-1); 1199 } 1200 addr += hp->_ptr & PGOFSET; 1201 } 1202 offset = BUS_ADDR_PADDR(addr) - pr->phys_lo; 1203 DPRINTF(PDB_BUSMAP, ("\npsycho_bus_offset: paddr %" PRIx64 1204 " offset %" PRIx64 "\n", addr, offset)); 1205 return (offset); 1206 } 1207 DPRINTF(PDB_BUSMAP, ("\n FAILED\n")); 1208 return (-1); 1209 } 1210 1211 1212 /* 1213 * install an interrupt handler for a PCI device 1214 */ 1215 void * 1216 psycho_intr_establish(bus_space_tag_t t, int ihandle, int level, 1217 int (*handler)(void *), void *arg, void (*fastvec)(void) /* ignored */) 1218 { 1219 struct psycho_pbm *pp = t->cookie; 1220 struct psycho_softc *sc = pp->pp_sc; 1221 struct intrhand *ih; 1222 volatile uint64_t *intrmapptr = NULL, *intrclrptr = NULL; 1223 int64_t imap = 0; 1224 int ino; 1225 long vec = INTVEC(ihandle); 1226 1227 ih = (struct intrhand *) 1228 malloc(sizeof(struct intrhand), M_DEVBUF, M_NOWAIT); 1229 if (ih == NULL) 1230 return (NULL); 1231 1232 ih->ih_ivec = ihandle; 1233 1234 /* 1235 * Hunt through all the interrupt mapping regs to look for our 1236 * interrupt vector. 1237 * 1238 * XXX We only compare INOs rather than IGNs since the firmware may 1239 * not provide the IGN and the IGN is constant for all device on that 1240 * PCI controller. This could cause problems for the FFB/external 1241 * interrupt which has a full vector that can be set arbitrarily. 1242 */ 1243 1244 DPRINTF(PDB_INTR, ("\npsycho_intr_establish: ihandle %x vec %lx", ihandle, vec)); 1245 ino = INTINO(vec); 1246 DPRINTF(PDB_INTR, (" ino %x", ino)); 1247 1248 /* If the device didn't ask for an IPL, use the one encoded. */ 1249 if (level == IPL_NONE) level = INTLEV(vec); 1250 /* If it still has no level, print a warning and assign IPL 2 */ 1251 if (level == IPL_NONE) { 1252 printf("ERROR: no IPL, setting IPL 2.\n"); 1253 level = 2; 1254 } 1255 1256 DPRINTF(PDB_INTR, ("\npsycho: intr %lx: %p\nHunting for IRQ...\n", 1257 (long)ino, intrlev[ino])); 1258 1259 /* 1260 * First look for PCI interrupts, otherwise the PCI A slot 0 1261 * INTA# interrupt might match an unused non-PCI (obio) 1262 * interrupt. 1263 */ 1264 for (intrmapptr = &sc->sc_regs->pcia_slot0_int, 1265 intrclrptr = &sc->sc_regs->pcia0_clr_int[0]; 1266 intrmapptr <= &sc->sc_regs->pcib_slot3_int; 1267 intrmapptr++, intrclrptr += 4) { 1268 if (sc->sc_mode == PSYCHO_MODE_PSYCHO && 1269 (intrmapptr == &sc->sc_regs->pcia_slot2_int || 1270 intrmapptr == &sc->sc_regs->pcia_slot3_int)) 1271 continue; 1272 if (((*intrmapptr ^ vec) & 0x3c) == 0) { 1273 intrclrptr += vec & 0x3; 1274 goto found; 1275 } 1276 } 1277 1278 /* Now hunt thru obio. */ 1279 for (intrmapptr = &sc->sc_regs->scsi_int_map, 1280 intrclrptr = &sc->sc_regs->scsi_clr_int; 1281 intrmapptr < &sc->sc_regs->ue_int_map; 1282 intrmapptr++, intrclrptr++) { 1283 if (INTINO(*intrmapptr) == ino) 1284 goto found; 1285 } 1286 1287 /* Finally check the two FFB slots */ 1288 intrclrptr = NULL; /* XXX? */ 1289 for (intrmapptr = &sc->sc_regs->ffb0_int_map; 1290 intrmapptr <= &sc->sc_regs->ffb1_int_map; 1291 intrmapptr++) { 1292 if (INTVEC(*intrmapptr) == ino) 1293 goto found; 1294 } 1295 1296 printf("Cannot find interrupt vector %lx\n", vec); 1297 return (NULL); 1298 1299 found: 1300 /* Register the map and clear intr registers */ 1301 ih->ih_map = intrmapptr; 1302 ih->ih_clr = intrclrptr; 1303 1304 ih->ih_fun = handler; 1305 ih->ih_arg = arg; 1306 ih->ih_pil = level; 1307 ih->ih_number = ino | sc->sc_ign; 1308 ih->ih_pending = 0; 1309 1310 DPRINTF(PDB_INTR, ( 1311 "; installing handler %p arg %p with ino %u pil %u\n", 1312 handler, arg, (u_int)ino, (u_int)ih->ih_pil)); 1313 1314 intr_establish(ih->ih_pil, level != IPL_VM, ih); 1315 1316 /* 1317 * Enable the interrupt now we have the handler installed. 1318 * Read the current value as we can't change it besides the 1319 * valid bit so so make sure only this bit is changed. 1320 * 1321 * XXXX --- we really should use bus_space for this. 1322 */ 1323 if (intrmapptr) { 1324 imap = *intrmapptr; 1325 DPRINTF(PDB_INTR, ("; read intrmap = %016qx", 1326 (unsigned long long)imap)); 1327 1328 /* Enable the interrupt */ 1329 imap |= INTMAP_V|(CPU_UPAID << INTMAP_TID_SHIFT); 1330 DPRINTF(PDB_INTR, ("; addr of intrmapptr = %p", intrmapptr)); 1331 DPRINTF(PDB_INTR, ("; writing intrmap = %016qx\n", 1332 (unsigned long long)imap)); 1333 *intrmapptr = imap; 1334 DPRINTF(PDB_INTR, ("; reread intrmap = %016qx", 1335 (unsigned long long)(imap = *intrmapptr))); 1336 } 1337 if (intrclrptr) { 1338 /* set state to IDLE */ 1339 *intrclrptr = 0; 1340 } 1341 return (ih); 1342 } 1343 1344 /* 1345 * per-controller driver calls 1346 */ 1347 1348 /* assume we are mapped little-endian/side-effect */ 1349 static pcireg_t 1350 psycho_pci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg) 1351 { 1352 struct psycho_pbm *pp = pc->cookie; 1353 struct psycho_softc *sc = pp->pp_sc; 1354 pcireg_t val = (pcireg_t)~0; 1355 1356 DPRINTF(PDB_CONF, ("%s: tag %lx reg %x ", __func__, 1357 (long)tag, reg)); 1358 if (PCITAG_NODE(tag) != -1) { 1359 1360 DPRINTF(PDB_CONF, ("asi=%x addr=%qx (offset=%x) ...", 1361 sc->sc_configaddr._asi, 1362 (long long)(sc->sc_configaddr._ptr + 1363 PCITAG_OFFSET(tag) + reg), 1364 (int)PCITAG_OFFSET(tag) + reg)); 1365 1366 val = bus_space_read_4(sc->sc_configtag, sc->sc_configaddr, 1367 PCITAG_OFFSET(tag) + reg); 1368 } 1369 #ifdef DEBUG 1370 else DPRINTF(PDB_CONF, ("%s: bogus pcitag %x\n", __func__, 1371 (int)PCITAG_OFFSET(tag))); 1372 #endif 1373 DPRINTF(PDB_CONF, (" returning %08x\n", (u_int)val)); 1374 1375 return (val); 1376 } 1377 1378 static void 1379 psycho_pci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data) 1380 { 1381 struct psycho_pbm *pp = pc->cookie; 1382 struct psycho_softc *sc = pp->pp_sc; 1383 1384 DPRINTF(PDB_CONF, ("%s: tag %lx; reg %x; data %x; ", __func__, 1385 (long)PCITAG_OFFSET(tag), reg, (int)data)); 1386 DPRINTF(PDB_CONF, ("asi = %x; readaddr = %qx (offset = %x)\n", 1387 sc->sc_configaddr._asi, 1388 (long long)(sc->sc_configaddr._ptr + PCITAG_OFFSET(tag) + reg), 1389 (int)PCITAG_OFFSET(tag) + reg)); 1390 1391 /* If we don't know it, just punt it. */ 1392 if (PCITAG_NODE(tag) == -1) { 1393 DPRINTF(PDB_CONF, ("%s: bad addr", __func__)); 1394 return; 1395 } 1396 1397 bus_space_write_4(sc->sc_configtag, sc->sc_configaddr, 1398 PCITAG_OFFSET(tag) + reg, data); 1399 } 1400 1401 static void * 1402 psycho_pci_intr_establish(pci_chipset_tag_t pc, pci_intr_handle_t ih, int level, 1403 int (*func)(void *), void *arg) 1404 { 1405 void *cookie; 1406 struct psycho_pbm *pp = (struct psycho_pbm *)pc->cookie; 1407 1408 DPRINTF(PDB_INTR, ("%s: ih %lx; level %d", __func__, (u_long)ih, level)); 1409 cookie = bus_intr_establish(pp->pp_memt, ih, level, func, arg); 1410 1411 DPRINTF(PDB_INTR, ("; returning handle %p\n", cookie)); 1412 return (cookie); 1413 } 1414 1415 static int 1416 psycho_pci_find_ino(const struct pci_attach_args *pa, pci_intr_handle_t *ihp) 1417 { 1418 struct psycho_pbm *pp = pa->pa_pc->cookie; 1419 struct psycho_softc *sc = pp->pp_sc; 1420 u_int bus; 1421 u_int dev; 1422 u_int pin; 1423 1424 DPRINTF(PDB_INTMAP, ("%s: pa_tag: node %x, %d:%d:%d\n", __func__, 1425 PCITAG_NODE(pa->pa_tag), (int)PCITAG_BUS(pa->pa_tag), 1426 (int)PCITAG_DEV(pa->pa_tag), 1427 (int)PCITAG_FUN(pa->pa_tag))); 1428 DPRINTF(PDB_INTMAP, 1429 ("%s: intrswiz %d, intrpin %d, intrline %d, rawintrpin %d\n", __func__, 1430 pa->pa_intrswiz, pa->pa_intrpin, pa->pa_intrline, pa->pa_rawintrpin)); 1431 DPRINTF(PDB_INTMAP, ("%s: pa_intrtag: node %x, %d:%d:%d\n", __func__, 1432 PCITAG_NODE(pa->pa_intrtag), 1433 (int)PCITAG_BUS(pa->pa_intrtag), 1434 (int)PCITAG_DEV(pa->pa_intrtag), 1435 (int)PCITAG_FUN(pa->pa_intrtag))); 1436 1437 bus = (pp->pp_id == PSYCHO_PBM_B); 1438 /* 1439 * If we are on a ppb, use the devno on the underlying bus when forming 1440 * the ivec. 1441 */ 1442 if (pa->pa_intrswiz != 0 && PCITAG_NODE(pa->pa_intrtag) != 0) 1443 dev = PCITAG_DEV(pa->pa_intrtag); 1444 else 1445 dev = pa->pa_device; 1446 dev--; 1447 1448 if (sc->sc_mode == PSYCHO_MODE_PSYCHO && 1449 pp->pp_id == PSYCHO_PBM_B) 1450 dev--; 1451 1452 pin = pa->pa_intrpin - 1; 1453 DPRINTF(PDB_INTMAP, ("%s: mode %d, pbm %d, dev %d, pin %d\n", __func__, 1454 sc->sc_mode, pp->pp_id, dev, pin)); 1455 1456 *ihp = sc->sc_ign | ((bus << 4) & INTMAP_PCIBUS) | 1457 ((dev << 2) & INTMAP_PCISLOT) | (pin & INTMAP_PCIINT); 1458 1459 return (0); 1460 } 1461 1462 /* 1463 * hooks into the iommu dvma calls. 1464 */ 1465 static int 1466 psycho_dmamap_create(bus_dma_tag_t t, bus_size_t size, int nsegments, 1467 bus_size_t maxsegsz, bus_size_t boundary, int flags, 1468 bus_dmamap_t *dmamp) 1469 { 1470 struct psycho_pbm *pp = (struct psycho_pbm *)t->_cookie; 1471 int error; 1472 1473 error = bus_dmamap_create(t->_parent, size, nsegments, maxsegsz, 1474 boundary, flags, dmamp); 1475 if (error == 0) 1476 (*dmamp)->_dm_cookie = &pp->pp_sb; 1477 return error; 1478 } 1479 1480 /* 1481 * UltraSPARC IIi and IIe have no streaming buffers, but have PCI DMA 1482 * Write Synchronization Register (see UltraSPARC-IIi User's Manual 1483 * section 19.3.0.5). So use it to synchronize with the DMA writes. 1484 */ 1485 static void 1486 psycho_sabre_dmamap_sync(bus_dma_tag_t t, bus_dmamap_t map, bus_addr_t offset, 1487 bus_size_t len, int ops) 1488 { 1489 struct psycho_pbm *pp; 1490 struct psycho_softc *sc; 1491 1492 /* If len is 0, then there is nothing to do. */ 1493 if (len == 0) 1494 return; 1495 1496 if (ops & BUS_DMASYNC_POSTREAD) { 1497 pp = (struct psycho_pbm *)t->_cookie; 1498 sc = pp->pp_sc; 1499 bus_space_read_8(sc->sc_bustag, sc->sc_bh, 1500 offsetof(struct psychoreg, pci_dma_write_sync)); 1501 } 1502 bus_dmamap_sync(t->_parent, map, offset, len, ops); 1503 } 1504
Indexes created Thu Sep 25 06:09:39 GMT 2025