psycho.c revision 1.115
1 /* $NetBSD: psycho.c,v 1.115 2013/08/22 09:57:30 nakayama Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000 Matthew R. Green 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * Copyright (c) 2001, 2002 Eduardo E. Horvath 31 * All rights reserved. 32 * 33 * Redistribution and use in source and binary forms, with or without 34 * modification, are permitted provided that the following conditions 35 * are met: 36 * 1. Redistributions of source code must retain the above copyright 37 * notice, this list of conditions and the following disclaimer. 38 * 2. Redistributions in binary form must reproduce the above copyright 39 * notice, this list of conditions and the following disclaimer in the 40 * documentation and/or other materials provided with the distribution. 41 * 3. The name of the author may not be used to endorse or promote products 42 * derived from this software without specific prior written permission. 43 * 44 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 45 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 46 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 47 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 48 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 49 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 50 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 51 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 52 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 53 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 54 * SUCH DAMAGE. 55 */ 56 57 #include <sys/cdefs.h> 58 __KERNEL_RCSID(0, "$NetBSD: psycho.c,v 1.115 2013/08/22 09:57:30 nakayama Exp $"); 59 60 #include "opt_ddb.h" 61 62 /* 63 * Support for `psycho' and `psycho+' UPA to PCI bridge and 64 * UltraSPARC IIi and IIe `sabre' PCI controllers. 65 */ 66 67 #ifdef DEBUG 68 #define PDB_PROM 0x01 69 #define PDB_BUSMAP 0x02 70 #define PDB_INTR 0x04 71 #define PDB_INTMAP 0x08 72 #define PDB_CONF 0x10 73 #define PDB_STICK 0x20 74 int psycho_debug = 0x0; 75 #define DPRINTF(l, s) do { if (psycho_debug & l) printf s; } while (0) 76 #else 77 #define DPRINTF(l, s) 78 #endif 79 80 #include <sys/param.h> 81 #include <sys/device.h> 82 #include <sys/errno.h> 83 #include <sys/extent.h> 84 #include <sys/malloc.h> 85 #include <sys/systm.h> 86 #include <sys/time.h> 87 #include <sys/reboot.h> 88 89 #include <uvm/uvm.h> 90 91 #define _SPARC_BUS_DMA_PRIVATE 92 #include <sys/bus.h> 93 #include <machine/autoconf.h> 94 #include <machine/psl.h> 95 96 #include <dev/pci/pcivar.h> 97 #include <dev/pci/pcireg.h> 98 #include <dev/sysmon/sysmon_taskq.h> 99 100 #include <sparc64/dev/iommureg.h> 101 #include <sparc64/dev/iommuvar.h> 102 #include <sparc64/dev/psychoreg.h> 103 #include <sparc64/dev/psychovar.h> 104 105 #include "ioconf.h" 106 107 static pci_chipset_tag_t psycho_alloc_chipset(struct psycho_pbm *, int, 108 pci_chipset_tag_t); 109 static struct extent *psycho_alloc_extent(struct psycho_pbm *, int, int, 110 const char *); 111 static void psycho_get_bus_range(int, int *); 112 static void psycho_get_ranges(int, struct psycho_ranges **, int *); 113 static void psycho_set_intr(struct psycho_softc *, int, void *, uint64_t *, 114 uint64_t *); 115 116 /* chipset handlers */ 117 static pcireg_t psycho_pci_conf_read(pci_chipset_tag_t, pcitag_t, int); 118 static void psycho_pci_conf_write(pci_chipset_tag_t, pcitag_t, int, 119 pcireg_t); 120 static void *psycho_pci_intr_establish(pci_chipset_tag_t, 121 pci_intr_handle_t, 122 int, int (*)(void *), void *); 123 static int psycho_pci_find_ino(const struct pci_attach_args *, 124 pci_intr_handle_t *); 125 126 /* Interrupt handlers */ 127 static int psycho_ue(void *); 128 static int psycho_ce(void *); 129 static int psycho_bus_a(void *); 130 static int psycho_bus_b(void *); 131 static int psycho_powerfail(void *); 132 static int psycho_wakeup(void *); 133 134 135 /* IOMMU support */ 136 static void psycho_iommu_init(struct psycho_softc *, int); 137 138 /* 139 * bus space and bus DMA support for UltraSPARC `psycho'. note that most 140 * of the bus DMA support is provided by the iommu dvma controller. 141 */ 142 static struct psycho_ranges *get_psychorange(struct psycho_pbm *, int); 143 144 static paddr_t psycho_bus_mmap(bus_space_tag_t, bus_addr_t, off_t, int, int); 145 static int _psycho_bus_map(bus_space_tag_t, bus_addr_t, bus_size_t, int, 146 vaddr_t, bus_space_handle_t *); 147 static void *psycho_intr_establish(bus_space_tag_t, int, int, int (*)(void *), 148 void *, void(*)(void)); 149 150 static int psycho_dmamap_create(bus_dma_tag_t, bus_size_t, int, bus_size_t, 151 bus_size_t, int, bus_dmamap_t *); 152 static void psycho_sabre_dmamap_sync(bus_dma_tag_t, bus_dmamap_t, bus_addr_t, 153 bus_size_t, int); 154 155 /* base pci_chipset */ 156 extern struct sparc_pci_chipset _sparc_pci_chipset; 157 158 /* power button handlers */ 159 static void psycho_register_power_button(struct psycho_softc *sc); 160 static void psycho_power_button_pressed(void *arg); 161 162 /* 163 * autoconfiguration 164 */ 165 static int psycho_match(device_t, cfdata_t, void *); 166 static void psycho_attach(device_t, device_t, void *); 167 static int psycho_print(void *aux, const char *p); 168 169 CFATTACH_DECL_NEW(psycho, sizeof(struct psycho_softc), 170 psycho_match, psycho_attach, NULL, NULL); 171 172 /* 173 * "sabre" is the UltraSPARC IIi onboard UPA to PCI bridge. It manages a 174 * single PCI bus and does not have a streaming buffer. It often has an APB 175 * (advanced PCI bridge) connected to it, which was designed specifically for 176 * the IIi. The APB let's the IIi handle two independednt PCI buses, and 177 * appears as two "simba"'s underneath the sabre. 178 * 179 * "psycho" and "psycho+" is a dual UPA to PCI bridge. It sits on the UPA bus 180 * and manages two PCI buses. "psycho" has two 64-bit 33 MHz buses, while 181 * "psycho+" controls both a 64-bit 33 MHz and a 64-bit 66 MHz PCI bus. You 182 * will usually find a "psycho+" since I don't think the original "psycho" 183 * ever shipped, and if it did it would be in the U30. 184 * 185 * Each "psycho" PCI bus appears as a separate OFW node, but since they are 186 * both part of the same IC, they only have a single register space. As such, 187 * they need to be configured together, even though the autoconfiguration will 188 * attach them separately. 189 * 190 * On UltraIIi machines, "sabre" itself usually takes pci0, with "simba" often 191 * as pci1 and pci2, although they have been implemented with other PCI bus 192 * numbers on some machines. 193 * 194 * On UltraII machines, there can be any number of "psycho+" ICs, each 195 * providing two PCI buses. 196 * 197 * 198 * XXXX The psycho/sabre node has an `interrupts' attribute. They contain 199 * the values of the following interrupts in this order: 200 * 201 * PCI Bus Error (30) 202 * DMA UE (2e) 203 * DMA CE (2f) 204 * Power Fail (25) 205 * 206 * We really should attach handlers for each. 207 * 208 */ 209 210 #define ROM_PCI_NAME "pci" 211 212 struct psycho_names { 213 const char *p_name; 214 int p_type; 215 } psycho_names[] = { 216 { "SUNW,psycho", PSYCHO_MODE_PSYCHO }, 217 { "pci108e,8000", PSYCHO_MODE_PSYCHO }, 218 { "SUNW,sabre", PSYCHO_MODE_SABRE }, 219 { "pci108e,a000", PSYCHO_MODE_SABRE }, 220 { "pci108e,a001", PSYCHO_MODE_SABRE }, 221 { NULL, 0 } 222 }; 223 224 struct psycho_softc *psycho0 = NULL; 225 226 static int 227 psycho_match(device_t parent, cfdata_t match, void *aux) 228 { 229 struct mainbus_attach_args *ma = aux; 230 char *model = prom_getpropstring(ma->ma_node, "model"); 231 int i; 232 233 /* match on a name of "pci" and a sabre or a psycho */ 234 if (strcmp(ma->ma_name, ROM_PCI_NAME) == 0) { 235 for (i=0; psycho_names[i].p_name; i++) 236 if (strcmp(model, psycho_names[i].p_name) == 0) 237 return (1); 238 239 model = prom_getpropstring(ma->ma_node, "compatible"); 240 for (i=0; psycho_names[i].p_name; i++) 241 if (strcmp(model, psycho_names[i].p_name) == 0) 242 return (1); 243 } 244 return (0); 245 } 246 247 #ifdef DEBUG 248 static void psycho_dump_intmap(struct psycho_softc *sc); 249 static void 250 psycho_dump_intmap(struct psycho_softc *sc) 251 { 252 volatile uint64_t *intrmapptr = NULL; 253 254 printf("psycho_dump_intmap: OBIO\n"); 255 256 for (intrmapptr = &sc->sc_regs->scsi_int_map; 257 intrmapptr < &sc->sc_regs->ue_int_map; 258 intrmapptr++) 259 printf("%p: %llx\n", intrmapptr, 260 (unsigned long long)*intrmapptr); 261 262 printf("\tintmap:pci\n"); 263 for (intrmapptr = &sc->sc_regs->pcia_slot0_int; 264 intrmapptr <= &sc->sc_regs->pcib_slot3_int; 265 intrmapptr++) 266 printf("%p: %llx\n", intrmapptr, 267 (unsigned long long)*intrmapptr); 268 269 printf("\tintmap:ffb\n"); 270 for (intrmapptr = &sc->sc_regs->ffb0_int_map; 271 intrmapptr <= &sc->sc_regs->ffb1_int_map; 272 intrmapptr++) 273 printf("%p: %llx\n", intrmapptr, 274 (unsigned long long)*intrmapptr); 275 } 276 #endif 277 278 /* 279 * SUNW,psycho initialisation .. 280 * - find the per-psycho registers 281 * - figure out the IGN. 282 * - find our partner psycho 283 * - configure ourselves 284 * - bus range, bus, 285 * - get interrupt-map and interrupt-map-mask 286 * - setup the chipsets. 287 * - if we're the first of the pair, initialise the IOMMU, otherwise 288 * just copy it's tags and addresses. 289 */ 290 static void 291 psycho_attach(device_t parent, device_t self, void *aux) 292 { 293 struct psycho_softc *sc = device_private(self); 294 struct psycho_softc *osc = NULL; 295 struct psycho_pbm *pp; 296 struct pcibus_attach_args pba; 297 struct mainbus_attach_args *ma = aux; 298 struct psycho_ranges *pr; 299 prop_dictionary_t dict; 300 bus_space_handle_t bh; 301 uint64_t csr, mem_base; 302 int psycho_br[2], n, i; 303 bus_space_handle_t pci_ctl; 304 char *model = prom_getpropstring(ma->ma_node, "model"); 305 extern char machine_model[]; 306 307 aprint_normal("\n"); 308 309 sc->sc_dev = self; 310 sc->sc_node = ma->ma_node; 311 sc->sc_bustag = ma->ma_bustag; 312 sc->sc_dmatag = ma->ma_dmatag; 313 sc->sc_last_stick = 0; 314 315 if (psycho0 == NULL) 316 psycho0 = sc; 317 DPRINTF(PDB_STICK, ("init psycho0 %lx\n", (long)sc)); 318 /* 319 * Identify the device. 320 */ 321 for (i=0; psycho_names[i].p_name; i++) 322 if (strcmp(model, psycho_names[i].p_name) == 0) { 323 sc->sc_mode = psycho_names[i].p_type; 324 goto found; 325 } 326 327 model = prom_getpropstring(ma->ma_node, "compatible"); 328 for (i=0; psycho_names[i].p_name; i++) 329 if (strcmp(model, psycho_names[i].p_name) == 0) { 330 sc->sc_mode = psycho_names[i].p_type; 331 goto found; 332 } 333 334 panic("unknown psycho model %s", model); 335 found: 336 337 /* 338 * The psycho gets three register banks: 339 * (0) per-PBM configuration and status registers 340 * (1) per-PBM PCI configuration space, containing only the 341 * PBM 256-byte PCI header 342 * (2) the shared psycho configuration registers (struct psychoreg) 343 */ 344 345 /* Register layouts are different. stuupid. */ 346 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) { 347 sc->sc_basepaddr = (paddr_t)ma->ma_reg[2].ur_paddr; 348 349 if (ma->ma_naddress > 2) { 350 sparc_promaddr_to_handle(sc->sc_bustag, 351 ma->ma_address[2], &sc->sc_bh); 352 sparc_promaddr_to_handle(sc->sc_bustag, 353 ma->ma_address[0], &pci_ctl); 354 355 sc->sc_regs = (struct psychoreg *) 356 bus_space_vaddr(sc->sc_bustag, sc->sc_bh); 357 } else if (ma->ma_nreg > 2) { 358 359 /* We need to map this in ourselves. */ 360 if (bus_space_map(sc->sc_bustag, 361 ma->ma_reg[2].ur_paddr, 362 ma->ma_reg[2].ur_len, BUS_SPACE_MAP_LINEAR, 363 &sc->sc_bh)) 364 panic("psycho_attach: cannot map regs"); 365 sc->sc_regs = (struct psychoreg *) 366 bus_space_vaddr(sc->sc_bustag, sc->sc_bh); 367 368 if (bus_space_map(sc->sc_bustag, 369 ma->ma_reg[0].ur_paddr, 370 ma->ma_reg[0].ur_len, BUS_SPACE_MAP_LINEAR, 371 &pci_ctl)) 372 panic("psycho_attach: cannot map ctl"); 373 } else 374 panic("psycho_attach: %d not enough registers", 375 ma->ma_nreg); 376 377 } else { 378 sc->sc_basepaddr = (paddr_t)ma->ma_reg[0].ur_paddr; 379 380 if (ma->ma_naddress) { 381 sparc_promaddr_to_handle(sc->sc_bustag, 382 ma->ma_address[0], &sc->sc_bh); 383 sc->sc_regs = (struct psychoreg *) 384 bus_space_vaddr(sc->sc_bustag, sc->sc_bh); 385 386 bus_space_subregion(sc->sc_bustag, sc->sc_bh, 387 offsetof(struct psychoreg, psy_pcictl), 388 sizeof(struct pci_ctl), &pci_ctl); 389 } else if (ma->ma_nreg) { 390 391 /* We need to map this in ourselves. */ 392 if (bus_space_map(sc->sc_bustag, 393 ma->ma_reg[0].ur_paddr, 394 ma->ma_reg[0].ur_len, BUS_SPACE_MAP_LINEAR, 395 &sc->sc_bh)) 396 panic("psycho_attach: cannot map regs"); 397 sc->sc_regs = (struct psychoreg *) 398 bus_space_vaddr(sc->sc_bustag, sc->sc_bh); 399 400 bus_space_subregion(sc->sc_bustag, sc->sc_bh, 401 offsetof(struct psychoreg, psy_pcictl), 402 sizeof(struct pci_ctl), &pci_ctl); 403 } else 404 panic("psycho_attach: %d not enough registers", 405 ma->ma_nreg); 406 } 407 408 csr = bus_space_read_8(sc->sc_bustag, sc->sc_bh, 409 offsetof(struct psychoreg, psy_csr)); 410 sc->sc_ign = 0x7c0; /* APB IGN is always 0x7c */ 411 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) 412 sc->sc_ign = PSYCHO_GCSR_IGN(csr) << 6; 413 414 aprint_normal_dev(self, "%s: impl %d, version %d: ign %x ", 415 model, PSYCHO_GCSR_IMPL(csr), PSYCHO_GCSR_VERS(csr), 416 sc->sc_ign); 417 /* 418 * Match other psycho's that are already configured against 419 * the base physical address. This will be the same for a 420 * pair of devices that share register space. 421 */ 422 for (n = 0; n < psycho_cd.cd_ndevs; n++) { 423 424 struct psycho_softc *asc = device_lookup_private(&psycho_cd, n); 425 426 if (asc == NULL || asc == sc) 427 /* This entry is not there or it is me */ 428 continue; 429 430 if (asc->sc_basepaddr != sc->sc_basepaddr) 431 /* This is an unrelated psycho */ 432 continue; 433 434 /* Found partner */ 435 osc = asc; 436 break; 437 } 438 439 440 /* Oh, dear. OK, lets get started */ 441 442 /* 443 * Setup the PCI control register 444 */ 445 csr = bus_space_read_8(sc->sc_bustag, pci_ctl, 446 offsetof(struct pci_ctl, pci_csr)); 447 csr |= PCICTL_MRLM | 448 PCICTL_ARB_PARK | 449 PCICTL_ERRINTEN | 450 PCICTL_4ENABLE; 451 csr &= ~(PCICTL_SERR | 452 PCICTL_CPU_PRIO | 453 PCICTL_ARB_PRIO | 454 PCICTL_RTRYWAIT); 455 bus_space_write_8(sc->sc_bustag, pci_ctl, 456 offsetof(struct pci_ctl, pci_csr), csr); 457 458 459 /* 460 * Allocate our psycho_pbm 461 */ 462 pp = sc->sc_psycho_this = malloc(sizeof *pp, M_DEVBUF, 463 M_NOWAIT | M_ZERO); 464 if (pp == NULL) 465 panic("could not allocate psycho pbm"); 466 467 pp->pp_sc = sc; 468 469 /* grab the psycho ranges */ 470 psycho_get_ranges(sc->sc_node, &pp->pp_range, &pp->pp_nrange); 471 472 /* get the bus-range for the psycho */ 473 psycho_get_bus_range(sc->sc_node, psycho_br); 474 475 pba.pba_bus = psycho_br[0]; 476 pba.pba_bridgetag = NULL; 477 478 aprint_normal("bus range %u to %u", psycho_br[0], psycho_br[1]); 479 aprint_normal("; PCI bus %d", psycho_br[0]); 480 481 pp->pp_pcictl = pci_ctl; 482 483 /* allocate our tags */ 484 pp->pp_memt = psycho_alloc_mem_tag(pp); 485 pp->pp_iot = psycho_alloc_io_tag(pp); 486 pp->pp_dmat = psycho_alloc_dma_tag(pp); 487 pp->pp_flags = (pp->pp_memt ? PCI_FLAGS_MEM_OKAY : 0) | 488 (pp->pp_iot ? PCI_FLAGS_IO_OKAY : 0); 489 490 /* allocate a chipset for this */ 491 pp->pp_pc = psycho_alloc_chipset(pp, sc->sc_node, &_sparc_pci_chipset); 492 pp->pp_pc->spc_busmax = psycho_br[1]; 493 494 switch((ma->ma_reg[0].ur_paddr) & 0xf000) { 495 case 0x2000: 496 pp->pp_id = PSYCHO_PBM_A; 497 break; 498 case 0x4000: 499 pp->pp_id = PSYCHO_PBM_B; 500 break; 501 } 502 503 aprint_normal("\n"); 504 505 /* allocate extents for free bus space */ 506 pp->pp_exmem = psycho_alloc_extent(pp, sc->sc_node, 0x02, "psycho mem"); 507 pp->pp_exio = psycho_alloc_extent(pp, sc->sc_node, 0x01, "psycho io"); 508 509 #ifdef DEBUG 510 if (psycho_debug & PDB_INTR) 511 psycho_dump_intmap(sc); 512 #endif 513 514 /* 515 * And finally, if we're a sabre or the first of a pair of psycho's to 516 * arrive here, start up the IOMMU and get a config space tag. 517 */ 518 if (osc == NULL) { 519 uint64_t timeo; 520 521 /* 522 * Establish handlers for interesting interrupts.... 523 * 524 * XXX We need to remember these and remove this to support 525 * hotplug on the UPA/FHC bus. 526 * 527 * XXX Not all controllers have these, but installing them 528 * is better than trying to sort through this mess. 529 */ 530 psycho_set_intr(sc, 15, psycho_ue, 531 &sc->sc_regs->ue_int_map, 532 &sc->sc_regs->ue_clr_int); 533 psycho_set_intr(sc, 1, psycho_ce, 534 &sc->sc_regs->ce_int_map, 535 &sc->sc_regs->ce_clr_int); 536 psycho_set_intr(sc, 15, psycho_bus_a, 537 &sc->sc_regs->pciaerr_int_map, 538 &sc->sc_regs->pciaerr_clr_int); 539 /* 540 * Netra X1 may hang when the powerfail interrupt is enabled. 541 */ 542 if (strcmp(machine_model, "SUNW,UltraAX-i2") != 0) { 543 psycho_set_intr(sc, 15, psycho_powerfail, 544 &sc->sc_regs->power_int_map, 545 &sc->sc_regs->power_clr_int); 546 psycho_register_power_button(sc); 547 } 548 if (sc->sc_mode != PSYCHO_MODE_SABRE) { 549 /* sabre doesn't have these interrupts */ 550 psycho_set_intr(sc, 15, psycho_bus_b, 551 &sc->sc_regs->pciberr_int_map, 552 &sc->sc_regs->pciberr_clr_int); 553 psycho_set_intr(sc, 1, psycho_wakeup, 554 &sc->sc_regs->pwrmgt_int_map, 555 &sc->sc_regs->pwrmgt_clr_int); 556 } 557 558 /* 559 * Apparently a number of machines with psycho and psycho+ 560 * controllers have interrupt latency issues. We'll try 561 * setting the interrupt retry timeout to 0xff which gives us 562 * a retry of 3-6 usec (which is what sysio is set to) for the 563 * moment, which seems to help alleviate this problem. 564 */ 565 timeo = sc->sc_regs->intr_retry_timer; 566 if (timeo > 0xfff) { 567 #ifdef DEBUG 568 printf("decreasing interrupt retry timeout " 569 "from %lx to 0xff\n", (long)timeo); 570 #endif 571 sc->sc_regs->intr_retry_timer = 0xff; 572 } 573 574 /* 575 * Allocate bus node, this contains a prom node per bus. 576 */ 577 pp->pp_pc->spc_busnode = 578 malloc(sizeof(*pp->pp_pc->spc_busnode), M_DEVBUF, 579 M_NOWAIT | M_ZERO); 580 if (pp->pp_pc->spc_busnode == NULL) 581 panic("psycho_attach: malloc busnode"); 582 583 /* 584 * Setup IOMMU and PCI configuration if we're the first 585 * of a pair of psycho's to arrive here. 586 * 587 * We should calculate a TSB size based on amount of RAM 588 * and number of bus controllers and number an type of 589 * child devices. 590 * 591 * For the moment, 32KB should be more than enough. 592 */ 593 sc->sc_is = malloc(sizeof(struct iommu_state), 594 M_DEVBUF, M_NOWAIT); 595 if (sc->sc_is == NULL) 596 panic("psycho_attach: malloc iommu_state"); 597 598 /* Point the strbuf_ctl at the iommu_state */ 599 pp->pp_sb.sb_is = sc->sc_is; 600 601 sc->sc_is->is_sb[0] = sc->sc_is->is_sb[1] = NULL; 602 if (prom_getproplen(sc->sc_node, "no-streaming-cache") < 0) { 603 struct strbuf_ctl *sb = &pp->pp_sb; 604 vaddr_t va = (vaddr_t)&pp->pp_flush[0x40]; 605 606 /* 607 * Initialize the strbuf_ctl. 608 * 609 * The flush sync buffer must be 64-byte aligned. 610 */ 611 sb->sb_flush = (void *)(va & ~0x3f); 612 613 bus_space_subregion(sc->sc_bustag, pci_ctl, 614 offsetof(struct pci_ctl, pci_strbuf), 615 sizeof (struct iommu_strbuf), &sb->sb_sb); 616 617 /* Point our iommu at the strbuf_ctl */ 618 sc->sc_is->is_sb[0] = sb; 619 } 620 621 psycho_iommu_init(sc, 2); 622 623 sc->sc_configtag = psycho_alloc_config_tag(sc->sc_psycho_this); 624 625 /* 626 * XXX This is a really ugly hack because PCI config space 627 * is explicitly handled with unmapped accesses. 628 */ 629 i = sc->sc_bustag->type; 630 sc->sc_bustag->type = PCI_CONFIG_BUS_SPACE; 631 if (bus_space_map(sc->sc_bustag, sc->sc_basepaddr + 0x01000000, 632 0x01000000, 0, &bh)) 633 panic("could not map psycho PCI configuration space"); 634 sc->sc_bustag->type = i; 635 sc->sc_configaddr = bh; 636 } else { 637 /* Share bus numbers with the pair of mine */ 638 pp->pp_pc->spc_busnode = 639 osc->sc_psycho_this->pp_pc->spc_busnode; 640 641 /* Just copy IOMMU state, config tag and address */ 642 sc->sc_is = osc->sc_is; 643 sc->sc_configtag = osc->sc_configtag; 644 sc->sc_configaddr = osc->sc_configaddr; 645 646 /* Point the strbuf_ctl at the iommu_state */ 647 pp->pp_sb.sb_is = sc->sc_is; 648 649 if (prom_getproplen(sc->sc_node, "no-streaming-cache") < 0) { 650 struct strbuf_ctl *sb = &pp->pp_sb; 651 vaddr_t va = (vaddr_t)&pp->pp_flush[0x40]; 652 653 /* 654 * Initialize the strbuf_ctl. 655 * 656 * The flush sync buffer must be 64-byte aligned. 657 */ 658 sb->sb_flush = (void *)(va & ~0x3f); 659 660 bus_space_subregion(sc->sc_bustag, pci_ctl, 661 offsetof(struct pci_ctl, pci_strbuf), 662 sizeof (struct iommu_strbuf), &sb->sb_sb); 663 664 /* Point our iommu at the strbuf_ctl */ 665 sc->sc_is->is_sb[1] = sb; 666 } 667 iommu_reset(sc->sc_is); 668 } 669 670 dict = device_properties(self); 671 pr = get_psychorange(pp, 2); /* memory range */ 672 #ifdef DEBUG 673 printf("memory range: %08x %08x\n", pr->phys_hi, pr->phys_lo); 674 #endif 675 mem_base = ((uint64_t)pr->phys_hi) << 32 | pr->phys_lo; 676 prop_dictionary_set_uint64(dict, "mem_base", mem_base); 677 678 /* 679 * attach the pci.. note we pass PCI A tags, etc., for the sabre here. 680 */ 681 pba.pba_flags = sc->sc_psycho_this->pp_flags; 682 pba.pba_dmat = sc->sc_psycho_this->pp_dmat; 683 pba.pba_dmat64 = NULL; 684 pba.pba_iot = sc->sc_psycho_this->pp_iot; 685 pba.pba_memt = sc->sc_psycho_this->pp_memt; 686 pba.pba_pc = pp->pp_pc; 687 688 config_found_ia(self, "pcibus", &pba, psycho_print); 689 } 690 691 static int 692 psycho_print(void *aux, const char *p) 693 { 694 695 if (p == NULL) 696 return (UNCONF); 697 return (QUIET); 698 } 699 700 static void 701 psycho_set_intr(struct psycho_softc *sc, int ipl, void *handler, 702 uint64_t *mapper, uint64_t *clearer) 703 { 704 struct intrhand *ih; 705 706 ih = (struct intrhand *)malloc(sizeof(struct intrhand), 707 M_DEVBUF, M_NOWAIT); 708 ih->ih_arg = sc; 709 ih->ih_map = mapper; 710 ih->ih_clr = clearer; 711 ih->ih_fun = handler; 712 ih->ih_pil = ipl; 713 ih->ih_number = INTVEC(*(ih->ih_map)); 714 ih->ih_pending = 0; 715 intr_establish(ipl, ipl != IPL_VM, ih); 716 *(ih->ih_map) |= INTMAP_V|(CPU_UPAID << INTMAP_TID_SHIFT); 717 } 718 719 /* 720 * power button handlers 721 */ 722 static void 723 psycho_register_power_button(struct psycho_softc *sc) 724 { 725 sysmon_task_queue_init(); 726 727 sc->sc_powerpressed = 0; 728 sc->sc_smcontext = malloc(sizeof(struct sysmon_pswitch), M_DEVBUF, 0); 729 if (!sc->sc_smcontext) { 730 aprint_error_dev(sc->sc_dev, "could not allocate power button context\n"); 731 return; 732 } 733 memset(sc->sc_smcontext, 0, sizeof(struct sysmon_pswitch)); 734 sc->sc_smcontext->smpsw_name = device_xname(sc->sc_dev); 735 sc->sc_smcontext->smpsw_type = PSWITCH_TYPE_POWER; 736 if (sysmon_pswitch_register(sc->sc_smcontext) != 0) 737 aprint_error_dev(sc->sc_dev, "unable to register power button with sysmon\n"); 738 } 739 740 static void 741 psycho_power_button_pressed(void *arg) 742 { 743 struct psycho_softc *sc = arg; 744 745 sysmon_pswitch_event(sc->sc_smcontext, PSWITCH_EVENT_PRESSED); 746 sc->sc_powerpressed = 0; 747 } 748 749 /* 750 * PCI bus support 751 */ 752 753 /* 754 * allocate a PCI chipset tag and set it's cookie. 755 */ 756 static pci_chipset_tag_t 757 psycho_alloc_chipset(struct psycho_pbm *pp, int node, pci_chipset_tag_t pc) 758 { 759 pci_chipset_tag_t npc; 760 761 npc = malloc(sizeof *npc, M_DEVBUF, M_NOWAIT); 762 if (npc == NULL) 763 panic("could not allocate pci_chipset_tag_t"); 764 memcpy(npc, pc, sizeof *pc); 765 npc->cookie = pp; 766 npc->rootnode = node; 767 npc->spc_conf_read = psycho_pci_conf_read; 768 npc->spc_conf_write = psycho_pci_conf_write; 769 npc->spc_intr_map = NULL; 770 npc->spc_intr_establish = psycho_pci_intr_establish; 771 npc->spc_find_ino = psycho_pci_find_ino; 772 773 return (npc); 774 } 775 776 /* 777 * create extent for free bus space, then allocate assigned regions. 778 */ 779 static struct extent * 780 psycho_alloc_extent(struct psycho_pbm *pp, int node, int ss, const char *name) 781 { 782 struct psycho_registers *pa = NULL; 783 struct psycho_ranges *pr; 784 struct extent *ex; 785 bus_addr_t baddr, addr; 786 bus_size_t bsize, size; 787 int i, num; 788 789 /* get bus space size */ 790 pr = get_psychorange(pp, ss); 791 if (pr == NULL) { 792 printf("psycho_alloc_extent: get_psychorange failed\n"); 793 return NULL; 794 } 795 baddr = 0x00000000; 796 bsize = BUS_ADDR(pr->size_hi, pr->size_lo); 797 798 /* get available lists */ 799 num = 0; 800 if (prom_getprop(node, "available", sizeof(*pa), &num, &pa)) { 801 printf("psycho_alloc_extent: no \"available\" property\n"); 802 return NULL; 803 } 804 805 /* create extent */ 806 ex = extent_create(name, baddr, bsize - baddr - 1, 0, 0, EX_NOWAIT); 807 if (ex == NULL) { 808 printf("psycho_alloc_extent: extent_create failed\n"); 809 goto ret; 810 } 811 812 /* allocate assigned regions */ 813 for (i = 0; i < num; i++) 814 if (((pa[i].phys_hi >> 24) & 0x03) == ss) { 815 /* allocate bus space */ 816 addr = BUS_ADDR(pa[i].phys_mid, pa[i].phys_lo); 817 size = BUS_ADDR(pa[i].size_hi, pa[i].size_lo); 818 if (extent_alloc_region(ex, baddr, addr - baddr, 819 EX_NOWAIT)) { 820 printf("psycho_alloc_extent: " 821 "extent_alloc_region %" PRIx64 "-%" 822 PRIx64 " failed\n", baddr, addr); 823 extent_destroy(ex); 824 ex = NULL; 825 goto ret; 826 } 827 baddr = addr + size; 828 } 829 /* allocate left region if available */ 830 if (baddr < bsize) 831 if (extent_alloc_region(ex, baddr, bsize - baddr, EX_NOWAIT)) { 832 printf("psycho_alloc_extent: extent_alloc_region %" 833 PRIx64 "-%" PRIx64 " failed\n", baddr, bsize); 834 extent_destroy(ex); 835 ex = NULL; 836 goto ret; 837 } 838 839 #ifdef DEBUG 840 /* print extent */ 841 extent_print(ex); 842 #endif 843 844 ret: 845 /* return extent */ 846 free(pa, M_DEVBUF); 847 return ex; 848 } 849 850 /* 851 * grovel the OBP for various psycho properties 852 */ 853 static void 854 psycho_get_bus_range(int node, int *brp) 855 { 856 int n, error; 857 858 n = 2; 859 error = prom_getprop(node, "bus-range", sizeof(*brp), &n, &brp); 860 if (error) 861 panic("could not get psycho bus-range, error %d", error); 862 if (n != 2) 863 panic("broken psycho bus-range"); 864 DPRINTF(PDB_PROM, ("psycho debug: got `bus-range' for node %08x: %u - %u\n", 865 node, brp[0], brp[1])); 866 } 867 868 static void 869 psycho_get_ranges(int node, struct psycho_ranges **rp, int *np) 870 { 871 872 if (prom_getprop(node, "ranges", sizeof(**rp), np, rp)) 873 panic("could not get psycho ranges"); 874 DPRINTF(PDB_PROM, ("psycho debug: got `ranges' for node %08x: %d entries\n", node, *np)); 875 } 876 877 /* 878 * Interrupt handlers. 879 */ 880 881 static int 882 psycho_ue(void *arg) 883 { 884 struct psycho_softc *sc = (struct psycho_softc *)arg; 885 struct psychoreg *regs = sc->sc_regs; 886 struct iommu_state *is = sc->sc_is; 887 uint64_t afsr = regs->psy_ue_afsr; 888 uint64_t afar = regs->psy_ue_afar; 889 psize_t size = PAGE_SIZE << is->is_tsbsize; 890 char bits[128]; 891 892 /* 893 * It's uncorrectable. Dump the regs and panic. 894 */ 895 snprintb(bits, sizeof(bits), PSYCHO_UE_AFSR_BITS, afsr); 896 aprint_error_dev(sc->sc_dev, 897 "uncorrectable DMA error AFAR %" PRIx64 " AFSR %s\n", afar, bits); 898 899 /* Sometimes the AFAR points to an IOTSB entry */ 900 if (afar >= is->is_ptsb && afar < is->is_ptsb + size) { 901 aprint_error_dev(sc->sc_dev, 902 "IOVA %" PRIx64 " IOTTE %" PRIx64 "\n", 903 (afar - is->is_ptsb) / sizeof(is->is_tsb[0]) * PAGE_SIZE 904 + is->is_dvmabase, ldxa(afar, ASI_PHYS_CACHED)); 905 } 906 #ifdef DDB 907 Debugger(); 908 #endif 909 regs->psy_ue_afar = 0; 910 regs->psy_ue_afsr = 0; 911 return (1); 912 } 913 914 static int 915 psycho_ce(void *arg) 916 { 917 struct psycho_softc *sc = (struct psycho_softc *)arg; 918 struct psychoreg *regs = sc->sc_regs; 919 920 /* 921 * It's correctable. Dump the regs and continue. 922 */ 923 aprint_error_dev(sc->sc_dev, 924 "correctable DMA error AFAR %" PRIx64 " AFSR %" PRIx64 "\n", 925 regs->psy_ce_afar, regs->psy_ce_afsr); 926 return (1); 927 } 928 929 static int 930 psycho_bus_a(void *arg) 931 { 932 struct psycho_softc *sc = (struct psycho_softc *)arg; 933 struct psychoreg *regs = sc->sc_regs; 934 935 /* 936 * It's uncorrectable. Dump the regs and panic. 937 */ 938 939 panic("%s: PCI bus A error AFAR %" PRIx64 " AFSR %" PRIx64, 940 device_xname(sc->sc_dev), 941 regs->psy_pcictl[0].pci_afar, regs->psy_pcictl[0].pci_afsr); 942 return (1); 943 } 944 945 static int 946 psycho_bus_b(void *arg) 947 { 948 struct psycho_softc *sc = (struct psycho_softc *)arg; 949 struct psychoreg *regs = sc->sc_regs; 950 951 /* 952 * It's uncorrectable. Dump the regs and panic. 953 */ 954 955 panic("%s: PCI bus B error AFAR %" PRIx64 " AFSR %" PRIx64, 956 device_xname(sc->sc_dev), 957 regs->psy_pcictl[0].pci_afar, regs->psy_pcictl[0].pci_afsr); 958 return (1); 959 } 960 961 static int 962 psycho_powerfail(void *arg) 963 { 964 struct psycho_softc *sc = (struct psycho_softc *)arg; 965 966 /* 967 * We lost power. Queue a callback with thread context to 968 * handle all the real work. 969 */ 970 if (sc->sc_powerpressed == 0 && sc->sc_smcontext != NULL) { 971 sc->sc_powerpressed = 1; 972 sysmon_task_queue_sched(0, psycho_power_button_pressed, sc); 973 } 974 return (1); 975 } 976 977 static 978 int psycho_wakeup(void *arg) 979 { 980 struct psycho_softc *sc = (struct psycho_softc *)arg; 981 982 /* 983 * Gee, we don't really have a framework to deal with this 984 * properly. 985 */ 986 aprint_error_dev(sc->sc_dev, "power management wakeup\n"); 987 return (1); 988 } 989 990 991 /* 992 * initialise the IOMMU.. 993 */ 994 void 995 psycho_iommu_init(struct psycho_softc *sc, int tsbsize) 996 { 997 char *name; 998 struct iommu_state *is = sc->sc_is; 999 uint32_t iobase = -1; 1000 int *vdma = NULL; 1001 int nitem; 1002 1003 /* punch in our copies */ 1004 is->is_bustag = sc->sc_bustag; 1005 bus_space_subregion(sc->sc_bustag, sc->sc_bh, 1006 offsetof(struct psychoreg, psy_iommu), 1007 sizeof (struct iommureg), 1008 &is->is_iommu); 1009 1010 /* 1011 * Separate the men from the boys. Get the `virtual-dma' 1012 * property for sabre and use that to make sure the damn 1013 * iommu works. 1014 * 1015 * We could query the `#virtual-dma-size-cells' and 1016 * `#virtual-dma-addr-cells' and DTRT, but I'm lazy. 1017 */ 1018 nitem = 0; 1019 if (!prom_getprop(sc->sc_node, "virtual-dma", sizeof(vdma), &nitem, 1020 &vdma)) { 1021 /* Damn. Gotta use these values. */ 1022 iobase = vdma[0]; 1023 #define TSBCASE(x) case 1<<((x)+23): tsbsize = (x); break 1024 switch (vdma[1]) { 1025 TSBCASE(1); TSBCASE(2); TSBCASE(3); 1026 TSBCASE(4); TSBCASE(5); TSBCASE(6); 1027 default: 1028 printf("bogus tsb size %x, using 7\n", vdma[1]); 1029 TSBCASE(7); 1030 } 1031 #undef TSBCASE 1032 } 1033 1034 /* give us a nice name.. */ 1035 name = (char *)malloc(32, M_DEVBUF, M_NOWAIT); 1036 if (name == 0) 1037 panic("couldn't malloc iommu name"); 1038 snprintf(name, 32, "%s dvma", device_xname(sc->sc_dev)); 1039 1040 iommu_init(name, is, tsbsize, iobase); 1041 } 1042 1043 /* 1044 * below here is bus space and bus DMA support 1045 */ 1046 bus_space_tag_t 1047 psycho_alloc_bus_tag(struct psycho_pbm *pp, int type) 1048 { 1049 struct psycho_softc *sc = pp->pp_sc; 1050 bus_space_tag_t bt; 1051 1052 bt = (bus_space_tag_t) malloc(sizeof(struct sparc_bus_space_tag), 1053 M_DEVBUF, M_NOWAIT | M_ZERO); 1054 if (bt == NULL) 1055 panic("could not allocate psycho bus tag"); 1056 1057 bt->cookie = pp; 1058 bt->parent = sc->sc_bustag; 1059 bt->type = type; 1060 bt->sparc_bus_map = _psycho_bus_map; 1061 bt->sparc_bus_mmap = psycho_bus_mmap; 1062 bt->sparc_intr_establish = psycho_intr_establish; 1063 return (bt); 1064 } 1065 1066 bus_dma_tag_t 1067 psycho_alloc_dma_tag(struct psycho_pbm *pp) 1068 { 1069 struct psycho_softc *sc = pp->pp_sc; 1070 bus_dma_tag_t dt, pdt = sc->sc_dmatag; 1071 1072 dt = (bus_dma_tag_t) 1073 malloc(sizeof(struct sparc_bus_dma_tag), M_DEVBUF, M_NOWAIT); 1074 if (dt == NULL) 1075 panic("could not allocate psycho DMA tag"); 1076 1077 memset(dt, 0, sizeof *dt); 1078 dt->_cookie = pp; 1079 dt->_parent = pdt; 1080 #define PCOPY(x) dt->x = pdt->x 1081 dt->_dmamap_create = psycho_dmamap_create; 1082 PCOPY(_dmamap_destroy); 1083 dt->_dmamap_load = iommu_dvmamap_load; 1084 PCOPY(_dmamap_load_mbuf); 1085 PCOPY(_dmamap_load_uio); 1086 dt->_dmamap_load_raw = iommu_dvmamap_load_raw; 1087 dt->_dmamap_unload = iommu_dvmamap_unload; 1088 if (sc->sc_mode == PSYCHO_MODE_SABRE) 1089 dt->_dmamap_sync = psycho_sabre_dmamap_sync; 1090 else 1091 dt->_dmamap_sync = iommu_dvmamap_sync; 1092 dt->_dmamem_alloc = iommu_dvmamem_alloc; 1093 dt->_dmamem_free = iommu_dvmamem_free; 1094 dt->_dmamem_map = iommu_dvmamem_map; 1095 dt->_dmamem_unmap = iommu_dvmamem_unmap; 1096 PCOPY(_dmamem_mmap); 1097 #undef PCOPY 1098 return (dt); 1099 } 1100 1101 /* 1102 * bus space support. <sparc64/dev/psychoreg.h> has a discussion about 1103 * PCI physical addresses. 1104 */ 1105 1106 static struct psycho_ranges * 1107 get_psychorange(struct psycho_pbm *pp, int ss) 1108 { 1109 int i; 1110 1111 for (i = 0; i < pp->pp_nrange; i++) { 1112 if (((pp->pp_range[i].cspace >> 24) & 0x03) == ss) 1113 return (&pp->pp_range[i]); 1114 } 1115 /* not found */ 1116 return (NULL); 1117 } 1118 1119 static int 1120 _psycho_bus_map(bus_space_tag_t t, bus_addr_t offset, bus_size_t size, 1121 int flags, vaddr_t unused, bus_space_handle_t *hp) 1122 { 1123 struct psycho_pbm *pp = t->cookie; 1124 struct psycho_softc *sc = pp->pp_sc; 1125 struct psycho_ranges *pr; 1126 bus_addr_t paddr; 1127 int ss; 1128 1129 DPRINTF(PDB_BUSMAP, 1130 ("_psycho_bus_map: type %d off %qx sz %qx flags %d", 1131 t->type, (unsigned long long)offset, 1132 (unsigned long long)size, flags)); 1133 1134 ss = sparc_pci_childspace(t->type); 1135 DPRINTF(PDB_BUSMAP, (" cspace %d", ss)); 1136 1137 pr = get_psychorange(pp, ss); 1138 if (pr != NULL) { 1139 paddr = BUS_ADDR(pr->phys_hi, pr->phys_lo + offset); 1140 DPRINTF(PDB_BUSMAP, ("\n_psycho_bus_map: mapping paddr " 1141 "space %lx offset %lx paddr %qx\n", 1142 (long)ss, (long)offset, 1143 (unsigned long long)paddr)); 1144 return ((*sc->sc_bustag->sparc_bus_map)(t, paddr, size, 1145 flags, 0, hp)); 1146 } 1147 DPRINTF(PDB_BUSMAP, (" FAILED\n")); 1148 return (EINVAL); 1149 } 1150 1151 static paddr_t 1152 psycho_bus_mmap(bus_space_tag_t t, bus_addr_t paddr, off_t off, int prot, 1153 int flags) 1154 { 1155 bus_addr_t offset = paddr; 1156 struct psycho_pbm *pp = t->cookie; 1157 struct psycho_softc *sc = pp->pp_sc; 1158 struct psycho_ranges *pr; 1159 int ss; 1160 1161 ss = sparc_pci_childspace(t->type); 1162 1163 DPRINTF(PDB_BUSMAP, ("_psycho_bus_mmap: prot %x flags %d pa %qx\n", 1164 prot, flags, (unsigned long long)paddr)); 1165 1166 pr = get_psychorange(pp, ss); 1167 if (pr != NULL) { 1168 paddr = BUS_ADDR(pr->phys_hi, pr->phys_lo + offset); 1169 DPRINTF(PDB_BUSMAP, ("\n_psycho_bus_mmap: mapping paddr " 1170 "space %lx offset %lx paddr %qx\n", 1171 (long)ss, (long)offset, 1172 (unsigned long long)paddr)); 1173 return (bus_space_mmap(sc->sc_bustag, paddr, off, 1174 prot, flags)); 1175 } 1176 1177 return (-1); 1178 } 1179 1180 /* 1181 * Get a PCI offset address from bus_space_handle_t. 1182 */ 1183 bus_addr_t 1184 psycho_bus_offset(bus_space_tag_t t, bus_space_handle_t *hp) 1185 { 1186 struct psycho_pbm *pp = t->cookie; 1187 struct psycho_ranges *pr; 1188 bus_addr_t addr, offset; 1189 vaddr_t va; 1190 int ss; 1191 1192 addr = hp->_ptr; 1193 ss = sparc_pci_childspace(t->type); 1194 DPRINTF(PDB_BUSMAP, ("psycho_bus_offset: type %d addr %" PRIx64 1195 " cspace %d", t->type, addr, ss)); 1196 1197 pr = get_psychorange(pp, ss); 1198 if (pr != NULL) { 1199 if (!PHYS_ASI(hp->_asi)) { 1200 va = trunc_page((vaddr_t)addr); 1201 if (pmap_extract(pmap_kernel(), va, &addr) == FALSE) { 1202 DPRINTF(PDB_BUSMAP, 1203 ("\n pmap_extract FAILED\n")); 1204 return (-1); 1205 } 1206 addr += hp->_ptr & PGOFSET; 1207 } 1208 offset = BUS_ADDR_PADDR(addr) - pr->phys_lo; 1209 DPRINTF(PDB_BUSMAP, ("\npsycho_bus_offset: paddr %" PRIx64 1210 " offset %" PRIx64 "\n", addr, offset)); 1211 return (offset); 1212 } 1213 DPRINTF(PDB_BUSMAP, ("\n FAILED\n")); 1214 return (-1); 1215 } 1216 1217 1218 /* 1219 * install an interrupt handler for a PCI device 1220 */ 1221 void * 1222 psycho_intr_establish(bus_space_tag_t t, int ihandle, int level, 1223 int (*handler)(void *), void *arg, void (*fastvec)(void) /* ignored */) 1224 { 1225 struct psycho_pbm *pp = t->cookie; 1226 struct psycho_softc *sc = pp->pp_sc; 1227 struct intrhand *ih; 1228 volatile uint64_t *intrmapptr = NULL, *intrclrptr = NULL; 1229 int64_t imap = 0; 1230 int ino; 1231 long vec = INTVEC(ihandle); 1232 1233 ih = (struct intrhand *) 1234 malloc(sizeof(struct intrhand), M_DEVBUF, M_NOWAIT); 1235 if (ih == NULL) 1236 return (NULL); 1237 1238 ih->ih_ivec = ihandle; 1239 1240 /* 1241 * Hunt through all the interrupt mapping regs to look for our 1242 * interrupt vector. 1243 * 1244 * XXX We only compare INOs rather than IGNs since the firmware may 1245 * not provide the IGN and the IGN is constant for all device on that 1246 * PCI controller. This could cause problems for the FFB/external 1247 * interrupt which has a full vector that can be set arbitrarily. 1248 */ 1249 1250 DPRINTF(PDB_INTR, ("\npsycho_intr_establish: ihandle %x vec %lx", ihandle, vec)); 1251 ino = INTINO(vec); 1252 DPRINTF(PDB_INTR, (" ino %x", ino)); 1253 1254 /* If the device didn't ask for an IPL, use the one encoded. */ 1255 if (level == IPL_NONE) level = INTLEV(vec); 1256 /* If it still has no level, print a warning and assign IPL 2 */ 1257 if (level == IPL_NONE) { 1258 printf("ERROR: no IPL, setting IPL 2.\n"); 1259 level = 2; 1260 } 1261 1262 DPRINTF(PDB_INTR, ("\npsycho: intr %lx: %p\nHunting for IRQ...\n", 1263 (long)ino, intrlev[ino])); 1264 1265 /* 1266 * First look for PCI interrupts, otherwise the PCI A slot 0 1267 * INTA# interrupt might match an unused non-PCI (obio) 1268 * interrupt. 1269 */ 1270 for (intrmapptr = &sc->sc_regs->pcia_slot0_int, 1271 intrclrptr = &sc->sc_regs->pcia0_clr_int[0]; 1272 intrmapptr <= &sc->sc_regs->pcib_slot3_int; 1273 intrmapptr++, intrclrptr += 4) { 1274 if (sc->sc_mode == PSYCHO_MODE_PSYCHO && 1275 (intrmapptr == &sc->sc_regs->pcia_slot2_int || 1276 intrmapptr == &sc->sc_regs->pcia_slot3_int)) 1277 continue; 1278 if (((*intrmapptr ^ vec) & 0x3c) == 0) { 1279 intrclrptr += vec & 0x3; 1280 goto found; 1281 } 1282 } 1283 1284 /* Now hunt thru obio. */ 1285 for (intrmapptr = &sc->sc_regs->scsi_int_map, 1286 intrclrptr = &sc->sc_regs->scsi_clr_int; 1287 intrmapptr < &sc->sc_regs->ue_int_map; 1288 intrmapptr++, intrclrptr++) { 1289 if (INTINO(*intrmapptr) == ino) 1290 goto found; 1291 } 1292 1293 /* Finally check the two FFB slots */ 1294 intrclrptr = NULL; /* XXX? */ 1295 for (intrmapptr = &sc->sc_regs->ffb0_int_map; 1296 intrmapptr <= &sc->sc_regs->ffb1_int_map; 1297 intrmapptr++) { 1298 if (INTVEC(*intrmapptr) == ino) 1299 goto found; 1300 } 1301 1302 printf("Cannot find interrupt vector %lx\n", vec); 1303 return (NULL); 1304 1305 found: 1306 /* Register the map and clear intr registers */ 1307 ih->ih_map = intrmapptr; 1308 ih->ih_clr = intrclrptr; 1309 1310 ih->ih_fun = handler; 1311 ih->ih_arg = arg; 1312 ih->ih_pil = level; 1313 ih->ih_number = ino | sc->sc_ign; 1314 ih->ih_pending = 0; 1315 1316 DPRINTF(PDB_INTR, ( 1317 "; installing handler %p arg %p with ino %u pil %u\n", 1318 handler, arg, (u_int)ino, (u_int)ih->ih_pil)); 1319 1320 intr_establish(ih->ih_pil, level != IPL_VM, ih); 1321 1322 /* 1323 * Enable the interrupt now we have the handler installed. 1324 * Read the current value as we can't change it besides the 1325 * valid bit so so make sure only this bit is changed. 1326 * 1327 * XXXX --- we really should use bus_space for this. 1328 */ 1329 if (intrmapptr) { 1330 imap = *intrmapptr; 1331 DPRINTF(PDB_INTR, ("; read intrmap = %016qx", 1332 (unsigned long long)imap)); 1333 1334 /* Enable the interrupt */ 1335 imap |= INTMAP_V|(CPU_UPAID << INTMAP_TID_SHIFT); 1336 DPRINTF(PDB_INTR, ("; addr of intrmapptr = %p", intrmapptr)); 1337 DPRINTF(PDB_INTR, ("; writing intrmap = %016qx\n", 1338 (unsigned long long)imap)); 1339 *intrmapptr = imap; 1340 DPRINTF(PDB_INTR, ("; reread intrmap = %016qx", 1341 (unsigned long long)(imap = *intrmapptr))); 1342 } 1343 if (intrclrptr) { 1344 /* set state to IDLE */ 1345 *intrclrptr = 0; 1346 } 1347 return (ih); 1348 } 1349 1350 /* 1351 * per-controller driver calls 1352 */ 1353 1354 /* assume we are mapped little-endian/side-effect */ 1355 static pcireg_t 1356 psycho_pci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg) 1357 { 1358 struct psycho_pbm *pp = pc->cookie; 1359 struct psycho_softc *sc = pp->pp_sc; 1360 struct cpu_info *ci = curcpu(); 1361 pcireg_t val = (pcireg_t)~0; 1362 int s; 1363 1364 DPRINTF(PDB_CONF, ("%s: tag %lx reg %x ", __func__, 1365 (long)tag, reg)); 1366 if (PCITAG_NODE(tag) != -1) { 1367 1368 DPRINTF(PDB_CONF, ("asi=%x addr=%qx (offset=%x) ...", 1369 sc->sc_configaddr._asi, 1370 (long long)(sc->sc_configaddr._ptr + 1371 PCITAG_OFFSET(tag) + reg), 1372 (int)PCITAG_OFFSET(tag) + reg)); 1373 1374 s = splhigh(); 1375 ci->ci_pci_probe = true; 1376 membar_Sync(); 1377 val = bus_space_read_4(sc->sc_configtag, sc->sc_configaddr, 1378 PCITAG_OFFSET(tag) + reg); 1379 membar_Sync(); 1380 if (ci->ci_pci_fault) 1381 val = (pcireg_t)~0; 1382 ci->ci_pci_probe = ci->ci_pci_fault = false; 1383 splx(s); 1384 } 1385 #ifdef DEBUG 1386 else DPRINTF(PDB_CONF, ("%s: bogus pcitag %x\n", __func__, 1387 (int)PCITAG_OFFSET(tag))); 1388 #endif 1389 DPRINTF(PDB_CONF, (" returning %08x\n", (u_int)val)); 1390 1391 return (val); 1392 } 1393 1394 static void 1395 psycho_pci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data) 1396 { 1397 struct psycho_pbm *pp = pc->cookie; 1398 struct psycho_softc *sc = pp->pp_sc; 1399 1400 DPRINTF(PDB_CONF, ("%s: tag %lx; reg %x; data %x; ", __func__, 1401 (long)PCITAG_OFFSET(tag), reg, (int)data)); 1402 DPRINTF(PDB_CONF, ("asi = %x; readaddr = %qx (offset = %x)\n", 1403 sc->sc_configaddr._asi, 1404 (long long)(sc->sc_configaddr._ptr + PCITAG_OFFSET(tag) + reg), 1405 (int)PCITAG_OFFSET(tag) + reg)); 1406 1407 /* If we don't know it, just punt it. */ 1408 if (PCITAG_NODE(tag) == -1) { 1409 DPRINTF(PDB_CONF, ("%s: bad addr", __func__)); 1410 return; 1411 } 1412 1413 bus_space_write_4(sc->sc_configtag, sc->sc_configaddr, 1414 PCITAG_OFFSET(tag) + reg, data); 1415 } 1416 1417 static void * 1418 psycho_pci_intr_establish(pci_chipset_tag_t pc, pci_intr_handle_t ih, int level, 1419 int (*func)(void *), void *arg) 1420 { 1421 void *cookie; 1422 struct psycho_pbm *pp = (struct psycho_pbm *)pc->cookie; 1423 1424 DPRINTF(PDB_INTR, ("%s: ih %lx; level %d", __func__, (u_long)ih, level)); 1425 cookie = bus_intr_establish(pp->pp_memt, ih, level, func, arg); 1426 1427 DPRINTF(PDB_INTR, ("; returning handle %p\n", cookie)); 1428 return (cookie); 1429 } 1430 1431 static int 1432 psycho_pci_find_ino(const struct pci_attach_args *pa, pci_intr_handle_t *ihp) 1433 { 1434 struct psycho_pbm *pp = pa->pa_pc->cookie; 1435 struct psycho_softc *sc = pp->pp_sc; 1436 u_int bus; 1437 u_int dev; 1438 u_int pin; 1439 1440 DPRINTF(PDB_INTMAP, ("%s: pa_tag: node %x, %d:%d:%d\n", __func__, 1441 PCITAG_NODE(pa->pa_tag), (int)PCITAG_BUS(pa->pa_tag), 1442 (int)PCITAG_DEV(pa->pa_tag), 1443 (int)PCITAG_FUN(pa->pa_tag))); 1444 DPRINTF(PDB_INTMAP, 1445 ("%s: intrswiz %d, intrpin %d, intrline %d, rawintrpin %d\n", __func__, 1446 pa->pa_intrswiz, pa->pa_intrpin, pa->pa_intrline, pa->pa_rawintrpin)); 1447 DPRINTF(PDB_INTMAP, ("%s: pa_intrtag: node %x, %d:%d:%d\n", __func__, 1448 PCITAG_NODE(pa->pa_intrtag), 1449 (int)PCITAG_BUS(pa->pa_intrtag), 1450 (int)PCITAG_DEV(pa->pa_intrtag), 1451 (int)PCITAG_FUN(pa->pa_intrtag))); 1452 1453 bus = (pp->pp_id == PSYCHO_PBM_B); 1454 /* 1455 * If we are on a ppb, use the devno on the underlying bus when forming 1456 * the ivec. 1457 */ 1458 if (pa->pa_intrswiz != 0 && PCITAG_NODE(pa->pa_intrtag) != 0) 1459 dev = PCITAG_DEV(pa->pa_intrtag); 1460 else 1461 dev = pa->pa_device; 1462 dev--; 1463 1464 if (sc->sc_mode == PSYCHO_MODE_PSYCHO && 1465 pp->pp_id == PSYCHO_PBM_B) 1466 dev--; 1467 1468 pin = pa->pa_intrpin - 1; 1469 DPRINTF(PDB_INTMAP, ("%s: mode %d, pbm %d, dev %d, pin %d\n", __func__, 1470 sc->sc_mode, pp->pp_id, dev, pin)); 1471 1472 *ihp = sc->sc_ign | ((bus << 4) & INTMAP_PCIBUS) | 1473 ((dev << 2) & INTMAP_PCISLOT) | (pin & INTMAP_PCIINT); 1474 1475 return (0); 1476 } 1477 1478 /* 1479 * hooks into the iommu dvma calls. 1480 */ 1481 static int 1482 psycho_dmamap_create(bus_dma_tag_t t, bus_size_t size, int nsegments, 1483 bus_size_t maxsegsz, bus_size_t boundary, int flags, 1484 bus_dmamap_t *dmamp) 1485 { 1486 struct psycho_pbm *pp = (struct psycho_pbm *)t->_cookie; 1487 int error; 1488 1489 error = bus_dmamap_create(t->_parent, size, nsegments, maxsegsz, 1490 boundary, flags, dmamp); 1491 if (error == 0) 1492 (*dmamp)->_dm_cookie = &pp->pp_sb; 1493 return error; 1494 } 1495 1496 /* 1497 * UltraSPARC IIi and IIe have no streaming buffers, but have PCI DMA 1498 * Write Synchronization Register (see UltraSPARC-IIi User's Manual 1499 * section 19.3.0.5). So use it to synchronize with the DMA writes. 1500 */ 1501 static void 1502 psycho_sabre_dmamap_sync(bus_dma_tag_t t, bus_dmamap_t map, bus_addr_t offset, 1503 bus_size_t len, int ops) 1504 { 1505 struct psycho_pbm *pp; 1506 struct psycho_softc *sc; 1507 1508 /* If len is 0, then there is nothing to do. */ 1509 if (len == 0) 1510 return; 1511 1512 if (ops & BUS_DMASYNC_POSTREAD) { 1513 pp = (struct psycho_pbm *)t->_cookie; 1514 sc = pp->pp_sc; 1515 bus_space_read_8(sc->sc_bustag, sc->sc_bh, 1516 offsetof(struct psychoreg, pci_dma_write_sync)); 1517 } 1518 bus_dmamap_sync(t->_parent, map, offset, len, ops); 1519 } 1520 1521 /* US-IIe STICK support */ 1522 1523 uint64_t 1524 psycho_getstick(void) 1525 { 1526 uint64_t stick; 1527 1528 stick = bus_space_read_8(psycho0->sc_bustag, psycho0->sc_bh, 1529 STICK_CNT_LOW) | 1530 (bus_space_read_8(psycho0->sc_bustag, psycho0->sc_bh, 1531 STICK_CNT_HIGH) & 0x7fffffff) << 32; 1532 return stick; 1533 } 1534 1535 void 1536 psycho_setstick(long cnt) 1537 { 1538 1539 /* 1540 * looks like we can't actually write the STICK counter, so instead we 1541 * prepare sc_last_stick for the coming interrupt setup 1542 */ 1543 #if 0 1544 bus_space_write_8(psycho0->sc_bustag, psycho0->sc_bh, 1545 STICK_CNT_HIGH, (cnt >> 32)); 1546 bus_space_write_8(psycho0->sc_bustag, psycho0->sc_bh, 1547 STICK_CNT_LOW, (uint32_t)(cnt & 0xffffffff)); 1548 #endif 1549 1550 if (cnt == 0) { 1551 bus_space_write_8(psycho0->sc_bustag, psycho0->sc_bh, 1552 STICK_CMP_HIGH, 0); 1553 bus_space_write_8(psycho0->sc_bustag, psycho0->sc_bh, 1554 STICK_CMP_LOW, 0); 1555 psycho0->sc_last_stick = 0; 1556 } 1557 1558 psycho0->sc_last_stick = psycho_getstick(); 1559 DPRINTF(PDB_STICK, ("stick: %ld\n", psycho0->sc_last_stick)); 1560 } 1561 1562 void 1563 psycho_nextstick(long diff) 1564 { 1565 uint64_t cmp, now; 1566 1567 /* 1568 * there is no way we'll ever overflow 1569 * the counter is 63 bits wide, at 12MHz that's >24000 years 1570 */ 1571 now = psycho_getstick() + 1000; 1572 cmp = psycho0->sc_last_stick; 1573 1574 while (cmp < now) 1575 cmp += diff; 1576 1577 bus_space_write_8(psycho0->sc_bustag, psycho0->sc_bh, 1578 STICK_CMP_HIGH, (cmp >> 32) & 0x7fffffff); 1579 bus_space_write_8(psycho0->sc_bustag, psycho0->sc_bh, 1580 STICK_CMP_LOW, (cmp & 0xffffffff)); 1581 1582 psycho0->sc_last_stick = cmp; 1583 } 1584
Indexes created Fri Sep 26 08:10:20 GMT 2025