psycho.c revision 1.120
1 /* $NetBSD: psycho.c,v 1.120 2014/10/18 08:33:27 snj Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000 Matthew R. Green 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * Copyright (c) 2001, 2002 Eduardo E. Horvath 31 * All rights reserved. 32 * 33 * Redistribution and use in source and binary forms, with or without 34 * modification, are permitted provided that the following conditions 35 * are met: 36 * 1. Redistributions of source code must retain the above copyright 37 * notice, this list of conditions and the following disclaimer. 38 * 2. Redistributions in binary form must reproduce the above copyright 39 * notice, this list of conditions and the following disclaimer in the 40 * documentation and/or other materials provided with the distribution. 41 * 3. The name of the author may not be used to endorse or promote products 42 * derived from this software without specific prior written permission. 43 * 44 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 45 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 46 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 47 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 48 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 49 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 50 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 51 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 52 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 53 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 54 * SUCH DAMAGE. 55 */ 56 57 #include <sys/cdefs.h> 58 __KERNEL_RCSID(0, "$NetBSD: psycho.c,v 1.120 2014/10/18 08:33:27 snj Exp $"); 59 60 #include "opt_ddb.h" 61 62 /* 63 * Support for `psycho' and `psycho+' UPA to PCI bridge and 64 * UltraSPARC IIi and IIe `sabre' PCI controllers. 65 */ 66 67 #ifdef DEBUG 68 #define PDB_PROM 0x01 69 #define PDB_BUSMAP 0x02 70 #define PDB_INTR 0x04 71 #define PDB_INTMAP 0x08 72 #define PDB_CONF 0x10 73 #define PDB_STICK 0x20 74 int psycho_debug = 0x0; 75 #define DPRINTF(l, s) do { if (psycho_debug & l) printf s; } while (0) 76 #else 77 #define DPRINTF(l, s) 78 #endif 79 80 #include <sys/param.h> 81 #include <sys/device.h> 82 #include <sys/errno.h> 83 #include <sys/extent.h> 84 #include <sys/malloc.h> 85 #include <sys/systm.h> 86 #include <sys/time.h> 87 #include <sys/reboot.h> 88 89 #include <uvm/uvm.h> 90 91 #define _SPARC_BUS_DMA_PRIVATE 92 #include <sys/bus.h> 93 #include <machine/autoconf.h> 94 #include <machine/psl.h> 95 96 #include <dev/pci/pcivar.h> 97 #include <dev/pci/pcireg.h> 98 #include <dev/sysmon/sysmon_taskq.h> 99 100 #include <sparc64/dev/iommureg.h> 101 #include <sparc64/dev/iommuvar.h> 102 #include <sparc64/dev/psychoreg.h> 103 #include <sparc64/dev/psychovar.h> 104 105 #include "ioconf.h" 106 107 static pci_chipset_tag_t psycho_alloc_chipset(struct psycho_pbm *, int, 108 pci_chipset_tag_t); 109 static struct extent *psycho_alloc_extent(struct psycho_pbm *, int, int, 110 const char *); 111 static void psycho_get_bus_range(int, int *); 112 static void psycho_fixup_bus_range(int, int *); 113 static void psycho_get_ranges(int, struct psycho_ranges **, int *); 114 static void psycho_set_intr(struct psycho_softc *, int, void *, uint64_t *, 115 uint64_t *); 116 117 /* chipset handlers */ 118 static pcireg_t psycho_pci_conf_read(pci_chipset_tag_t, pcitag_t, int); 119 static void psycho_pci_conf_write(pci_chipset_tag_t, pcitag_t, int, 120 pcireg_t); 121 static void *psycho_pci_intr_establish(pci_chipset_tag_t, 122 pci_intr_handle_t, 123 int, int (*)(void *), void *); 124 static int psycho_pci_find_ino(const struct pci_attach_args *, 125 pci_intr_handle_t *); 126 127 /* Interrupt handlers */ 128 static int psycho_ue(void *); 129 static int psycho_ce(void *); 130 static int psycho_bus_a(void *); 131 static int psycho_bus_b(void *); 132 static int psycho_powerfail(void *); 133 static int psycho_wakeup(void *); 134 135 136 /* IOMMU support */ 137 static void psycho_iommu_init(struct psycho_softc *, int); 138 139 /* 140 * bus space and bus DMA support for UltraSPARC `psycho'. note that most 141 * of the bus DMA support is provided by the iommu dvma controller. 142 */ 143 static struct psycho_ranges *get_psychorange(struct psycho_pbm *, int); 144 145 static paddr_t psycho_bus_mmap(bus_space_tag_t, bus_addr_t, off_t, int, int); 146 static int _psycho_bus_map(bus_space_tag_t, bus_addr_t, bus_size_t, int, 147 vaddr_t, bus_space_handle_t *); 148 static void *psycho_intr_establish(bus_space_tag_t, int, int, int (*)(void *), 149 void *, void(*)(void)); 150 151 static int psycho_dmamap_create(bus_dma_tag_t, bus_size_t, int, bus_size_t, 152 bus_size_t, int, bus_dmamap_t *); 153 static void psycho_sabre_dmamap_sync(bus_dma_tag_t, bus_dmamap_t, bus_addr_t, 154 bus_size_t, int); 155 156 /* base pci_chipset */ 157 extern struct sparc_pci_chipset _sparc_pci_chipset; 158 159 /* power button handlers */ 160 static void psycho_register_power_button(struct psycho_softc *sc); 161 static void psycho_power_button_pressed(void *arg); 162 163 /* 164 * autoconfiguration 165 */ 166 static int psycho_match(device_t, cfdata_t, void *); 167 static void psycho_attach(device_t, device_t, void *); 168 static int psycho_print(void *aux, const char *p); 169 170 CFATTACH_DECL_NEW(psycho, sizeof(struct psycho_softc), 171 psycho_match, psycho_attach, NULL, NULL); 172 173 /* 174 * "sabre" is the UltraSPARC IIi onboard UPA to PCI bridge. It manages a 175 * single PCI bus and does not have a streaming buffer. It often has an APB 176 * (advanced PCI bridge) connected to it, which was designed specifically for 177 * the IIi. The APB let's the IIi handle two independednt PCI buses, and 178 * appears as two "simba"'s underneath the sabre. 179 * 180 * "psycho" and "psycho+" is a dual UPA to PCI bridge. It sits on the UPA bus 181 * and manages two PCI buses. "psycho" has two 64-bit 33 MHz buses, while 182 * "psycho+" controls both a 64-bit 33 MHz and a 64-bit 66 MHz PCI bus. You 183 * will usually find a "psycho+" since I don't think the original "psycho" 184 * ever shipped, and if it did it would be in the U30. 185 * 186 * Each "psycho" PCI bus appears as a separate OFW node, but since they are 187 * both part of the same IC, they only have a single register space. As such, 188 * they need to be configured together, even though the autoconfiguration will 189 * attach them separately. 190 * 191 * On UltraIIi machines, "sabre" itself usually takes pci0, with "simba" often 192 * as pci1 and pci2, although they have been implemented with other PCI bus 193 * numbers on some machines. 194 * 195 * On UltraII machines, there can be any number of "psycho+" ICs, each 196 * providing two PCI buses. 197 * 198 * 199 * XXXX The psycho/sabre node has an `interrupts' attribute. They contain 200 * the values of the following interrupts in this order: 201 * 202 * PCI Bus Error (30) 203 * DMA UE (2e) 204 * DMA CE (2f) 205 * Power Fail (25) 206 * 207 * We really should attach handlers for each. 208 * 209 */ 210 211 #define ROM_PCI_NAME "pci" 212 213 struct psycho_names { 214 const char *p_name; 215 int p_type; 216 } psycho_names[] = { 217 { "SUNW,psycho", PSYCHO_MODE_PSYCHO }, 218 { "pci108e,8000", PSYCHO_MODE_PSYCHO }, 219 { "SUNW,sabre", PSYCHO_MODE_SABRE }, 220 { "pci108e,a000", PSYCHO_MODE_SABRE }, 221 { "pci108e,a001", PSYCHO_MODE_SABRE }, 222 { NULL, 0 } 223 }; 224 225 struct psycho_softc *psycho0 = NULL; 226 227 static int 228 psycho_match(device_t parent, cfdata_t match, void *aux) 229 { 230 struct mainbus_attach_args *ma = aux; 231 char *model = prom_getpropstring(ma->ma_node, "model"); 232 int i; 233 234 /* match on a name of "pci" and a sabre or a psycho */ 235 if (strcmp(ma->ma_name, ROM_PCI_NAME) == 0) { 236 for (i=0; psycho_names[i].p_name; i++) 237 if (strcmp(model, psycho_names[i].p_name) == 0) 238 return (1); 239 240 model = prom_getpropstring(ma->ma_node, "compatible"); 241 for (i=0; psycho_names[i].p_name; i++) 242 if (strcmp(model, psycho_names[i].p_name) == 0) 243 return (1); 244 } 245 return (0); 246 } 247 248 #ifdef DEBUG 249 static void psycho_dump_intmap(struct psycho_softc *sc); 250 static void 251 psycho_dump_intmap(struct psycho_softc *sc) 252 { 253 volatile uint64_t *intrmapptr = NULL; 254 255 printf("psycho_dump_intmap: OBIO\n"); 256 257 for (intrmapptr = &sc->sc_regs->scsi_int_map; 258 intrmapptr < &sc->sc_regs->ue_int_map; 259 intrmapptr++) 260 printf("%p: %llx\n", intrmapptr, 261 (unsigned long long)*intrmapptr); 262 263 printf("\tintmap:pci\n"); 264 for (intrmapptr = &sc->sc_regs->pcia_slot0_int; 265 intrmapptr <= &sc->sc_regs->pcib_slot3_int; 266 intrmapptr++) 267 printf("%p: %llx\n", intrmapptr, 268 (unsigned long long)*intrmapptr); 269 270 printf("\tintmap:ffb\n"); 271 for (intrmapptr = &sc->sc_regs->ffb0_int_map; 272 intrmapptr <= &sc->sc_regs->ffb1_int_map; 273 intrmapptr++) 274 printf("%p: %llx\n", intrmapptr, 275 (unsigned long long)*intrmapptr); 276 } 277 #endif 278 279 /* 280 * SUNW,psycho initialisation .. 281 * - find the per-psycho registers 282 * - figure out the IGN. 283 * - find our partner psycho 284 * - configure ourselves 285 * - bus range, bus, 286 * - get interrupt-map and interrupt-map-mask 287 * - setup the chipsets. 288 * - if we're the first of the pair, initialise the IOMMU, otherwise 289 * just copy its tags and addresses. 290 */ 291 static void 292 psycho_attach(device_t parent, device_t self, void *aux) 293 { 294 struct psycho_softc *sc = device_private(self); 295 struct psycho_softc *osc = NULL; 296 struct psycho_pbm *pp; 297 struct pcibus_attach_args pba; 298 struct mainbus_attach_args *ma = aux; 299 struct psycho_ranges *pr; 300 prop_dictionary_t dict; 301 bus_space_handle_t bh; 302 uint64_t csr, mem_base; 303 int psycho_br[2], n, i; 304 bus_space_handle_t pci_ctl; 305 char *model = prom_getpropstring(ma->ma_node, "model"); 306 307 aprint_normal("\n"); 308 309 sc->sc_dev = self; 310 sc->sc_node = ma->ma_node; 311 sc->sc_bustag = ma->ma_bustag; 312 sc->sc_dmatag = ma->ma_dmatag; 313 sc->sc_last_stick = 0; 314 315 if (psycho0 == NULL) 316 psycho0 = sc; 317 DPRINTF(PDB_STICK, ("init psycho0 %lx\n", (long)sc)); 318 /* 319 * Identify the device. 320 */ 321 for (i=0; psycho_names[i].p_name; i++) 322 if (strcmp(model, psycho_names[i].p_name) == 0) { 323 sc->sc_mode = psycho_names[i].p_type; 324 goto found; 325 } 326 327 model = prom_getpropstring(ma->ma_node, "compatible"); 328 for (i=0; psycho_names[i].p_name; i++) 329 if (strcmp(model, psycho_names[i].p_name) == 0) { 330 sc->sc_mode = psycho_names[i].p_type; 331 goto found; 332 } 333 334 panic("unknown psycho model %s", model); 335 found: 336 337 /* 338 * The psycho gets three register banks: 339 * (0) per-PBM configuration and status registers 340 * (1) per-PBM PCI configuration space, containing only the 341 * PBM 256-byte PCI header 342 * (2) the shared psycho configuration registers (struct psychoreg) 343 */ 344 345 /* Register layouts are different. stuupid. */ 346 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) { 347 sc->sc_basepaddr = (paddr_t)ma->ma_reg[2].ur_paddr; 348 349 if (ma->ma_naddress > 2) { 350 sparc_promaddr_to_handle(sc->sc_bustag, 351 ma->ma_address[2], &sc->sc_bh); 352 sparc_promaddr_to_handle(sc->sc_bustag, 353 ma->ma_address[0], &pci_ctl); 354 355 sc->sc_regs = (struct psychoreg *) 356 bus_space_vaddr(sc->sc_bustag, sc->sc_bh); 357 } else if (ma->ma_nreg > 2) { 358 359 /* We need to map this in ourselves. */ 360 if (bus_space_map(sc->sc_bustag, 361 ma->ma_reg[2].ur_paddr, 362 ma->ma_reg[2].ur_len, BUS_SPACE_MAP_LINEAR, 363 &sc->sc_bh)) 364 panic("psycho_attach: cannot map regs"); 365 sc->sc_regs = (struct psychoreg *) 366 bus_space_vaddr(sc->sc_bustag, sc->sc_bh); 367 368 if (bus_space_map(sc->sc_bustag, 369 ma->ma_reg[0].ur_paddr, 370 ma->ma_reg[0].ur_len, BUS_SPACE_MAP_LINEAR, 371 &pci_ctl)) 372 panic("psycho_attach: cannot map ctl"); 373 } else 374 panic("psycho_attach: %d not enough registers", 375 ma->ma_nreg); 376 377 } else { 378 sc->sc_basepaddr = (paddr_t)ma->ma_reg[0].ur_paddr; 379 380 if (ma->ma_naddress) { 381 sparc_promaddr_to_handle(sc->sc_bustag, 382 ma->ma_address[0], &sc->sc_bh); 383 sc->sc_regs = (struct psychoreg *) 384 bus_space_vaddr(sc->sc_bustag, sc->sc_bh); 385 386 bus_space_subregion(sc->sc_bustag, sc->sc_bh, 387 offsetof(struct psychoreg, psy_pcictl), 388 sizeof(struct pci_ctl), &pci_ctl); 389 } else if (ma->ma_nreg) { 390 391 /* We need to map this in ourselves. */ 392 if (bus_space_map(sc->sc_bustag, 393 ma->ma_reg[0].ur_paddr, 394 ma->ma_reg[0].ur_len, BUS_SPACE_MAP_LINEAR, 395 &sc->sc_bh)) 396 panic("psycho_attach: cannot map regs"); 397 sc->sc_regs = (struct psychoreg *) 398 bus_space_vaddr(sc->sc_bustag, sc->sc_bh); 399 400 bus_space_subregion(sc->sc_bustag, sc->sc_bh, 401 offsetof(struct psychoreg, psy_pcictl), 402 sizeof(struct pci_ctl), &pci_ctl); 403 } else 404 panic("psycho_attach: %d not enough registers", 405 ma->ma_nreg); 406 } 407 408 csr = bus_space_read_8(sc->sc_bustag, sc->sc_bh, 409 offsetof(struct psychoreg, psy_csr)); 410 sc->sc_ign = 0x7c0; /* APB IGN is always 0x7c */ 411 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) 412 sc->sc_ign = PSYCHO_GCSR_IGN(csr) << 6; 413 414 aprint_normal_dev(self, "%s: impl %d, version %d: ign %x ", 415 model, PSYCHO_GCSR_IMPL(csr), PSYCHO_GCSR_VERS(csr), 416 sc->sc_ign); 417 /* 418 * Match other psycho's that are already configured against 419 * the base physical address. This will be the same for a 420 * pair of devices that share register space. 421 */ 422 for (n = 0; n < psycho_cd.cd_ndevs; n++) { 423 424 struct psycho_softc *asc = device_lookup_private(&psycho_cd, n); 425 426 if (asc == NULL || asc == sc) 427 /* This entry is not there or it is me */ 428 continue; 429 430 if (asc->sc_basepaddr != sc->sc_basepaddr) 431 /* This is an unrelated psycho */ 432 continue; 433 434 /* Found partner */ 435 osc = asc; 436 break; 437 } 438 439 440 /* Oh, dear. OK, lets get started */ 441 442 /* 443 * Setup the PCI control register 444 */ 445 csr = bus_space_read_8(sc->sc_bustag, pci_ctl, 446 offsetof(struct pci_ctl, pci_csr)); 447 csr |= PCICTL_MRLM | 448 PCICTL_ARB_PARK | 449 PCICTL_ERRINTEN | 450 PCICTL_4ENABLE; 451 csr &= ~(PCICTL_SERR | 452 PCICTL_CPU_PRIO | 453 PCICTL_ARB_PRIO | 454 PCICTL_RTRYWAIT); 455 bus_space_write_8(sc->sc_bustag, pci_ctl, 456 offsetof(struct pci_ctl, pci_csr), csr); 457 458 459 /* 460 * Allocate our psycho_pbm 461 */ 462 pp = sc->sc_psycho_this = malloc(sizeof *pp, M_DEVBUF, 463 M_NOWAIT | M_ZERO); 464 if (pp == NULL) 465 panic("could not allocate psycho pbm"); 466 467 pp->pp_sc = sc; 468 469 /* grab the psycho ranges */ 470 psycho_get_ranges(sc->sc_node, &pp->pp_range, &pp->pp_nrange); 471 472 /* get the bus-range for the psycho */ 473 psycho_get_bus_range(sc->sc_node, psycho_br); 474 475 pba.pba_bus = psycho_br[0]; 476 pba.pba_bridgetag = NULL; 477 478 /* Fix up invalid 0x00-0xff bus-range, as found on SPARCle */ 479 if (psycho_br[0] == 0 && psycho_br[1] == 0xff) 480 psycho_fixup_bus_range(sc->sc_node, psycho_br); 481 482 aprint_normal("bus range %u to %u", psycho_br[0], psycho_br[1]); 483 aprint_normal("; PCI bus %d", psycho_br[0]); 484 485 pp->pp_pcictl = pci_ctl; 486 487 /* allocate our tags */ 488 pp->pp_memt = psycho_alloc_mem_tag(pp); 489 pp->pp_iot = psycho_alloc_io_tag(pp); 490 pp->pp_dmat = psycho_alloc_dma_tag(pp); 491 pp->pp_flags = (pp->pp_memt ? PCI_FLAGS_MEM_OKAY : 0) | 492 (pp->pp_iot ? PCI_FLAGS_IO_OKAY : 0); 493 494 /* allocate a chipset for this */ 495 pp->pp_pc = psycho_alloc_chipset(pp, sc->sc_node, &_sparc_pci_chipset); 496 pp->pp_pc->spc_busmax = psycho_br[1]; 497 498 switch((ma->ma_reg[0].ur_paddr) & 0xf000) { 499 case 0x2000: 500 pp->pp_id = PSYCHO_PBM_A; 501 break; 502 case 0x4000: 503 pp->pp_id = PSYCHO_PBM_B; 504 break; 505 } 506 507 aprint_normal("\n"); 508 509 /* allocate extents for free bus space */ 510 pp->pp_exmem = psycho_alloc_extent(pp, sc->sc_node, 0x02, "psycho mem"); 511 pp->pp_exio = psycho_alloc_extent(pp, sc->sc_node, 0x01, "psycho io"); 512 513 #ifdef DEBUG 514 if (psycho_debug & PDB_INTR) 515 psycho_dump_intmap(sc); 516 #endif 517 518 /* 519 * And finally, if we're a sabre or the first of a pair of psycho's to 520 * arrive here, start up the IOMMU and get a config space tag. 521 */ 522 if (osc == NULL) { 523 uint64_t timeo; 524 525 /* 526 * Establish handlers for interesting interrupts.... 527 * 528 * XXX We need to remember these and remove this to support 529 * hotplug on the UPA/FHC bus. 530 * 531 * XXX Not all controllers have these, but installing them 532 * is better than trying to sort through this mess. 533 */ 534 psycho_set_intr(sc, 15, psycho_ue, 535 &sc->sc_regs->ue_int_map, 536 &sc->sc_regs->ue_clr_int); 537 psycho_set_intr(sc, 1, psycho_ce, 538 &sc->sc_regs->ce_int_map, 539 &sc->sc_regs->ce_clr_int); 540 psycho_set_intr(sc, 15, psycho_bus_a, 541 &sc->sc_regs->pciaerr_int_map, 542 &sc->sc_regs->pciaerr_clr_int); 543 /* 544 * Netra X1 may hang when the powerfail interrupt is enabled. 545 */ 546 if (strcmp(machine_model, "SUNW,UltraAX-i2") != 0) { 547 psycho_set_intr(sc, 15, psycho_powerfail, 548 &sc->sc_regs->power_int_map, 549 &sc->sc_regs->power_clr_int); 550 psycho_register_power_button(sc); 551 } 552 if (sc->sc_mode != PSYCHO_MODE_SABRE) { 553 /* sabre doesn't have these interrupts */ 554 psycho_set_intr(sc, 15, psycho_bus_b, 555 &sc->sc_regs->pciberr_int_map, 556 &sc->sc_regs->pciberr_clr_int); 557 psycho_set_intr(sc, 1, psycho_wakeup, 558 &sc->sc_regs->pwrmgt_int_map, 559 &sc->sc_regs->pwrmgt_clr_int); 560 } 561 562 /* 563 * Apparently a number of machines with psycho and psycho+ 564 * controllers have interrupt latency issues. We'll try 565 * setting the interrupt retry timeout to 0xff which gives us 566 * a retry of 3-6 usec (which is what sysio is set to) for the 567 * moment, which seems to help alleviate this problem. 568 */ 569 timeo = sc->sc_regs->intr_retry_timer; 570 if (timeo > 0xfff) { 571 #ifdef DEBUG 572 printf("decreasing interrupt retry timeout " 573 "from %lx to 0xff\n", (long)timeo); 574 #endif 575 sc->sc_regs->intr_retry_timer = 0xff; 576 } 577 578 /* 579 * Allocate bus node, this contains a prom node per bus. 580 */ 581 pp->pp_pc->spc_busnode = 582 malloc(sizeof(*pp->pp_pc->spc_busnode), M_DEVBUF, 583 M_NOWAIT | M_ZERO); 584 if (pp->pp_pc->spc_busnode == NULL) 585 panic("psycho_attach: malloc busnode"); 586 587 /* 588 * Setup IOMMU and PCI configuration if we're the first 589 * of a pair of psycho's to arrive here. 590 * 591 * We should calculate a TSB size based on amount of RAM 592 * and number of bus controllers and number an type of 593 * child devices. 594 * 595 * For the moment, 32KB should be more than enough. 596 */ 597 sc->sc_is = malloc(sizeof(struct iommu_state), 598 M_DEVBUF, M_NOWAIT); 599 if (sc->sc_is == NULL) 600 panic("psycho_attach: malloc iommu_state"); 601 602 /* Point the strbuf_ctl at the iommu_state */ 603 pp->pp_sb.sb_is = sc->sc_is; 604 605 sc->sc_is->is_sb[0] = sc->sc_is->is_sb[1] = NULL; 606 if (prom_getproplen(sc->sc_node, "no-streaming-cache") < 0) { 607 struct strbuf_ctl *sb = &pp->pp_sb; 608 vaddr_t va = (vaddr_t)&pp->pp_flush[0x40]; 609 610 /* 611 * Initialize the strbuf_ctl. 612 * 613 * The flush sync buffer must be 64-byte aligned. 614 */ 615 sb->sb_flush = (void *)(va & ~0x3f); 616 617 bus_space_subregion(sc->sc_bustag, pci_ctl, 618 offsetof(struct pci_ctl, pci_strbuf), 619 sizeof (struct iommu_strbuf), &sb->sb_sb); 620 621 /* Point our iommu at the strbuf_ctl */ 622 sc->sc_is->is_sb[0] = sb; 623 } 624 625 psycho_iommu_init(sc, 2); 626 627 sc->sc_configtag = psycho_alloc_config_tag(sc->sc_psycho_this); 628 629 /* 630 * XXX This is a really ugly hack because PCI config space 631 * is explicitly handled with unmapped accesses. 632 */ 633 i = sc->sc_bustag->type; 634 sc->sc_bustag->type = PCI_CONFIG_BUS_SPACE; 635 if (bus_space_map(sc->sc_bustag, sc->sc_basepaddr + 0x01000000, 636 0x01000000, 0, &bh)) 637 panic("could not map psycho PCI configuration space"); 638 sc->sc_bustag->type = i; 639 sc->sc_configaddr = bh; 640 } else { 641 /* Share bus numbers with the pair of mine */ 642 pp->pp_pc->spc_busnode = 643 osc->sc_psycho_this->pp_pc->spc_busnode; 644 645 /* Just copy IOMMU state, config tag and address */ 646 sc->sc_is = osc->sc_is; 647 sc->sc_configtag = osc->sc_configtag; 648 sc->sc_configaddr = osc->sc_configaddr; 649 650 /* Point the strbuf_ctl at the iommu_state */ 651 pp->pp_sb.sb_is = sc->sc_is; 652 653 if (prom_getproplen(sc->sc_node, "no-streaming-cache") < 0) { 654 struct strbuf_ctl *sb = &pp->pp_sb; 655 vaddr_t va = (vaddr_t)&pp->pp_flush[0x40]; 656 657 /* 658 * Initialize the strbuf_ctl. 659 * 660 * The flush sync buffer must be 64-byte aligned. 661 */ 662 sb->sb_flush = (void *)(va & ~0x3f); 663 664 bus_space_subregion(sc->sc_bustag, pci_ctl, 665 offsetof(struct pci_ctl, pci_strbuf), 666 sizeof (struct iommu_strbuf), &sb->sb_sb); 667 668 /* Point our iommu at the strbuf_ctl */ 669 sc->sc_is->is_sb[1] = sb; 670 } 671 iommu_reset(sc->sc_is); 672 } 673 674 dict = device_properties(self); 675 pr = get_psychorange(pp, 2); /* memory range */ 676 #ifdef DEBUG 677 printf("memory range: %08x %08x\n", pr->phys_hi, pr->phys_lo); 678 #endif 679 mem_base = ((uint64_t)pr->phys_hi) << 32 | pr->phys_lo; 680 prop_dictionary_set_uint64(dict, "mem_base", mem_base); 681 682 /* 683 * attach the pci.. note we pass PCI A tags, etc., for the sabre here. 684 */ 685 pba.pba_flags = sc->sc_psycho_this->pp_flags; 686 pba.pba_dmat = sc->sc_psycho_this->pp_dmat; 687 pba.pba_dmat64 = NULL; 688 pba.pba_iot = sc->sc_psycho_this->pp_iot; 689 pba.pba_memt = sc->sc_psycho_this->pp_memt; 690 pba.pba_pc = pp->pp_pc; 691 692 config_found_ia(self, "pcibus", &pba, psycho_print); 693 } 694 695 static int 696 psycho_print(void *aux, const char *p) 697 { 698 699 if (p == NULL) 700 return (UNCONF); 701 return (QUIET); 702 } 703 704 static void 705 psycho_set_intr(struct psycho_softc *sc, int ipl, void *handler, 706 uint64_t *mapper, uint64_t *clearer) 707 { 708 struct intrhand *ih; 709 710 ih = (struct intrhand *)malloc(sizeof(struct intrhand), 711 M_DEVBUF, M_NOWAIT); 712 ih->ih_arg = sc; 713 ih->ih_map = mapper; 714 ih->ih_clr = clearer; 715 ih->ih_fun = handler; 716 ih->ih_pil = ipl; 717 ih->ih_number = INTVEC(*(ih->ih_map)); 718 ih->ih_pending = 0; 719 intr_establish(ipl, ipl != IPL_VM, ih); 720 *(ih->ih_map) |= INTMAP_V|(CPU_UPAID << INTMAP_TID_SHIFT); 721 } 722 723 /* 724 * power button handlers 725 */ 726 static void 727 psycho_register_power_button(struct psycho_softc *sc) 728 { 729 sysmon_task_queue_init(); 730 731 sc->sc_powerpressed = 0; 732 sc->sc_smcontext = malloc(sizeof(struct sysmon_pswitch), M_DEVBUF, 0); 733 if (!sc->sc_smcontext) { 734 aprint_error_dev(sc->sc_dev, "could not allocate power button context\n"); 735 return; 736 } 737 memset(sc->sc_smcontext, 0, sizeof(struct sysmon_pswitch)); 738 sc->sc_smcontext->smpsw_name = device_xname(sc->sc_dev); 739 sc->sc_smcontext->smpsw_type = PSWITCH_TYPE_POWER; 740 if (sysmon_pswitch_register(sc->sc_smcontext) != 0) 741 aprint_error_dev(sc->sc_dev, "unable to register power button with sysmon\n"); 742 } 743 744 static void 745 psycho_power_button_pressed(void *arg) 746 { 747 struct psycho_softc *sc = arg; 748 749 sysmon_pswitch_event(sc->sc_smcontext, PSWITCH_EVENT_PRESSED); 750 sc->sc_powerpressed = 0; 751 } 752 753 /* 754 * PCI bus support 755 */ 756 757 /* 758 * allocate a PCI chipset tag and set its cookie. 759 */ 760 static pci_chipset_tag_t 761 psycho_alloc_chipset(struct psycho_pbm *pp, int node, pci_chipset_tag_t pc) 762 { 763 pci_chipset_tag_t npc; 764 765 npc = malloc(sizeof *npc, M_DEVBUF, M_NOWAIT); 766 if (npc == NULL) 767 panic("could not allocate pci_chipset_tag_t"); 768 memcpy(npc, pc, sizeof *pc); 769 npc->cookie = pp; 770 npc->rootnode = node; 771 npc->spc_conf_read = psycho_pci_conf_read; 772 npc->spc_conf_write = psycho_pci_conf_write; 773 npc->spc_intr_map = NULL; 774 npc->spc_intr_establish = psycho_pci_intr_establish; 775 npc->spc_find_ino = psycho_pci_find_ino; 776 777 return (npc); 778 } 779 780 /* 781 * create extent for free bus space, then allocate assigned regions. 782 */ 783 static struct extent * 784 psycho_alloc_extent(struct psycho_pbm *pp, int node, int ss, const char *name) 785 { 786 struct psycho_registers *pa = NULL; 787 struct psycho_ranges *pr; 788 struct extent *ex; 789 bus_addr_t baddr, addr; 790 bus_size_t bsize, size; 791 int i, num; 792 793 /* get bus space size */ 794 pr = get_psychorange(pp, ss); 795 if (pr == NULL) { 796 printf("psycho_alloc_extent: get_psychorange failed\n"); 797 return NULL; 798 } 799 baddr = 0x00000000; 800 bsize = BUS_ADDR(pr->size_hi, pr->size_lo); 801 802 /* get available lists */ 803 num = 0; 804 if (prom_getprop(node, "available", sizeof(*pa), &num, &pa)) { 805 printf("psycho_alloc_extent: no \"available\" property\n"); 806 return NULL; 807 } 808 809 /* create extent */ 810 ex = extent_create(name, baddr, bsize - baddr - 1, 0, 0, EX_NOWAIT); 811 if (ex == NULL) { 812 printf("psycho_alloc_extent: extent_create failed\n"); 813 goto ret; 814 } 815 816 /* allocate assigned regions */ 817 for (i = 0; i < num; i++) 818 if (((pa[i].phys_hi >> 24) & 0x03) == ss) { 819 /* allocate bus space */ 820 addr = BUS_ADDR(pa[i].phys_mid, pa[i].phys_lo); 821 size = BUS_ADDR(pa[i].size_hi, pa[i].size_lo); 822 if (extent_alloc_region(ex, baddr, addr - baddr, 823 EX_NOWAIT)) { 824 printf("psycho_alloc_extent: " 825 "extent_alloc_region %" PRIx64 "-%" 826 PRIx64 " failed\n", baddr, addr); 827 extent_destroy(ex); 828 ex = NULL; 829 goto ret; 830 } 831 baddr = addr + size; 832 } 833 /* allocate left region if available */ 834 if (baddr < bsize) 835 if (extent_alloc_region(ex, baddr, bsize - baddr, EX_NOWAIT)) { 836 printf("psycho_alloc_extent: extent_alloc_region %" 837 PRIx64 "-%" PRIx64 " failed\n", baddr, bsize); 838 extent_destroy(ex); 839 ex = NULL; 840 goto ret; 841 } 842 843 #ifdef DEBUG 844 /* print extent */ 845 extent_print(ex); 846 #endif 847 848 ret: 849 /* return extent */ 850 free(pa, M_DEVBUF); 851 return ex; 852 } 853 854 /* 855 * grovel the OBP for various psycho properties 856 */ 857 static void 858 psycho_get_bus_range(int node, int *brp) 859 { 860 int n, error; 861 862 n = 2; 863 error = prom_getprop(node, "bus-range", sizeof(*brp), &n, &brp); 864 if (error) 865 panic("could not get psycho bus-range, error %d", error); 866 if (n != 2) 867 panic("broken psycho bus-range"); 868 DPRINTF(PDB_PROM, ("psycho debug: got `bus-range' for node %08x: %u - %u\n", 869 node, brp[0], brp[1])); 870 } 871 872 static void 873 psycho_fixup_bus_range(int node0, int *brp0) 874 { 875 int node; 876 int len, busrange[2], *brp; 877 878 DPRINTF(PDB_PROM, 879 ("psycho debug: fixing up `bus-range' for node %08x: %u - %u\n", 880 node0, brp0[0], brp0[1])); 881 882 /* 883 * Check all nodes under this one and increase the bus range to 884 * match. Recurse through PCI-PCI bridges. Cardbus bridges are 885 * fixed up in pccbb_attach_hook(). Assumes that "bus-range" for 886 * PCI-PCI bridges apart from this one is correct. 887 */ 888 brp0[1] = brp0[0]; 889 node = prom_firstchild(node0); 890 for (node = ((node)); node; node = prom_nextsibling(node)) { 891 len = 2; 892 brp = busrange; 893 if (prom_getprop(node, "bus-range", sizeof(*brp), 894 &len, &brp) != 0) 895 break; 896 if (len != 2) 897 break; 898 psycho_fixup_bus_range(node, busrange); 899 if (brp0[0] > busrange[0] && busrange[0] >= 0) 900 brp0[0] = busrange[0]; 901 if (brp0[1] < busrange[1] && busrange[1] < 256) 902 brp0[1] = busrange[1]; 903 } 904 905 DPRINTF(PDB_PROM, 906 ("psycho debug: fixed up `bus-range' for node %08x: %u - %u\n", 907 node0, brp[0], brp[1])); 908 } 909 910 static void 911 psycho_get_ranges(int node, struct psycho_ranges **rp, int *np) 912 { 913 914 if (prom_getprop(node, "ranges", sizeof(**rp), np, rp)) 915 panic("could not get psycho ranges"); 916 DPRINTF(PDB_PROM, ("psycho debug: got `ranges' for node %08x: %d entries\n", node, *np)); 917 } 918 919 /* 920 * Interrupt handlers. 921 */ 922 923 static int 924 psycho_ue(void *arg) 925 { 926 struct psycho_softc *sc = (struct psycho_softc *)arg; 927 struct psychoreg *regs = sc->sc_regs; 928 struct iommu_state *is = sc->sc_is; 929 uint64_t afsr = regs->psy_ue_afsr; 930 uint64_t afar = regs->psy_ue_afar; 931 psize_t size = PAGE_SIZE << is->is_tsbsize; 932 char bits[128]; 933 934 /* 935 * It's uncorrectable. Dump the regs and panic. 936 */ 937 snprintb(bits, sizeof(bits), PSYCHO_UE_AFSR_BITS, afsr); 938 aprint_error_dev(sc->sc_dev, 939 "uncorrectable DMA error AFAR %" PRIx64 " AFSR %s\n", afar, bits); 940 941 /* Sometimes the AFAR points to an IOTSB entry */ 942 if (afar >= is->is_ptsb && afar < is->is_ptsb + size) { 943 aprint_error_dev(sc->sc_dev, 944 "IOVA %" PRIx64 " IOTTE %" PRIx64 "\n", 945 (afar - is->is_ptsb) / sizeof(is->is_tsb[0]) * PAGE_SIZE 946 + is->is_dvmabase, ldxa(afar, ASI_PHYS_CACHED)); 947 } 948 #ifdef DDB 949 Debugger(); 950 #endif 951 regs->psy_ue_afar = 0; 952 regs->psy_ue_afsr = 0; 953 return (1); 954 } 955 956 static int 957 psycho_ce(void *arg) 958 { 959 struct psycho_softc *sc = (struct psycho_softc *)arg; 960 struct psychoreg *regs = sc->sc_regs; 961 962 /* 963 * It's correctable. Dump the regs and continue. 964 */ 965 aprint_error_dev(sc->sc_dev, 966 "correctable DMA error AFAR %" PRIx64 " AFSR %" PRIx64 "\n", 967 regs->psy_ce_afar, regs->psy_ce_afsr); 968 return (1); 969 } 970 971 static int 972 psycho_bus_a(void *arg) 973 { 974 struct psycho_softc *sc = (struct psycho_softc *)arg; 975 struct psychoreg *regs = sc->sc_regs; 976 977 /* 978 * It's uncorrectable. Dump the regs and panic. 979 */ 980 981 panic("%s: PCI bus A error AFAR %" PRIx64 " AFSR %" PRIx64, 982 device_xname(sc->sc_dev), 983 regs->psy_pcictl[0].pci_afar, regs->psy_pcictl[0].pci_afsr); 984 return (1); 985 } 986 987 static int 988 psycho_bus_b(void *arg) 989 { 990 struct psycho_softc *sc = (struct psycho_softc *)arg; 991 struct psychoreg *regs = sc->sc_regs; 992 993 /* 994 * It's uncorrectable. Dump the regs and panic. 995 */ 996 997 panic("%s: PCI bus B error AFAR %" PRIx64 " AFSR %" PRIx64, 998 device_xname(sc->sc_dev), 999 regs->psy_pcictl[0].pci_afar, regs->psy_pcictl[0].pci_afsr); 1000 return (1); 1001 } 1002 1003 static int 1004 psycho_powerfail(void *arg) 1005 { 1006 struct psycho_softc *sc = (struct psycho_softc *)arg; 1007 1008 /* 1009 * We lost power. Queue a callback with thread context to 1010 * handle all the real work. 1011 */ 1012 if (sc->sc_powerpressed == 0 && sc->sc_smcontext != NULL) { 1013 sc->sc_powerpressed = 1; 1014 sysmon_task_queue_sched(0, psycho_power_button_pressed, sc); 1015 } 1016 return (1); 1017 } 1018 1019 static 1020 int psycho_wakeup(void *arg) 1021 { 1022 struct psycho_softc *sc = (struct psycho_softc *)arg; 1023 1024 /* 1025 * Gee, we don't really have a framework to deal with this 1026 * properly. 1027 */ 1028 aprint_error_dev(sc->sc_dev, "power management wakeup\n"); 1029 return (1); 1030 } 1031 1032 1033 /* 1034 * initialise the IOMMU.. 1035 */ 1036 void 1037 psycho_iommu_init(struct psycho_softc *sc, int tsbsize) 1038 { 1039 char *name; 1040 struct iommu_state *is = sc->sc_is; 1041 uint32_t iobase = -1; 1042 int *vdma = NULL; 1043 int nitem; 1044 1045 /* punch in our copies */ 1046 is->is_bustag = sc->sc_bustag; 1047 bus_space_subregion(sc->sc_bustag, sc->sc_bh, 1048 offsetof(struct psychoreg, psy_iommu), 1049 sizeof (struct iommureg), 1050 &is->is_iommu); 1051 1052 /* 1053 * Separate the men from the boys. Get the `virtual-dma' 1054 * property for sabre and use that to make sure the damn 1055 * iommu works. 1056 * 1057 * We could query the `#virtual-dma-size-cells' and 1058 * `#virtual-dma-addr-cells' and DTRT, but I'm lazy. 1059 */ 1060 nitem = 0; 1061 if (!prom_getprop(sc->sc_node, "virtual-dma", sizeof(vdma), &nitem, 1062 &vdma)) { 1063 /* Damn. Gotta use these values. */ 1064 iobase = vdma[0]; 1065 #define TSBCASE(x) case 1<<((x)+23): tsbsize = (x); break 1066 switch (vdma[1]) { 1067 TSBCASE(1); TSBCASE(2); TSBCASE(3); 1068 TSBCASE(4); TSBCASE(5); TSBCASE(6); 1069 default: 1070 printf("bogus tsb size %x, using 7\n", vdma[1]); 1071 TSBCASE(7); 1072 } 1073 #undef TSBCASE 1074 } 1075 1076 /* give us a nice name.. */ 1077 name = (char *)malloc(32, M_DEVBUF, M_NOWAIT); 1078 if (name == 0) 1079 panic("couldn't malloc iommu name"); 1080 snprintf(name, 32, "%s dvma", device_xname(sc->sc_dev)); 1081 1082 iommu_init(name, is, tsbsize, iobase); 1083 } 1084 1085 /* 1086 * below here is bus space and bus DMA support 1087 */ 1088 bus_space_tag_t 1089 psycho_alloc_bus_tag(struct psycho_pbm *pp, int type) 1090 { 1091 struct psycho_softc *sc = pp->pp_sc; 1092 bus_space_tag_t bt; 1093 1094 bt = (bus_space_tag_t) malloc(sizeof(struct sparc_bus_space_tag), 1095 M_DEVBUF, M_NOWAIT | M_ZERO); 1096 if (bt == NULL) 1097 panic("could not allocate psycho bus tag"); 1098 1099 bt->cookie = pp; 1100 bt->parent = sc->sc_bustag; 1101 bt->type = type; 1102 bt->sparc_bus_map = _psycho_bus_map; 1103 bt->sparc_bus_mmap = psycho_bus_mmap; 1104 bt->sparc_intr_establish = psycho_intr_establish; 1105 return (bt); 1106 } 1107 1108 bus_dma_tag_t 1109 psycho_alloc_dma_tag(struct psycho_pbm *pp) 1110 { 1111 struct psycho_softc *sc = pp->pp_sc; 1112 bus_dma_tag_t dt, pdt = sc->sc_dmatag; 1113 1114 dt = (bus_dma_tag_t) 1115 malloc(sizeof(struct sparc_bus_dma_tag), M_DEVBUF, M_NOWAIT); 1116 if (dt == NULL) 1117 panic("could not allocate psycho DMA tag"); 1118 1119 memset(dt, 0, sizeof *dt); 1120 dt->_cookie = pp; 1121 dt->_parent = pdt; 1122 #define PCOPY(x) dt->x = pdt->x 1123 dt->_dmamap_create = psycho_dmamap_create; 1124 PCOPY(_dmamap_destroy); 1125 dt->_dmamap_load = iommu_dvmamap_load; 1126 PCOPY(_dmamap_load_mbuf); 1127 PCOPY(_dmamap_load_uio); 1128 dt->_dmamap_load_raw = iommu_dvmamap_load_raw; 1129 dt->_dmamap_unload = iommu_dvmamap_unload; 1130 if (sc->sc_mode == PSYCHO_MODE_SABRE) 1131 dt->_dmamap_sync = psycho_sabre_dmamap_sync; 1132 else 1133 dt->_dmamap_sync = iommu_dvmamap_sync; 1134 dt->_dmamem_alloc = iommu_dvmamem_alloc; 1135 dt->_dmamem_free = iommu_dvmamem_free; 1136 dt->_dmamem_map = iommu_dvmamem_map; 1137 dt->_dmamem_unmap = iommu_dvmamem_unmap; 1138 PCOPY(_dmamem_mmap); 1139 #undef PCOPY 1140 return (dt); 1141 } 1142 1143 /* 1144 * bus space support. <sparc64/dev/psychoreg.h> has a discussion about 1145 * PCI physical addresses. 1146 */ 1147 1148 static struct psycho_ranges * 1149 get_psychorange(struct psycho_pbm *pp, int ss) 1150 { 1151 int i; 1152 1153 for (i = 0; i < pp->pp_nrange; i++) { 1154 if (((pp->pp_range[i].cspace >> 24) & 0x03) == ss) 1155 return (&pp->pp_range[i]); 1156 } 1157 /* not found */ 1158 return (NULL); 1159 } 1160 1161 static int 1162 _psycho_bus_map(bus_space_tag_t t, bus_addr_t offset, bus_size_t size, 1163 int flags, vaddr_t unused, bus_space_handle_t *hp) 1164 { 1165 struct psycho_pbm *pp = t->cookie; 1166 struct psycho_softc *sc = pp->pp_sc; 1167 struct psycho_ranges *pr; 1168 bus_addr_t paddr; 1169 int ss; 1170 1171 DPRINTF(PDB_BUSMAP, 1172 ("_psycho_bus_map: type %d off %qx sz %qx flags %d", 1173 t->type, (unsigned long long)offset, 1174 (unsigned long long)size, flags)); 1175 1176 ss = sparc_pci_childspace(t->type); 1177 DPRINTF(PDB_BUSMAP, (" cspace %d", ss)); 1178 1179 pr = get_psychorange(pp, ss); 1180 if (pr != NULL) { 1181 paddr = BUS_ADDR(pr->phys_hi, pr->phys_lo + offset); 1182 DPRINTF(PDB_BUSMAP, ("\n_psycho_bus_map: mapping paddr " 1183 "space %lx offset %lx paddr %qx\n", 1184 (long)ss, (long)offset, 1185 (unsigned long long)paddr)); 1186 return ((*sc->sc_bustag->sparc_bus_map)(t, paddr, size, 1187 flags, 0, hp)); 1188 } 1189 DPRINTF(PDB_BUSMAP, (" FAILED\n")); 1190 return (EINVAL); 1191 } 1192 1193 static paddr_t 1194 psycho_bus_mmap(bus_space_tag_t t, bus_addr_t paddr, off_t off, int prot, 1195 int flags) 1196 { 1197 bus_addr_t offset = paddr; 1198 struct psycho_pbm *pp = t->cookie; 1199 struct psycho_softc *sc = pp->pp_sc; 1200 struct psycho_ranges *pr; 1201 int ss; 1202 1203 ss = sparc_pci_childspace(t->type); 1204 1205 DPRINTF(PDB_BUSMAP, ("_psycho_bus_mmap: prot %x flags %d pa %qx\n", 1206 prot, flags, (unsigned long long)paddr)); 1207 1208 pr = get_psychorange(pp, ss); 1209 if (pr != NULL) { 1210 paddr = BUS_ADDR(pr->phys_hi, pr->phys_lo + offset); 1211 DPRINTF(PDB_BUSMAP, ("\n_psycho_bus_mmap: mapping paddr " 1212 "space %lx offset %lx paddr %qx\n", 1213 (long)ss, (long)offset, 1214 (unsigned long long)paddr)); 1215 return (bus_space_mmap(sc->sc_bustag, paddr, off, 1216 prot, flags)); 1217 } 1218 1219 return (-1); 1220 } 1221 1222 /* 1223 * Get a PCI offset address from bus_space_handle_t. 1224 */ 1225 bus_addr_t 1226 psycho_bus_offset(bus_space_tag_t t, bus_space_handle_t *hp) 1227 { 1228 struct psycho_pbm *pp = t->cookie; 1229 struct psycho_ranges *pr; 1230 bus_addr_t addr, offset; 1231 vaddr_t va; 1232 int ss; 1233 1234 addr = hp->_ptr; 1235 ss = sparc_pci_childspace(t->type); 1236 DPRINTF(PDB_BUSMAP, ("psycho_bus_offset: type %d addr %" PRIx64 1237 " cspace %d", t->type, addr, ss)); 1238 1239 pr = get_psychorange(pp, ss); 1240 if (pr != NULL) { 1241 if (!PHYS_ASI(hp->_asi)) { 1242 va = trunc_page((vaddr_t)addr); 1243 if (pmap_extract(pmap_kernel(), va, &addr) == FALSE) { 1244 DPRINTF(PDB_BUSMAP, 1245 ("\n pmap_extract FAILED\n")); 1246 return (-1); 1247 } 1248 addr += hp->_ptr & PGOFSET; 1249 } 1250 offset = BUS_ADDR_PADDR(addr) - pr->phys_lo; 1251 DPRINTF(PDB_BUSMAP, ("\npsycho_bus_offset: paddr %" PRIx64 1252 " offset %" PRIx64 "\n", addr, offset)); 1253 return (offset); 1254 } 1255 DPRINTF(PDB_BUSMAP, ("\n FAILED\n")); 1256 return (-1); 1257 } 1258 1259 1260 /* 1261 * install an interrupt handler for a PCI device 1262 */ 1263 void * 1264 psycho_intr_establish(bus_space_tag_t t, int ihandle, int level, 1265 int (*handler)(void *), void *arg, void (*fastvec)(void) /* ignored */) 1266 { 1267 struct psycho_pbm *pp = t->cookie; 1268 struct psycho_softc *sc = pp->pp_sc; 1269 struct intrhand *ih; 1270 volatile uint64_t *intrmapptr = NULL, *intrclrptr = NULL; 1271 int64_t imap = 0; 1272 int ino; 1273 long vec = INTVEC(ihandle); 1274 1275 ih = malloc(sizeof(struct intrhand), M_DEVBUF, M_NOWAIT); 1276 if (ih == NULL) 1277 return (NULL); 1278 1279 ih->ih_ivec = ihandle; 1280 1281 /* 1282 * Hunt through all the interrupt mapping regs to look for our 1283 * interrupt vector. 1284 * 1285 * XXX We only compare INOs rather than IGNs since the firmware may 1286 * not provide the IGN and the IGN is constant for all device on that 1287 * PCI controller. This could cause problems for the FFB/external 1288 * interrupt which has a full vector that can be set arbitrarily. 1289 */ 1290 1291 DPRINTF(PDB_INTR, ("\npsycho_intr_establish: ihandle %x vec %lx", ihandle, vec)); 1292 ino = INTINO(vec); 1293 DPRINTF(PDB_INTR, (" ino %x", ino)); 1294 1295 /* If the device didn't ask for an IPL, use the one encoded. */ 1296 if (level == IPL_NONE) level = INTLEV(vec); 1297 /* If it still has no level, print a warning and assign IPL 2 */ 1298 if (level == IPL_NONE) { 1299 printf("ERROR: no IPL, setting IPL 2.\n"); 1300 level = 2; 1301 } 1302 1303 DPRINTF(PDB_INTR, ("\npsycho: intr %lx: %p\nHunting for IRQ...\n", 1304 (long)ino, intrlev[ino])); 1305 1306 /* 1307 * First look for PCI interrupts, otherwise the PCI A slot 0 1308 * INTA# interrupt might match an unused non-PCI (obio) 1309 * interrupt. 1310 */ 1311 for (intrmapptr = &sc->sc_regs->pcia_slot0_int, 1312 intrclrptr = &sc->sc_regs->pcia0_clr_int[0]; 1313 intrmapptr <= &sc->sc_regs->pcib_slot3_int; 1314 intrmapptr++, intrclrptr += 4) { 1315 if (sc->sc_mode == PSYCHO_MODE_PSYCHO && 1316 (intrmapptr == &sc->sc_regs->pcia_slot2_int || 1317 intrmapptr == &sc->sc_regs->pcia_slot3_int)) 1318 continue; 1319 if (((*intrmapptr ^ vec) & 0x3c) == 0) { 1320 intrclrptr += vec & 0x3; 1321 goto found; 1322 } 1323 } 1324 1325 /* Now hunt thru obio. */ 1326 for (intrmapptr = &sc->sc_regs->scsi_int_map, 1327 intrclrptr = &sc->sc_regs->scsi_clr_int; 1328 intrmapptr < &sc->sc_regs->ue_int_map; 1329 intrmapptr++, intrclrptr++) { 1330 if (INTINO(*intrmapptr) == ino) 1331 goto found; 1332 } 1333 1334 /* Finally check the two FFB slots */ 1335 intrclrptr = NULL; /* XXX? */ 1336 for (intrmapptr = &sc->sc_regs->ffb0_int_map; 1337 intrmapptr <= &sc->sc_regs->ffb1_int_map; 1338 intrmapptr++) { 1339 if (INTVEC(*intrmapptr) == ino) 1340 goto found; 1341 } 1342 1343 printf("Cannot find interrupt vector %lx\n", vec); 1344 free(ih, M_DEVBUF); 1345 return (NULL); 1346 1347 found: 1348 /* Register the map and clear intr registers */ 1349 ih->ih_map = intrmapptr; 1350 ih->ih_clr = intrclrptr; 1351 1352 ih->ih_fun = handler; 1353 ih->ih_arg = arg; 1354 ih->ih_pil = level; 1355 ih->ih_number = ino | sc->sc_ign; 1356 ih->ih_pending = 0; 1357 1358 DPRINTF(PDB_INTR, ( 1359 "; installing handler %p arg %p with ino %u pil %u\n", 1360 handler, arg, (u_int)ino, (u_int)ih->ih_pil)); 1361 1362 intr_establish(ih->ih_pil, level != IPL_VM, ih); 1363 1364 /* 1365 * Enable the interrupt now we have the handler installed. 1366 * Read the current value as we can't change it besides the 1367 * valid bit so so make sure only this bit is changed. 1368 * 1369 * XXXX --- we really should use bus_space for this. 1370 */ 1371 if (intrmapptr) { 1372 imap = *intrmapptr; 1373 DPRINTF(PDB_INTR, ("; read intrmap = %016qx", 1374 (unsigned long long)imap)); 1375 1376 /* Enable the interrupt */ 1377 imap |= INTMAP_V|(CPU_UPAID << INTMAP_TID_SHIFT); 1378 DPRINTF(PDB_INTR, ("; addr of intrmapptr = %p", intrmapptr)); 1379 DPRINTF(PDB_INTR, ("; writing intrmap = %016qx\n", 1380 (unsigned long long)imap)); 1381 *intrmapptr = imap; 1382 DPRINTF(PDB_INTR, ("; reread intrmap = %016qx", 1383 (unsigned long long)(imap = *intrmapptr))); 1384 } 1385 if (intrclrptr) { 1386 /* set state to IDLE */ 1387 *intrclrptr = 0; 1388 } 1389 return (ih); 1390 } 1391 1392 /* 1393 * per-controller driver calls 1394 */ 1395 1396 /* assume we are mapped little-endian/side-effect */ 1397 static pcireg_t 1398 psycho_pci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg) 1399 { 1400 struct psycho_pbm *pp = pc->cookie; 1401 struct psycho_softc *sc = pp->pp_sc; 1402 struct cpu_info *ci = curcpu(); 1403 pcireg_t val = (pcireg_t)~0; 1404 int s; 1405 1406 DPRINTF(PDB_CONF, ("%s: tag %lx reg %x ", __func__, 1407 (long)tag, reg)); 1408 if (PCITAG_NODE(tag) != -1) { 1409 1410 DPRINTF(PDB_CONF, ("asi=%x addr=%qx (offset=%x) ...", 1411 sc->sc_configaddr._asi, 1412 (long long)(sc->sc_configaddr._ptr + 1413 PCITAG_OFFSET(tag) + reg), 1414 (int)PCITAG_OFFSET(tag) + reg)); 1415 1416 s = splhigh(); 1417 ci->ci_pci_probe = true; 1418 membar_Sync(); 1419 val = bus_space_read_4(sc->sc_configtag, sc->sc_configaddr, 1420 PCITAG_OFFSET(tag) + reg); 1421 membar_Sync(); 1422 if (ci->ci_pci_fault) 1423 val = (pcireg_t)~0; 1424 ci->ci_pci_probe = ci->ci_pci_fault = false; 1425 splx(s); 1426 } 1427 #ifdef DEBUG 1428 else DPRINTF(PDB_CONF, ("%s: bogus pcitag %x\n", __func__, 1429 (int)PCITAG_OFFSET(tag))); 1430 #endif 1431 DPRINTF(PDB_CONF, (" returning %08x\n", (u_int)val)); 1432 1433 return (val); 1434 } 1435 1436 static void 1437 psycho_pci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data) 1438 { 1439 struct psycho_pbm *pp = pc->cookie; 1440 struct psycho_softc *sc = pp->pp_sc; 1441 1442 DPRINTF(PDB_CONF, ("%s: tag %lx; reg %x; data %x; ", __func__, 1443 (long)PCITAG_OFFSET(tag), reg, (int)data)); 1444 DPRINTF(PDB_CONF, ("asi = %x; readaddr = %qx (offset = %x)\n", 1445 sc->sc_configaddr._asi, 1446 (long long)(sc->sc_configaddr._ptr + PCITAG_OFFSET(tag) + reg), 1447 (int)PCITAG_OFFSET(tag) + reg)); 1448 1449 /* If we don't know it, just punt it. */ 1450 if (PCITAG_NODE(tag) == -1) { 1451 DPRINTF(PDB_CONF, ("%s: bad addr", __func__)); 1452 return; 1453 } 1454 1455 bus_space_write_4(sc->sc_configtag, sc->sc_configaddr, 1456 PCITAG_OFFSET(tag) + reg, data); 1457 } 1458 1459 static void * 1460 psycho_pci_intr_establish(pci_chipset_tag_t pc, pci_intr_handle_t ih, int level, 1461 int (*func)(void *), void *arg) 1462 { 1463 void *cookie; 1464 struct psycho_pbm *pp = (struct psycho_pbm *)pc->cookie; 1465 1466 DPRINTF(PDB_INTR, ("%s: ih %lx; level %d", __func__, (u_long)ih, level)); 1467 cookie = bus_intr_establish(pp->pp_memt, ih, level, func, arg); 1468 1469 DPRINTF(PDB_INTR, ("; returning handle %p\n", cookie)); 1470 return (cookie); 1471 } 1472 1473 static int 1474 psycho_pci_find_ino(const struct pci_attach_args *pa, pci_intr_handle_t *ihp) 1475 { 1476 struct psycho_pbm *pp = pa->pa_pc->cookie; 1477 struct psycho_softc *sc = pp->pp_sc; 1478 u_int bus; 1479 u_int dev; 1480 u_int pin; 1481 1482 DPRINTF(PDB_INTMAP, ("%s: pa_tag: node %x, %d:%d:%d\n", __func__, 1483 PCITAG_NODE(pa->pa_tag), (int)PCITAG_BUS(pa->pa_tag), 1484 (int)PCITAG_DEV(pa->pa_tag), 1485 (int)PCITAG_FUN(pa->pa_tag))); 1486 DPRINTF(PDB_INTMAP, 1487 ("%s: intrswiz %d, intrpin %d, intrline %d, rawintrpin %d\n", __func__, 1488 pa->pa_intrswiz, pa->pa_intrpin, pa->pa_intrline, pa->pa_rawintrpin)); 1489 DPRINTF(PDB_INTMAP, ("%s: pa_intrtag: node %x, %d:%d:%d\n", __func__, 1490 PCITAG_NODE(pa->pa_intrtag), 1491 (int)PCITAG_BUS(pa->pa_intrtag), 1492 (int)PCITAG_DEV(pa->pa_intrtag), 1493 (int)PCITAG_FUN(pa->pa_intrtag))); 1494 1495 bus = (pp->pp_id == PSYCHO_PBM_B); 1496 /* 1497 * If we are on a ppb, use the devno on the underlying bus when forming 1498 * the ivec. 1499 */ 1500 if (pa->pa_intrswiz != 0 && PCITAG_NODE(pa->pa_intrtag) != 0) 1501 dev = PCITAG_DEV(pa->pa_intrtag); 1502 else 1503 dev = pa->pa_device; 1504 dev--; 1505 1506 if (sc->sc_mode == PSYCHO_MODE_PSYCHO && 1507 pp->pp_id == PSYCHO_PBM_B) 1508 dev--; 1509 1510 pin = pa->pa_intrpin - 1; 1511 DPRINTF(PDB_INTMAP, ("%s: mode %d, pbm %d, dev %d, pin %d\n", __func__, 1512 sc->sc_mode, pp->pp_id, dev, pin)); 1513 1514 *ihp = sc->sc_ign | ((bus << 4) & INTMAP_PCIBUS) | 1515 ((dev << 2) & INTMAP_PCISLOT) | (pin & INTMAP_PCIINT); 1516 1517 return (0); 1518 } 1519 1520 /* 1521 * hooks into the iommu dvma calls. 1522 */ 1523 static int 1524 psycho_dmamap_create(bus_dma_tag_t t, bus_size_t size, int nsegments, 1525 bus_size_t maxsegsz, bus_size_t boundary, int flags, 1526 bus_dmamap_t *dmamp) 1527 { 1528 struct psycho_pbm *pp = (struct psycho_pbm *)t->_cookie; 1529 int error; 1530 1531 error = bus_dmamap_create(t->_parent, size, nsegments, maxsegsz, 1532 boundary, flags, dmamp); 1533 if (error == 0) 1534 (*dmamp)->_dm_cookie = &pp->pp_sb; 1535 return error; 1536 } 1537 1538 /* 1539 * UltraSPARC IIi and IIe have no streaming buffers, but have PCI DMA 1540 * Write Synchronization Register (see UltraSPARC-IIi User's Manual 1541 * section 19.3.0.5). So use it to synchronize with the DMA writes. 1542 */ 1543 static void 1544 psycho_sabre_dmamap_sync(bus_dma_tag_t t, bus_dmamap_t map, bus_addr_t offset, 1545 bus_size_t len, int ops) 1546 { 1547 struct psycho_pbm *pp; 1548 struct psycho_softc *sc; 1549 1550 /* If len is 0, then there is nothing to do. */ 1551 if (len == 0) 1552 return; 1553 1554 if (ops & BUS_DMASYNC_POSTREAD) { 1555 pp = (struct psycho_pbm *)t->_cookie; 1556 sc = pp->pp_sc; 1557 bus_space_read_8(sc->sc_bustag, sc->sc_bh, 1558 offsetof(struct psychoreg, pci_dma_write_sync)); 1559 } 1560 bus_dmamap_sync(t->_parent, map, offset, len, ops); 1561 } 1562 1563 /* US-IIe STICK support */ 1564 1565 uint64_t 1566 psycho_getstick(void) 1567 { 1568 uint64_t stick; 1569 1570 stick = bus_space_read_8(psycho0->sc_bustag, psycho0->sc_bh, 1571 STICK_CNT_LOW) | 1572 (bus_space_read_8(psycho0->sc_bustag, psycho0->sc_bh, 1573 STICK_CNT_HIGH) & 0x7fffffff) << 32; 1574 return stick; 1575 } 1576 1577 uint32_t 1578 psycho_getstick32(void) 1579 { 1580 1581 return bus_space_read_8(psycho0->sc_bustag, psycho0->sc_bh, 1582 STICK_CNT_LOW); 1583 } 1584 1585 void 1586 psycho_setstick(long cnt) 1587 { 1588 1589 /* 1590 * looks like we can't actually write the STICK counter, so instead we 1591 * prepare sc_last_stick for the coming interrupt setup 1592 */ 1593 #if 0 1594 bus_space_write_8(psycho0->sc_bustag, psycho0->sc_bh, 1595 STICK_CNT_HIGH, (cnt >> 32)); 1596 bus_space_write_8(psycho0->sc_bustag, psycho0->sc_bh, 1597 STICK_CNT_LOW, (uint32_t)(cnt & 0xffffffff)); 1598 #endif 1599 1600 if (cnt == 0) { 1601 bus_space_write_8(psycho0->sc_bustag, psycho0->sc_bh, 1602 STICK_CMP_HIGH, 0); 1603 bus_space_write_8(psycho0->sc_bustag, psycho0->sc_bh, 1604 STICK_CMP_LOW, 0); 1605 psycho0->sc_last_stick = 0; 1606 } 1607 1608 psycho0->sc_last_stick = psycho_getstick(); 1609 DPRINTF(PDB_STICK, ("stick: %ld\n", psycho0->sc_last_stick)); 1610 } 1611 1612 void 1613 psycho_nextstick(long diff) 1614 { 1615 uint64_t cmp, now; 1616 1617 /* 1618 * there is no way we'll ever overflow 1619 * the counter is 63 bits wide, at 12MHz that's >24000 years 1620 */ 1621 now = psycho_getstick() + 1000; 1622 cmp = psycho0->sc_last_stick; 1623 1624 while (cmp < now) 1625 cmp += diff; 1626 1627 bus_space_write_8(psycho0->sc_bustag, psycho0->sc_bh, 1628 STICK_CMP_HIGH, (cmp >> 32) & 0x7fffffff); 1629 bus_space_write_8(psycho0->sc_bustag, psycho0->sc_bh, 1630 STICK_CMP_LOW, (cmp & 0xffffffff)); 1631 1632 psycho0->sc_last_stick = cmp; 1633 } 1634
Indexes created Thu Sep 25 16:09:42 GMT 2025