psycho.c revision 1.132
1 /* $NetBSD: psycho.c,v 1.132 2021/01/17 00:18:28 mrg Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000 Matthew R. Green 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * Copyright (c) 2001, 2002 Eduardo E. Horvath 31 * All rights reserved. 32 * 33 * Redistribution and use in source and binary forms, with or without 34 * modification, are permitted provided that the following conditions 35 * are met: 36 * 1. Redistributions of source code must retain the above copyright 37 * notice, this list of conditions and the following disclaimer. 38 * 2. Redistributions in binary form must reproduce the above copyright 39 * notice, this list of conditions and the following disclaimer in the 40 * documentation and/or other materials provided with the distribution. 41 * 3. The name of the author may not be used to endorse or promote products 42 * derived from this software without specific prior written permission. 43 * 44 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 45 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 46 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 47 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 48 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 49 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 50 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 51 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 52 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 53 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 54 * SUCH DAMAGE. 55 */ 56 57 #include <sys/cdefs.h> 58 __KERNEL_RCSID(0, "$NetBSD: psycho.c,v 1.132 2021/01/17 00:18:28 mrg Exp $"); 59 60 #include "opt_ddb.h" 61 62 /* 63 * Support for `psycho' and `psycho+' UPA to PCI bridge and 64 * UltraSPARC IIi and IIe `sabre' PCI controllers. 65 */ 66 67 #ifdef DEBUG 68 #define PDB_PROM 0x01 69 #define PDB_BUSMAP 0x02 70 #define PDB_INTR 0x04 71 #define PDB_INTMAP 0x08 72 #define PDB_CONF 0x10 73 #define PDB_STICK 0x20 74 int psycho_debug = 0x0; 75 #define DPRINTF(l, s) do { if (psycho_debug & l) printf s; } while (0) 76 #else 77 #define DPRINTF(l, s) 78 #endif 79 80 #include <sys/param.h> 81 #include <sys/device.h> 82 #include <sys/errno.h> 83 #include <sys/extent.h> 84 #include <sys/malloc.h> 85 #include <sys/kmem.h> 86 #include <sys/systm.h> 87 #include <sys/time.h> 88 #include <sys/reboot.h> 89 90 #include <uvm/uvm.h> 91 92 #define _SPARC_BUS_DMA_PRIVATE 93 #include <sys/bus.h> 94 #include <machine/autoconf.h> 95 #include <machine/psl.h> 96 97 #include <dev/pci/pcivar.h> 98 #include <dev/pci/pcireg.h> 99 #include <dev/sysmon/sysmon_taskq.h> 100 101 #include <sparc64/dev/iommureg.h> 102 #include <sparc64/dev/iommuvar.h> 103 #include <sparc64/dev/psychoreg.h> 104 #include <sparc64/dev/psychovar.h> 105 106 #include "ioconf.h" 107 108 static pci_chipset_tag_t psycho_alloc_chipset(struct psycho_pbm *, int, 109 pci_chipset_tag_t); 110 static struct extent *psycho_alloc_extent(struct psycho_pbm *, int, int, 111 const char *); 112 static void psycho_get_bus_range(int, int *); 113 static void psycho_fixup_bus_range(int, int *); 114 static void psycho_get_ranges(int, struct psycho_ranges **, int *); 115 static void psycho_set_intr(struct psycho_softc *, int, void *, uint64_t *, 116 uint64_t *); 117 118 /* chipset handlers */ 119 static pcireg_t psycho_pci_conf_read(pci_chipset_tag_t, pcitag_t, int); 120 static void psycho_pci_conf_write(pci_chipset_tag_t, pcitag_t, int, 121 pcireg_t); 122 static void *psycho_pci_intr_establish(pci_chipset_tag_t, 123 pci_intr_handle_t, 124 int, int (*)(void *), void *); 125 static int psycho_pci_find_ino(const struct pci_attach_args *, 126 pci_intr_handle_t *); 127 128 /* Interrupt handlers */ 129 static int psycho_ue(void *); 130 static int psycho_ce(void *); 131 static int psycho_bus_a(void *); 132 static int psycho_bus_b(void *); 133 static int psycho_powerfail(void *); 134 static int psycho_wakeup(void *); 135 136 137 /* IOMMU support */ 138 static void psycho_iommu_init(struct psycho_softc *, int); 139 140 /* 141 * bus space and bus DMA support for UltraSPARC `psycho'. note that most 142 * of the bus DMA support is provided by the iommu dvma controller. 143 */ 144 static struct psycho_ranges *get_psychorange(struct psycho_pbm *, int); 145 146 static paddr_t psycho_bus_mmap(bus_space_tag_t, bus_addr_t, off_t, int, int); 147 static int _psycho_bus_map(bus_space_tag_t, bus_addr_t, bus_size_t, int, 148 vaddr_t, bus_space_handle_t *); 149 static void *psycho_intr_establish(bus_space_tag_t, int, int, int (*)(void *), 150 void *, void(*)(void)); 151 152 static int psycho_dmamap_create(bus_dma_tag_t, bus_size_t, int, bus_size_t, 153 bus_size_t, int, bus_dmamap_t *); 154 static void psycho_sabre_dmamap_sync(bus_dma_tag_t, bus_dmamap_t, bus_addr_t, 155 bus_size_t, int); 156 157 /* base pci_chipset */ 158 extern struct sparc_pci_chipset _sparc_pci_chipset; 159 160 /* power button handlers */ 161 static void psycho_register_power_button(struct psycho_softc *sc); 162 static void psycho_power_button_pressed(void *arg); 163 164 /* 165 * autoconfiguration 166 */ 167 static int psycho_match(device_t, cfdata_t, void *); 168 static void psycho_attach(device_t, device_t, void *); 169 static int psycho_print(void *aux, const char *p); 170 171 CFATTACH_DECL_NEW(psycho, sizeof(struct psycho_softc), 172 psycho_match, psycho_attach, NULL, NULL); 173 174 /* 175 * "sabre" is the UltraSPARC IIi onboard UPA to PCI bridge. It manages a 176 * single PCI bus and does not have a streaming buffer. It often has an APB 177 * (advanced PCI bridge) connected to it, which was designed specifically for 178 * the IIi. The APB let's the IIi handle two independednt PCI buses, and 179 * appears as two "simba"'s underneath the sabre. 180 * 181 * "psycho" and "psycho+" is a dual UPA to PCI bridge. It sits on the UPA bus 182 * and manages two PCI buses. "psycho" has two 64-bit 33 MHz buses, while 183 * "psycho+" controls both a 64-bit 33 MHz and a 64-bit 66 MHz PCI bus. You 184 * will usually find a "psycho+" since I don't think the original "psycho" 185 * ever shipped, and if it did it would be in the U30. 186 * 187 * Each "psycho" PCI bus appears as a separate OFW node, but since they are 188 * both part of the same IC, they only have a single register space. As such, 189 * they need to be configured together, even though the autoconfiguration will 190 * attach them separately. 191 * 192 * On UltraIIi machines, "sabre" itself usually takes pci0, with "simba" often 193 * as pci1 and pci2, although they have been implemented with other PCI bus 194 * numbers on some machines. 195 * 196 * On UltraII machines, there can be any number of "psycho+" ICs, each 197 * providing two PCI buses. 198 * 199 * 200 * XXXX The psycho/sabre node has an `interrupts' attribute. They contain 201 * the values of the following interrupts in this order: 202 * 203 * PCI Bus Error (30) 204 * DMA UE (2e) 205 * DMA CE (2f) 206 * Power Fail (25) 207 * 208 * We really should attach handlers for each. 209 * 210 */ 211 212 #define ROM_PCI_NAME "pci" 213 214 struct psycho_names { 215 const char *p_name; 216 int p_type; 217 } psycho_names[] = { 218 { "SUNW,psycho", PSYCHO_MODE_PSYCHO }, 219 { "pci108e,8000", PSYCHO_MODE_PSYCHO }, 220 { "SUNW,sabre", PSYCHO_MODE_SABRE }, 221 { "pci108e,a000", PSYCHO_MODE_SABRE }, 222 { "pci108e,a001", PSYCHO_MODE_SABRE }, 223 { NULL, 0 } 224 }; 225 226 struct psycho_softc *psycho0 = NULL; 227 228 static int 229 psycho_match(device_t parent, cfdata_t match, void *aux) 230 { 231 struct mainbus_attach_args *ma = aux; 232 char *model; 233 int i; 234 235 if (ma->ma_node == 0) 236 return 0; /* no OF node, can't be us */ 237 238 model = prom_getpropstring(ma->ma_node, "model"); 239 /* match on a name of "pci" and a sabre or a psycho */ 240 if (strcmp(ma->ma_name, ROM_PCI_NAME) == 0) { 241 for (i=0; psycho_names[i].p_name; i++) 242 if (strcmp(model, psycho_names[i].p_name) == 0) 243 return (1); 244 245 model = prom_getpropstring(ma->ma_node, "compatible"); 246 for (i=0; psycho_names[i].p_name; i++) 247 if (strcmp(model, psycho_names[i].p_name) == 0) 248 return (1); 249 } 250 return (0); 251 } 252 253 #ifdef DEBUG 254 static void psycho_dump_intmap(struct psycho_softc *sc); 255 static void 256 psycho_dump_intmap(struct psycho_softc *sc) 257 { 258 volatile uint64_t *intrmapptr = NULL; 259 260 printf("psycho_dump_intmap: OBIO\n"); 261 262 for (intrmapptr = &sc->sc_regs->scsi_int_map; 263 intrmapptr < &sc->sc_regs->ue_int_map; 264 intrmapptr++) 265 printf("%p: %llx\n", intrmapptr, 266 (unsigned long long)*intrmapptr); 267 268 printf("\tintmap:pci\n"); 269 for (intrmapptr = &sc->sc_regs->pcia_slot0_int; 270 intrmapptr <= &sc->sc_regs->pcib_slot3_int; 271 intrmapptr++) 272 printf("%p: %llx\n", intrmapptr, 273 (unsigned long long)*intrmapptr); 274 275 printf("\tintmap:ffb\n"); 276 for (intrmapptr = &sc->sc_regs->ffb0_int_map; 277 intrmapptr <= &sc->sc_regs->ffb1_int_map; 278 intrmapptr++) 279 printf("%p: %llx\n", intrmapptr, 280 (unsigned long long)*intrmapptr); 281 } 282 #endif 283 284 /* 285 * SUNW,psycho initialisation .. 286 * - find the per-psycho registers 287 * - figure out the IGN. 288 * - find our partner psycho 289 * - configure ourselves 290 * - bus range, bus, 291 * - get interrupt-map and interrupt-map-mask 292 * - setup the chipsets. 293 * - if we're the first of the pair, initialise the IOMMU, otherwise 294 * just copy its tags and addresses. 295 */ 296 static void 297 psycho_attach(device_t parent, device_t self, void *aux) 298 { 299 struct psycho_softc *sc = device_private(self); 300 struct psycho_softc *osc = NULL; 301 struct psycho_pbm *pp; 302 struct pcibus_attach_args pba; 303 struct mainbus_attach_args *ma = aux; 304 struct psycho_ranges *pr; 305 prop_dictionary_t dict; 306 bus_space_handle_t bh; 307 uint64_t csr, mem_base; 308 int psycho_br[2], n, i; 309 bus_space_handle_t pci_ctl; 310 char *model = prom_getpropstring(ma->ma_node, "model"); 311 312 aprint_normal("\n"); 313 314 sc->sc_dev = self; 315 sc->sc_node = ma->ma_node; 316 sc->sc_bustag = ma->ma_bustag; 317 sc->sc_dmatag = ma->ma_dmatag; 318 sc->sc_last_stick = 0; 319 320 if (psycho0 == NULL) 321 psycho0 = sc; 322 DPRINTF(PDB_STICK, ("init psycho0 %lx\n", (long)sc)); 323 /* 324 * Identify the device. 325 */ 326 for (i=0; psycho_names[i].p_name; i++) 327 if (strcmp(model, psycho_names[i].p_name) == 0) { 328 sc->sc_mode = psycho_names[i].p_type; 329 goto found; 330 } 331 332 model = prom_getpropstring(ma->ma_node, "compatible"); 333 for (i=0; psycho_names[i].p_name; i++) 334 if (strcmp(model, psycho_names[i].p_name) == 0) { 335 sc->sc_mode = psycho_names[i].p_type; 336 goto found; 337 } 338 339 panic("unknown psycho model %s", model); 340 found: 341 342 /* 343 * The psycho gets three register banks: 344 * (0) per-PBM configuration and status registers 345 * (1) per-PBM PCI configuration space, containing only the 346 * PBM 256-byte PCI header 347 * (2) the shared psycho configuration registers (struct psychoreg) 348 */ 349 350 /* Register layouts are different. stuupid. */ 351 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) { 352 sc->sc_basepaddr = (paddr_t)ma->ma_reg[2].ur_paddr; 353 354 if (ma->ma_naddress > 2) { 355 sparc_promaddr_to_handle(sc->sc_bustag, 356 ma->ma_address[2], &sc->sc_bh); 357 sparc_promaddr_to_handle(sc->sc_bustag, 358 ma->ma_address[0], &pci_ctl); 359 360 sc->sc_regs = (struct psychoreg *) 361 bus_space_vaddr(sc->sc_bustag, sc->sc_bh); 362 } else if (ma->ma_nreg > 2) { 363 364 /* We need to map this in ourselves. */ 365 if (bus_space_map(sc->sc_bustag, 366 ma->ma_reg[2].ur_paddr, 367 ma->ma_reg[2].ur_len, BUS_SPACE_MAP_LINEAR, 368 &sc->sc_bh)) 369 panic("psycho_attach: cannot map regs"); 370 sc->sc_regs = (struct psychoreg *) 371 bus_space_vaddr(sc->sc_bustag, sc->sc_bh); 372 373 if (bus_space_map(sc->sc_bustag, 374 ma->ma_reg[0].ur_paddr, 375 ma->ma_reg[0].ur_len, BUS_SPACE_MAP_LINEAR, 376 &pci_ctl)) 377 panic("psycho_attach: cannot map ctl"); 378 } else 379 panic("psycho_attach: %d not enough registers", 380 ma->ma_nreg); 381 382 } else { 383 sc->sc_basepaddr = (paddr_t)ma->ma_reg[0].ur_paddr; 384 385 if (ma->ma_naddress) { 386 sparc_promaddr_to_handle(sc->sc_bustag, 387 ma->ma_address[0], &sc->sc_bh); 388 sc->sc_regs = (struct psychoreg *) 389 bus_space_vaddr(sc->sc_bustag, sc->sc_bh); 390 391 bus_space_subregion(sc->sc_bustag, sc->sc_bh, 392 offsetof(struct psychoreg, psy_pcictl), 393 sizeof(struct pci_ctl), &pci_ctl); 394 } else if (ma->ma_nreg) { 395 396 /* We need to map this in ourselves. */ 397 if (bus_space_map(sc->sc_bustag, 398 ma->ma_reg[0].ur_paddr, 399 ma->ma_reg[0].ur_len, BUS_SPACE_MAP_LINEAR, 400 &sc->sc_bh)) 401 panic("psycho_attach: cannot map regs"); 402 sc->sc_regs = (struct psychoreg *) 403 bus_space_vaddr(sc->sc_bustag, sc->sc_bh); 404 405 bus_space_subregion(sc->sc_bustag, sc->sc_bh, 406 offsetof(struct psychoreg, psy_pcictl), 407 sizeof(struct pci_ctl), &pci_ctl); 408 } else 409 panic("psycho_attach: %d not enough registers", 410 ma->ma_nreg); 411 } 412 413 csr = bus_space_read_8(sc->sc_bustag, sc->sc_bh, 414 offsetof(struct psychoreg, psy_csr)); 415 sc->sc_ign = 0x7c0; /* APB IGN is always 0x7c */ 416 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) 417 sc->sc_ign = PSYCHO_GCSR_IGN(csr) << 6; 418 419 aprint_normal_dev(self, "%s: impl %d, version %d: ign %x ", 420 model, PSYCHO_GCSR_IMPL(csr), PSYCHO_GCSR_VERS(csr), 421 sc->sc_ign); 422 /* 423 * Match other psycho's that are already configured against 424 * the base physical address. This will be the same for a 425 * pair of devices that share register space. 426 */ 427 for (n = 0; n < psycho_cd.cd_ndevs; n++) { 428 429 struct psycho_softc *asc = device_lookup_private(&psycho_cd, n); 430 431 if (asc == NULL || asc == sc) 432 /* This entry is not there or it is me */ 433 continue; 434 435 if (asc->sc_basepaddr != sc->sc_basepaddr) 436 /* This is an unrelated psycho */ 437 continue; 438 439 /* Found partner */ 440 osc = asc; 441 break; 442 } 443 444 445 /* Oh, dear. OK, lets get started */ 446 447 /* 448 * Setup the PCI control register 449 */ 450 csr = bus_space_read_8(sc->sc_bustag, pci_ctl, 451 offsetof(struct pci_ctl, pci_csr)); 452 csr |= PCICTL_MRLM | 453 PCICTL_ARB_PARK | 454 PCICTL_ERRINTEN | 455 PCICTL_4ENABLE; 456 csr &= ~(PCICTL_SERR | 457 PCICTL_CPU_PRIO | 458 PCICTL_ARB_PRIO | 459 PCICTL_RTRYWAIT); 460 bus_space_write_8(sc->sc_bustag, pci_ctl, 461 offsetof(struct pci_ctl, pci_csr), csr); 462 463 464 /* 465 * Allocate our psycho_pbm 466 */ 467 pp = sc->sc_psycho_this = kmem_zalloc(sizeof *pp, KM_SLEEP); 468 pp->pp_sc = sc; 469 470 /* grab the psycho ranges */ 471 psycho_get_ranges(sc->sc_node, &pp->pp_range, &pp->pp_nrange); 472 473 /* get the bus-range for the psycho */ 474 psycho_get_bus_range(sc->sc_node, psycho_br); 475 476 pba.pba_bus = psycho_br[0]; 477 pba.pba_bridgetag = NULL; 478 479 /* Fix up invalid 0x00-0xff bus-range, as found on SPARCle */ 480 if (psycho_br[0] == 0 && psycho_br[1] == 0xff) 481 psycho_fixup_bus_range(sc->sc_node, psycho_br); 482 483 aprint_normal("bus range %u to %u", psycho_br[0], psycho_br[1]); 484 aprint_normal("; PCI bus %d", psycho_br[0]); 485 486 pp->pp_pcictl = pci_ctl; 487 488 /* allocate our tags */ 489 pp->pp_memt = psycho_alloc_mem_tag(pp); 490 pp->pp_iot = psycho_alloc_io_tag(pp); 491 pp->pp_dmat = psycho_alloc_dma_tag(pp); 492 pp->pp_flags = (pp->pp_memt ? PCI_FLAGS_MEM_OKAY : 0) | 493 (pp->pp_iot ? PCI_FLAGS_IO_OKAY : 0); 494 495 /* allocate a chipset for this */ 496 pp->pp_pc = psycho_alloc_chipset(pp, sc->sc_node, &_sparc_pci_chipset); 497 pp->pp_pc->spc_busmax = psycho_br[1]; 498 499 switch((ma->ma_reg[0].ur_paddr) & 0xf000) { 500 case 0x2000: 501 pp->pp_id = PSYCHO_PBM_A; 502 break; 503 case 0x4000: 504 pp->pp_id = PSYCHO_PBM_B; 505 break; 506 } 507 508 aprint_normal("\n"); 509 510 /* allocate extents for free bus space */ 511 pp->pp_exmem = psycho_alloc_extent(pp, sc->sc_node, 0x02, "psycho mem"); 512 pp->pp_exio = psycho_alloc_extent(pp, sc->sc_node, 0x01, "psycho io"); 513 514 #ifdef DEBUG 515 if (psycho_debug & PDB_INTR) 516 psycho_dump_intmap(sc); 517 #endif 518 519 /* 520 * And finally, if we're a sabre or the first of a pair of psycho's to 521 * arrive here, start up the IOMMU and get a config space tag. 522 */ 523 if (osc == NULL) { 524 uint64_t timeo; 525 526 /* 527 * Establish handlers for interesting interrupts.... 528 * 529 * XXX We need to remember these and remove this to support 530 * hotplug on the UPA/FHC bus. 531 * 532 * XXX Not all controllers have these, but installing them 533 * is better than trying to sort through this mess. 534 */ 535 psycho_set_intr(sc, 15, psycho_ue, 536 &sc->sc_regs->ue_int_map, 537 &sc->sc_regs->ue_clr_int); 538 psycho_set_intr(sc, 1, psycho_ce, 539 &sc->sc_regs->ce_int_map, 540 &sc->sc_regs->ce_clr_int); 541 psycho_set_intr(sc, 15, psycho_bus_a, 542 &sc->sc_regs->pciaerr_int_map, 543 &sc->sc_regs->pciaerr_clr_int); 544 /* 545 * Netra X1 may hang when the powerfail interrupt is enabled. 546 */ 547 if (strcmp(machine_model, "SUNW,UltraAX-i2") != 0) { 548 psycho_set_intr(sc, 15, psycho_powerfail, 549 &sc->sc_regs->power_int_map, 550 &sc->sc_regs->power_clr_int); 551 psycho_register_power_button(sc); 552 } 553 if (sc->sc_mode != PSYCHO_MODE_SABRE) { 554 /* sabre doesn't have these interrupts */ 555 psycho_set_intr(sc, 15, psycho_bus_b, 556 &sc->sc_regs->pciberr_int_map, 557 &sc->sc_regs->pciberr_clr_int); 558 psycho_set_intr(sc, 1, psycho_wakeup, 559 &sc->sc_regs->pwrmgt_int_map, 560 &sc->sc_regs->pwrmgt_clr_int); 561 } 562 563 /* 564 * Apparently a number of machines with psycho and psycho+ 565 * controllers have interrupt latency issues. We'll try 566 * setting the interrupt retry timeout to 0xff which gives us 567 * a retry of 3-6 usec (which is what sysio is set to) for the 568 * moment, which seems to help alleviate this problem. 569 */ 570 timeo = sc->sc_regs->intr_retry_timer; 571 if (timeo > 0xfff) { 572 #ifdef DEBUG 573 printf("decreasing interrupt retry timeout " 574 "from %lx to 0xff\n", (long)timeo); 575 #endif 576 sc->sc_regs->intr_retry_timer = 0xff; 577 } 578 579 /* 580 * Allocate bus node, this contains a prom node per bus. 581 */ 582 pp->pp_pc->spc_busnode = 583 kmem_zalloc(sizeof(*pp->pp_pc->spc_busnode), KM_SLEEP); 584 585 /* 586 * Setup IOMMU and PCI configuration if we're the first 587 * of a pair of psycho's to arrive here. 588 * 589 * We should calculate a TSB size based on amount of RAM 590 * and number of bus controllers and number an type of 591 * child devices. 592 * 593 * For the moment, 32KB should be more than enough. 594 */ 595 sc->sc_is = kmem_alloc(sizeof(struct iommu_state), KM_SLEEP); 596 597 /* Point the strbuf_ctl at the iommu_state */ 598 pp->pp_sb.sb_is = sc->sc_is; 599 600 sc->sc_is->is_sb[0] = sc->sc_is->is_sb[1] = NULL; 601 if (prom_getproplen(sc->sc_node, "no-streaming-cache") < 0) { 602 struct strbuf_ctl *sb = &pp->pp_sb; 603 vaddr_t va = (vaddr_t)&pp->pp_flush[0x40]; 604 605 /* 606 * Initialize the strbuf_ctl. 607 * 608 * The flush sync buffer must be 64-byte aligned. 609 */ 610 sb->sb_flush = (void *)(va & ~0x3f); 611 612 bus_space_subregion(sc->sc_bustag, pci_ctl, 613 offsetof(struct pci_ctl, pci_strbuf), 614 sizeof (struct iommu_strbuf), &sb->sb_sb); 615 616 /* Point our iommu at the strbuf_ctl */ 617 sc->sc_is->is_sb[0] = sb; 618 } 619 620 psycho_iommu_init(sc, 2); 621 622 sc->sc_configtag = psycho_alloc_config_tag(sc->sc_psycho_this); 623 624 /* 625 * XXX This is a really ugly hack because PCI config space 626 * is explicitly handled with unmapped accesses. 627 */ 628 i = sc->sc_bustag->type; 629 sc->sc_bustag->type = PCI_CONFIG_BUS_SPACE; 630 if (bus_space_map(sc->sc_bustag, sc->sc_basepaddr + 0x01000000, 631 0x01000000, 0, &bh)) 632 panic("could not map psycho PCI configuration space"); 633 sc->sc_bustag->type = i; 634 sc->sc_configaddr = bh; 635 } else { 636 /* Share bus numbers with the pair of mine */ 637 pp->pp_pc->spc_busnode = 638 osc->sc_psycho_this->pp_pc->spc_busnode; 639 640 /* Just copy IOMMU state, config tag and address */ 641 sc->sc_is = osc->sc_is; 642 sc->sc_configtag = osc->sc_configtag; 643 sc->sc_configaddr = osc->sc_configaddr; 644 645 /* Point the strbuf_ctl at the iommu_state */ 646 pp->pp_sb.sb_is = sc->sc_is; 647 648 if (prom_getproplen(sc->sc_node, "no-streaming-cache") < 0) { 649 struct strbuf_ctl *sb = &pp->pp_sb; 650 vaddr_t va = (vaddr_t)&pp->pp_flush[0x40]; 651 652 /* 653 * Initialize the strbuf_ctl. 654 * 655 * The flush sync buffer must be 64-byte aligned. 656 */ 657 sb->sb_flush = (void *)(va & ~0x3f); 658 659 bus_space_subregion(sc->sc_bustag, pci_ctl, 660 offsetof(struct pci_ctl, pci_strbuf), 661 sizeof (struct iommu_strbuf), &sb->sb_sb); 662 663 /* Point our iommu at the strbuf_ctl */ 664 sc->sc_is->is_sb[1] = sb; 665 } 666 iommu_reset(sc->sc_is); 667 } 668 669 dict = device_properties(self); 670 pr = get_psychorange(pp, 2); /* memory range */ 671 #ifdef DEBUG 672 printf("memory range: %08x %08x\n", pr->phys_hi, pr->phys_lo); 673 #endif 674 mem_base = ((uint64_t)pr->phys_hi) << 32 | pr->phys_lo; 675 prop_dictionary_set_uint64(dict, "mem_base", mem_base); 676 677 /* 678 * attach the pci.. note we pass PCI A tags, etc., for the sabre here. 679 */ 680 pba.pba_flags = sc->sc_psycho_this->pp_flags; 681 pba.pba_dmat = sc->sc_psycho_this->pp_dmat; 682 pba.pba_dmat64 = NULL; 683 pba.pba_iot = sc->sc_psycho_this->pp_iot; 684 pba.pba_memt = sc->sc_psycho_this->pp_memt; 685 pba.pba_pc = pp->pp_pc; 686 687 config_found_ia(self, "pcibus", &pba, psycho_print); 688 } 689 690 static int 691 psycho_print(void *aux, const char *p) 692 { 693 694 if (p == NULL) 695 return (UNCONF); 696 return (QUIET); 697 } 698 699 static void 700 psycho_set_intr(struct psycho_softc *sc, int ipl, void *handler, 701 uint64_t *mapper, uint64_t *clearer) 702 { 703 struct intrhand *ih; 704 705 ih = intrhand_alloc(); 706 ih->ih_arg = sc; 707 ih->ih_map = mapper; 708 ih->ih_clr = clearer; 709 ih->ih_fun = handler; 710 ih->ih_pil = ipl; 711 ih->ih_number = INTVEC(*(ih->ih_map)); 712 ih->ih_pending = 0; 713 intr_establish(ipl, ipl != IPL_VM, ih); 714 *(ih->ih_map) |= INTMAP_V|(CPU_UPAID << INTMAP_TID_SHIFT); 715 } 716 717 /* 718 * power button handlers 719 */ 720 static void 721 psycho_register_power_button(struct psycho_softc *sc) 722 { 723 sysmon_task_queue_init(); 724 725 sc->sc_powerpressed = 0; 726 sc->sc_smcontext = kmem_zalloc(sizeof(struct sysmon_pswitch), KM_SLEEP); 727 sc->sc_smcontext->smpsw_name = device_xname(sc->sc_dev); 728 sc->sc_smcontext->smpsw_type = PSWITCH_TYPE_POWER; 729 if (sysmon_pswitch_register(sc->sc_smcontext) != 0) 730 aprint_error_dev(sc->sc_dev, "unable to register power button with sysmon\n"); 731 } 732 733 static void 734 psycho_power_button_pressed(void *arg) 735 { 736 struct psycho_softc *sc = arg; 737 738 sysmon_pswitch_event(sc->sc_smcontext, PSWITCH_EVENT_PRESSED); 739 sc->sc_powerpressed = 0; 740 } 741 742 /* 743 * PCI bus support 744 */ 745 746 /* 747 * allocate a PCI chipset tag and set its cookie. 748 */ 749 static pci_chipset_tag_t 750 psycho_alloc_chipset(struct psycho_pbm *pp, int node, pci_chipset_tag_t pc) 751 { 752 pci_chipset_tag_t npc; 753 754 npc = kmem_alloc(sizeof *npc, KM_SLEEP); 755 memcpy(npc, pc, sizeof *pc); 756 npc->cookie = pp; 757 npc->rootnode = node; 758 npc->spc_conf_read = psycho_pci_conf_read; 759 npc->spc_conf_write = psycho_pci_conf_write; 760 npc->spc_intr_map = NULL; 761 npc->spc_intr_establish = psycho_pci_intr_establish; 762 npc->spc_find_ino = psycho_pci_find_ino; 763 764 return (npc); 765 } 766 767 /* 768 * create extent for free bus space, then allocate assigned regions. 769 */ 770 static struct extent * 771 psycho_alloc_extent(struct psycho_pbm *pp, int node, int ss, const char *name) 772 { 773 struct psycho_registers *pa = NULL; 774 struct psycho_ranges *pr; 775 struct extent *ex; 776 bus_addr_t baddr, addr; 777 bus_size_t bsize, size; 778 int i, num; 779 780 /* get bus space size */ 781 pr = get_psychorange(pp, ss); 782 if (pr == NULL) { 783 printf("psycho_alloc_extent: get_psychorange failed\n"); 784 return NULL; 785 } 786 baddr = 0x00000000; 787 bsize = BUS_ADDR(pr->size_hi, pr->size_lo); 788 789 /* get available lists */ 790 num = 0; 791 if (prom_getprop(node, "available", sizeof(*pa), &num, &pa)) { 792 printf("psycho_alloc_extent: no \"available\" property\n"); 793 return NULL; 794 } 795 796 /* create extent */ 797 ex = extent_create(name, baddr, bsize - baddr - 1, 0, 0, EX_NOWAIT); 798 if (ex == NULL) { 799 printf("psycho_alloc_extent: extent_create failed\n"); 800 goto ret; 801 } 802 803 /* allocate assigned regions */ 804 for (i = 0; i < num; i++) 805 if (((pa[i].phys_hi >> 24) & 0x03) == ss) { 806 /* allocate bus space */ 807 addr = BUS_ADDR(pa[i].phys_mid, pa[i].phys_lo); 808 size = BUS_ADDR(pa[i].size_hi, pa[i].size_lo); 809 if (extent_alloc_region(ex, baddr, addr - baddr, 810 EX_NOWAIT)) { 811 printf("psycho_alloc_extent: " 812 "extent_alloc_region %" PRIx64 "-%" 813 PRIx64 " failed\n", baddr, addr); 814 extent_destroy(ex); 815 ex = NULL; 816 goto ret; 817 } 818 baddr = addr + size; 819 } 820 /* allocate left region if available */ 821 if (baddr < bsize) 822 if (extent_alloc_region(ex, baddr, bsize - baddr, EX_NOWAIT)) { 823 printf("psycho_alloc_extent: extent_alloc_region %" 824 PRIx64 "-%" PRIx64 " failed\n", baddr, bsize); 825 extent_destroy(ex); 826 ex = NULL; 827 goto ret; 828 } 829 830 #ifdef DEBUG 831 /* print extent */ 832 extent_print(ex); 833 #endif 834 835 ret: 836 /* return extent */ 837 free(pa, M_DEVBUF); 838 return ex; 839 } 840 841 /* 842 * grovel the OBP for various psycho properties 843 */ 844 static void 845 psycho_get_bus_range(int node, int *brp) 846 { 847 int n, error; 848 849 n = 2; 850 error = prom_getprop(node, "bus-range", sizeof(*brp), &n, &brp); 851 if (error) 852 panic("could not get psycho bus-range, error %d", error); 853 if (n != 2) 854 panic("broken psycho bus-range"); 855 DPRINTF(PDB_PROM, ("%s: got `bus-range' for node %08x: %u - %u\n", 856 __func__, node, brp[0], brp[1])); 857 } 858 859 static void 860 psycho_fixup_bus_range(int node0, int *brp0) 861 { 862 int node; 863 int len, busrange[2], *brp; 864 865 DPRINTF(PDB_PROM, 866 ("%s: fixing up `bus-range' for node %08x: %u - %u\n", 867 __func__, node0, brp0[0], brp0[1])); 868 869 /* 870 * Check all nodes under this one and increase the bus range to 871 * match. Recurse through PCI-PCI bridges. Cardbus bridges are 872 * fixed up in pccbb_attach_hook(). Assumes that "bus-range" for 873 * PCI-PCI bridges apart from this one is correct. 874 */ 875 brp0[1] = brp0[0]; 876 node = prom_firstchild(node0); 877 for (node = ((node)); node; node = prom_nextsibling(node)) { 878 len = 2; 879 brp = busrange; 880 if (prom_getprop(node, "bus-range", sizeof(*brp), 881 &len, &brp) != 0) 882 break; 883 if (len != 2) 884 break; 885 psycho_fixup_bus_range(node, busrange); 886 if (brp0[0] > busrange[0] && busrange[0] >= 0) 887 brp0[0] = busrange[0]; 888 if (brp0[1] < busrange[1] && busrange[1] < 256) 889 brp0[1] = busrange[1]; 890 } 891 892 DPRINTF(PDB_PROM, 893 ("%s: fixed up `bus-range' for node %08x: %u - %u\n", 894 __func__, node0, brp[0], brp[1])); 895 } 896 897 static void 898 psycho_get_ranges(int node, struct psycho_ranges **rp, int *np) 899 { 900 901 if (prom_getprop(node, "ranges", sizeof(**rp), np, rp)) 902 panic("could not get psycho ranges"); 903 DPRINTF(PDB_PROM, ("%s: got `ranges' for node %08x: %d entries\n", 904 __func__, node, *np)); 905 } 906 907 /* 908 * Interrupt handlers. 909 */ 910 911 static int 912 psycho_ue(void *arg) 913 { 914 struct psycho_softc *sc = (struct psycho_softc *)arg; 915 struct psychoreg *regs = sc->sc_regs; 916 struct iommu_state *is = sc->sc_is; 917 uint64_t afsr = regs->psy_ue_afsr; 918 uint64_t afar = regs->psy_ue_afar; 919 psize_t size = PAGE_SIZE << is->is_tsbsize; 920 char bits[128]; 921 922 /* 923 * It's uncorrectable. Dump the regs and panic. 924 */ 925 snprintb(bits, sizeof(bits), PSYCHO_UE_AFSR_BITS, afsr); 926 aprint_error_dev(sc->sc_dev, 927 "uncorrectable DMA error AFAR %" PRIx64 " AFSR %s\n", afar, bits); 928 929 /* Sometimes the AFAR points to an IOTSB entry */ 930 if (afar >= is->is_ptsb && afar < is->is_ptsb + size) { 931 aprint_error_dev(sc->sc_dev, 932 "IOVA %" PRIx64 " IOTTE %" PRIx64 "\n", 933 (afar - is->is_ptsb) / sizeof(is->is_tsb[0]) * PAGE_SIZE 934 + is->is_dvmabase, ldxa(afar, ASI_PHYS_CACHED)); 935 } 936 #ifdef DDB 937 Debugger(); 938 #endif 939 regs->psy_ue_afar = 0; 940 regs->psy_ue_afsr = 0; 941 return (1); 942 } 943 944 static int 945 psycho_ce(void *arg) 946 { 947 struct psycho_softc *sc = (struct psycho_softc *)arg; 948 struct psychoreg *regs = sc->sc_regs; 949 950 /* 951 * It's correctable. Dump the regs and continue. 952 */ 953 aprint_error_dev(sc->sc_dev, 954 "correctable DMA error AFAR %" PRIx64 " AFSR %" PRIx64 "\n", 955 regs->psy_ce_afar, regs->psy_ce_afsr); 956 return (1); 957 } 958 959 static int 960 psycho_bus_a(void *arg) 961 { 962 struct psycho_softc *sc = (struct psycho_softc *)arg; 963 struct psychoreg *regs = sc->sc_regs; 964 965 /* 966 * It's uncorrectable. Dump the regs and panic. 967 */ 968 969 panic("%s: PCI bus A error AFAR %" PRIx64 " AFSR %" PRIx64, 970 device_xname(sc->sc_dev), 971 regs->psy_pcictl[0].pci_afar, regs->psy_pcictl[0].pci_afsr); 972 return (1); 973 } 974 975 static int 976 psycho_bus_b(void *arg) 977 { 978 struct psycho_softc *sc = (struct psycho_softc *)arg; 979 struct psychoreg *regs = sc->sc_regs; 980 981 /* 982 * It's uncorrectable. Dump the regs and panic. 983 */ 984 985 panic("%s: PCI bus B error AFAR %" PRIx64 " AFSR %" PRIx64, 986 device_xname(sc->sc_dev), 987 regs->psy_pcictl[0].pci_afar, regs->psy_pcictl[0].pci_afsr); 988 return (1); 989 } 990 991 static int 992 psycho_powerfail(void *arg) 993 { 994 struct psycho_softc *sc = (struct psycho_softc *)arg; 995 996 /* 997 * We lost power. Queue a callback with thread context to 998 * handle all the real work. 999 */ 1000 if (sc->sc_powerpressed == 0 && sc->sc_smcontext != NULL) { 1001 sc->sc_powerpressed = 1; 1002 sysmon_task_queue_sched(0, psycho_power_button_pressed, sc); 1003 } 1004 return (1); 1005 } 1006 1007 static 1008 int psycho_wakeup(void *arg) 1009 { 1010 struct psycho_softc *sc = (struct psycho_softc *)arg; 1011 1012 /* 1013 * Gee, we don't really have a framework to deal with this 1014 * properly. 1015 */ 1016 aprint_error_dev(sc->sc_dev, "power management wakeup\n"); 1017 return (1); 1018 } 1019 1020 1021 /* 1022 * initialise the IOMMU.. 1023 */ 1024 void 1025 psycho_iommu_init(struct psycho_softc *sc, int tsbsize) 1026 { 1027 char *name; 1028 struct iommu_state *is = sc->sc_is; 1029 uint32_t iobase = -1; 1030 int *vdma = NULL; 1031 int nitem; 1032 1033 /* punch in our copies */ 1034 is->is_bustag = sc->sc_bustag; 1035 bus_space_subregion(sc->sc_bustag, sc->sc_bh, 1036 offsetof(struct psychoreg, psy_iommu), 1037 sizeof (struct iommureg), 1038 &is->is_iommu); 1039 1040 /* 1041 * Separate the men from the boys. Get the `virtual-dma' 1042 * property for sabre and use that to make sure the damn 1043 * iommu works. 1044 * 1045 * We could query the `#virtual-dma-size-cells' and 1046 * `#virtual-dma-addr-cells' and DTRT, but I'm lazy. 1047 */ 1048 nitem = 0; 1049 if (!prom_getprop(sc->sc_node, "virtual-dma", sizeof(vdma), &nitem, 1050 &vdma)) { 1051 /* Damn. Gotta use these values. */ 1052 iobase = vdma[0]; 1053 #define TSBCASE(x) case 1<<((x)+23): tsbsize = (x); break 1054 switch (vdma[1]) { 1055 TSBCASE(1); 1056 TSBCASE(2); 1057 TSBCASE(3); 1058 TSBCASE(4); 1059 TSBCASE(5); 1060 TSBCASE(6); 1061 TSBCASE(7); 1062 default: 1063 printf("bogus tsb size %x, using 7\n", vdma[1]); 1064 tsbsize = 7; 1065 } 1066 #undef TSBCASE 1067 } 1068 1069 /* give us a nice name.. */ 1070 name = kmem_asprintf("%s dvma", device_xname(sc->sc_dev)); 1071 1072 iommu_init(name, is, tsbsize, iobase); 1073 } 1074 1075 /* 1076 * below here is bus space and bus DMA support 1077 */ 1078 bus_space_tag_t 1079 psycho_alloc_bus_tag(struct psycho_pbm *pp, int type) 1080 { 1081 struct psycho_softc *sc = pp->pp_sc; 1082 bus_space_tag_t bt; 1083 1084 bt = kmem_zalloc(sizeof(*bt), KM_SLEEP); 1085 bt->cookie = pp; 1086 bt->parent = sc->sc_bustag; 1087 bt->type = type; 1088 bt->sparc_bus_map = _psycho_bus_map; 1089 bt->sparc_bus_mmap = psycho_bus_mmap; 1090 bt->sparc_intr_establish = psycho_intr_establish; 1091 return (bt); 1092 } 1093 1094 bus_dma_tag_t 1095 psycho_alloc_dma_tag(struct psycho_pbm *pp) 1096 { 1097 struct psycho_softc *sc = pp->pp_sc; 1098 bus_dma_tag_t dt, pdt = sc->sc_dmatag; 1099 1100 dt = kmem_zalloc(sizeof(*dt), KM_SLEEP); 1101 dt->_cookie = pp; 1102 dt->_parent = pdt; 1103 #define PCOPY(x) dt->x = pdt->x 1104 dt->_dmamap_create = psycho_dmamap_create; 1105 PCOPY(_dmamap_destroy); 1106 dt->_dmamap_load = iommu_dvmamap_load; 1107 PCOPY(_dmamap_load_mbuf); 1108 PCOPY(_dmamap_load_uio); 1109 dt->_dmamap_load_raw = iommu_dvmamap_load_raw; 1110 dt->_dmamap_unload = iommu_dvmamap_unload; 1111 if (sc->sc_mode == PSYCHO_MODE_SABRE) 1112 dt->_dmamap_sync = psycho_sabre_dmamap_sync; 1113 else 1114 dt->_dmamap_sync = iommu_dvmamap_sync; 1115 dt->_dmamem_alloc = iommu_dvmamem_alloc; 1116 dt->_dmamem_free = iommu_dvmamem_free; 1117 dt->_dmamem_map = iommu_dvmamem_map; 1118 dt->_dmamem_unmap = iommu_dvmamem_unmap; 1119 PCOPY(_dmamem_mmap); 1120 #undef PCOPY 1121 return (dt); 1122 } 1123 1124 /* 1125 * bus space support. <sparc64/dev/psychoreg.h> has a discussion about 1126 * PCI physical addresses. 1127 */ 1128 1129 static struct psycho_ranges * 1130 get_psychorange(struct psycho_pbm *pp, int ss) 1131 { 1132 int i; 1133 1134 for (i = 0; i < pp->pp_nrange; i++) { 1135 if (((pp->pp_range[i].cspace >> 24) & 0x03) == ss) 1136 return (&pp->pp_range[i]); 1137 } 1138 /* not found */ 1139 return (NULL); 1140 } 1141 1142 static int 1143 _psycho_bus_map(bus_space_tag_t t, bus_addr_t offset, bus_size_t size, 1144 int flags, vaddr_t unused, bus_space_handle_t *hp) 1145 { 1146 struct psycho_pbm *pp = t->cookie; 1147 struct psycho_softc *sc = pp->pp_sc; 1148 struct psycho_ranges *pr; 1149 bus_addr_t paddr; 1150 int ss; 1151 1152 DPRINTF(PDB_BUSMAP, 1153 ("%s: type %d off %qx sz %qx flags %d", 1154 __func__, t->type, (unsigned long long)offset, 1155 (unsigned long long)size, flags)); 1156 1157 flags &= ~BUS_SPACE_MAP_PREFETCHABLE; 1158 1159 ss = sparc_pci_childspace(t->type); 1160 DPRINTF(PDB_BUSMAP, (" cspace %d", ss)); 1161 1162 pr = get_psychorange(pp, ss); 1163 if (pr != NULL) { 1164 paddr = BUS_ADDR(pr->phys_hi, pr->phys_lo + offset); 1165 DPRINTF(PDB_BUSMAP, ("\n%s: mapping paddr " 1166 "space %lx offset %lx paddr %qx\n", 1167 __func__, (long)ss, (long)offset, 1168 (unsigned long long)paddr)); 1169 return ((*sc->sc_bustag->sparc_bus_map)(t, paddr, size, 1170 flags, 0, hp)); 1171 } 1172 DPRINTF(PDB_BUSMAP, (" FAILED\n")); 1173 return (EINVAL); 1174 } 1175 1176 static paddr_t 1177 psycho_bus_mmap(bus_space_tag_t t, bus_addr_t paddr, off_t off, int prot, 1178 int flags) 1179 { 1180 bus_addr_t offset = paddr; 1181 struct psycho_pbm *pp = t->cookie; 1182 struct psycho_softc *sc = pp->pp_sc; 1183 struct psycho_ranges *pr; 1184 int ss; 1185 1186 flags &= ~BUS_SPACE_MAP_PREFETCHABLE; 1187 1188 ss = sparc_pci_childspace(t->type); 1189 1190 DPRINTF(PDB_BUSMAP, ("%s: prot %x flags %d busaddr %qx\n", 1191 __func__, prot, flags, (unsigned long long)paddr)); 1192 1193 pr = get_psychorange(pp, ss); 1194 if (pr != NULL) { 1195 paddr = BUS_ADDR(pr->phys_hi, pr->phys_lo + offset); 1196 DPRINTF(PDB_BUSMAP, ("%s: mapping paddr " 1197 "space %lx offset %lx paddr %qx\n", 1198 __func__, (long)ss, (long)offset, 1199 (unsigned long long)paddr)); 1200 return (bus_space_mmap(sc->sc_bustag, paddr, off, 1201 prot, flags)); 1202 } 1203 1204 return (-1); 1205 } 1206 1207 /* 1208 * Get a PCI offset address from bus_space_handle_t. 1209 */ 1210 bus_addr_t 1211 psycho_bus_offset(bus_space_tag_t t, bus_space_handle_t *hp) 1212 { 1213 struct psycho_pbm *pp = t->cookie; 1214 struct psycho_ranges *pr; 1215 bus_addr_t addr, offset; 1216 vaddr_t va; 1217 int ss; 1218 1219 addr = hp->_ptr; 1220 ss = sparc_pci_childspace(t->type); 1221 DPRINTF(PDB_BUSMAP, ("%s: type %d addr %" PRIx64" cspace %d", 1222 __func__, t->type, addr, ss)); 1223 1224 pr = get_psychorange(pp, ss); 1225 if (pr != NULL) { 1226 if (!PHYS_ASI(hp->_asi)) { 1227 va = trunc_page((vaddr_t)addr); 1228 if (pmap_extract(pmap_kernel(), va, &addr) == FALSE) { 1229 DPRINTF(PDB_BUSMAP, 1230 ("- pmap_extract FAILED\n")); 1231 return (-1); 1232 } 1233 addr += hp->_ptr & PGOFSET; 1234 } 1235 offset = BUS_ADDR_PADDR(addr) - pr->phys_lo; 1236 DPRINTF(PDB_BUSMAP, ("- paddr %" PRIx64" offset %" PRIx64 "\n", 1237 addr, offset)); 1238 return (offset); 1239 } 1240 DPRINTF(PDB_BUSMAP, ("- FAILED\n")); 1241 return (-1); 1242 } 1243 1244 1245 /* 1246 * install an interrupt handler for a PCI device 1247 */ 1248 void * 1249 psycho_intr_establish(bus_space_tag_t t, int ihandle, int level, 1250 int (*handler)(void *), void *arg, void (*fastvec)(void) /* ignored */) 1251 { 1252 struct psycho_pbm *pp = t->cookie; 1253 struct psycho_softc *sc = pp->pp_sc; 1254 struct intrhand *ih; 1255 volatile uint64_t *intrmapptr = NULL, *intrclrptr = NULL; 1256 int64_t imap = 0; 1257 int ino; 1258 long vec = INTVEC(ihandle); 1259 1260 ih = intrhand_alloc(); 1261 1262 ih->ih_ivec = ihandle; 1263 1264 /* 1265 * Hunt through all the interrupt mapping regs to look for our 1266 * interrupt vector. 1267 * 1268 * XXX We only compare INOs rather than IGNs since the firmware may 1269 * not provide the IGN and the IGN is constant for all device on that 1270 * PCI controller. This could cause problems for the FFB/external 1271 * interrupt which has a full vector that can be set arbitrarily. 1272 */ 1273 1274 DPRINTF(PDB_INTR, ("%s: ihandle %x vec %lx", __func__, ihandle, vec)); 1275 ino = INTINO(vec); 1276 DPRINTF(PDB_INTR, (" ino %x\n", ino)); 1277 1278 /* If the device didn't ask for an IPL, use the one encoded. */ 1279 if (level == IPL_NONE) level = INTLEV(vec); 1280 /* If it still has no level, print a warning and assign IPL 2 */ 1281 if (level == IPL_NONE) { 1282 printf("ERROR: no IPL, setting IPL 2.\n"); 1283 level = 2; 1284 } 1285 1286 DPRINTF(PDB_INTR, ("%s: intr %lx: %p\nHunting for IRQ...\n", 1287 __func__, (long)ino, intrlev[ino])); 1288 1289 /* 1290 * First look for PCI interrupts, otherwise the PCI A slot 0 1291 * INTA# interrupt might match an unused non-PCI (obio) 1292 * interrupt. 1293 */ 1294 for (intrmapptr = &sc->sc_regs->pcia_slot0_int, 1295 intrclrptr = &sc->sc_regs->pcia0_clr_int[0]; 1296 intrmapptr <= &sc->sc_regs->pcib_slot3_int; 1297 intrmapptr++, intrclrptr += 4) { 1298 if (sc->sc_mode == PSYCHO_MODE_PSYCHO && 1299 (intrmapptr == &sc->sc_regs->pcia_slot2_int || 1300 intrmapptr == &sc->sc_regs->pcia_slot3_int)) 1301 continue; 1302 if (((*intrmapptr ^ vec) & 0x3c) == 0) { 1303 intrclrptr += vec & 0x3; 1304 goto found; 1305 } 1306 } 1307 1308 /* Now hunt thru obio. */ 1309 for (intrmapptr = &sc->sc_regs->scsi_int_map, 1310 intrclrptr = &sc->sc_regs->scsi_clr_int; 1311 intrmapptr < &sc->sc_regs->ue_int_map; 1312 intrmapptr++, intrclrptr++) { 1313 if (INTINO(*intrmapptr) == ino) 1314 goto found; 1315 } 1316 1317 /* Finally check the two FFB slots */ 1318 intrclrptr = NULL; /* XXX? */ 1319 for (intrmapptr = &sc->sc_regs->ffb0_int_map; 1320 intrmapptr <= &sc->sc_regs->ffb1_int_map; 1321 intrmapptr++) { 1322 if (INTVEC(*intrmapptr) == ino) 1323 goto found; 1324 } 1325 1326 printf("Cannot find interrupt vector %lx\n", vec); 1327 kmem_free(ih, sizeof(*ih)); 1328 return (NULL); 1329 1330 found: 1331 /* Register the map and clear intr registers */ 1332 ih->ih_map = intrmapptr; 1333 ih->ih_clr = intrclrptr; 1334 1335 ih->ih_fun = handler; 1336 ih->ih_arg = arg; 1337 ih->ih_pil = level; 1338 ih->ih_number = ino | sc->sc_ign; 1339 ih->ih_pending = 0; 1340 1341 DPRINTF(PDB_INTR, ( 1342 "%s: installing handler %p arg %p with ino %u pil %u\n", 1343 __func__, handler, arg, (u_int)ino, (u_int)ih->ih_pil)); 1344 1345 intr_establish(ih->ih_pil, level != IPL_VM, ih); 1346 1347 /* 1348 * Enable the interrupt now we have the handler installed. 1349 * Read the current value as we can't change it besides the 1350 * valid bit so so make sure only this bit is changed. 1351 * 1352 * XXXX --- we really should use bus_space for this. 1353 */ 1354 if (intrmapptr) { 1355 imap = *intrmapptr; 1356 DPRINTF(PDB_INTR, ("%s: read intrmap = %016qx", 1357 __func__, (unsigned long long)imap)); 1358 1359 /* Enable the interrupt */ 1360 imap |= INTMAP_V|(CPU_UPAID << INTMAP_TID_SHIFT); 1361 DPRINTF(PDB_INTR, ("; addr of intrmapptr = %p", intrmapptr)); 1362 DPRINTF(PDB_INTR, ("; writing intrmap = %016qx\n", 1363 (unsigned long long)imap)); 1364 *intrmapptr = imap; 1365 DPRINTF(PDB_INTR, ("; reread intrmap = %016qx\n", 1366 (unsigned long long)(imap = *intrmapptr))); 1367 } 1368 if (intrclrptr) { 1369 /* set state to IDLE */ 1370 *intrclrptr = 0; 1371 } 1372 return (ih); 1373 } 1374 1375 /* 1376 * per-controller driver calls 1377 */ 1378 1379 /* assume we are mapped little-endian/side-effect */ 1380 static pcireg_t 1381 psycho_pci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg) 1382 { 1383 struct psycho_pbm *pp = pc->cookie; 1384 struct psycho_softc *sc = pp->pp_sc; 1385 pcireg_t val = (pcireg_t)~0; 1386 int s; 1387 1388 DPRINTF(PDB_CONF, ("%s: tag %lx reg %x ", __func__, 1389 (long)tag, reg)); 1390 if (PCITAG_NODE(tag) != -1 && (unsigned int)reg < PCI_CONF_SIZE) { 1391 1392 DPRINTF(PDB_CONF, ("asi=%x addr=%qx (offset=%x) ...", 1393 sc->sc_configaddr._asi, 1394 (long long)(sc->sc_configaddr._ptr + 1395 PCITAG_OFFSET(tag) + reg), 1396 (int)PCITAG_OFFSET(tag) + reg)); 1397 1398 s = splhigh(); 1399 struct cpu_info *ci = curcpu(); 1400 ci->ci_pci_probe = true; 1401 membar_Sync(); 1402 val = bus_space_read_4(sc->sc_configtag, sc->sc_configaddr, 1403 PCITAG_OFFSET(tag) + reg); 1404 membar_Sync(); 1405 if (ci->ci_pci_fault) 1406 val = (pcireg_t)~0; 1407 ci->ci_pci_probe = ci->ci_pci_fault = false; 1408 splx(s); 1409 } 1410 #ifdef DEBUG 1411 else DPRINTF(PDB_CONF, ("%s: bogus pcitag %x -", __func__, 1412 (int)PCITAG_OFFSET(tag))); 1413 #endif 1414 DPRINTF(PDB_CONF, (" returning %08x\n", (u_int)val)); 1415 1416 return (val); 1417 } 1418 1419 static void 1420 psycho_pci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data) 1421 { 1422 struct psycho_pbm *pp = pc->cookie; 1423 struct psycho_softc *sc = pp->pp_sc; 1424 1425 DPRINTF(PDB_CONF, ("%s: tag %lx; reg %x; data %x; ", __func__, 1426 (long)PCITAG_OFFSET(tag), reg, (int)data)); 1427 DPRINTF(PDB_CONF, ("asi = %x; readaddr = %qx (offset = %x)\n", 1428 sc->sc_configaddr._asi, 1429 (long long)(sc->sc_configaddr._ptr + PCITAG_OFFSET(tag) + reg), 1430 (int)PCITAG_OFFSET(tag) + reg)); 1431 1432 /* If we don't know it, just punt it. */ 1433 if (PCITAG_NODE(tag) == -1) { 1434 DPRINTF(PDB_CONF, ("%s: bad addr", __func__)); 1435 return; 1436 } 1437 1438 if ((unsigned int)reg >= PCI_CONF_SIZE) 1439 return; 1440 1441 bus_space_write_4(sc->sc_configtag, sc->sc_configaddr, 1442 PCITAG_OFFSET(tag) + reg, data); 1443 } 1444 1445 static void * 1446 psycho_pci_intr_establish(pci_chipset_tag_t pc, pci_intr_handle_t ih, int level, 1447 int (*func)(void *), void *arg) 1448 { 1449 void *cookie; 1450 struct psycho_pbm *pp = (struct psycho_pbm *)pc->cookie; 1451 1452 DPRINTF(PDB_INTR, ("%s: ih %lx; level %d", __func__, (u_long)ih, level)); 1453 cookie = bus_intr_establish(pp->pp_memt, ih, level, func, arg); 1454 1455 DPRINTF(PDB_INTR, ("; returning handle %p\n", cookie)); 1456 return (cookie); 1457 } 1458 1459 static int 1460 psycho_pci_find_ino(const struct pci_attach_args *pa, pci_intr_handle_t *ihp) 1461 { 1462 struct psycho_pbm *pp = pa->pa_pc->cookie; 1463 struct psycho_softc *sc = pp->pp_sc; 1464 u_int bus; 1465 u_int dev; 1466 u_int pin; 1467 1468 DPRINTF(PDB_INTMAP, ("%s: pa_tag: node %x, %d:%d:%d\n", __func__, 1469 PCITAG_NODE(pa->pa_tag), (int)PCITAG_BUS(pa->pa_tag), 1470 (int)PCITAG_DEV(pa->pa_tag), 1471 (int)PCITAG_FUN(pa->pa_tag))); 1472 DPRINTF(PDB_INTMAP, 1473 ("%s: intrswiz %d, intrpin %d, intrline %d, rawintrpin %d\n", __func__, 1474 pa->pa_intrswiz, pa->pa_intrpin, pa->pa_intrline, pa->pa_rawintrpin)); 1475 DPRINTF(PDB_INTMAP, ("%s: pa_intrtag: node %x, %d:%d:%d\n", __func__, 1476 PCITAG_NODE(pa->pa_intrtag), 1477 (int)PCITAG_BUS(pa->pa_intrtag), 1478 (int)PCITAG_DEV(pa->pa_intrtag), 1479 (int)PCITAG_FUN(pa->pa_intrtag))); 1480 1481 bus = (pp->pp_id == PSYCHO_PBM_B); 1482 /* 1483 * If we are on a ppb, use the devno on the underlying bus when forming 1484 * the ivec. 1485 */ 1486 if (pa->pa_intrswiz != 0 && PCITAG_NODE(pa->pa_intrtag) != 0) 1487 dev = PCITAG_DEV(pa->pa_intrtag); 1488 else 1489 dev = pa->pa_device; 1490 dev--; 1491 1492 if (sc->sc_mode == PSYCHO_MODE_PSYCHO && 1493 pp->pp_id == PSYCHO_PBM_B) 1494 dev--; 1495 1496 pin = pa->pa_intrpin - 1; 1497 DPRINTF(PDB_INTMAP, ("%s: mode %d, pbm %d, dev %d, pin %d\n", __func__, 1498 sc->sc_mode, pp->pp_id, dev, pin)); 1499 1500 *ihp = sc->sc_ign | ((bus << 4) & INTMAP_PCIBUS) | 1501 ((dev << 2) & INTMAP_PCISLOT) | (pin & INTMAP_PCIINT); 1502 1503 return (0); 1504 } 1505 1506 /* 1507 * hooks into the iommu dvma calls. 1508 */ 1509 static int 1510 psycho_dmamap_create(bus_dma_tag_t t, bus_size_t size, int nsegments, 1511 bus_size_t maxsegsz, bus_size_t boundary, int flags, 1512 bus_dmamap_t *dmamp) 1513 { 1514 struct psycho_pbm *pp = (struct psycho_pbm *)t->_cookie; 1515 int error; 1516 1517 error = bus_dmamap_create(t->_parent, size, nsegments, maxsegsz, 1518 boundary, flags, dmamp); 1519 if (error == 0) 1520 (*dmamp)->_dm_cookie = &pp->pp_sb; 1521 return error; 1522 } 1523 1524 /* 1525 * UltraSPARC IIi and IIe have no streaming buffers, but have PCI DMA 1526 * Write Synchronization Register (see UltraSPARC-IIi User's Manual 1527 * section 19.3.0.5). So use it to synchronize with the DMA writes. 1528 */ 1529 static void 1530 psycho_sabre_dmamap_sync(bus_dma_tag_t t, bus_dmamap_t map, bus_addr_t offset, 1531 bus_size_t len, int ops) 1532 { 1533 struct psycho_pbm *pp; 1534 struct psycho_softc *sc; 1535 1536 /* If len is 0, then there is nothing to do. */ 1537 if (len == 0) 1538 return; 1539 1540 if (ops & BUS_DMASYNC_POSTREAD) { 1541 pp = (struct psycho_pbm *)t->_cookie; 1542 sc = pp->pp_sc; 1543 bus_space_read_8(sc->sc_bustag, sc->sc_bh, 1544 offsetof(struct psychoreg, pci_dma_write_sync)); 1545 } 1546 bus_dmamap_sync(t->_parent, map, offset, len, ops); 1547 } 1548 1549 /* US-IIe STICK support */ 1550 1551 uint64_t 1552 psycho_getstick(void) 1553 { 1554 uint64_t stick; 1555 1556 stick = bus_space_read_8(psycho0->sc_bustag, psycho0->sc_bh, 1557 STICK_CNT_LOW) | 1558 (bus_space_read_8(psycho0->sc_bustag, psycho0->sc_bh, 1559 STICK_CNT_HIGH) & 0x7fffffff) << 32; 1560 return stick; 1561 } 1562 1563 uint32_t 1564 psycho_getstick32(void) 1565 { 1566 1567 return bus_space_read_8(psycho0->sc_bustag, psycho0->sc_bh, 1568 STICK_CNT_LOW); 1569 } 1570 1571 void 1572 psycho_setstick(long cnt) 1573 { 1574 1575 /* 1576 * looks like we can't actually write the STICK counter, so instead we 1577 * prepare sc_last_stick for the coming interrupt setup 1578 */ 1579 #if 0 1580 bus_space_write_8(psycho0->sc_bustag, psycho0->sc_bh, 1581 STICK_CNT_HIGH, (cnt >> 32)); 1582 bus_space_write_8(psycho0->sc_bustag, psycho0->sc_bh, 1583 STICK_CNT_LOW, (uint32_t)(cnt & 0xffffffff)); 1584 #endif 1585 1586 if (cnt == 0) { 1587 bus_space_write_8(psycho0->sc_bustag, psycho0->sc_bh, 1588 STICK_CMP_HIGH, 0); 1589 bus_space_write_8(psycho0->sc_bustag, psycho0->sc_bh, 1590 STICK_CMP_LOW, 0); 1591 psycho0->sc_last_stick = 0; 1592 } 1593 1594 psycho0->sc_last_stick = psycho_getstick(); 1595 DPRINTF(PDB_STICK, ("%s: %ld\n", __func__, psycho0->sc_last_stick)); 1596 } 1597 1598 void 1599 psycho_nextstick(long diff) 1600 { 1601 uint64_t cmp, now; 1602 1603 /* 1604 * there is no way we'll ever overflow 1605 * the counter is 63 bits wide, at 12MHz that's >24000 years 1606 */ 1607 now = psycho_getstick() + 1000; 1608 cmp = psycho0->sc_last_stick; 1609 1610 while (cmp < now) 1611 cmp += diff; 1612 1613 bus_space_write_8(psycho0->sc_bustag, psycho0->sc_bh, 1614 STICK_CMP_HIGH, (cmp >> 32) & 0x7fffffff); 1615 bus_space_write_8(psycho0->sc_bustag, psycho0->sc_bh, 1616 STICK_CMP_LOW, (cmp & 0xffffffff)); 1617 1618 psycho0->sc_last_stick = cmp; 1619 } 1620
Indexes created Thu Sep 25 16:09:42 GMT 2025