psycho.c revision 1.66
1 /* $NetBSD: psycho.c,v 1.66 2003/08/27 15:59:54 mrg Exp $ */ 2 3 /* 4 * Copyright (c) 2001, 2002 Eduardo E. Horvath 5 * Copyright (c) 1999, 2000 Matthew R. Green 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. The name of the author may not be used to endorse or promote products 17 * derived from this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 24 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 26 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 27 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: psycho.c,v 1.66 2003/08/27 15:59:54 mrg Exp $"); 34 35 #include "opt_ddb.h" 36 37 /* 38 * Support for `psycho' and `psycho+' UPA to PCI bridge and 39 * UltraSPARC IIi and IIe `sabre' PCI controllers. 40 */ 41 42 #ifdef DEBUG 43 #define PDB_PROM 0x01 44 #define PDB_BUSMAP 0x02 45 #define PDB_INTR 0x04 46 int psycho_debug = 0x0; 47 #define DPRINTF(l, s) do { if (psycho_debug & l) printf s; } while (0) 48 #else 49 #define DPRINTF(l, s) 50 #endif 51 52 #include <sys/param.h> 53 #include <sys/device.h> 54 #include <sys/errno.h> 55 #include <sys/extent.h> 56 #include <sys/malloc.h> 57 #include <sys/systm.h> 58 #include <sys/time.h> 59 #include <sys/reboot.h> 60 61 #include <uvm/uvm.h> 62 63 #define _SPARC_BUS_DMA_PRIVATE 64 #include <machine/bus.h> 65 #include <machine/autoconf.h> 66 #include <machine/psl.h> 67 68 #include <dev/pci/pcivar.h> 69 #include <dev/pci/pcireg.h> 70 #include <dev/sysmon/sysmon_taskq.h> 71 72 #include <sparc64/dev/iommureg.h> 73 #include <sparc64/dev/iommuvar.h> 74 #include <sparc64/dev/psychoreg.h> 75 #include <sparc64/dev/psychovar.h> 76 #include <sparc64/sparc64/cache.h> 77 78 #include "ioconf.h" 79 80 static pci_chipset_tag_t psycho_alloc_chipset __P((struct psycho_pbm *, int, 81 pci_chipset_tag_t)); 82 static struct extent *psycho_alloc_extent __P((struct psycho_pbm *, int, int, 83 char *)); 84 static void psycho_get_bus_range __P((int, int *)); 85 static void psycho_get_ranges __P((int, struct psycho_ranges **, int *)); 86 static void psycho_set_intr __P((struct psycho_softc *, int, void *, 87 u_int64_t *, u_int64_t *)); 88 89 /* Interrupt handlers */ 90 static int psycho_ue __P((void *)); 91 static int psycho_ce __P((void *)); 92 static int psycho_bus_a __P((void *)); 93 static int psycho_bus_b __P((void *)); 94 static int psycho_powerfail __P((void *)); 95 static int psycho_wakeup __P((void *)); 96 97 98 /* IOMMU support */ 99 static void psycho_iommu_init __P((struct psycho_softc *, int)); 100 101 /* 102 * bus space and bus DMA support for UltraSPARC `psycho'. note that most 103 * of the bus DMA support is provided by the iommu dvma controller. 104 */ 105 static int get_childspace __P((int)); 106 static struct psycho_ranges *get_psychorange __P((struct psycho_pbm *, int)); 107 108 static paddr_t psycho_bus_mmap __P((bus_space_tag_t, bus_addr_t, off_t, 109 int, int)); 110 static int _psycho_bus_map __P((bus_space_tag_t, bus_addr_t, bus_size_t, int, 111 vaddr_t, bus_space_handle_t *)); 112 static void *psycho_intr_establish __P((bus_space_tag_t, int, int, 113 int (*) __P((void *)), void *, void(*)__P((void)))); 114 115 static int psycho_dmamap_load __P((bus_dma_tag_t, bus_dmamap_t, void *, 116 bus_size_t, struct proc *, int)); 117 static void psycho_dmamap_unload __P((bus_dma_tag_t, bus_dmamap_t)); 118 static int psycho_dmamap_load_raw __P((bus_dma_tag_t, bus_dmamap_t, 119 bus_dma_segment_t *, int, bus_size_t, int)); 120 static void psycho_dmamap_sync __P((bus_dma_tag_t, bus_dmamap_t, bus_addr_t, 121 bus_size_t, int)); 122 int psycho_dmamem_alloc __P((bus_dma_tag_t, bus_size_t, bus_size_t, bus_size_t, 123 bus_dma_segment_t *, int, int *, int)); 124 void psycho_dmamem_free __P((bus_dma_tag_t, bus_dma_segment_t *, int)); 125 int psycho_dmamem_map __P((bus_dma_tag_t, bus_dma_segment_t *, int, size_t, 126 caddr_t *, int)); 127 void psycho_dmamem_unmap __P((bus_dma_tag_t, caddr_t, size_t)); 128 129 /* base pci_chipset */ 130 extern struct sparc_pci_chipset _sparc_pci_chipset; 131 132 /* power button handlers */ 133 static void psycho_register_power_button(struct psycho_softc *sc); 134 static void psycho_power_button_pressed(void *arg); 135 136 /* 137 * autoconfiguration 138 */ 139 static int psycho_match __P((struct device *, struct cfdata *, void *)); 140 static void psycho_attach __P((struct device *, struct device *, void *)); 141 static int psycho_print __P((void *aux, const char *p)); 142 143 CFATTACH_DECL(psycho, sizeof(struct psycho_softc), 144 psycho_match, psycho_attach, NULL, NULL); 145 146 /* 147 * "sabre" is the UltraSPARC IIi onboard UPA to PCI bridge. It manages a 148 * single PCI bus and does not have a streaming buffer. It often has an APB 149 * (advanced PCI bridge) connected to it, which was designed specifically for 150 * the IIi. The APB let's the IIi handle two independednt PCI buses, and 151 * appears as two "simba"'s underneath the sabre. 152 * 153 * "psycho" and "psycho+" is a dual UPA to PCI bridge. It sits on the UPA bus 154 * and manages two PCI buses. "psycho" has two 64-bit 33MHz buses, while 155 * "psycho+" controls both a 64-bit 33Mhz and a 64-bit 66Mhz PCI bus. You 156 * will usually find a "psycho+" since I don't think the original "psycho" 157 * ever shipped, and if it did it would be in the U30. 158 * 159 * Each "psycho" PCI bus appears as a separate OFW node, but since they are 160 * both part of the same IC, they only have a single register space. As such, 161 * they need to be configured together, even though the autoconfiguration will 162 * attach them separately. 163 * 164 * On UltraIIi machines, "sabre" itself usually takes pci0, with "simba" often 165 * as pci1 and pci2, although they have been implemented with other PCI bus 166 * numbers on some machines. 167 * 168 * On UltraII machines, there can be any number of "psycho+" ICs, each 169 * providing two PCI buses. 170 * 171 * 172 * XXXX The psycho/sabre node has an `interrupts' attribute. They contain 173 * the values of the following interrupts in this order: 174 * 175 * PCI Bus Error (30) 176 * DMA UE (2e) 177 * DMA CE (2f) 178 * Power Fail (25) 179 * 180 * We really should attach handlers for each. 181 * 182 */ 183 184 #define ROM_PCI_NAME "pci" 185 186 struct psycho_names { 187 char *p_name; 188 int p_type; 189 } psycho_names[] = { 190 { "SUNW,psycho", PSYCHO_MODE_PSYCHO }, 191 { "pci108e,8000", PSYCHO_MODE_PSYCHO }, 192 { "SUNW,sabre", PSYCHO_MODE_SABRE }, 193 { "pci108e,a000", PSYCHO_MODE_SABRE }, 194 { "pci108e,a001", PSYCHO_MODE_SABRE }, 195 { NULL, 0 } 196 }; 197 198 static int 199 psycho_match(parent, match, aux) 200 struct device *parent; 201 struct cfdata *match; 202 void *aux; 203 { 204 struct mainbus_attach_args *ma = aux; 205 char *model = PROM_getpropstring(ma->ma_node, "model"); 206 int i; 207 208 /* match on a name of "pci" and a sabre or a psycho */ 209 if (strcmp(ma->ma_name, ROM_PCI_NAME) == 0) { 210 for (i=0; psycho_names[i].p_name; i++) 211 if (strcmp(model, psycho_names[i].p_name) == 0) 212 return (1); 213 214 model = PROM_getpropstring(ma->ma_node, "compatible"); 215 for (i=0; psycho_names[i].p_name; i++) 216 if (strcmp(model, psycho_names[i].p_name) == 0) 217 return (1); 218 } 219 return (0); 220 } 221 222 /* 223 * SUNW,psycho initialisation .. 224 * - find the per-psycho registers 225 * - figure out the IGN. 226 * - find our partner psycho 227 * - configure ourselves 228 * - bus range, bus, 229 * - get interrupt-map and interrupt-map-mask 230 * - setup the chipsets. 231 * - if we're the first of the pair, initialise the IOMMU, otherwise 232 * just copy it's tags and addresses. 233 */ 234 static void 235 psycho_attach(parent, self, aux) 236 struct device *parent, *self; 237 void *aux; 238 { 239 struct psycho_softc *sc = (struct psycho_softc *)self; 240 struct psycho_softc *osc = NULL; 241 struct psycho_pbm *pp; 242 struct pcibus_attach_args pba; 243 struct mainbus_attach_args *ma = aux; 244 bus_space_handle_t bh; 245 u_int64_t csr; 246 int psycho_br[2], n, i; 247 bus_space_handle_t pci_ctl; 248 char *model = PROM_getpropstring(ma->ma_node, "model"); 249 250 printf("\n"); 251 252 sc->sc_node = ma->ma_node; 253 sc->sc_bustag = ma->ma_bustag; 254 sc->sc_dmatag = ma->ma_dmatag; 255 256 /* 257 * Identify the device. 258 */ 259 for (i=0; psycho_names[i].p_name; i++) 260 if (strcmp(model, psycho_names[i].p_name) == 0) { 261 sc->sc_mode = psycho_names[i].p_type; 262 goto found; 263 } 264 265 model = PROM_getpropstring(ma->ma_node, "compatible"); 266 for (i=0; psycho_names[i].p_name; i++) 267 if (strcmp(model, psycho_names[i].p_name) == 0) { 268 sc->sc_mode = psycho_names[i].p_type; 269 goto found; 270 } 271 272 panic("unknown psycho model %s", model); 273 found: 274 275 /* 276 * The psycho gets three register banks: 277 * (0) per-PBM configuration and status registers 278 * (1) per-PBM PCI configuration space, containing only the 279 * PBM 256-byte PCI header 280 * (2) the shared psycho configuration registers (struct psychoreg) 281 */ 282 283 /* Register layouts are different. stuupid. */ 284 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) { 285 sc->sc_basepaddr = (paddr_t)ma->ma_reg[2].ur_paddr; 286 287 if (ma->ma_naddress > 2) { 288 sparc_promaddr_to_handle(sc->sc_bustag, 289 ma->ma_address[2], &sc->sc_bh); 290 sparc_promaddr_to_handle(sc->sc_bustag, 291 ma->ma_address[0], &pci_ctl); 292 293 sc->sc_regs = (struct psychoreg *) 294 bus_space_vaddr(sc->sc_bustag, sc->sc_bh); 295 } else if (ma->ma_nreg > 2) { 296 297 /* We need to map this in ourselves. */ 298 if (bus_space_map(sc->sc_bustag, 299 ma->ma_reg[2].ur_paddr, 300 ma->ma_reg[2].ur_len, BUS_SPACE_MAP_LINEAR, 301 &sc->sc_bh)) 302 panic("psycho_attach: cannot map regs"); 303 sc->sc_regs = (struct psychoreg *) 304 bus_space_vaddr(sc->sc_bustag, sc->sc_bh); 305 306 if (bus_space_map(sc->sc_bustag, 307 ma->ma_reg[0].ur_paddr, 308 ma->ma_reg[0].ur_len, BUS_SPACE_MAP_LINEAR, 309 &pci_ctl)) 310 panic("psycho_attach: cannot map ctl"); 311 } else 312 panic("psycho_attach: %d not enough registers", 313 ma->ma_nreg); 314 } else { 315 sc->sc_basepaddr = (paddr_t)ma->ma_reg[0].ur_paddr; 316 317 if (ma->ma_naddress) { 318 sparc_promaddr_to_handle(sc->sc_bustag, 319 ma->ma_address[0], &sc->sc_bh); 320 sc->sc_regs = (struct psychoreg *) 321 bus_space_vaddr(sc->sc_bustag, sc->sc_bh); 322 bus_space_subregion(sc->sc_bustag, sc->sc_bh, 323 offsetof(struct psychoreg, psy_pcictl), 324 sizeof(struct pci_ctl), &pci_ctl); 325 } else if (ma->ma_nreg) { 326 327 /* We need to map this in ourselves. */ 328 if (bus_space_map(sc->sc_bustag, 329 ma->ma_reg[0].ur_paddr, 330 ma->ma_reg[0].ur_len, BUS_SPACE_MAP_LINEAR, 331 &sc->sc_bh)) 332 panic("psycho_attach: cannot map regs"); 333 sc->sc_regs = (struct psychoreg *) 334 bus_space_vaddr(sc->sc_bustag, sc->sc_bh); 335 336 bus_space_subregion(sc->sc_bustag, sc->sc_bh, 337 offsetof(struct psychoreg, psy_pcictl), 338 sizeof(struct pci_ctl), &pci_ctl); 339 } else 340 panic("psycho_attach: %d not enough registers", 341 ma->ma_nreg); 342 } 343 344 345 csr = bus_space_read_8(sc->sc_bustag, sc->sc_bh, 346 offsetof(struct psychoreg, psy_csr)); 347 sc->sc_ign = 0x7c0; /* APB IGN is always 0x7c */ 348 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) 349 sc->sc_ign = PSYCHO_GCSR_IGN(csr) << 6; 350 351 printf("%s: impl %d, version %d: ign %x ", 352 model, PSYCHO_GCSR_IMPL(csr), PSYCHO_GCSR_VERS(csr), 353 sc->sc_ign); 354 /* 355 * Match other psycho's that are already configured against 356 * the base physical address. This will be the same for a 357 * pair of devices that share register space. 358 */ 359 for (n = 0; n < psycho_cd.cd_ndevs; n++) { 360 361 struct psycho_softc *asc = 362 (struct psycho_softc *)psycho_cd.cd_devs[n]; 363 364 if (asc == NULL || asc == sc) 365 /* This entry is not there or it is me */ 366 continue; 367 368 if (asc->sc_basepaddr != sc->sc_basepaddr) 369 /* This is an unrelated psycho */ 370 continue; 371 372 /* Found partner */ 373 osc = asc; 374 break; 375 } 376 377 378 /* Oh, dear. OK, lets get started */ 379 380 /* 381 * Setup the PCI control register 382 */ 383 csr = bus_space_read_8(sc->sc_bustag, pci_ctl, 384 offsetof(struct pci_ctl, pci_csr)); 385 csr |= PCICTL_MRLM | 386 PCICTL_ARB_PARK | 387 PCICTL_ERRINTEN | 388 PCICTL_4ENABLE; 389 csr &= ~(PCICTL_SERR | 390 PCICTL_CPU_PRIO | 391 PCICTL_ARB_PRIO | 392 PCICTL_RTRYWAIT); 393 bus_space_write_8(sc->sc_bustag, pci_ctl, 394 offsetof(struct pci_ctl, pci_csr), csr); 395 396 397 /* 398 * Allocate our psycho_pbm 399 */ 400 pp = sc->sc_psycho_this = malloc(sizeof *pp, M_DEVBUF, 401 M_NOWAIT | M_ZERO); 402 if (pp == NULL) 403 panic("could not allocate psycho pbm"); 404 405 pp->pp_sc = sc; 406 407 /* grab the psycho ranges */ 408 psycho_get_ranges(sc->sc_node, &pp->pp_range, &pp->pp_nrange); 409 410 /* get the bus-range for the psycho */ 411 psycho_get_bus_range(sc->sc_node, psycho_br); 412 413 pba.pba_bus = psycho_br[0]; 414 pba.pba_bridgetag = NULL; 415 pp->pp_busmax = psycho_br[1]; 416 417 printf("bus range %u to %u", psycho_br[0], psycho_br[1]); 418 printf("; PCI bus %d", psycho_br[0]); 419 420 pp->pp_pcictl = pci_ctl; 421 422 /* allocate our tags */ 423 pp->pp_memt = psycho_alloc_mem_tag(pp); 424 pp->pp_iot = psycho_alloc_io_tag(pp); 425 pp->pp_dmat = psycho_alloc_dma_tag(pp); 426 pp->pp_flags = (pp->pp_memt ? PCI_FLAGS_MEM_ENABLED : 0) | 427 (pp->pp_iot ? PCI_FLAGS_IO_ENABLED : 0); 428 429 /* allocate a chipset for this */ 430 pp->pp_pc = psycho_alloc_chipset(pp, sc->sc_node, &_sparc_pci_chipset); 431 432 /* setup the rest of the psycho pbm */ 433 pba.pba_pc = psycho_alloc_chipset(pp, sc->sc_node, pp->pp_pc); 434 435 printf("\n"); 436 437 /* allocate extents for free bus space */ 438 pp->pp_exmem = psycho_alloc_extent(pp, sc->sc_node, 0x02, "psycho mem"); 439 pp->pp_exio = psycho_alloc_extent(pp, sc->sc_node, 0x01, "psycho io"); 440 441 /* 442 * And finally, if we're a sabre or the first of a pair of psycho's to 443 * arrive here, start up the IOMMU and get a config space tag. 444 */ 445 if (osc == NULL) { 446 uint64_t timeo; 447 448 /* 449 * Establish handlers for interesting interrupts.... 450 * 451 * XXX We need to remember these and remove this to support 452 * hotplug on the UPA/FHC bus. 453 * 454 * XXX Not all controllers have these, but installing them 455 * is better than trying to sort through this mess. 456 */ 457 psycho_set_intr(sc, 15, psycho_ue, 458 &sc->sc_regs->ue_int_map, 459 &sc->sc_regs->ue_clr_int); 460 psycho_set_intr(sc, 1, psycho_ce, 461 &sc->sc_regs->ce_int_map, 462 &sc->sc_regs->ce_clr_int); 463 psycho_set_intr(sc, 15, psycho_bus_a, 464 &sc->sc_regs->pciaerr_int_map, 465 &sc->sc_regs->pciaerr_clr_int); 466 psycho_set_intr(sc, 15, psycho_powerfail, 467 &sc->sc_regs->power_int_map, 468 &sc->sc_regs->power_clr_int); 469 if (sc->sc_mode != PSYCHO_MODE_SABRE) { 470 /* sabre doesn't have these interrups */ 471 psycho_set_intr(sc, 15, psycho_bus_b, 472 &sc->sc_regs->pciberr_int_map, 473 &sc->sc_regs->pciberr_clr_int); 474 psycho_register_power_button(sc); 475 psycho_set_intr(sc, 1, psycho_wakeup, 476 &sc->sc_regs->pwrmgt_int_map, 477 &sc->sc_regs->pwrmgt_clr_int); 478 } 479 480 /* 481 * Apparently a number of machines with psycho and psycho+ 482 * controllers have interrupt latency issues. We'll try 483 * setting the interrupt retry timeout to 0xff which gives us 484 * a retry of 3-6 usec (which is what sysio is set to) for the 485 * moment, which seems to help alleviate this problem. 486 */ 487 timeo = sc->sc_regs->intr_retry_timer; 488 if (timeo > 0xfff) { 489 #ifdef DEBUG 490 printf("decreasing interrupt retry timeout " 491 "from %lx to 0xff\n", (long)timeo); 492 #endif 493 sc->sc_regs->intr_retry_timer = 0xff; 494 } 495 496 /* 497 * Allocate bus node, this contains a prom node per bus. 498 */ 499 pp->pp_busnode = malloc(sizeof(*pp->pp_busnode), M_DEVBUF, 500 M_NOWAIT | M_ZERO); 501 if (pp->pp_busnode == NULL) 502 panic("psycho_attach: malloc pp->pp_busnode"); 503 504 /* 505 * Setup IOMMU and PCI configuration if we're the first 506 * of a pair of psycho's to arrive here. 507 * 508 * We should calculate a TSB size based on amount of RAM 509 * and number of bus controllers and number an type of 510 * child devices. 511 * 512 * For the moment, 32KB should be more than enough. 513 */ 514 sc->sc_is = malloc(sizeof(struct iommu_state), 515 M_DEVBUF, M_NOWAIT); 516 if (sc->sc_is == NULL) 517 panic("psycho_attach: malloc iommu_state"); 518 519 /* Point the strbuf_ctl at the iommu_state */ 520 pp->pp_sb.sb_is = sc->sc_is; 521 522 sc->sc_is->is_sb[0] = sc->sc_is->is_sb[1] = NULL; 523 if (PROM_getproplen(sc->sc_node, "no-streaming-cache") < 0) { 524 struct strbuf_ctl *sb = &pp->pp_sb; 525 vaddr_t va = (vaddr_t)&pp->pp_flush[0x40]; 526 527 /* 528 * Initialize the strbuf_ctl. 529 * 530 * The flush sync buffer must be 64-byte aligned. 531 */ 532 sb->sb_flush = (void *)(va & ~0x3f); 533 534 bus_space_subregion(sc->sc_bustag, pci_ctl, 535 offsetof(struct pci_ctl, pci_strbuf), 536 sizeof (struct iommu_strbuf), &sb->sb_sb); 537 538 /* Point our iommu at the strbuf_ctl */ 539 sc->sc_is->is_sb[0] = sb; 540 } 541 542 psycho_iommu_init(sc, 2); 543 544 sc->sc_configtag = psycho_alloc_config_tag(sc->sc_psycho_this); 545 546 /* 547 * XXX This is a really ugly hack because PCI config space 548 * is explicitly handled with unmapped accesses. 549 */ 550 i = sc->sc_bustag->type; 551 sc->sc_bustag->type = PCI_CONFIG_BUS_SPACE; 552 if (bus_space_map(sc->sc_bustag, sc->sc_basepaddr + 0x01000000, 553 0x01000000, 0, &bh)) 554 panic("could not map psycho PCI configuration space"); 555 sc->sc_bustag->type = i; 556 sc->sc_configaddr = bh; 557 } else { 558 /* Share bus numbers with the pair of mine */ 559 pp->pp_busnode = osc->sc_psycho_this->pp_busnode; 560 561 /* Just copy IOMMU state, config tag and address */ 562 sc->sc_is = osc->sc_is; 563 sc->sc_configtag = osc->sc_configtag; 564 sc->sc_configaddr = osc->sc_configaddr; 565 566 /* Point the strbuf_ctl at the iommu_state */ 567 pp->pp_sb.sb_is = sc->sc_is; 568 569 if (PROM_getproplen(sc->sc_node, "no-streaming-cache") < 0) { 570 struct strbuf_ctl *sb = &pp->pp_sb; 571 vaddr_t va = (vaddr_t)&pp->pp_flush[0x40]; 572 573 /* 574 * Initialize the strbuf_ctl. 575 * 576 * The flush sync buffer must be 64-byte aligned. 577 */ 578 sb->sb_flush = (void *)(va & ~0x3f); 579 580 bus_space_subregion(sc->sc_bustag, pci_ctl, 581 offsetof(struct pci_ctl, pci_strbuf), 582 sizeof (struct iommu_strbuf), &sb->sb_sb); 583 584 /* Point our iommu at the strbuf_ctl */ 585 sc->sc_is->is_sb[1] = sb; 586 } 587 iommu_reset(sc->sc_is); 588 } 589 590 /* 591 * attach the pci.. note we pass PCI A tags, etc., for the sabre here. 592 */ 593 pba.pba_busname = "pci"; 594 pba.pba_flags = sc->sc_psycho_this->pp_flags; 595 pba.pba_dmat = sc->sc_psycho_this->pp_dmat; 596 pba.pba_dmat64 = NULL; 597 pba.pba_iot = sc->sc_psycho_this->pp_iot; 598 pba.pba_memt = sc->sc_psycho_this->pp_memt; 599 600 config_found(self, &pba, psycho_print); 601 } 602 603 static int 604 psycho_print(aux, p) 605 void *aux; 606 const char *p; 607 { 608 609 if (p == NULL) 610 return (UNCONF); 611 return (QUIET); 612 } 613 614 static void 615 psycho_set_intr(sc, ipl, handler, mapper, clearer) 616 struct psycho_softc *sc; 617 int ipl; 618 void *handler; 619 u_int64_t *mapper; 620 u_int64_t *clearer; 621 { 622 struct intrhand *ih; 623 624 ih = (struct intrhand *)malloc(sizeof(struct intrhand), 625 M_DEVBUF, M_NOWAIT); 626 ih->ih_arg = sc; 627 ih->ih_map = mapper; 628 ih->ih_clr = clearer; 629 ih->ih_fun = handler; 630 ih->ih_pil = (1<<ipl); 631 ih->ih_number = INTVEC(*(ih->ih_map)); 632 intr_establish(ipl, ih); 633 *(ih->ih_map) |= INTMAP_V; 634 } 635 636 /* 637 * power button handlers 638 */ 639 static void 640 psycho_register_power_button(struct psycho_softc *sc) 641 { 642 sysmon_task_queue_init(); 643 644 sc->sc_powerpressed = 0; 645 sc->sc_smcontext = malloc(sizeof(struct sysmon_pswitch), M_DEVBUF, 0); 646 if (!sc->sc_smcontext) { 647 printf("%s: could not allocate power button context\n", 648 sc->sc_dev.dv_xname); 649 return; 650 } 651 memset(sc->sc_smcontext, 0, sizeof(struct sysmon_pswitch)); 652 sc->sc_smcontext->smpsw_name = sc->sc_dev.dv_xname; 653 sc->sc_smcontext->smpsw_type = PSWITCH_TYPE_POWER; 654 if (sysmon_pswitch_register(sc->sc_smcontext) != 0) 655 printf("%s: unable to register power button with sysmon\n", 656 sc->sc_dev.dv_xname); 657 } 658 659 static void 660 psycho_power_button_pressed(void *arg) 661 { 662 struct psycho_softc *sc = arg; 663 664 sysmon_pswitch_event(sc->sc_smcontext, PSWITCH_EVENT_PRESSED); 665 sc->sc_powerpressed = 0; 666 } 667 668 /* 669 * PCI bus support 670 */ 671 672 /* 673 * allocate a PCI chipset tag and set it's cookie. 674 */ 675 static pci_chipset_tag_t 676 psycho_alloc_chipset(pp, node, pc) 677 struct psycho_pbm *pp; 678 int node; 679 pci_chipset_tag_t pc; 680 { 681 pci_chipset_tag_t npc; 682 683 npc = malloc(sizeof *npc, M_DEVBUF, M_NOWAIT); 684 if (npc == NULL) 685 panic("could not allocate pci_chipset_tag_t"); 686 memcpy(npc, pc, sizeof *pc); 687 npc->cookie = pp; 688 npc->rootnode = node; 689 690 return (npc); 691 } 692 693 /* 694 * create extent for free bus space, then allocate assigned regions. 695 */ 696 static struct extent * 697 psycho_alloc_extent(pp, node, ss, name) 698 struct psycho_pbm *pp; 699 int node; 700 int ss; 701 char *name; 702 { 703 struct psycho_registers *pa = NULL; 704 struct psycho_ranges *pr; 705 struct extent *ex; 706 bus_addr_t baddr, addr; 707 bus_size_t bsize, size; 708 int i, num; 709 710 /* get bus space size */ 711 pr = get_psychorange(pp, ss); 712 if (pr == NULL) { 713 printf("psycho_alloc_extent: get_psychorange failed\n"); 714 return NULL; 715 } 716 baddr = 0x00000000; 717 bsize = BUS_ADDR(pr->size_hi, pr->size_lo); 718 719 /* get available lists */ 720 if (PROM_getprop(node, "available", sizeof(*pa), &num, &pa)) { 721 printf("psycho_alloc_extent: PROM_getprop failed\n"); 722 return NULL; 723 } 724 725 /* create extent */ 726 ex = extent_create(name, baddr, bsize - baddr - 1, M_DEVBUF, 0, 0, 727 EX_NOWAIT); 728 if (ex == NULL) { 729 printf("psycho_alloc_extent: extent_create failed\n"); 730 goto ret; 731 } 732 733 /* allocate assigned regions */ 734 for (i = 0; i < num; i++) 735 if (((pa[i].phys_hi >> 24) & 0x03) == ss) { 736 /* allocate bus space */ 737 addr = BUS_ADDR(pa[i].phys_mid, pa[i].phys_lo); 738 size = BUS_ADDR(pa[i].size_hi, pa[i].size_lo); 739 if (extent_alloc_region(ex, baddr, addr - baddr, 740 EX_NOWAIT)) { 741 printf("psycho_alloc_extent: " 742 "extent_alloc_region %" PRIx64 "-%" 743 PRIx64 " failed\n", baddr, addr); 744 extent_destroy(ex); 745 ex = NULL; 746 goto ret; 747 } 748 baddr = addr + size; 749 } 750 /* allocate left region if available */ 751 if (baddr < bsize) 752 if (extent_alloc_region(ex, baddr, bsize - baddr, EX_NOWAIT)) { 753 printf("psycho_alloc_extent: extent_alloc_region %" 754 PRIx64 "-%" PRIx64 " failed\n", baddr, bsize); 755 extent_destroy(ex); 756 ex = NULL; 757 goto ret; 758 } 759 760 #ifdef DEBUG 761 /* print extent */ 762 extent_print(ex); 763 #endif 764 765 ret: 766 /* return extent */ 767 free(pa, M_DEVBUF); 768 return ex; 769 } 770 771 /* 772 * grovel the OBP for various psycho properties 773 */ 774 static void 775 psycho_get_bus_range(node, brp) 776 int node; 777 int *brp; 778 { 779 int n; 780 781 if (PROM_getprop(node, "bus-range", sizeof(*brp), &n, &brp)) 782 panic("could not get psycho bus-range"); 783 if (n != 2) 784 panic("broken psycho bus-range"); 785 DPRINTF(PDB_PROM, ("psycho debug: got `bus-range' for node %08x: %u - %u\n", node, brp[0], brp[1])); 786 } 787 788 static void 789 psycho_get_ranges(node, rp, np) 790 int node; 791 struct psycho_ranges **rp; 792 int *np; 793 { 794 795 if (PROM_getprop(node, "ranges", sizeof(**rp), np, rp)) 796 panic("could not get psycho ranges"); 797 DPRINTF(PDB_PROM, ("psycho debug: got `ranges' for node %08x: %d entries\n", node, *np)); 798 } 799 800 /* 801 * Interrupt handlers. 802 */ 803 804 static int 805 psycho_ue(arg) 806 void *arg; 807 { 808 struct psycho_softc *sc = (struct psycho_softc *)arg; 809 struct psychoreg *regs = sc->sc_regs; 810 long long afsr = regs->psy_ue_afsr; 811 long long afar = regs->psy_ue_afar; 812 long size = PAGE_SIZE<<(sc->sc_is->is_tsbsize); 813 struct iommu_state *is = sc->sc_is; 814 char bits[128]; 815 816 /* 817 * It's uncorrectable. Dump the regs and panic. 818 */ 819 printf("%s: uncorrectable DMA error AFAR %llx pa %llx AFSR %llx:\n%s\n", 820 sc->sc_dev.dv_xname, afar, 821 (long long)iommu_extract(is, (vaddr_t)afar), afsr, 822 bitmask_snprintf(afsr, PSYCHO_UE_AFSR_BITS, 823 bits, sizeof(bits))); 824 825 /* Sometimes the AFAR points to an IOTSB entry */ 826 if (afar >= is->is_ptsb && afar < is->is_ptsb + size) { 827 printf("IOVA %llx IOTTE %llx\n", 828 (long long)((afar - is->is_ptsb) * PAGE_SIZE + is->is_dvmabase), 829 (long long)ldxa(afar, ASI_PHYS_CACHED)); 830 } 831 #ifdef DDB 832 Debugger(); 833 #endif 834 regs->psy_ue_afar = 0; 835 regs->psy_ue_afsr = 0; 836 return (1); 837 } 838 static int 839 psycho_ce(arg) 840 void *arg; 841 { 842 struct psycho_softc *sc = (struct psycho_softc *)arg; 843 struct psychoreg *regs = sc->sc_regs; 844 845 /* 846 * It's correctable. Dump the regs and continue. 847 */ 848 849 printf("%s: correctable DMA error AFAR %llx AFSR %llx\n", 850 sc->sc_dev.dv_xname, 851 (long long)regs->psy_ce_afar, (long long)regs->psy_ce_afsr); 852 return (1); 853 } 854 static int 855 psycho_bus_a(arg) 856 void *arg; 857 { 858 struct psycho_softc *sc = (struct psycho_softc *)arg; 859 struct psychoreg *regs = sc->sc_regs; 860 861 /* 862 * It's uncorrectable. Dump the regs and panic. 863 */ 864 865 panic("%s: PCI bus A error AFAR %llx AFSR %llx", 866 sc->sc_dev.dv_xname, 867 (long long)regs->psy_pcictl[0].pci_afar, 868 (long long)regs->psy_pcictl[0].pci_afsr); 869 return (1); 870 } 871 static int 872 psycho_bus_b(arg) 873 void *arg; 874 { 875 struct psycho_softc *sc = (struct psycho_softc *)arg; 876 struct psychoreg *regs = sc->sc_regs; 877 878 /* 879 * It's uncorrectable. Dump the regs and panic. 880 */ 881 882 panic("%s: PCI bus B error AFAR %llx AFSR %llx", 883 sc->sc_dev.dv_xname, 884 (long long)regs->psy_pcictl[0].pci_afar, 885 (long long)regs->psy_pcictl[0].pci_afsr); 886 return (1); 887 } 888 889 static int 890 psycho_powerfail(arg) 891 void *arg; 892 { 893 struct psycho_softc *sc = (struct psycho_softc *)arg; 894 895 /* 896 * We lost power. Queue a callback with thread context to 897 * handle all the real work. 898 */ 899 if (sc->sc_powerpressed == 0 && sc->sc_smcontext != NULL) { 900 sc->sc_powerpressed = 1; 901 sysmon_task_queue_sched(0, psycho_power_button_pressed, sc); 902 } 903 return (1); 904 } 905 906 static 907 int psycho_wakeup(arg) 908 void *arg; 909 { 910 struct psycho_softc *sc = (struct psycho_softc *)arg; 911 912 /* 913 * Gee, we don't really have a framework to deal with this 914 * properly. 915 */ 916 printf("%s: power management wakeup\n", sc->sc_dev.dv_xname); 917 return (1); 918 } 919 920 921 922 /* 923 * initialise the IOMMU.. 924 */ 925 void 926 psycho_iommu_init(sc, tsbsize) 927 struct psycho_softc *sc; 928 int tsbsize; 929 { 930 char *name; 931 struct iommu_state *is = sc->sc_is; 932 u_int32_t iobase = -1; 933 int *vdma = NULL; 934 int nitem; 935 936 /* punch in our copies */ 937 is->is_bustag = sc->sc_bustag; 938 bus_space_subregion(sc->sc_bustag, sc->sc_bh, 939 offsetof(struct psychoreg, psy_iommu), 940 sizeof (struct iommureg), 941 &is->is_iommu); 942 943 /* 944 * Separate the men from the boys. Get the `virtual-dma' 945 * property for sabre and use that to make sure the damn 946 * iommu works. 947 * 948 * We could query the `#virtual-dma-size-cells' and 949 * `#virtual-dma-addr-cells' and DTRT, but I'm lazy. 950 */ 951 if (!PROM_getprop(sc->sc_node, "virtual-dma", sizeof(vdma), &nitem, 952 &vdma)) { 953 /* Damn. Gotta use these values. */ 954 iobase = vdma[0]; 955 #define TSBCASE(x) case 1<<((x)+23): tsbsize = (x); break 956 switch (vdma[1]) { 957 TSBCASE(1); TSBCASE(2); TSBCASE(3); 958 TSBCASE(4); TSBCASE(5); TSBCASE(6); 959 default: 960 printf("bogus tsb size %x, using 7\n", vdma[1]); 961 TSBCASE(7); 962 } 963 #undef TSBCASE 964 } 965 966 /* give us a nice name.. */ 967 name = (char *)malloc(32, M_DEVBUF, M_NOWAIT); 968 if (name == 0) 969 panic("couldn't malloc iommu name"); 970 snprintf(name, 32, "%s dvma", sc->sc_dev.dv_xname); 971 972 iommu_init(name, is, tsbsize, iobase); 973 } 974 975 /* 976 * below here is bus space and bus DMA support 977 */ 978 bus_space_tag_t 979 psycho_alloc_bus_tag(pp, type) 980 struct psycho_pbm *pp; 981 int type; 982 { 983 struct psycho_softc *sc = pp->pp_sc; 984 bus_space_tag_t bt; 985 986 bt = (bus_space_tag_t) 987 malloc(sizeof(struct sparc_bus_space_tag), M_DEVBUF, M_NOWAIT); 988 if (bt == NULL) 989 panic("could not allocate psycho bus tag"); 990 991 bzero(bt, sizeof *bt); 992 bt->cookie = pp; 993 bt->parent = sc->sc_bustag; 994 bt->type = type; 995 bt->sparc_bus_map = _psycho_bus_map; 996 bt->sparc_bus_mmap = psycho_bus_mmap; 997 bt->sparc_intr_establish = psycho_intr_establish; 998 return (bt); 999 } 1000 1001 bus_dma_tag_t 1002 psycho_alloc_dma_tag(pp) 1003 struct psycho_pbm *pp; 1004 { 1005 struct psycho_softc *sc = pp->pp_sc; 1006 bus_dma_tag_t dt, pdt = sc->sc_dmatag; 1007 1008 dt = (bus_dma_tag_t) 1009 malloc(sizeof(struct sparc_bus_dma_tag), M_DEVBUF, M_NOWAIT); 1010 if (dt == NULL) 1011 panic("could not allocate psycho DMA tag"); 1012 1013 bzero(dt, sizeof *dt); 1014 dt->_cookie = pp; 1015 dt->_parent = pdt; 1016 #define PCOPY(x) dt->x = pdt->x 1017 PCOPY(_dmamap_create); 1018 PCOPY(_dmamap_destroy); 1019 dt->_dmamap_load = psycho_dmamap_load; 1020 PCOPY(_dmamap_load_mbuf); 1021 PCOPY(_dmamap_load_uio); 1022 dt->_dmamap_load_raw = psycho_dmamap_load_raw; 1023 dt->_dmamap_unload = psycho_dmamap_unload; 1024 dt->_dmamap_sync = psycho_dmamap_sync; 1025 dt->_dmamem_alloc = psycho_dmamem_alloc; 1026 dt->_dmamem_free = psycho_dmamem_free; 1027 dt->_dmamem_map = psycho_dmamem_map; 1028 dt->_dmamem_unmap = psycho_dmamem_unmap; 1029 PCOPY(_dmamem_mmap); 1030 #undef PCOPY 1031 return (dt); 1032 } 1033 1034 /* 1035 * bus space support. <sparc64/dev/psychoreg.h> has a discussion about 1036 * PCI physical addresses. 1037 */ 1038 1039 static int 1040 get_childspace(type) 1041 int type; 1042 { 1043 int ss; 1044 1045 switch (type) { 1046 case PCI_CONFIG_BUS_SPACE: 1047 ss = 0x00; 1048 break; 1049 case PCI_IO_BUS_SPACE: 1050 ss = 0x01; 1051 break; 1052 case PCI_MEMORY_BUS_SPACE: 1053 ss = 0x02; 1054 break; 1055 #if 0 1056 /* we don't do 64 bit memory space */ 1057 case PCI_MEMORY64_BUS_SPACE: 1058 ss = 0x03; 1059 break; 1060 #endif 1061 default: 1062 panic("get_childspace: unknown bus type"); 1063 } 1064 1065 return (ss); 1066 } 1067 1068 static struct psycho_ranges * 1069 get_psychorange(pp, ss) 1070 struct psycho_pbm *pp; 1071 int ss; 1072 { 1073 int i; 1074 1075 for (i = 0; i < pp->pp_nrange; i++) { 1076 if (((pp->pp_range[i].cspace >> 24) & 0x03) == ss) 1077 return (&pp->pp_range[i]); 1078 } 1079 /* not found */ 1080 return (NULL); 1081 } 1082 1083 static int 1084 _psycho_bus_map(t, offset, size, flags, unused, hp) 1085 bus_space_tag_t t; 1086 bus_addr_t offset; 1087 bus_size_t size; 1088 int flags; 1089 vaddr_t unused; 1090 bus_space_handle_t *hp; 1091 { 1092 struct psycho_pbm *pp = t->cookie; 1093 struct psycho_softc *sc = pp->pp_sc; 1094 struct psycho_ranges *pr; 1095 bus_addr_t paddr; 1096 int ss; 1097 1098 DPRINTF(PDB_BUSMAP, 1099 ("_psycho_bus_map: type %d off %qx sz %qx flags %d", 1100 t->type, (unsigned long long)offset, 1101 (unsigned long long)size, flags)); 1102 1103 ss = get_childspace(t->type); 1104 DPRINTF(PDB_BUSMAP, (" cspace %d", ss)); 1105 1106 pr = get_psychorange(pp, ss); 1107 if (pr != NULL) { 1108 paddr = BUS_ADDR(pr->phys_hi, pr->phys_lo + offset); 1109 DPRINTF(PDB_BUSMAP, ("\n_psycho_bus_map: mapping paddr " 1110 "space %lx offset %lx paddr %qx\n", 1111 (long)ss, (long)offset, 1112 (unsigned long long)paddr)); 1113 return ((*sc->sc_bustag->sparc_bus_map)(t, paddr, size, 1114 flags, 0, hp)); 1115 } 1116 DPRINTF(PDB_BUSMAP, (" FAILED\n")); 1117 return (EINVAL); 1118 } 1119 1120 static paddr_t 1121 psycho_bus_mmap(t, paddr, off, prot, flags) 1122 bus_space_tag_t t; 1123 bus_addr_t paddr; 1124 off_t off; 1125 int prot; 1126 int flags; 1127 { 1128 bus_addr_t offset = paddr; 1129 struct psycho_pbm *pp = t->cookie; 1130 struct psycho_softc *sc = pp->pp_sc; 1131 struct psycho_ranges *pr; 1132 int ss; 1133 1134 ss = get_childspace(t->type); 1135 1136 DPRINTF(PDB_BUSMAP, ("_psycho_bus_mmap: prot %x flags %d pa %qx\n", 1137 prot, flags, (unsigned long long)paddr)); 1138 1139 pr = get_psychorange(pp, ss); 1140 if (pr != NULL) { 1141 paddr = BUS_ADDR(pr->phys_hi, pr->phys_lo + offset); 1142 DPRINTF(PDB_BUSMAP, ("\n_psycho_bus_mmap: mapping paddr " 1143 "space %lx offset %lx paddr %qx\n", 1144 (long)ss, (long)offset, 1145 (unsigned long long)paddr)); 1146 return (bus_space_mmap(sc->sc_bustag, paddr, off, 1147 prot, flags)); 1148 } 1149 1150 return (-1); 1151 } 1152 1153 /* 1154 * Get a PCI offset address from bus_space_handle_t. 1155 */ 1156 bus_addr_t 1157 psycho_bus_offset(t, hp) 1158 bus_space_tag_t t; 1159 bus_space_handle_t *hp; 1160 { 1161 struct psycho_pbm *pp = t->cookie; 1162 struct psycho_ranges *pr; 1163 bus_addr_t addr, offset; 1164 vaddr_t va; 1165 int ss; 1166 1167 addr = hp->_ptr; 1168 ss = get_childspace(t->type); 1169 DPRINTF(PDB_BUSMAP, ("psycho_bus_offset: type %d addr %" PRIx64 1170 " cspace %d", t->type, addr, ss)); 1171 1172 pr = get_psychorange(pp, ss); 1173 if (pr != NULL) { 1174 if (!PHYS_ASI(hp->_asi)) { 1175 va = trunc_page((vaddr_t)addr); 1176 if (pmap_extract(pmap_kernel(), va, &addr) == FALSE) { 1177 DPRINTF(PDB_BUSMAP, 1178 ("\n pmap_extract FAILED\n")); 1179 return (-1); 1180 } 1181 addr += hp->_ptr & PGOFSET; 1182 } 1183 offset = BUS_ADDR_PADDR(addr) - pr->phys_lo; 1184 DPRINTF(PDB_BUSMAP, ("\npsycho_bus_offset: paddr %" PRIx64 1185 " offset %" PRIx64 "\n", addr, offset)); 1186 return (offset); 1187 } 1188 DPRINTF(PDB_BUSMAP, ("\n FAILED\n")); 1189 return (-1); 1190 } 1191 1192 1193 /* 1194 * install an interrupt handler for a PCI device 1195 */ 1196 void * 1197 psycho_intr_establish(t, ihandle, level, handler, arg, fastvec) 1198 bus_space_tag_t t; 1199 int ihandle; 1200 int level; 1201 int (*handler) __P((void *)); 1202 void *arg; 1203 void (*fastvec) __P((void)); /* ignored */ 1204 { 1205 struct psycho_pbm *pp = t->cookie; 1206 struct psycho_softc *sc = pp->pp_sc; 1207 struct intrhand *ih; 1208 volatile u_int64_t *intrmapptr = NULL, *intrclrptr = NULL; 1209 int64_t intrmap = 0; 1210 int ino; 1211 long vec = INTVEC(ihandle); 1212 1213 ih = (struct intrhand *) 1214 malloc(sizeof(struct intrhand), M_DEVBUF, M_NOWAIT); 1215 if (ih == NULL) 1216 return (NULL); 1217 1218 /* 1219 * Hunt through all the interrupt mapping regs to look for our 1220 * interrupt vector. 1221 * 1222 * XXX We only compare INOs rather than IGNs since the firmware may 1223 * not provide the IGN and the IGN is constant for all device on that 1224 * PCI controller. This could cause problems for the FFB/external 1225 * interrupt which has a full vector that can be set arbitrarily. 1226 */ 1227 1228 DPRINTF(PDB_INTR, ("\npsycho_intr_establish: ihandle %x vec %lx", ihandle, vec)); 1229 ino = INTINO(vec); 1230 DPRINTF(PDB_INTR, (" ino %x", ino)); 1231 1232 /* If the device didn't ask for an IPL, use the one encoded. */ 1233 if (level == IPL_NONE) level = INTLEV(vec); 1234 /* If it still has no level, print a warning and assign IPL 2 */ 1235 if (level == IPL_NONE) { 1236 printf("ERROR: no IPL, setting IPL 2.\n"); 1237 level = 2; 1238 } 1239 1240 DPRINTF(PDB_INTR, ("\npsycho: intr %lx: %p\nHunting for IRQ...\n", 1241 (long)ino, intrlev[ino])); 1242 1243 /* Hunt thru obio first */ 1244 for (intrmapptr = &sc->sc_regs->scsi_int_map, 1245 intrclrptr = &sc->sc_regs->scsi_clr_int; 1246 intrmapptr < &sc->sc_regs->ue_int_map; 1247 intrmapptr++, intrclrptr++) { 1248 if (INTINO(*intrmapptr) == ino) 1249 goto found; 1250 } 1251 1252 /* Now do PCI interrupts */ 1253 for (intrmapptr = &sc->sc_regs->pcia_slot0_int, 1254 intrclrptr = &sc->sc_regs->pcia0_clr_int[0]; 1255 intrmapptr <= &sc->sc_regs->pcib_slot3_int; 1256 intrmapptr++, intrclrptr += 4) { 1257 if (((*intrmapptr ^ vec) & 0x3c) == 0) { 1258 intrclrptr += vec & 0x3; 1259 goto found; 1260 } 1261 } 1262 1263 /* Finally check the two FFB slots */ 1264 intrclrptr = NULL; /* XXX? */ 1265 for (intrmapptr = &sc->sc_regs->ffb0_int_map; 1266 intrmapptr <= &sc->sc_regs->ffb1_int_map; 1267 intrmapptr++) { 1268 if (INTVEC(*intrmapptr) == ino) 1269 goto found; 1270 } 1271 1272 printf("Cannot find interrupt vector %lx\n", vec); 1273 return (NULL); 1274 1275 found: 1276 /* Register the map and clear intr registers */ 1277 ih->ih_map = intrmapptr; 1278 ih->ih_clr = intrclrptr; 1279 1280 ih->ih_fun = handler; 1281 ih->ih_arg = arg; 1282 ih->ih_pil = level; 1283 ih->ih_number = ino | sc->sc_ign; 1284 1285 DPRINTF(PDB_INTR, ( 1286 "; installing handler %p arg %p with ino %u pil %u\n", 1287 handler, arg, (u_int)ino, (u_int)ih->ih_pil)); 1288 1289 intr_establish(ih->ih_pil, ih); 1290 1291 /* 1292 * Enable the interrupt now we have the handler installed. 1293 * Read the current value as we can't change it besides the 1294 * valid bit so so make sure only this bit is changed. 1295 * 1296 * XXXX --- we really should use bus_space for this. 1297 */ 1298 if (intrmapptr) { 1299 intrmap = *intrmapptr; 1300 DPRINTF(PDB_INTR, ("; read intrmap = %016qx", 1301 (unsigned long long)intrmap)); 1302 1303 /* Enable the interrupt */ 1304 intrmap |= INTMAP_V; 1305 DPRINTF(PDB_INTR, ("; addr of intrmapptr = %p", intrmapptr)); 1306 DPRINTF(PDB_INTR, ("; writing intrmap = %016qx\n", 1307 (unsigned long long)intrmap)); 1308 *intrmapptr = intrmap; 1309 DPRINTF(PDB_INTR, ("; reread intrmap = %016qx", 1310 (unsigned long long)(intrmap = *intrmapptr))); 1311 } 1312 return (ih); 1313 } 1314 1315 /* 1316 * hooks into the iommu dvma calls. 1317 */ 1318 int 1319 psycho_dmamap_load(t, map, buf, buflen, p, flags) 1320 bus_dma_tag_t t; 1321 bus_dmamap_t map; 1322 void *buf; 1323 bus_size_t buflen; 1324 struct proc *p; 1325 int flags; 1326 { 1327 struct psycho_pbm *pp = (struct psycho_pbm *)t->_cookie; 1328 1329 return (iommu_dvmamap_load(t, &pp->pp_sb, map, buf, buflen, p, flags)); 1330 } 1331 1332 void 1333 psycho_dmamap_unload(t, map) 1334 bus_dma_tag_t t; 1335 bus_dmamap_t map; 1336 { 1337 struct psycho_pbm *pp = (struct psycho_pbm *)t->_cookie; 1338 1339 iommu_dvmamap_unload(t, &pp->pp_sb, map); 1340 } 1341 1342 int 1343 psycho_dmamap_load_raw(t, map, segs, nsegs, size, flags) 1344 bus_dma_tag_t t; 1345 bus_dmamap_t map; 1346 bus_dma_segment_t *segs; 1347 int nsegs; 1348 bus_size_t size; 1349 int flags; 1350 { 1351 struct psycho_pbm *pp = (struct psycho_pbm *)t->_cookie; 1352 1353 return (iommu_dvmamap_load_raw(t, &pp->pp_sb, map, segs, nsegs, flags, size)); 1354 } 1355 1356 void 1357 psycho_dmamap_sync(t, map, offset, len, ops) 1358 bus_dma_tag_t t; 1359 bus_dmamap_t map; 1360 bus_addr_t offset; 1361 bus_size_t len; 1362 int ops; 1363 { 1364 struct psycho_pbm *pp = (struct psycho_pbm *)t->_cookie; 1365 1366 if (ops & (BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE)) { 1367 /* Flush the CPU then the IOMMU */ 1368 bus_dmamap_sync(t->_parent, map, offset, len, ops); 1369 iommu_dvmamap_sync(t, &pp->pp_sb, map, offset, len, ops); 1370 } 1371 if (ops & (BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE)) { 1372 /* Flush the IOMMU then the CPU */ 1373 iommu_dvmamap_sync(t, &pp->pp_sb, map, offset, len, ops); 1374 bus_dmamap_sync(t->_parent, map, offset, len, ops); 1375 } 1376 1377 } 1378 1379 int 1380 psycho_dmamem_alloc(t, size, alignment, boundary, segs, nsegs, rsegs, flags) 1381 bus_dma_tag_t t; 1382 bus_size_t size; 1383 bus_size_t alignment; 1384 bus_size_t boundary; 1385 bus_dma_segment_t *segs; 1386 int nsegs; 1387 int *rsegs; 1388 int flags; 1389 { 1390 struct psycho_pbm *pp = (struct psycho_pbm *)t->_cookie; 1391 1392 return (iommu_dvmamem_alloc(t, &pp->pp_sb, size, alignment, boundary, 1393 segs, nsegs, rsegs, flags)); 1394 } 1395 1396 void 1397 psycho_dmamem_free(t, segs, nsegs) 1398 bus_dma_tag_t t; 1399 bus_dma_segment_t *segs; 1400 int nsegs; 1401 { 1402 struct psycho_pbm *pp = (struct psycho_pbm *)t->_cookie; 1403 1404 iommu_dvmamem_free(t, &pp->pp_sb, segs, nsegs); 1405 } 1406 1407 int 1408 psycho_dmamem_map(t, segs, nsegs, size, kvap, flags) 1409 bus_dma_tag_t t; 1410 bus_dma_segment_t *segs; 1411 int nsegs; 1412 size_t size; 1413 caddr_t *kvap; 1414 int flags; 1415 { 1416 struct psycho_pbm *pp = (struct psycho_pbm *)t->_cookie; 1417 1418 return (iommu_dvmamem_map(t, &pp->pp_sb, segs, nsegs, size, kvap, flags)); 1419 } 1420 1421 void 1422 psycho_dmamem_unmap(t, kva, size) 1423 bus_dma_tag_t t; 1424 caddr_t kva; 1425 size_t size; 1426 { 1427 struct psycho_pbm *pp = (struct psycho_pbm *)t->_cookie; 1428 1429 iommu_dvmamem_unmap(t, &pp->pp_sb, kva, size); 1430 } 1431
Indexes created Thu Sep 25 16:09:42 GMT 2025